MB82D01171A-80LLPBN

FUJITSU SEMICONDUCTOR DATA SHEET DS05-11404-2E MEMORY Mobile FCRAMTM CMOS 16 Mbit (1 M word × 16 bit) Mobile Phone Application Specific Memory MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL CMOS 1,048,576-WORD × 16 BIT Fast Cycle Random Access Memory with Low Power SRAM Interface s DESCRIPTION The Fujitsu MB82D01171A is a CMOS Fast Cycle Random Access Memory (FCRAM) with asynchronous Static Random Access Memory (SRAM) interface containing 16,777,216 storages accessible in a 16-bit format. This MB82D01171A is suited for low power applications such as Cellular Handset and PDA. Note: FCRAM is a trademark of Fujitsu Limited, Japan. s PRODUCT LINEUP Parameter Access Time (tAA Max, tCE Max) Active Current (IDDA1 Max) Standby Current (IDDS1 Max) Power Down Current (IDDP Max) MB82D01171A 80 80L 80 ns 80LL 85 85L 85 ns 20 mA 200 µA 100 µA 70 µA 200 µA 100 µA 70 µA 200 µA 100 µA 70 µA 10 µA 85LL 90 90L 90 ns 90LL s PACKAGES 48-ball plastic FBGA 48-ball plastic FBGA (BGA-48P-M16) (BGA-48P-M18) MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL s FEATURES • • • • • • Asynchronous SRAM Interface 1 M word × 16 bit Organization Fast Random Cycle Time : tRC = 90 ns Fast Random Access Time : tAA = tCE = 80 ns, 85 ns, 90 ns Low Power Consumption : IDDS1 = 200 µA, 100 µA (L version) , 70 µA (LL version) Wide Operating Conditions : VDD = +2.3 V to +2.7 V +2.7 V to +3.1 V +3.1 V to +3.5 V TA = −30 °C to +85 °C • Byte Write Control • 4 words Address Access Capability • Power Down Control by CE2 2 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL s PIN ASSIGNMENTS (TOP VIEW) Flash Compatible FBGA (suffix PBT) 1 2 3 4 5 6 1 SRAM Compatible FBGA (suffix PBN) 2 3 4 5 6 A B C D E F G H A4 A3 A2 A1 A0 CE1 OE VSS A17 A7 A6 A5 DQ1 DQ9 UB LB A18 NC DQ3 CE2 WE NC A19 DQ6 A8 A9 A10 A11 DQ8 A12 A13 A14 A15 A16 NC A B C D E F G H LB DQ9 OE UB A0 A3 A5 A17 NC A14 A12 A9 A1 A4 A6 A7 A16 A15 A13 A10 A2 CE1 DQ2 DQ4 DQ5 DQ6 WE A11 CE2 DQ1 DQ3 VDD VSS DQ7 DQ8 NC DQ10 DQ11 VSS VDD DQ12 DQ13 DQ11 DQ13 DQ15 VDD DQ5 DQ15 DQ14 DQ16 A18 A19 A8 DQ10 DQ12 DQ2 DQ4 DQ14 DQ16 DQ7 VSS (BGA-48P-M16) (BGA-48P-M18) s PIN DESCRIPTION Pin Name A0 to A19 CE1 CE2 WE OE LB UB DQ1 to DQ8 DQ9 to DQ16 VDD VSS NC Address Input Chip Enable (Low Active) Chip Enable (High Active) Write Enable (Low Active) Output Enable (Low Active) Lower Byte Write Control (Low Active) Upper Byte Write Control (Low Active) Lower Byte Data Input/Output Upper Byte Data Input/Output Power Supply Ground No Connection Description 3 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL s BLOCK DIAGRAM VDD VSS A0 to A19 Address Latch & Buffer Row Decoder Memory Cell Array 16,777,216 bit DQ1 to DQ8 I/O Buffer DQ9 to DQ16 Input Data Latch & Control Sense / Switch Output Data Control Column / Decoder Address Latch & Buffer CE2 Power Control Timing Control CE1 WE LB UB OE 4 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL s FUNCTION TRUTH TABLE *1 Mode Power Down *2 Standby (Deselect) Output Disable*3 Read*4 Write Write (Lower Byte) Write (Upper Byte) H L H H CE1 X H CE2 L WE X X OE X X H L LB X X X X L L H UB X X X X L H L DQ1 to DQ8 High-Z High-Z High-Z Output Valid Input Valid Input Valid Invalid DQ9 to DQ16 High-Z High-Z High-Z Output Valid Input Valid Invalid Input Valid IDDA Yes IDD IDDP IDDS Data Retention No L *1 : V = Valid, L = Logic Low, H = Logic High, X = either “L” or “H”, High-Z = High Impedance *2 : Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. *3 : Output Disable mode should not be kept longer than 1 µs. *4 : Byte control at Read mode is not supported. 5 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL s ABSOLUTE MAXIMUM RATINGS Parameter Voltage of VDD Supply Relative to VSS Voltage at Any Pin Relative to VSS Short Circuit Output Current Storage Temperature Symbol VDD VIN VOUT IOUT TSTG Rating Min −0.5 −0.5 −0.5 −50 −55 Max +3.6 +3.6 +3.6 +50 +125 Unit V V V mA °C WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. s RECOMMENDED OPERATING CONDITIONS Parameter Symbol VDD (31) Supply Voltage *1 VDD (27) VDD (23) VSS VIH (31) High Level Input Voltage *1, *2 VIH (27) VIH (23) VIL (31) Low Level Input Voltage *1, *2 Ambient Temperature *1 : All voltages are referenced to VSS. *2 : Minimum DC voltage on input or I/O pins are −0.3 V. During voltage transitions, inputs may undershoot VSS to −1.0 V for periods of up to 5 ns. Maximum DC voltage on input and I/O pins are VDD + 0.3 V. During voltage transitions, inputs may positive overshoot to VDD + 1.0 V for periods of up to 5 ns. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. VIL (27) VIL (23) TA 2.2 2.0 −0.3 −0.3 −0.3 −30 Value Min 3.1 2.7 2.3 0 2.6 Max 3.5 3.1 2.7 0 VDD + 0.3 and ≤ 3.6 VDD + 0.3 VDD + 0.3 0.5 0.5 0.4 85 Unit V V V V V V V V V V °C 6 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL s PIN CAPACITANCE (f = 1.0 MHz, TA = +25 °C) Value Unit Typ Max    5 5 8 pF pF pF Parameter Address Input Capacitance Control Input Capacitance Data Input/Output Capacitance Symbol CIN1 CIN2 CIO Conditions VIN = 0 V VIN = 0 V VIO = 0 V Min    s ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level Symbol ILI ILO VOH(31) VOH(27) VOH(23) VOL Conditions VSS ≤ VIN ≤ VDD 0 V ≤ VOUT ≤ VDD, Output Disable VDD = VDD(31), IOH = −0.5 mA VDD = VDD(27), IOH = −0.5 mA VDD = VDD(23), IOH = −0.5 mA IOL = 1 mA VDD = VDD(31) Max, VIN = VIH or VIL, CE2 ≤ 0.2 V VDD = VDD(27, 23) Max, VIN = VIH or VIL, CE2 ≤ 0.2 V VDD = VDD(31) Max, VIN = VIH or VIL CE1 = CE2 = VIH, IOUT = 0 mA VDD = VDD(27, 23) Max, VIN = VIH or VIL CE1 = CE2 = VIH, IOUT = 0 mA VDD = VDD(31) Max, VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, CE1 = CE2 ≥ VDD − 0.2 V, IOUT = 0 mA VDD = VDD(27, 23) Max, VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, CE1 = CE2 ≥ VDD − 0.2 V, IOUT = 0 mA Value Min −1.0 −1.0 2.4 2.25 1.8                Max +1.0 +1.0    0.4 20 10 5.5 2.0 1.5 5 1.5 1 250 150 120 200 100 70 µA µA mA mA Unit µA µA V V V V µA µA VDD Power Down Current IDDP L Version LL Version L Version VDD Standby Current LL Version L Version LL Version L Version LL Version IDDS IDDS IDDS1 IDDS1 (Continued) 7 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL (Continued) Parameter Symbol Conditions VDD(31) = VDD Max, VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA tRC / tWC = Min VDD(27, 23) = VDD Max, VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA VDD(31) = VDD Max, VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA tRC / tWC = 1 µs VDD(27, 23) = VDD Max, VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA Value Min Max Unit 25  20 mA IDDA1 VDD Active Current 4.0  3.0 mA IDDA2 Notes: • All voltages are referenced to Vss. • DC Characteristics are measured after following POWER-UP timing. • IOUT depends on the output load conditions. 8 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 2. AC Characteristics (1) Read Operation Parameter Read Cycle Time Chip Enable Access Time Output Enable Access Time Address Access Time Output Data Hold Time CE1 Low to Output Low-Z OE Low to Output Low-Z CE1 High to Output High-Z OE High to Output High-Z Address Setup Time to CE1 Low Address Setup Time to OE Low Address Invalid Time CE1 Low to Address Hold Time OE Low to Address Hold Time CE1 High to Address Hold Time OE High to Address Hold Time CE1 Low to OE Low Delay Time OE Low to CE1 High Delay Time CE1 High Pulse Width OE High Pulse Width *1: The output load is 30 pF. *2: The output load is 5 pF. *3: The tCE is applicable if OE is brought to Low before CE1 goes Low and is also applicable if actual value of both or either tASO or tCLOL is shorter than specified value. *4: Applicable only to A0 and A1 when both CE1 and OE are kept at Low for the address access. *5: Applicable if OE is brought to Low before CE1 goes Low. *6: The tASO, tCLOL (Min) and tOP (Min) are reference values when the access time is determined by tOE. If actual value of each parameter is shorter than specified minimum value, tOE become longer by the amount of subtraction actual value from specified minimum value. For example, if actual tASO, tASO (actual) , is shorter than specified minimum value, tASO (Min) , during OE control access (i.e., CE1 stays Low) , the tOE become tOE (Max) + tASO (Min) − tASO (actual) . *7: The tASO[ABS] and tOP[ABS] is the absolute minimum value during OE control access. *8: If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC (Min) − tCLOL (actual) or tRC (Min) − tOP (actual) . *9: Maximum value is applicable if CE1 is kept at Low. 9 Symbol tRC tCE tOE tAA tOH tCLZ tOLZ tCHZ tOHZ tASC tASO tASO[ABS] tAX tCLAH tOLAH tCHAH tOHAH tCLOL tOLCH tCP tOP tOP[ABS] -80/-80L/ -80LL Min 90    5 5 0   −5 45 10  90 45 −5 −5 45 45 20 45 20 Max  80 45 80    30 25    5     1000   1000  -85/-85L/ -85LL Min 90    5 5 0   −5 45 10  90 45 −5 −5 45 45 20 45 20 Max  85 45 85    30 25    5     1000   1000  -90/-90L/ -90LL Min 90    5 5 0   −5 45 10  90 45 −5 −5 45 45 20 45 20 Max  90 45 90    30 25    5     1000   1000  ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *6, *8, *9 *7 *3, *6, *8, *9 *8 *1, *3 *1 *1, *4 *1 *2 *2 *2 *2 *5 *3, *6 *7 *4 *4 *4, *8 Unit Notes MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL (2) Write Operation Parameter Write Cycle Time Address Setup Time Address Hold Time CE1 Write Setup Time CE1 Write Hold Time WE Setup Time WE Hold Time LB and UB Setup Time LB and UB Hold Time OE Setup Time OE Hold Time OE High to CE1 Low Setup Time Address Hold Time to OE High CE1 Write Pulse Width WE Write Pulse Width CE1 Write Recovery Time WE Write Recovery Time Data Setup Time Data Hold Time CE1 High Pulse Width Symbol tWC tAS tAH tCS tCH tWS tWH tBS tBH tOES tOEH tOEH[ABS] tOHCL tOHAH tCW tWP tWRC tWR tDS tDH tCP -80/-80L/ -80LL Min 90 0 45 0 0 0 0 −5 −5 0 45 20 −3 0 60 60 15 15 20 0 20 Max    1000 1000     1000 1000       1000    -85/-85L/ -85LL Min 90 0 45 0 0 0 0 −5 −5 0 45 20 −3 0 60 60 15 15 20 0 20 Max    1000 1000     1000 1000       1000    -90/-90L/ -90LL Min 90 0 45 0 0 0 0 −5 −5 0 45 20 −3 0 60 60 15 15 20 0 20 Max    1000 1000     1000 1000       1000    ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *9 *3 *3, *4 *5 *6 *7 *1, *8 *1, *8 *1, *9 *1, *3, *9 *1 *2 *2 Unit Notes *1: Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR) . *2: New write address is valid from either CE1 or WE is brought to High. *3: Maximum value is applicable if CE1 is kept at Low and both WE and OE are kept at High. *4: The tOEH is specified from end of tWC (Min) and is a reference value when access time is determined by tOE. If actual value is shorter than specified minimum value, tOE become longer by the amount of subtracting actual value from specified minimum value. *5: The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1 stays Low. *6: tOHCL (Min) must be satisfied if read operation is not performed prior to write operation. In case OE is disabled after tOHCL (Min) , WE Low must be asserted after tRC (Min) from CE1 Low. In other words, read operation is initiated if tOHCL (Min) is not satisfied. *7: Applicable if CE1 stays Low after read operation. *8: tCW and tWP is applicable if write operation is initiated by CE1 and WE, respectively. *9: tWRC and tWR is applicable if write operation is terminated by CE1 and WE, respectively. The tWR (Min) can be ignored if CE1 is brought to High together or after WE is brought to High. In such case, the tCP (Min) must be satisfied. 10 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL (3) Power Down Parameters Parameter CE2 Low Setup Time for Power Down Entry CE2 Low Hold Time after Power Down Entry CE1 High Hold Time following CE2 High after Power Down Exit CE1 High Setup Time following CE2 High after Power Down Exit (4) Other Timing Parameters Parameter CE1 High to OE Invalid Time for Standby Entry CE1 High to WE Invalid Time for Standby Entry CE2 Low Hold Time after Power-up CE2 High Hold Time after Power-up CE1 High Hold Time following CE2 High after Power-up Input Transition Time Symbol tCHOX tCHWX tC2LH tC2HL tCHH tT Value Min 20 20 50 50 350 1 Max      25 Unit ns ns µs µs µs ns *1 *2 *3 *2 *4 Note Symbol tCSP tC2LP tCHH tCHS Value Min 10 100 350 10 Max     Unit ns ns µs ns Note *1: It may write some data into any address location if tCHWX is not satisfied. *2: Must satisfy tCHH (Min) after tC2LH (Min) . *3: Requires Power Down mode entry and exit after tC2HL. *4: The Input Transition Time (tT) at AC testing is 5 ns as shown in below. If actual tT is longer than 5 ns, it may violate some timing parameters of AC specification. (5) AC Test Conditions Parameter Input High Level Symbol VIH Conditions VDD = 3.1 V to 3.5 V VDD = 2.7 V to 3.1 V VDD = 2.3 V to 2.7 V VDD = 3.1 V to 3.5 V Input Low Level VIL VDD = 2.7 V to 3.1 V VDD = 2.3 V to 2.7 V VDD = 3.1 V to 3.5 V Input Timing Measurement Level Input Transition Time VREF tT VDD = 2.7 V to 3.1 V VDD = 2.3 V to 2.7 V Between VIL and VIH Measured Value 2.6 2.3 2.0 0.5 0.5 0.4 1.5 1.3 1.1 5 Unit V V V V V V V V V ns Note 11 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL s TIMING DIAGRAM 1. READ Timing #1 (OE Control Access) tRC tRC Address Valid tASO tOHAH tOHAH Address Address Valid tCE CE1 tOLCH tCLOL tOE tOP tOE OE tASO tOLZ tOHZ tOH tOLZ tOHZ tOH DQ (Output) Valid Data Output Valid Data Output Note : CE2 and WE must be High for entire read cycle. 2. READ Timing #2 (CE1 Control Access) tRC tRC Address Valid tCHAH tASC tCE tCHAH Address tASC Address Valid tCE CE1 tOLCH tOE tCHZ tCP tCHZ OE tCLZ tOH tCLZ tOH DQ (Output) Valid Data Output Valid Data Output Note : CE2 and WE must be High for entire read cycle. 12 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 3. READ Timing #3 (Address Access after OE Control Access) tRC tRC Address Valid (No change) Address (A19 - A2) Address Valid Address (A1, A0) tASO Address Valid tOLAH tAX Address Valid tAA tOHAH CE1 tOE tOHZ OE tOLZ tOH tOH DQ (Output) Valid Data Output Valid Data Output Note : CE2 and WE must be High for entire read cycle. 4. READ Timing #4 (Address Access after CE1 Control Access) tRC tRC Address Valid (No change) Address (A19-A2) Address Valid Address (A1, A0) tASC Address Valid tCLAH tAX Address Valid tAA tCHAH CE1 tCE tCHZ OE tCLZ tOH tOH DQ (Output) Valid Data Output Valid Data Output Note : CE2 and WE must be High for entire read cycle. 13 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 5. WRITE Timing #1 (CE1 Control) tWC Address tAS Address Valid tAH tAS CE1 tCW tWS tWH tWRC tWS WE tBS tBH tBS UB, LB tOHCL OE tDS tDH DQ (Input) Valid Data Input Note : CE2 must be High for write cycle. 14 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 6. WRITE Timing #2-1 (WE Control, Single Write Operation) tWC Address tOHAH tAS Address Valid tAH tCH tAS CE1 tCP tOHCL tCS tWP tWR WE tBS tBH UB, LB tOES OE tOHZ tDS tDH DQ (Input) Valid Data Input Note : CE2 must be High for write cycle. 15 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 7. WRITE Timing #2 (WE Control, Continuous Write Operation) tWC Address Valid tOHAH tAS tAH tAS Address CE1 tOHCL tCS tWP tWR WE tBS tBH tBS UB, LB tOES OE tOHZ tDS tDH DQ (Input) Valid Data Input 16 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 8. READ/WRITE Timing #1-1 (CE1 Control) tWC Address tCHAH tAS Write Address tAH tASC Read Address CE1 tCP tWH tWS tCW tWH tWRC tWS WE tBS tBH UB, LB tOHCL tCLOL OE tCHZ tOH tDS tDH tOLZ tCLZ DQ Read Data Output Write Data Input Note : Write address is valid from either CE1 or WE of last falling edge. 17 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 9. READ/WRITE Timing #1-2 (CE1 Control) tRC Address tASC tWRC Read Address tCHAH tAS Write Address CE1 tWRC (Min) tWH tWS tWH tCP tWS WE tBH tCE tBS UB, LB tOEH tOHCL OE tCHZ tDH tCLZ tOH DQ Write Data Input Read Data Output Note : The tOEH is specified from the time satisfied both tWRC and tWR (Min) . 18 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 10. READ (OE Control) /WRITE (WE Control) Timing #2-1 tWC Write Address tOHAH tAS tAH tASO Read Address Address CE1 Low tWP tWR WE tBS tBH UB, LB tOES tOEH OE tOHZ tOH tDS tDH tOLZ DQ Read Data Output Write Data Input Note : CE1 can be tied to Low for WE and OE controlled operation. When CE1 is tied to Low, output is exclusively controlled by OE. 19 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 11. READ (OE Control) /WRITE (WE Control) Timing #2-2 tRC Address tASO Read Address Valid tOHAH tAS Write Address CE1 Low tWR WE tBH tBS UB, LB tOEH tOE tOES OE tOHZ tDH tOLZ tOH DQ Write Data Input Read Data Output Note : CE1 can be tied to Low for WE and OE controlled operation. When CE1 is tied to Low, output is exclusively controlled by OE. 20 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 12. POWER DOWN Timing CE1 tCHS CE2 tCSP tC2LP High-Z tCHH DQ Power Down Entry Power Down Mode Power Down Exit 13. Standby Entry Timing after Read or Write CE1 tCHOX tCHWX OE WE Active (Read) Standby Active (Write) Standby Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (Min) period from either last address transition of A0 and A1, or CE1 Low to High transition. 14. POWER-UP Timing 1 CE1 tCHS tC2LH tCHH CE2 VDD 0V VDD Min Note : It is recommended to keep CE2 at Low during VDD power-up. The tC2LH specifies after VDD reaches specified minimum level. 21 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL 15. POWER-UP Timing 2 CE1 tCHS tC2HL tCSP tC2LP tCHH CE2 tC2HL VDD 0V VDD Min Note : The tC2HL specifies from CE2 Low to High transition after VDD reaches specified minimum level. CE1 must be brought to High prior to or together with CE2 Low to High transition. 22 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL s DATA RETENTION 1. Low VDD Characteristics Parameter VDD Data Retention Supply Voltage L Version VDD Data Retention Supply Current LL Version L Version LL Version Data Retention Setup Time Data Retention Recovery Time VDD Voltage Transition Time tDRS tDRR ∆V/∆t IDR1 Symbol VDR Test Conditions CE1 = CE2 ≥ VDD − 0.2 V or, CE1 = CE2 = VIH, VDD = VDD (23) , VIN = VIH (23) or VIL CE1 = CE2 = VIH (23) , IOUT = 0 mA VDD = VDD (23) , VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, CE1 = CE2 ≥ VDD − 0.2 V, IOUT = 0 mA VDD = VDD (27) at data retention entry VDD = VDD (27) after data retention  Value Min 2.1       0 90 0.5 Max 3.5 5 1.5 1 200 100 70    ns ns V/µs µA mA Unit V IDR 2. Data Retention Timing tDRS tDRR 3.5 V VDD ∆V/∆t ∆V/∆t 2.7 V CE2 2.1 V CE1 CE1 = CE2 ≥ VDD - 0.2 V or VIH (23) Min 0.4 V VSS Data Retention Mode Data bus must be in High-Z at data retention entry. 23 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL s ORDERING INFORMATION Part Number MB82D01171A-80PBT MB82D01171A-80LPBT MB82D01171A-80LLPBT MB82D01171A-85PBT MB82D01171A-85LPBT MB82D01171A-85LLPBT MB82D01171A-90PBT MB82D01171A-90LPBT MB82D01171A-90LLPBT MB82D01171A-80PBN MB82D01171A-80LPBN MB82D01171A-80LLPBN MB82D01171A-85PBN MB82D01171A-85LPBN MB82D01171A-85LLPBN MB82D01171A-90PBN MB82D01171A-90LPBN MB82D01171A-90LLPBN Package 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) 48-ball plastic FBGA 0.8 mm pitch (BGA-48P-M16) 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) 48-ball plastic FBGA 0.75 mm pitch (BGA-48P-M18) Remarks tCE = 80 ns Max, IDDS1 = 200 µA Max Flash Compatible Package tCE = 80 ns Max, IDDS1 = 100 µA Max Flash Compatible Package tCE = 80 ns Max, IDDS1 = 70 µA Max Flash Compatible Package tCE = 85 ns Max, IDDS1 = 200 µA Max Flash Compatible Package tCE = 85 ns Max, IDDS1 = 100 µA Max Flash Compatible Package tCE = 85 ns Max, IDDS1 = 70 µA Max Flash Compatible Package tCE = 90 ns Max, IDDS1 = 200 µA Max Flash Compatible Package tCE = 90 ns Max, IDDS1 = 100 µA Max Flash Compatible Package tCE = 90 ns Max, IDDS1 = 70 µA Max Flash Compatible Package tCE = 80 ns Max, IDDS1 = 200 µA Max SRAM Compatible Package tCE = 80 ns Max, IDDS1 = 100 µA Max SRAM Compatible Package tCE = 80 ns Max, IDDS1 = 70 µA Max SRAM Compatible Package tCE = 85 ns Max, IDDS1 = 200 µA Max SRAM Compatible Package tCE = 85 ns Max, IDDS1 = 100 µA Max SRAM Compatible Package tCE = 85 ns Max, IDDS1 = 70 µA Max SRAM Compatible Package tCE = 90 ns Max, IDDS1 = 200 µA Max SRAM Compatible Package tCE = 90 ns Max, IDDS1 = 100 µA Max SRAM Compatible Package tCE = 90 ns Max, IDDS1 = 70 µA Max SRAM Compatible Package 24 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL s PACKAGE DIMENSIONS 48-ball plastic FBGA (BGA-48P-M16) 1.05 –0.10 9.00±0.10(.354±.004) .041 –.004 +0.15 +.006 (Mounting height) (5.60(.220)) 0.80(.031) TYP 0.36±0.10 (Stand off) (.014±.004) 6 5 6.00±0.10 (.236±.004) (4.00(.157)) 4 3 2 1 0.80(.031) TYP INDEX AREA HG F E DC B A 0.08(.003) M 48-Ø0.45±0.10 (48-Ø.018±.004) 0.20(.008) S S 0.10(.004) C 2000 FUJITSU LIMITED B48016S-1c-1 Dimensions in mm (inches) (Continued) 25 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL (Continued) 48-ball plastic FBGA (BGA-48P-M18) 1.05 –0.10 9.00±0.10(.354±.004) .041 –.004 +0.15 +.006 (Mounting height) (5.25(.207)) 0.75(.030) TYP 0.25±0.10 (.010±.004) (Stand off) 6 5 6.00±0.10 (.236±.004) (3.75(.148)) 4 3 2 1 0.75(.030) TYP INDEX AREA H GFE DC BA INDEX MARK 0.08(.003) M 48-ø0.35±0.10 (48-ø.014±.004) 0.20(.008) S S 0.10(.004) S C 2001 FUJITSU LIMITED B48018S-c-1-1 Dimensions in mm (inches) 26 MB82D01171A-80/80L/80LL/85/85L/85LL/90/90L/90LL FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0112 © FUJITSU LIMITED Printed in Japan