MB82DBS02163C-70LPBT

FUJITSU SEMICONDUCTOR DATA SHEET DS05-11429-3E MEMORY Mobile FCRAMTM CMOS 32 M Bit (2 M word×16 bit) MB82DBS02163C-70L ■ DESCRIPTION Mobile Phone Application Specific Memory The FUJITSU MB82DBS02163C is a CMOS Fast Cycle Random Access Memory (FCRAM*) with asynchronous Static Random Access Memory (SRAM) interface containing 33,554,432 storages accessible in a 16-bit format. MB82DBS02163C is utilized using a FUJITSU advanced FCRAM core technology and improved integration in comparison to regular SRAM. The MB82DBS02163C adopts asynchronous page mode and synchronous burst mode for fast memory access as user configurable options. This MB82DBS02163C is suited for mobile applications such as Cellular Handset and PDA. *: FCRAM is a trademark of Fujitsu Limited, Japan ■ FEATURES • • • • • • • • Asynchronous SRAM Interface Fast Access Time : tCE = 70 ns Max 8 words Page Access Capability : tPAA = 20 ns Max Burst Read/Write Access Capability : tAC = 12 ns Max Low Voltage Operating Condition : VDD = +1.65 V to +1.95 V Wide Operating Temperature : TA = -30 °C to +85 °C Byte Control by LB and UB Low-Power Consumption : IDDA1 = 30 mA Max IDDS1 = 80 µA Max • Various Power Down mode : Sleep 4 M-bit Partial 8 M-bit Partial • Shipping Form : Wafer/Chip, 71-ball plastic FBGA package Copyright© 2005-2006 FUJITSU LIMITED All rights reserved MB82DBS02163C-70L ■ PRODUCT LINEUP Parameter Access Time (Max) (tCE, tAA) CLK Access Time (Max) (tAC) Active Current (Max) (IDDA1) Standby Current (Max) (IDDS1) Power Down Current (Max) (IDDPS) MB82DBS02163C-70L 70 ns 12 ns 30 mA 80 µA 10 µA ■ PIN ASSIGNMENT (TOP VIEW) A B C D E F G H J K L M 8 7 6 5 4 3 2 1 NC NC NC NC A11 A8 WE CLK LB A15 A12 A19 CE2 NC A13 A9 A20 NC A14 A10 A16 NC DQ7 NC DQ16 VSS DQ8 DQ15 DQ6 NC DQ12 DQ3 DQ9 NC NC NC NC DQ14 DQ13 DQ5 DQ4 VDD VDD ADV WAIT UB A6 A3 A18 A5 A2 A17 A4 A1 DQ2 VSS A0 DQ10 DQ11 OE NC DQ1 CE1 NC NC NC A7 NC NC NC NC (BGA-71P-M03) 2 MB82DBS02163C-70L ■ PIN DESCRIPTION Pin Name A20 to A0 CE1 CE2 WE OE LB UB CLK ADV WAIT DQ8 to DQ1 DQ16 to DQ9 VDD VSS NC Address Input Chip Enable 1 (Low Active) Chip Enable 2(High Active) Write Enable (Low Active) Output Enable (Low Active) Lower Byte Control (Low Active) Upper Byte Control (Low Active) Clock Input Address Valid Input (Low Active) Wait Output Lower Byte Data Input/Output Upper Byte Data Input/Output Power Supply Voltage Ground No Connection Description ■ BLOCK DIAGRAM VDD VSS A20 to A3 A2 to A0 MODE CONTROLLER ADDRESS LATCH & BUFFER X CONTROLLER Y CONTROLLER BURST ADDRESS COUNTER MEMORY CELL ARRAY 33,554,432 bits CE2 CE1 ADV WE OE LB UB CLK WAIT DQ16 to DQ9 COMMAND DECODER ADDRESS CONTROLLER READ AMP WRITE AMP MEMORY CORE CONTROLLER BURST CONTROLLER BUS CONTROLLER PARALLEL SERIAL TO SERIAL TO PARALLEL CONVERSION CONVERSION CONVERTER I/O BUFFER DQ8 to DQ1 3 MB82DBS02163C-70L ■ FUNCTION TRUTH TABLE 1. Asynchronous Operation (Page Mode) Mode Standby (Deselect) Output Disable*1 Output Disable (No Read) Read (Upper Byte) Read (Lower Byte) Read (Word) Page Read No Write Write (Upper Byte) Write (Lower Byte) Write (Word) Power Down*2 L X H L CE2 CE1 CLK ADV WE H H X X X X X X X X X X X X X *3 *3 *3 *3 *3 *3 *3 *3 *3 *3 X X X L H*4 H L X H OE X H LB X X H H L L L/H H H L L X UB A20 to A0 DQ8 to DQ1 DQ16 to DQ9 X X H L H L L/H H L H L X X *5 Valid Valid Valid Valid Valid Valid Valid Valid Valid X High-Z High-Z High-Z High-Z Output Valid Output Valid *6 Invalid Invalid Input Valid Input Valid High-Z High-Z High-Z High-Z Output Valid High-Z Output Valid *6 Invalid WAIT High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Input Valid High-Z Invalid High-Z Input Valid High-Z High-Z High-Z Note : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance *1: Should not be kept this logic condition longer than 1 µs. *2: Power Down mode can be entered from Standby state and all output are in High-Z state. Data retention depends on the selection of Partial Size for Power Down Program. Refer to "Power Down" in "■FUNCTIONAL DESCRIPTION" for the details. *3: "L" for address pass through and "H" for address latch on the rising edge of ADV. *4: OE can be VIL during write operation if the following conditions are satisfied; (1) Write pulse is initiated by CE1. Refer to "(14) Asynchronous Read/Write Timing #1-1 (CE1 Control)" in "■TIMING DIAGRAMS". (2) OE stays VIL during Write cycle. *5: Can be either VIL or VIH but must be valid before Read or Write. *6: Output of upper and lower byte data is either Valid or High-Z depending on the level of LB and UB input. 4 MB82DBS02163C-70L 2. Synchronous Operation (Burst Mode) Mode Standby(Deselect) Start Address Latch*1 Advance Burst Read to Next Address*1 Burst Read Suspend*1 Advance Burst Write to Next Address*1 Burst Write Suspend* 1 CE2 CE1 CLK ADV WE H X *3 *3 H L *3 *3 *3 X X L X X X H L* 5 OE X X*4 L LB X UB A20 to A0 DQ8 to DQ1 DQ16 to DQ9 X X Valid*7 High-Z High-Z*8 Output Valid*9 High-Z High-Z High-Z*8 Output Valid*9 High-Z Input Valid*10 Input Invalid High-Z High-Z High-Z WAIT High-Z High-Z*11 Output Valid High*12 High*13 High*12 High-Z High-Z High-Z X X X*4 H H X*6 H H* H X X 5 X*6 X Input Valid*10 Input Invalid Terminate Burst Read Terminate Burst Write Power Down*2 X H X X X X High-Z High-Z High-Z Note : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High impedance = valid edge, = rising edge of Low pulse, *1: Should not be kept this logic condition longer than 8 µs. *2: Power Down mode can be entered from Standby state and all output are in High-Z state. Data retention depends on the selection of Partial Size for Power Down Program. Refer to "Power Down" in “■FUNCTIONAL DESCRIPTION” for the details. *3: Valid clock edge shall be set on either rising or falling edge through CR set. CLK must be started and stable prior to memory access. *4: Can be either VIL or VIH except for the case the both of OE and WE are VIL. It is prohibited to bring the both of OE and WE to VIL. *5: When device is operating in "WE Single Clock Pulse Control" mode, WE is Don’t care once write operation is determined by WE Low Pulse at the beginning of write access together with address latching. Burst write suspend feature is not supported in "WE Single Clock Pulse Control" mode. *6: Can be either VIL or VIH but must be valid before Read or Write is determined. And once LB and UB input levels are determined, they must not be changed until the end of burst. *7: Once valid address is determined, input address must not be changed during ADV = L. *8: If OE = L, output is either Invalid or High-Z depending on the level of LB and UB input. If WE = L, input is Invalid. If OE = WE = H, output is High-Z. *9: Outputs is either Valid or High-Z depending on the level of LB and UB input. *10: Input is either Valid or Invalid depending on the level of LB and UB input. *11: Output is either High-Z or Invalid depending on the level of OE and WE input. *12: Keep the level from previous cycle except for suspending on last data. Refer to "WAIT Output Function" in "■FUNCTIONAL DESCRIPTION" for the details. *13: WAIT output is driven in High level during burst write operation. 5 MB82DBS02163C-70L ■ STATE DIAGRAM • Initial/Standby State Asynchronous Operation (Page Mode) Power Up Synchronous Operation (Burst Mode) Pause Time Power Down CE2 = H CR Set Common State @M = 1 @M = 0 CE2 = H Power Down CE2 = L CE2 = L Standby Standby • Asynchronous Operation CE2 = CE1 = H Standby CE1 = L CE1 = H CE1 = H CE1 = L & WE = L CE1 = L & OE = L CE1 = H OE = L Byte Control Write Output Disable WE = H WE = L OE = H Address Change or Byte Control Read Byte Control @OE = L • Synchronous Operation CE2 = CE1 = H Standby CE1 = H CE1 = H CE1 = H Write Suspend CE1 = H Read Suspend OE = L WE = H WE = L CE1 = L, ADV Low Pulse, & WE = L CE1 = L, ADV Low Pulse, & OE = L OE = H ADV Low Pulse Write ADV Low Pulse (@BL = 8 or 16, and after burst operation is completed) Read ADV Low Pulse Note : Assuming all the parameters specified in AC CHARACTERISTICS are satisfied. Refer to the "■FUNCTIONAL DESCRIPTION", "2. AC Characteristics" in "■ELECTRICAL CHARACTERISTICS", and "■TIMING DIAGRAMS" for details. 6 MB82DBS02163C-70L ■ FUNCTIONAL DESCRIPTION This device supports asynchronous read, page read & normal write operation and synchronous burst read and burst write operation for faster memory access and features 3 kinds of power down modes for power saving as user configurable option. • Power-up It is required to follow the power-up timing to start executing proper device operation. Refer to "Power-up Timing". After Power-up, the device defaults to asynchronous page read & normal write operation mode with sleep power down feature. • Configuration Register The Configuration Register(CR) is used to configure the type of device function among optional features. Each selection of features is set through CR set sequence after power-up. If CR set sequence is not performed after power-up, the device is configured for asynchronous operation with sleep power down feature as default configuration. • CR Set Sequence The CR set requires total 6 read/write cycles with unique address. Operation other than read/write operation requires that device being in standby mode. Following table shows the detail sequence. Cycle # #1 #2 #3 #4 #5 #6 Operation Read Write Write Write Write Read Address 1FFFFFh (MSB) 1FFFFFh 1FFFFFh 1FFFFFh 1FFFFFh Address Key Data Read Data (RDa) RDa RDa X X Read Data (RDb) The first cycle is to read from most significant address(MSB). The second and third cycles are to write to MSB. If the second or third cycle is written into the different address, the CR set is cancelled and the data written by the second or third cycle is valid as a normal write operation. It is recommended to write back the data(RDa) read by first cycle to MSB in order to secure the data. The forth and fifth cycles are to write to MSB. The data of forth and fifth cycle is don't-care. If the forth or fifth cycle is written into different address, the CR set is also cancelled, but write data may not be written as normal write operation. The last cycle is to read from specific address key for mode selection. And read data(RDb) is invalid. Once this CR set sequence is performed from an initial CR set to the other new CR set, the written data stored in memory cell array may be lost. So, it should perform the CR set sequence prior to regular read/write operation if necessary to change from default configuration. 7 MB82DBS02163C-70L • Address Key The address key has the following format. Address Register Function Key Pin Name 00 A20, A19 PS Partial Size 01 10 11 000 001 010 A18 to A16 BL Burst Length 011 100 101 110 111 A15 M Mode 0 1 000 001 A14 to A12 RL Read Latency 010 011 1xx A11 A10 A9 A8 A7 A6 to A0 BS SW VE ⎯ WC ⎯ Burst Sequence Single Write Valid Clock Edge ⎯ Write Control ⎯ 0 1 0 1 0 1 1 0 1 1 8 M-bit Partial 4 M-bit Partial Reserved for future use Sleep [Default] Reserved for future use Reserved for future use 8 words 16 words Reserved for future use Reserved for future use Reserved for future use Continuous Synchronous Mode (Burst Read / Write) Asynchronous Mode [Default] (Page Read / Normal Write) Reserved for future use 3 clocks 4 clocks 5 clocks Reserved for future use Reserved for future use Sequential Burst Read & Burst Write Burst Read & Single Write Falling Clock Edge Rising Clock Edge Unused bits must be 1 WE Single Clock Pulse Control without Write Suspend Function WE Level Control with Write Suspend Function Unused bits must be 1 *5 *5 *4 *4 *1 *1 *2 *3 *1 *1 *1 *1 *1 *1 *1 Description Note *1: It is prohibited to apply this key. *2: If M = 0, all the registers must be set with appropriate Key input at the same time. *3: If M = 1, PS must be set with appropriate Key input at the same time. Except for PS, all the other key inputs must be "1". *4: Burst Read & Single Write is not supported at WE Single Clock Pulse Control. *5: A8 and A6 to A0 must be all "1" in any cases. 8 MB82DBS02163C-70L • Power Down The Power Down is low power idle state controlled by CE2. CE2 Low drives the device in power down mode and maintains low power idle state as long as CE2 is kept Low. CE2 High resumes the device from power down mode. This device has 3 power down modes, Sleep, 4 M-bit Partial, and 8 M-bit Partial. The selection of power down mode is set through CR set sequence. Each mode has following data retention features. Mode Sleep [default] 4 M-bit Partial 8 M-bit Partial Data Retention Size No 4 M bits 8 M bits Retention Address N/A 000000h to 03FFFFh 000000h to 07FFFFh The default state after power-up is Sleep and it is the lowest power consumption but all data will be lost once CE2 is brought to Low for Power Down. It is not required to perform CR set sequence to set to Sleep mode after power-up in case of asynchronous operation. • Burst Read/Write Operation Synchronous burst read/write operation provides faster memory access that synchronized to microcontroller or system bus frequency. Configuration Register(CR) Set is required to perform burst read & write operation after power-up. Once CR set sequence is performed to select synchronous burst mode, the device is configured to synchronous burst read/write operation mode with corresponding RL and BL that is set through CR set sequence together with operation mode. In order to perform synchronous burst read & write operation, it is required to control new signals, CLK, ADV and WAIT that Low Power SRAMs do not have. • Burst Read Operation CLK Address Valid address ADV CE1 OE WE DQ High RL High-Z Q1 BL WAIT High-Z Q2 QBL (Continued) 9 MB82DBS02163C-70L (Continued) • Burst Write Operation CLK Address Valid address ADV CE1 High OE WE RL-1 DQ High-Z D1 BL WAIT High-Z D2 DBL • CLK Input Function The CLK is input signal to synchronize memory to microcontroller or system bus frequency during synchronous burst read & write operation. The CLK input increments device internal address counter and the valid edge of CLK is referred for latency counts from address latch, burst write data latch, and burst read data output. During synchronous operation mode, CLK input must be supplied except for standby state and power down state. CLK is Don't care during asynchronous operation. • ADV Input Function The ADV is input signal to latch valid address. It is applicable to synchronous operation as well as asynchronous operation. ADV input is active during CE1 = L and CE1 = H disables ADV input. All addresses are determined on the rising edge of ADV. During synchronous burst read/write operation, ADV = H disables all address inputs. Once ADV is brought to High after valid address latch, it is inhibited to bring ADV Low until the end of burst or until burst operation is terminated. ADV Low pulse is mandatory for synchronous burst read/write operation mode to latch the valid address input. During asynchronous operation, ADV = H also disables all address inputs. ADV can be tied to Low during asynchronous operation and it is not necessary to control ADV to High. 10 MB82DBS02163C-70L • WAIT Output Function The WAIT is output signal to indicate data bus status when the device is operating in synchronous burst mode. During burst read operation, WAIT output is enabled after specified time duration from OE = L or CE1 = L whichever occurs last. WAIT output Low indicates data output at next clock cycle is invalid, and WAIT output becomes High one clock cycle prior to valid data output. During continuous burst read operation, an additional output delay may occur when a burst sequence crosses it's device-row boundary. The WAIT output notifies this delay to controller. Refer to the section "Burst Length" for the additional delay cycles in details. During OE read suspend, WAIT output does not indicate data bus status but carries the same level from previous clock cycle (kept High) except for read suspend on the final data output. If final read data output is suspended, WAIT output becomes high impedance after specified time duration from OE = H. During burst write operation, WAIT output is enabled to High level after specified time duration from WE = L or CE1 = L whichever occurs last and kept High for entire write cycles including WE write suspend. The actual write data latching starts on the appropriate clock edge with respect to Valid Clock Edge, Read Latency, and Burst Length. During WE Write suspend, WAIT output does not indicate data bus status but carries the same level from previous clock cycle (kept High) except for write suspend on the final data input. If final write data input is suspended, WAIT output becomes high impedance after specified time duration from WE = H. The burst operation is always started after fixed latency with respect to Read Latency set in CR. When the device is operating in asynchronous mode, WAIT output is always in High Impedance. 11 MB82DBS02163C-70L • Latency Read Latency (RL) is the number of clock cycles between the address being latched and first read data becoming available during synchronous burst read operation. It is set through CR set sequence after power-up. Once specific RL is set through CR set sequence, write latency, that is the number of clock cycles between address being latched and first write data being latched, is automatically set to RL-1. The burst operation is always started after fixed latency with respect to Read Latency set in CR. CLK 0 Address 1 2 3 4 5 6 Valid address ADV CE1 OE or WE RL = 3 DQ [Output] Q1 High-Z D1 High-Z RL = 4 D2 Q2 Q3 Q4 Q5 WAIT DQ [Input] WAIT D3 D4 D5 D6 DQ [Output] WAIT High-Z D1 High-Z RL = 5 DQ [Output] WAIT High-Z Q1 Q2 Q3 Q4 DQ [Input] WAIT D2 D3 D4 D5 Q1 Q2 Q3 DQ [Input] WAIT High-Z D1 D2 D3 D4 12 MB82DBS02163C-70L • Address Latch by ADV The ADV latches valid address presence on address inputs. During synchronous burst read/write operation mode, all the address are determined on the rising edge of ADV when CE1 = L. The specified minimum value of ADV = L setup time and hold time against valid edge of clock where RL count is begun must be satisfied. Valid address must be determined with specified setup time against either the falling edge of ADV or falling edge of CE1 whichever comes late. And the determined valid address must not be changed during ADV = L period. • Burst Length Burst Length is the number of word to be read or written during synchronous burst read/write operation as the result of a single address latch cycle. It can be set on 8,16 words boundary or continuous for entire address through CR set sequence. The burst type is sequential that is incremental decoding scheme within a boundary address. Starting from initial address being latched, device internal address counter assigns +1 to the previous address until reaching the end of boundary address and then wrap round to least significant address (= 0). After completing read data output or write data latch for the set burst length, operation automatically ended except for continuous burst length. When continuous burst length is set, read/write is endless unless it is terminated by the rising edge of CE1. During continuous burst read, an additional output delay may occur when a burst sequence cross it's device-row boundary. This is the case when A0 to A6 of starting address is either 7Dh, 7Eh, or 7Fh as shown in the following table. The WAIT signal indicates this delay. Start Address (A6 to A0) 00h 01h 02h 03h ... 7Ch 7Dh 7Eh 7Fh BL = 8 00-01-02-...-06-07 01-02-03-...-07-00 02-03-...-07-00-01 03-...-07-00-01-02 ... 7C-...-7F-78-...-7B 7D-7E-7F-78-...-7C 7E-7F-78-79-...-7D 7F-78-79-7A-...-7E Read Address Sequence BL = 16 00-01-02-...-0E-0F 01-02-03-...-0F-00 02-03-...-0F-00-01 03-...-0F-00-01-02 ... 7C-...-7F-70-...-7B 7D-7E-7F-70-...-7C 7E-7F-70-71-...-7D 7F-70-71-72-...-7E Continuous 00-01-02-03-04-... 01-02-03-04-05-... 02-03-04-05-06-... 03-04-05-06-07-... ... 7C-7D-7E-7F-80-81-... 7D-7E-7F-WAIT-80-81-... 7E-7F-WAIT-WAIT-80-81-... 7F-WAIT-WAIT-WAIT-80-81 Note : Read address in Hexadecimal • Single Write Single write is synchronous write operation with Burst Length = 1. The device can be configured either to "Burst Read & Single Write" or to "Burst Read & Burst Write" through CR set sequence. Once the device is configured to "Burst Read & Single Write" mode, the burst length for synchronous write operation is always fixed 1 regardless of BL values set in CR, while burst length for read is in accordance with BL values set in CR. 13 MB82DBS02163C-70L • Write control The device has two types of WE signal control method, "WE Level Control" and "WE Single Clock Pulse Control", for synchronous burst write operation. It is configured through CR set sequence. CLK 0 Address 1 2 3 4 5 6 Valid address RL = 5 ADV CE1 WE Level Control WE tWLD DQ [Input] D1 tWLTH High-Z D2 D3 D4 WAIT WE Single Clock Pulse Control WE tWSCK tCKWH DQ [Input] WAIT tCLTH tWLTH High-Z D1 D2 D3 D4 14 MB82DBS02163C-70L • Burst Read Suspend Burst read operation can be suspended by OE High pulse. During burst read operation, OE brought to High from Low suspends burst read operation. Once OE is brought to High with the specified setup time against clock where the data being suspended, the device internal counter is suspended, and the data output becomes high impedance after specified time duration. It is inhibited to suspend the first data output at the beginning of burst read. OE brought to Low from High resumes burst read operation. Once OE is brought to Low, data output becomes valid after specified time duration, and internal address counter is reactivated. The last data output being suspended as the result of OE = H and first data output as the result of OE = L are from the same address. In order to guarantee to output last data before suspension and first data after resumption, the specified minimum value of OE hold time and setup time against clock edge must be satisfied respectively. CLK tCKOH tOSCK OE tCKOH tOSCK tAC DQ tCKTV WAIT Q1 tCKQX tOHZ Q2 tOLZ tAC Q2 tAC Q3 tAC Q4 tCKQX tCKQX • Burst Write Suspend Burst write operation can be suspended by WE High pulse. During burst write operation, WE brought to High from Low suspends burst write operation. Once WE is brought to High with the specified setup time against clock where the data being suspended, device internal counter is suspended, data input is ignored. It is inhibited to suspend the first data input at the beginning of burst write. WE brought to Low from High resumes burst write operation. Once WE is brought to Low, data input becomes valid after specified time duration, and internal address counter is reactivated. The write address of the cycle where data being suspended and the first write address as the result of WE = L are the same address. In order to guarantee to latch the last data input before suspension and first data input after resumption, the specified minimum value of WE hold time and setup time against clock edge must be satisfied respectively. Burst write suspend function is available when the device is operating in WE level controlled burst write only. CLK tCKWH tWSCK WE tCKWH tWSCK tDSCK DQ D1 tDHCK WAIT High D2 tDSCK D2 tDSCK D3 tDSCK D4 tDHCK tDHCK 15 MB82DBS02163C-70L • Burst Read Termination Burst read operation can be terminated by CE1 brought to High. If BL is set on Continuous, burst read operation is continued endless unless terminated by CE1 = H. It is inhibited to terminate burst read before first data output is completed. In order to guarantee last data output, the specified minimum value of CE1 = L hold time from clock edge must be satisfied. After termination, the specified minimum recovery time is required to start new access. CLK Address Valid address tTRB tCKCLH tCHZ tOHZ ADV CE1 tCKOH OE WAIT DQ Q1 tCHTZ tCKQX Q2 High-Z tAC • Burst Write Termination Burst write operation can be terminated by CE1 brought to High. If BL is set on Continuous, burst write operation is continued endless unless terminated by CE1 = H. It is inhibited to terminate burst write before first data input is completed. In order to guarantee last data input being latched, the specified minimum values of CE1 = L hold time from clock edge must be satisfied. After termination, the specified minimum recovery time is required to start new access. CLK Address Valid address tTRB tCKCLH tCHCK ADV CE1 tCKWH WE WAIT DQ tDSCK D1 tDHCK tDSCK D2 tDHCK tCHTZ High-Z 16 MB82DBS02163C-70L ■ ABSOLUTE MAXIMUM RATINGS Parameter Voltage of VDD Supply Relative to VSS * Voltage at Any Pin Relative to VSS * Short Circuit Output Current * Storage Temperature * : All voltages are referenced to VSS = 0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Symbol VDD VIN, VOUT IOUT TSTG Rating Min − 0.5 − 0.5 − 50 − 55 Max + 3.6 + 3.6 + 50 + 125 Unit V V mA °C ■ RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage*1 High Level Input Voltage* * Ambient Temperature *1 : All voltages are referenced to VSS = 0 V. *2 : Maximum DC voltage on input and I/O pins is VDD + 0.2 V. During voltage transitions, inputs may overshoot to VDD + 1.0 V for the periods of up to 5 ns. *3 : Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, inputs may undershoot VSS to -1.0 V for the periods of up to 5 ns. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 1, 2 Symbol VDD VSS VIH VIL TA Value Min 1.65 0 VDD × 0.8 − 0.3 − 30 Max 1.95 0 VDD + 0.2 VDD × 0.2 + 85 Unit V V V V °C Low Level Input Voltage*1, *3 ■ PACKAGE CAPACITANCE (f = 1 MHz, TA = +25 °C) Parameter Address Input Capacitance Control Input Capacitance Data Input/Output Capacitance Symbol CIN1 CIN2 CI/O Test conditions VIN = 0 V VIN = 0 V VIO = 0 V Value Min ⎯ ⎯ ⎯ Typ ⎯ ⎯ ⎯ Max 5 5 8 Unit pF pF pF 17 MB82DBS02163C-70L ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level VDD Power Down Current Symbol ILI ILO VOH VOL IDDPS IDDP4 IDDP8 IDDS (At recommended operating conditions unless otherwise noted) Value Test Conditions Unit Min Max VSS ≤ VIN ≤ VDD 0 V ≤ VOUT ≤ VDD, Output Disable VDD = VDD (Min), IOH = −0.5 mA IOL = 1 mA VDD = VDD (Max), VIN = VIH or VIL, CE2 ≤ 0.2 V SLEEP 4 M-bit Partial 8 M-bit Partial −1.0 −1.0 1.4 ⎯ ⎯ ⎯ ⎯ ⎯ +1.0 +1.0 ⎯ 0.4 10 40 50 1.5 µA µA V V µA µA µA mA VDD = VDD (Max), VIN (including CLK) = VIH or VIL, CE1 = CE2 = VIH VDD = VDD (Max), VIN (including CLK) ≤ 0.2 V or VIN (including CLK) ≥ VDD − 0.2 V, CE1 = CE2 ≥ VDD − 0.2 V VDD = VDD (Max), tCK = Min VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, CE1 = CE2 ≥ VDD − 0.2 V VDD = VDD (Max), VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA tRC/tWC = Min tRC/tWC = 1 µs VDD Standby Current IDDS1 ⎯ 80 µA IDDS2 IDDA1 VDD Active Current IDDA2 ⎯ ⎯ ⎯ ⎯ 200 30 3 µA mA mA VDD Page Read Current IDDA3 VDD = VDD (Max), VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA, tPRC = Min VDD = VDD (Max), VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, tCK = tCK (Min), BL = Continuous, IOUT = 0 mA 10 mA VDD Burst Access Current IDDA4 ⎯ 15 mA Notes : • All voltages are referenced to VSS = 0 V. • IDD depends on the output termination, load conditions, and AC characteristics. • After power on, initialization following POWER-UP timing is required. DC characteristics are guaranteed after the initialization. 18 MB82DBS02163C-70L 2. AC Characteristics (1) Asynchronous Read Operation (Page mode) (At recommended operating conditions unless otherwise noted) Value Parameter Symbol Unit Notes Min Max Read Cycle Time CE1 Access Time OE Access Time Address Access Time ADV Access Time LB, UB Access Time Page Address Access Time Page Read Cycle Time Output Data Hold Time CE1 Low to Output Low-Z OE Low to Output Low-Z LB, UB Low to Output Low-Z CE1 High to Output High-Z OE High to Output High-Z LB, UB High to Output High-Z Address Setup Time to CE1 Low Address Setup Time to OE Low ADV Low Pulse Width ADV High Pulse Width Address Setup Time to ADV High Address Hold Time from ADV High Address Invalid Time Address Hold Time from CE1 High Address Hold Time from OE High WE High to OE Low Time for Read CE1 High Pulse Width tRC tCE tOE tAA tAV tBA tPAA tPRC tOH tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tASC tASO tVPL tVPH tASV tAHV tAX tCHAH tOHAH tWHOL tCP 70 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 20 5 5 10 0 ⎯ ⎯ ⎯ −5 10 10 15 5 10 ⎯ −5 −5 15 15 1000 70 40 70 70 30 20 1000 ⎯ ⎯ ⎯ ⎯ 14 14 14 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 10 ⎯ ⎯ 1000 ⎯ ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *11 *5, *9 *10 *8 *8 *1, *2 *3 *3 *3, *5 *3 *3 *3, *6 *1, *6, *7 *3 *4 *4 *4 *3 *3 *3 *1 : Maximum value is applicable if CE1 is kept at Low without change of address input of A20 to A3. *2 : Address should not be changed within minimum tRC. *3 : The output load 50 pF with 50 Ω termination to VDD × 0.5 V. *4 : The output load 5 pF without any other load. *5 : Applicable to A20 to A3 when CE1 is kept at Low. *6 : Applicable only to A2, A1 and A0 when CE1 is kept at Low for the page address access. (Continued) 19 MB82DBS02163C-70L (Continued) *7 : In case Page Read Cycle is continued with keeping CE1 stays Low, CE1 must be brought to High within 4 µs. In other words, Page Read Cycle must be closed within 4 µs. *8 : tVPL is specified from the falling edge of either CE1 or ADV whichever comes late. The sum of tVPL and tVPH must be equal or greater than tRC for each access. *9 : Applicable to address access when at least two of address inputs are switched from previous state. *10 : tRC (Min) and tPRC (Min) must be satisfied. *11 : If actual value of tWHOL is shorter than specified minimum values, the actual tAA of following Read may become longer by the amount of subtracting actual value from specified minimum value. 20 MB82DBS02163C-70L (2) Asynchronous Write Operation (At recommended operating conditions unless otherwise noted) Value Symbol Unit Notes Min Max tWC tAS tVPL tVPH tASV tAHV tCW tWP tBW tBS tBH tWR tCP tWHP tBHP tDS tDH tOHCL tOES tBWO 70 0 10 15 5 10 45 45 45 −5 −5 0 15 15 15 15 0 −5 0 30 1000 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 1000 1000 ⎯ ⎯ ⎯ ⎯ ⎯ ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *8 *9 *3 *3 *3 *5 *6 *7 *1, *2 *3 *4 *4 Parameter Write Cycle Time Address Setup Time ADV Low Pulse Width ADV High Pulse Width Address Setup Time to ADV High Address Hold Time from ADV High CE1 Write Pulse Width WE Write Pulse Width LB, UB Write Pulse Width LB, UB Byte Mask Setup Time LB, UB Byte Mask Hold Time Write Recovery Time CE1 High Pulse Width WE High Pulse Width LB, UB High Pulse Width Data Setup Time Data Hold Time OE High to CE1 Low Setup Time for Write OE High to Address Setup Time for Write LB and UB Write Pulse Overlap *1 : Maximum value is applicable if CE1 is kept at Low without any address change. *2 : Minimum value must be equal or greater than the sum of write pulse width (tCW, tWP or tBW) and write recovery time (tWR). *3 : Write pulse width is defined from High to Low transition of CE1, WE, LB, or UB, whichever occurs last. *4: tVPL is specified from the falling edge of either CE1 or ADV whichever comes late. The sum of tVPL and tVPH must be equal or greater than tWC for each access. *5: Applicable for byte mask only. Byte mask setup time is defined from the High to Low transition of CE1 or WE whichever occurs last. *6: Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1 or WE whichever occurs first. *7: Write recovery time is defined from Low to High transition of CE1, WE, LB, or UB, whichever occurs first. *8: If OE is Low after minimum tOHCL, read cycle is initiated. In other word, OE must be brought to High within 5 ns after CE1 is brought to Low. *9: If OE is Low after new address input, read cycle is initiated. In other word, OE must be brought to High at the same time or before new address is valid. 21 MB82DBS02163C-70L (3) Synchronous Operation - Clock Input (Burst mode) (At recommended operating conditions unless otherwise noted) Value Parameter Symbol Unit Notes Min Max RL = 5 Clock Period Clock High Pulse Width Clock Low Pulse Width Clock Transition Time RL = 4 RL = 3 tCKH tCKL tCKT tCK 15 20 30 5 5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 3 ns ns ns ns ns ns *2 *1 *1 *1 *1: Clock period is defined between valid clock edges. *2: Clock transition time is defined between VIH (Min) and VIL (Max) (4) Synchronous Operation - Address Latch (Burst mode) (At recommended operating conditions unless otherwise noted) Value Parameter Symbol Unit Notes Min Max Address Setup Time to CE1 Low Address Setup Time to ADV Low Address Hold Time from ADV High ADV Low Pulse Width ADV Low Setup Time to CLK CE1 Low Setup Time to CLK ADV Low Hold Time from CLK Burst End ADV High Hold Time from CLK tASCL tASVL tAHV tVPL tVSCK tCLCK tCKVH tVHVL −5 −5 10 10 7 7 1 15 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns ns ns ns ns ns ns ns *3 *4 *4 *4 *1 *2 *1: tASCL is applicable if CE1 is brought to Low after ADV is brought to Low. *2: tASVL is applicable if ADV is brought to Low after CE1 is brought to Low. *3: tVPL is specified from the falling edge of either CE1 or ADV whichever comes late. *4: Applicable to the 1st valid clock edge. 22 MB82DBS02163C-70L (5) Synchronous Read Operation (Burst mode) (At recommended operating conditions unless otherwise noted) Value Parameter Symbol Unit Notes Min Max Burst Read Cycle Time CLK Access Time Output Hold Time from CLK CE1 Low to WAIT Low OE Low to WAIT Low CLK to WAIT Valid Time WAIT Valid Hold Time from CLK CE1 Low to Output Low-Z OE Low to Output Low-Z LB, UB Low to Output Low-Z CE1 High to Output High-Z OE High to Output High-Z LB, UB High to Output High-Z CE1 High to WAIT High-Z OE High to WAIT High-Z OE Low Setup Time to 1st Data-output LB, UB Setup Time to 1st Data-output OE Setup Time to CLK OE Hold Time from CLK Burst End CE1 Low Hold Time from CLK Burst End LB, UB Hold Time from CLK Burst Terminate Recovery Time BL = 8, 16 BL = Continuous tRCB tAC tCKQX tCLTL tOLTL tCKTV tCKTX tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tCHTZ tOHTZ tOLQ tBLQ tOSCK tCKOH tCKCLH tCKBH tTRB ⎯ ⎯ 3 5 0 ⎯ 3 5 10 0 ⎯ ⎯ ⎯ ⎯ ⎯ 30 30 5 5 5 5 30 70 8000 12 ⎯ 20 20 12 ⎯ ⎯ ⎯ ⎯ 14 14 14 20 20 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *6 *6 *5 *1 *1 *1 *1, *2 *1, *3 *1 *4 *4 *4 *1 *1 *1 *1 *1 *1: The output load 50 pF with 50 Ω termination to VDD × 0.5 V. *2: WAIT drives High at the beginning depending on OE falling edge timing. *3: tCKTV is guaranteed after tOLTL (Max) from OE falling edge and tOSCK must be satisfied. *4: The output load 5 pF without any other load. *5: Once LB and UB are determined, they must not be changed until the end of burst read. *6: Defined from the Low to High transition of CE1 to the High to Low transition of either ADV or CE1 whichever occurs late. 23 MB82DBS02163C-70L (6) Synchronous Write Operation (Burst mode) (At recommended operating conditions unless otherwise noted) Value Parameter Symbol Unit Notes Min Max Burst Write Cycle Time Data Setup Time to CLK Data Hold Time from CLK WE Low Setup Time to 1st Data Input LB, UB Setup Time for Write WE Setup Time to CLK WE Hold Time from CLK CE1 Low to WAIT High WE Low to WAIT High CE1 High to WAIT High-Z WE High to WAIT High-Z Burst End CE1 Low Hold Time from CLK Burst End CE1 High Setup Time to next CLK Burst End LB, UB Hold Time from CLK Burst Write Recovery Time Burst Terminate Recovery Time BL = 8, 16 BL = Continuous tWCB tDSCK tDHCK tWLD tBS tWSCK tCKWH tCLTH tWLTH tCHTZ tWHTZ tCKCLH tCHCK tCKBH tWRB tTRB ⎯ 7 3 30 -5 5 5 5 0 ⎯ ⎯ 5 5 5 30 30 70 8000 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 20 20 20 20 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *3 *4 *4 *2 *2 *2 *2 *1 *1: Defined from the valid input edge to the High to Low transition of either ADV, CE1, or WE, whichever occurs last. And once LB, UB are determined, LB, UB must not be changed until the end of burst write. *2: The output load 50 pF with 50 Ω termination to VDD × 0.5 V. *3: Defined from the valid clock edge where last data-input being latched at the end of burst write to the High to Low transition of either ADV or CE1 whichever occurs late for the next access. *4: Defined from the Low to High transition of CE1 to the High to Low transition of either ADV or CE1 whichever occurs late for the next access. 24 MB82DBS02163C-70L (7) Power Down Parameters (At recommended operating conditions unless otherwise noted) Value Symbol Unit Notes Min Max tCSP tC2LP tCHH tCHHP tCHS 20 70 300 70 0 ⎯ ⎯ ⎯ ⎯ ⎯ ns ns µs ns ns *1 *2 *1 Parameter CE2 Low Setup Time for Power Down Entry CE2 Low Hold Time after Power Down Entry CE1 High Hold Time following CE2 High after Power Down Exit [Sleep mode only] CE1 High Hold Time following CE2 High after Power Down Exit [not in Sleep mode] CE1 High Setup Time following CE2 High after Power Down Exit *1 : Applicable also to power-up. *2 : Applicable when 4 M-bit and 8 M-bit Partial mode is set. (8) Other Timing Parameters (At recommended operating conditions unless otherwise noted) Value Symbol Unit Notes Min Max tCHOX tCHWX tC2LH tCHH tT 10 10 50 300 1 ⎯ ⎯ ⎯ ⎯ 25 ns ns µs µs ns *2, *3 *1 Parameter CE1 High to OE Invalid Time for Standby Entry CE1 High to WE Invalid Time for Standby Entry CE2 Low Hold Time after Power-up CE1 High Hold Time following CE2 High after Power-up Input Transition Time (except for CLK) *1 : Some data might be written into any address location if tCHWX (Min) is not satisfied. *2 : Except for clock input transition time. *3 : The Input Transition Time (tT) at AC testing is 5 ns for Asynchronous operation and 3 ns for Synchronous operation respectively. If actual tT is longer than 5 ns or 3 ns specified as AC test condition, it may violate AC specification of some timing parameters. Refer to " (9) AC Test Conditions". 25 MB82DBS02163C-70L (9) AC Test Conditions Description Input High Level Input Low Level Input Timing Measurement Level Input Transition Time Async. Sync. Symbol VIH VIL VREF tT Test Setup ⎯ ⎯ ⎯ Between VIL and VIH Value VDD × 0.8 VDD × 0.2 VDD × 0.5 5 3 Unit V V V ns ns Notes • AC MEASUREMENT OUTPUT LOAD CIRCUIT VDD 0.5 V VDD 0.1 µF VSS 50 Device under Test 50 pF Output 26 MB82DBS02163C-70L ■ TIMING DIAGRAMS (1) Asynchronous Read Timing #1-1 (Basic Timing) tRC Address Address Valid ADV Low tASC tCHAH tASC tCE CE1 tOE tCP tCHZ OE tOHZ tBA LB, UB tBLZ tOLZ tOH tBHZ DQ (Output) Valid Data Output Note : This timing diagram assumes CE2 = H and WE = H. 27 MB82DBS02163C-70L (2) Asynchronous Read Timing #1-2 (Basic Timing) tRC Address Address Valid tASV tAV tAHV ADV tVPH tVPL tCE tASC CE1 tASC tOE tCP tCHZ OE tOHZ tBA LB, UB tBLZ tOLZ tBHZ DQ (Output) tOH Valid Data Output Note : This timing diagram assumes CE2 = H and WE = H. 28 MB82DBS02163C-70L (3) Asynchronous Read Timing #2 (OE Control & Address Access) tRC tAX tRC Address Address Valid Address Valid tAA tOHAH tAA CE1 Low tASO tOE OE LB, UB tOHZ tOLZ tOH Valid Data Output tOH Valid Data Output DQ (Output) Note : This timing diagram assumes CE2 = H, ADV = L and WE = H. 29 MB82DBS02163C-70L (4) Asynchronous Read Timing #3 (LB, UB Byte Control Access) tAX tRC tAX Address tAA Address Valid CE1, OE Low tBA tBA LB tBA UB tBHZ tBLZ tOH tBLZ tBHZ tOH DQ8 to DQ1 (Output) Valid Data Output tBLZ Valid Data Output tBHZ tOH DQ16 to DQ9 (Output) Valid Data Output Note : This timing diagram assumes CE2 = H, ADV = L and WE = H. 30 MB82DBS02163C-70L (5) Asynchronous Read Timing #4 (Page Address Access after CE1 Control Access) tRC Address (A20 to A3) tRC Address Valid tPRC Address Valid tPRC Address Valid tPRC Address Valid Address (A2 to A0) tASC Address Valid tPAA tPAA tPAA tCHAH ADV CE1 tCE tCHZ OE LB, UB tCLZ tOH tOH tOH tOH DQ (Output) Valid Data Output (Normal Access) Note : This timing diagram assumes CE2 = H and WE = H. Valid Data Output (Page Access) 31 MB82DBS02163C-70L (6) Asynchronous Read Timing #5 (Random and Page Address Access) tRC tAX tRC tAX Address (A20 to A3) tRC Address Valid tPRC Address Valid Address Valid tRC Address Valid tPRC Address Valid Address (A2 to A0) Address Valid tAA tPAA tAA tPAA CE1 LOW tASO tOE OE tBA LB, UB tOLZ tOH tOH tOH tOH DQ tBLZ (Output) Valid Data Output (Normal Access) Valid Data Output (Page Access) Notes : • This timing diagram assumes CE2 = H, ADV = L and WE = H. • Either or both LB and UB must be Low when both CE1 and OE are Low. 32 MB82DBS02163C-70L (7) Asynchronous Write Timing #1-1 (Basic Timing) tWC Address Address Valid ADV Low tAS tCW tWR tAS CE1 tAS tWP tWR tCP tAS WE tAS tBW tWR tWHP tAS LB, UB tOHCL tBHP OE tDS tDH (Input) Valid Data Input DQ Note : This timing diagram assumes CE2 = H. 33 MB82DBS02163C-70L (8) Asynchronous Write Timing #1-2 (Basic Timing) tWC Address Address Valid tASV tAHV tVPL tVPH tWR tAS ADV tAS tCW CE1 tAS tWP tWR tCP tAS WE tAS tBW tWR tWHP tAS LB, UB tOHCL tBHP OE tDS tDH DQ (Input) Valid Data Input Note : This timing diagram assumes CE2 = H. 34 MB82DBS02163C-70L (9) Asynchronous Write Timing #2 (WE Control) tWC tWC Address Address Valid Address Valid tOHAH CE1 Low tAS tWP tWR tAS tWP tWR WE tWHP LB, UB tOES OE tOHZ tDS tDH tDS tDH DQ (Input) Valid Data Input Valid Data Input Note : This timing diagram assumes CE2 = H and ADV = L. 35 MB82DBS02163C-70L (10) Asynchronous Write Timing #3-1 (WE, LB, UB Byte Write Control) tWC tWC Address Address Valid Address Valid CE1 Low tAS tWP tAS tWP WE tWR tWHP tBS tBH LB tBS tBH tWR UB tDS tDH DQ8 to DQ1 (Input) tDS tDH DQ16 to DQ9 (Input) Valid Data Input Valid Data Input Note : This timing diagram assumes CE2 = H, ADV = L and OE = H. 36 MB82DBS02163C-70L (11) Asynchronous Write Timing #3-2 (WE, LB, UB Byte Write Control) tWC tWC Address Address Valid Address Valid CE1 Low tWR tWR WE tAS tBW tWHP tBS tBH LB tBH tAS tBW tBS UB tDS tDH DQ8 to DQ1 (Input) tDS tDH DQ16 to DQ9 (Input) Valid Data Input Valid Data Input Note : This timing diagram assumes CE2 = H, ADV = L and OE = H. 37 MB82DBS02163C-70L (12) Asynchronous Write Timing #3-3 (WE, LB, UB Byte Write Control) tWC tWC Address Address Valid Address Valid CE1 Low WE tAS tBW tWR tWHP tBS tBH LB tBS tBH tAS tBW tWR UB tDS tDH DQ8 to DQ1 (Input) tDS tDH DQ16 to DQ9 (Input) Valid Data Input Valid Data Input Note : This timing diagram assumes CE2 = H, ADV = L and OE = H. 38 MB82DBS02163C-70L (13) Asynchronous Write Timing #3-4 (WE, LB, UB Byte Write Control) tWC tWC Address Address Valid Address Valid CE1 Low WE tAS tBW tWR tBHP tBWO tDS tDH tDS tDH tAS tBW tWR LB DQ8 to DQ1 (Input) tAS Valid Data Input tBW tWR tBHP tDS tDH tAS tBW Valid Data Input tBWO tWR UB tDS tDH DQ16 to DQ9 (Input) Valid Data Input Valid Data Input Note : This timing diagram assumes CE2 = H, ADV = L and OE = H. 39 MB82DBS02163C-70L (14) Asynchronous Read/Write Timing #1-1 (CE1 Control) tWC tRC Address tCHAH CE1 tCP tAS Write Address tWR tCW tASC Read Address tCHAH tCE tCP WE LB, UB tOHCL OE tCHZ tOH DQ tDS tDH tCLZ tOH Read Data Output Write Data Input Read Data Output Notes : • This timing diagram assumes CE2 = H and ADV = L • Write address is valid from either CE1 or WE of last falling edge. 40 MB82DBS02163C-70L (15) Asynchronous Read/Write Timing #1-2 (CE1, WE, OE Control) tWC tRC Address tCHAH CE1 tCP tAS Write Address tWR tASC Read Address tCHAH tCE tCP tWP WE LB, UB tOHCL OE tCHZ tOH DQ tDS tDH tOLZ tOH tOE Read Data Output Write Data Input Read Data Output Notes : • This timing diagram assumes CE2 = H and ADV = L. • OE can be fixed Low during write operation if it is CE1 controlled write at Read-Write-Read sequence. 41 MB82DBS02163C-70L (16) Asynchronous Read/Write Timing #2 (OE, WE Control) tWC tRC Address Write Address Read Address tAA tOHAH CE1 Low tAS WE tOES tWP tWR tOHAH LB, UB tASO OE tOHZ tOH DQ tDS tDH tWHOL tOLZ tOH tOHZ tOE Read Data Output Write Data Input Read Data Output Notes : • This timing diagram assumes CE2 = H and ADV = L. • CE1 can be tied to Low for WE and OE controlled operation. 42 MB82DBS02163C-70L (17) Asynchronous Read/Write Timing #3 (OE, WE, LB, UB Control) tWC tRC Address Write Address Read Address tAA tOHAH CE1 Low tOHAH WE tOES LB, UB tBHZ tASO tAS tBW tWR tBA OE tOH DQ tDS tDH tWHOL tBHZ tBLZ tOH Read Data Output Write Data Input Read Data Output Notes : • This timing diagram assumes CE2 = H and ADV = L. • CE1 can be tied to Low for WE and OE controlled operation. 43 MB82DBS02163C-70L (18) Clock Input Timing tCK CLK tCK tCKH tCKL tCKT tCKT Notes : • Stable clock input must be required during CE1 = L. • tCK is defined between valid clock edges. • tCKT is defined between VIH (Min) and VIL (Max) (19) Address Latch Timing (Synchronous Mode) Case #1 CLK Case #2 Address tASCL tVSCK Valid tAHV tCKVH tASVL tVSCK Valid tAHV tCKVH ADV tVPL tVPL tCLCK CE1 Low Notes : • Case #1 is the timing when CE1 is brought to Low after ADV is brought to Low. Case #2 is the timing when ADV is brought to Low after CE1 is brought to Low. • tVPL is specified from the falling edge of either CE1 or ADV whichever comes late. At least one valid clock edge must be input during ADV = L. • tVSCK and tCLCK are applied to the 1st valid clock edge during ADV=L. 44 MB82DBS02163C-70L (20) Synchronous Read Timing #1 (OE Control) RL = 5 CLK tRCB Address tASVL Address Valid Address Valid tAHV tVSCK tCKVH tASVL tVSCK tCKVH ADV tVPL tASCL tVHVL tASCL tVPL CE1 tCLCK tCKOH tCP tCLCK OE tOLQ WE High tCKBH tBLQ LB, UB tCKTV tCKTV tOHTZ WAIT High-Z tOLTL tCKTX tAC tAC tAC tCKTX tOHZ DQ High-Z tOLZ Q1 tCKQX QBL tCKQX Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16. 45 MB82DBS02163C-70L (21) Synchronous Read Timing #2 (CE1 Control) RL = 5 CLK tRCB Address tASVL Address Valid Address Valid tAHV tVSCK tCKVH tVPL tASVL tAHV tVSCK tCKVH ADV tVHVL tVPL tASCL tCP tCLCK tCKCLH tCLCK tASCL CE1 OE WE High tCKBH LB, UB tCKTV tCKTV tCHTZ tCLTL WAIT tCLTL tCKTX tAC tAC tAC tCKTX tCLZ tCHZ DQ tCLZ Q1 tCKQX QBL tCKQX Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16. 46 MB82DBS02163C-70L (22) Synchronous Read Timing #3 (ADV Control) RL = 5 CLK tRCB Address tASVL Address Valid tAHV tVSCK tCKVH tASVL Address Valid tAHV tVSCK tCKVH ADV tVPL tVHVL tVPL CE1 Low OE Low WE High LB, UB tCKTV tCKTV WAIT tCKTX tAC tAC tAC tCKTX DQ Q1 tCKQX QBL tCKQX Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16. 47 MB82DBS02163C-70L (23) Synchronous Read - WAIT Output Timing (Continuous Read) RL = 5 CLK Address tASVL XXX7Fh tAHV tVSCK tCKVH tVPL tASCL ADV CE1 tCLCK OE tOLQ WE High LB,UB tBLQ tCKTV tCKTV tCKTV WAIT High-Z tCKTX tOLTL tCKTX tAC tCKTX tAC tAC tAC DQ High-Z tOLZ Q1 tCKQX Q2 tCKQX Q3 tCKQX Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = Continuous. 48 MB82DBS02163C-70L (24) Synchronous Write Timing #1 (WE Level Control) RL = 5 CLK tWCB Address tASVL Address Valid Address Valid tAHV tVSCK tCKVH tVPL tWRB tASVL tVSCK tAHV tCKVH tVPL tCLCK ADV tASCL tASCL tCP CE1 tCLCK OE High tCKWH tWLD WE tBS tCKBH tBS LB, UB WAIT High-Z tWLTH tDSCK tDSCK tDSCK tWHTZ DQ D1 tDHCK D2 DBL tDHCK Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16. 49 MB82DBS02163C-70L (25) Synchronous Write Timing #2 (WE Single Clock Pulse Timing) RL = 5 CLK tWCB Address tASVL Address Valid Address Valid tAHV tVSCK tCKVH tVPL tASVL tVSCK tAHV tCKVH ADV tWRB tASCL tASCL tVPL tCLCK CE1 tCLCK tCKCLH tCP OE High tWSCK tCKWH tWSCK tCKWH WE tBS tCKBH tBS LB, UB WAIT High-Z tWLTH tDSCK tDSCK tDSCK tCHTZ tWLTH DQ D1 tDHCK D2 DBL tDHCK Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16. 50 MB82DBS02163C-70L (26) Synchronous Write Timing #3 (ADV Control) RL = 5 CLK tWCB Address tASVL Address Valid Address Valid tAHV tVSCK tCKVH tVPL tASVL tVSCK tAHV tCKVH ADV tVPL tWRB CE1 OE High WE tBS tCKBH tBS LB, UB High WAIT tDSCK tDSCK tDSCK DQ D1 tDHCK D2 DBL tDHCK Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16. 51 MB82DBS02163C-70L (27) Synchronous Write Timing #4 (WE Level Control, Single Write) RL = 5 CLK tWCB Address tASVL tVSCK Address Valid Address Valid tAHV tVSCK tCKVH tVPL tWRB tASVL tVSCK tAHV tAHV tCKVH ADV tVPL tCLCK tASCL tASCL CE1 tCLCK tCP OE High tWLD tCKWH WE tBS tCKBH tBS LB, UB WAIT High-Z tWLTH tDSCK tWHTZ tWLTH DQ D1 tDHCK Notes : • This timing diagram assumes CE2 = H, the valid clock edge on rising edge and single write operation. • Write data is latched on the valid clock edge. 52 MB82DBS02163C-70L (28) Synchronous Read to Write Timing #1 (CE1 Control) RL = 5 CLK tWCB Address tASVL Address Valid tAHV tVSCK tCKVH tVPL tCLCK tCKCLH ADV tVHVL CE1 tCKCLH tASCL tCP OE WE tCKBH tBS tCKBH LB,UB tCKTV tCHTZ WAIT tAC tCKTX tCHZ tCLTH tDSCK tDSCK tDSCK tDSCK DQ QBL-1 tCKQX QBL tCKQX D1 tDHCK D2 tDHCK D3 tDHCK DBL tDHCK Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16. 53 MB82DBS02163C-70L (29) Synchronous Read to Write Timing #2 (ADV Control) RL = 5 CLK Address tASVL Address Valid tAHV tVSCK tCKVH ADV tVPL tVHVL CE1 tCKOH OE tWLD tCKWH WE tCKBH tBS tCKBH LB,UB tOHTZ tCKTV WAIT tAC tCKTX tOHZ tWLTH tDSCK tDSCK tDSCK tDSCK DQ QBL-1 tCKQX QBL tCKQX D1 tDHCK D2 tDHCK D3 tDHCK DBL tDHCK Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16. 54 MB82DBS02163C-70L (30) Synchronous Write to Read Timing #1(CE1 Control) RL = 5 CLK tCKT Address tASVL Address Valid tAHV tVSCK tCKVH ADV tVPL tCKCLH tASCL CE1 tCP tWRB tCLCK OE WE tCKBH LB,UB tCKTV WAIT tDSCK tDSCK tCHTZ High-Z tCLTL tCKTX tAC tAC DQ DBL-1 tDHCK DBL tDHCK tCLZ Q1 tCKQX Q2 tCKQX Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16. 55 MB82DBS02163C-70L (31) Synchronous Write to Read Timing #2 (ADV Control) RL = 5 CLK tCKT Address tASVL Address Valid tAHV tVSCK tCKVH ADV tVPL tWRB CE1 Low OE tCKWH tOLQ WE tCKBH tBLQ LB,UB tCKTV WAIT tDSCK tDSCK tWHTZ High-Z tOLTL tCKTX tAC tAC DQ DBL-1 tDHCK DBL tDHCK tOLZ Q1 tCKQX Q2 tCKQX Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16. 56 MB82DBS02163C-70L (32) Power-up Timing #1 CE1 tCHS tC2LH CE2 tCHH VDD 0V VDD (Min) Note : The tC2LH specifies after VDD reaches specified minimum level. (33) Power-up Timing #2 CE1 tCHH CE2 VDD 0V VDD (Min) Note : The tCHH specifies after VDD reaches specified minimum level and applicable both CE1 and CE2. If transition time of VDD (from 0 V to VDD (Min)) is longer than 50 ms, Power-up Timing #1 must be applied. 57 MB82DBS02163C-70L (34) Power Down Entry and Exit Timing CE1 tCHS CE2 tCSP tC2LP High-Z tCHH (tCHHP) DQ Power Down Entry Power Down Mode Power Down Exit Note : This Power Down mode can be also used as a reset timing if “Power-up timing” above could not be satisfied and Power Down program was not performed prior to this reset. (35) Standby Entry Timing after Read or Write CE1 tCHOX tCHWX OE WE Active (Read) Standby Active (Write) Standby Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. 58 MB82DBS02163C-70L (36) Configuration Register Set Timing #1 (Asynchronous Operation) tRC tWC MSB*1 tWC MSB*1 tWC MSB*1 tWC MSB*1 tRC Address MSB*1 Key*2 tCP tCP*3 (tRC) tCP tCP tCP tCP CE1 OE WE LB, UB*4 DQ*3 RDa RDa RDa X X RDb Cycle #1 Cycle #2 Cycle #3 Cycle #4 Cycle #5 Cycle #6 *1 : The all address inputs must be High from Cycle #1 to #5. *2 : The address key must confirm the format specified in “■FUNCTIONAL DESCRIPTION”. If not, the operation and data are not guaranteed. *3 : After tCP or tRC following Cycle #6, the Configuration Register Set is completed and returned to the normal operation. tCP and tRC are applicable to returning to asynchronous mode and to synchronous mode respectively. *4 : Byte read or write is available in addition to Word read or write. At least one byte control signal (LB or UB) need to be Low. 59 MB82DBS02163C-70L (37) Configuration Register Set Timing #2 (Synchronous Operation) CLK Address MSB*1 MSB*1 MSB*1 MSB*1 MSB*1 Key*2 tRCB tWCB tWCB tWCB tWCB tRCB ADV tTRB tTRB tTRB tTRB tTRB * tTRB 3 CE1 OE WE LB,UB* 4 WAIT RL RL-1 RDa RDa RL-1 RDa RL-1 X RL-1 X RL RDb DQ Cycle #1 Cycle #2 Cycle #3 Cycle #4 Cycle #5 Cycle #6 *1 : The all address inputs must be High from Cycle #1 to #5. *2 : The address key must confirm the format specified in “■FUNCTIONAL DESCRIPTION”. If not, the operation and data are not guaranteed. *3 : After tTRB following Cycle #6, the Configuration Register Set is completed and returned to the normal operation. *4 : Byte read or write is available in addition to Word read or write. At least one byte control signal (LB or UB) need to be Low. 60 MB82DBS02163C-70L ■ BONDING PAD INFORMATION Please contact local FUJITSU representative for pad layout and pad coordinate information. ■ ORDERING INFORMATION Part Number MB82DBS02163C-70LWT MB82DBS02163C-70LPBT Shipping Form / Package wafer 71-ball plastic FBGA (BGA-71P-M03) Remarks 61 MB82DBS02163C-70L ■ PACKAGE DIMENSION 71-ball plastic FBGA Ball pitch Package width × package length Lead shape Sealing method Ball size Mounting height 0.80 mm 7.00 × 11.00 mm Soldering ball Plastic mold ∅0.45 mm 1.20 mm Max. 0.14 g (BGA-71P-M03) Weight 71-ball plastic FBGA (BGA-71P-M03) 11.00±0.10(.433±.004) 0.20(.008) S B 1.09 .043 +0.11 –0.10 +.004 –.004 B (Seated height) 0.80(.031) REF A 0.40(.016) REF 0.80(.031) REF 8 7 6 5 4 3 2 1 MLKJHGFEDCBA 7.00±0.10 (.276±.004) 0.40(.016) REF 0.10(.004) S INDEX-MARK AREA S 0.39±0.10 (Stand off) (.015±.004) 0.20(.008) S A 71-ø0.45 +0.10 –0.05 +.004 71-ø.018 –.002 ø0.08(.003) M S AB 0.10(.004) S C 2003 FUJITSU LIMITED B71003S-c-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values. 62 MB82DBS02163C-70L FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Edited Business Promotion Dept. F0604