MB82DBS08164D-70L

FUJITSU MICROELECTRONICS DATA SHEET DS05-11454-1E MEMORY Mobile FCRAMTM CMOS 128 M Bit (8 M word×16 bit) MB82DBS08164D-70L ■ DESCRIPTION Mobile Phone Application Specific Memory The FUJITSU MICROELECTRONICS MB82DBS08164D is a CMOS Fast Cycle Random Access Memory (FCRAM*) with asynchronous Static Random Access Memory (SRAM) interface containing 134,217,728 storages accessible in a 16-bit format. The MB82DBS08164D adopts asynchronous mode and synchronous burst mode for fast memory access as user configurable options. The MB82DBS08164D is suited for mobile applications such as Cellular Handset and PDA. * : FCRAM is a trademark of Fujitsu Microelectronics Limited, Japan ■ FEATURES • Asynchronous SRAM Interface • COSMORAM Revision 3 Compliance (COSMORAM : Common Specifications of Mobile RAM) • Fast Access Time : tCE = 70 ns Max • Burst Read/Write Access Capability : tCK = 13 ns Min /77 MHz Max tAC = 6 ns Max • Low Voltage Operating Condition : VDD = 1.7 V to 1.95 V • Wide Operating Temperature : TA = 0 °C to + 70 °C • Byte Control by LB and UB • Low-Power Consumption : IDDA1 = 35 mA Max IDDS1 = 200 μA Max (TA ≤ + 40 °C) • Various Power Down mode : Sleep 16 M-bit Partial 32 M-bit Partial 64 M-bit Partial Copyright©2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.10 MB82DBS08164D-70L ■ PIN ASSIGNMENT (TOP VIEW) A B C D E F G H J K L M 8 7 6 5 4 3 2 1 NC NC NC NC A11 A8 WE CLK LB A15 A12 A19 CE2 A21 A13 A9 A20 A22 A14 A10 A16 NC DQ6 NC DQ15 VSS DQ7 DQ14 DQ5 NC DQ11 DQ2 DQ8 NC NC NC NC DQ13 DQ12 DQ4 DQ3 VDD VDD DQ10 DQ0 CE1 ADV WAIT UB A6 A3 A18 A5 A2 A17 A4 A1 DQ1 VSS A0 DQ9 OE NC NC NC NC A7 NC NC NC NC (BGA-71P-M03) ■ PIN DESCRIPTION Pin Name A22 to A0 CE1 CE2 WE OE LB UB CLK ADV WAIT DQ7 to DQ0 DQ15 to DQ8 VDD VSS NC 2 Address Input Chip Enable 1 (Low Active) Chip Enable 2(High Active) Write Enable (Low Active) Output Enable (Low Active) Lower Byte Control (Low Active) Upper Byte Control (Low Active) Clock Input Address Valid Input (Low Active) Wait Output Lower Byte Data Input/Output Upper Byte Data Input/Output Power Supply Voltage Ground No Connection DS05-11454-1E Description MB82DBS08164D-70L ■ BLOCK DIAGRAM VDD VSS A22 to A0 ADDRESS LATCH & BUFFER X CONTROLLER Y CONTROLLER MODE CONTROLLER BURST ADDRESS COUNTER MEMORY CELL ARRAY 134,217,728 bits CE2 CE1 ADV WE OE LB UB CLK WAIT DQ15 to DQ8 DQ7 to DQ0 COMMAND DECODER ADDRESS CONTROLLER READ AMP WRITE AMP MEMORY CORE CONTROLLER BURST CONTROLLER BUS CONTROLLER I/O BUFFER DS05-11454-1E 3 MB82DBS08164D-70L ■ FUNCTION TRUTH TABLE 1. Asynchronous Operation Mode Standby (Deselect) Output Disable*1 Output Disable (No Read) Read (Upper Byte) Read (Lower Byte) Read (Word) No Write Write (Upper Byte) Write (Lower Byte) Write (Word) Power Down*2 L X H L CE2 CE1 CLK ADV H H X X X X X X X X X X X X *3 *3 *3 H *3 *3 *3 *3 *3 *3 X X X L H*4 L L L H H L L X H L H L H L X Valid Valid Valid Valid Valid Valid X WE X H OE X H LB X X H H UB A22 to A0 DQ7 to DQ0 DQ15 to DQ8 X X H L X *5 Valid Valid High-Z High-Z High-Z High-Z Output Valid Output Valid Invalid Invalid Input Valid Input Valid High-Z High-Z High-Z High-Z Output Valid High-Z Output Valid Invalid WAIT High-Z High-Z High-Z High-Z High-Z High-Z High-Z Input Valid High-Z Invalid High-Z Input Valid High-Z High-Z High-Z Note : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance *1 : Should not be kept this logic condition longer than 1 μs. *2 : Power Down mode can be entered from Standby state and all output are in High-Z state. Data retention depends on the selection of Partial Size for Power Down Program. Refer to "Power Down" in "■FUNCTIONAL DESCRIPTION" for the details. *3 : "L" for address pass through and "H" for address latch on the rising edge of ADV. *4 : OE can be VIL during write operation if the following conditions are satisfied; (1) Write pulse is initiated by CE1. Refer to "(12) Asynchronous Read/Write Timing 1-1 (CE1 Control)" in "■TIMING DIAGRAMS". (2) OE stays VIL during Write cycle. *5 : Can be either VIL or VIH but must be valid before Read or Write. 4 DS05-11454-1E MB82DBS08164D-70L 2. Synchronous Operation (Burst Mode) Mode Standby(Deselect) Start Address Latch*1 Advance Burst Read to Next Address*1 Burst Read Suspend*1 Advance Burst Write to Next Address*1 Burst Write Suspend* 1 CE2 CE1 H CLK X *3 *3 ADV X L WE X X*4 OE X X*6 L LB X UB A22 to A0 DQ15 to DQ0 X X Valid*8 High-Z High-Z*9 Output Valid*10 High-Z WAIT High-Z Output Invalid Output Valid High*12 High*13 High*12 High-Z High-Z High-Z H H L *3 *3 * 3 H X*7 H L*5 H H* X X H X X X 5 X*7 X Input Valid*11 Input Invalid High-Z High-Z Terminate Burst Read Terminate Burst Write Power Down* 2 X H X X X X L X X High-Z Note : L = VIL, H = VIH, X can be either VIL or VIH, *1 *2 = valid edge, High-Z = High impedance : Should not be kept this logic condition longer than 8 μs. : Power Down mode can be entered from Standby state and all output are in High-Z state. Data retention depends on the selection of Partial Size for Power Down Program. Refer to "Power Down" in “■FUNCTIONAL DESCRIPTION” for the details. : CLK must be started and stable prior to memory access. : Can be VIH for the burst write operation in "WE Level Control" mode but must be VIL for the burst write operation in "WE Single Clock Pulse Control" mode. WE must be VIH for the burst read operation. : When device is operating in "WE Single Clock Pulse Control" mode, WE is a “don't care” once write operation is determined by WE Low Pulse at the beginning of write access together with address latching. Burst write suspend feature is not supported in "WE Single Clock Pulse Control" mode. : Can be VIL for the burst read operation but must be VIH for the burst write operation. : Can be either VIL or VIH. During burst write operation, byte write control by LB and UB can be performed at each clock cycle. During read operation, LB and UB must be valid before read operation is initiated. And once LB and UB input levels are determined, they must not be changed until the end of burst read. : Once a valid address is determined, the input address must not be changed during ADV = L. : If OE = L, data output is either Invalid or High-Z depending on the level of LB and UB input. If WE = L, data input is Invalid. If OE = WE = H, data output is High-Z. *3 *4 *5 *6 *7 *8 *9 *10 : Data output is either Valid or High-Z depending on the level of LB and UB input. *11 : Data input is either Valid or Invalid depending on the level of LB and UB input. *12 : Keep the level from previous cycle except for suspending on last data. Refer to "WAIT Output Function" in "■FUNCTIONAL DESCRIPTION" for the details. *13 : WAIT output is driven in High level during burst write operation. DS05-11454-1E 5 MB82DBS08164D-70L ■ STATE DIAGRAM • Initial/Standby State Asynchronous Operation Power Up CR Verify CR Set @M = 1 @M = 0 Synchronous Operation (Burst Mode) Common State Pause Time Power Down CE2 = H CE2 = H Power Down CE2 = L Standby CE2 Low Pulse @RA = 0 Standby CE2 = L @RA = 1 • Asynchronous Operation Standby CE1 = L & WE = L CE1 = H CE1 = L CE1 = H CE1 = L & OE = L CE1 = H OE = L Output Disable Byte Control Write WE = H WE = L OE = H Address Change or Byte Control Read Byte Control @OE = L • Synchronous Operation Standby CE1 = H CE1 = H CE1 = L & ADV = L & CLK = WE = L CE1 = H CE1 = H Write Suspend Read Suspend WE = H WE = L OE = H OE = L Write * : Assuming WE Level Control Address Latch OE = L Read Note : Assuming all the parameters specified in AC CHARACTERISTICS are satisfied. Refer to the "■ FUNCTION TRUTH TABLE", "■ FUNCTIONAL DESCRIPTION", "2. AC Characteristics" in "■ ELECTRICAL CHARACTERISTICS", and "■TIMING DIAGRAMS" for details. 6 DS05-11454-1E MB82DBS08164D-70L ■ FUNCTIONAL DESCRIPTION This device supports asynchronous read & write operation and synchronous burst read and burst write operations for faster memory access and features four kinds of power down modes for power saving as user configurable option. • Power-up It is required to follow the power-up timing to start executing proper device operation. Refer to "Power-up Timing". After Power-up, the device defaults to asynchronous read & write operation mode with sleep power down feature. • Configuration Register The Configuration Register(CR) is used to configure the type of device function among optional features. Each selection of features is set through CR Set sequence after power-up. If CR Set sequence is not performed after power-up, the device is configured for asynchronous operations with sleep power down feature as default configuration. The content of CR can be confirmed using CR Verify sequence. • CR Set & Verify Sequence The CR Set and CR Verify requires total 6 read/write operations with unique address and data. The device should be in standby mode in the interval between each read/write operation. The following table shows the detail sequence of CR Set and CR Verify. CR Set Operation Read Write Write Write Write Write Data Read Data (RDa) RDa RDa CR Key 0 CR Key 1 CR Key 2 Operation Read Write Write Write Read Read CR Verify Data Read Data (RDa) RDa RDa CR Key 0 CR Key 1 CR Key 2 Cycle # 1st 2nd 3rd 4th 5th 6th Address 7FFFFFh (MSB) 7FFFFFh 7FFFFFh 7FFFFFh 7FFFFFh 7FFFFFh The 1st cycle is to read from most significant address(MSB). The 2nd and 3rd cycles are to write to MSB. If the 2nd or 3rd cycle is written into the different address, the CR Set is cancelled and the data written by the 2nd or 3rd cycle is valid as a normal write operation. It is recommended to write back the data(RDa) read by 1st cycle to MSB in order to secure the data. The 4th cycle is to write the appropriate “CR Key 0” to select the CR Set or CR Verify. The 5th and 6th cycles are to access into MSB to set the “CR Keys” or to verify the “CR Keys”. Refer to the "CR Key Table". If the 4th to 6th cycles are not access into MSB , the CR Set or CR Verify are cancelled and CR input or output data will be invalid. Once this CR Set sequence is performed from an initial CR Set to the other new CR Set, the written data stored in the memory cell array may be lost. Therefore CR Set sequence should be performed prior to regular read/ write operation if necessary to change from the default configuration. DS05-11454-1E 7 MB82DBS08164D-70L • CR Key Table CR Key 0 CR Key 0 should be set at 4th cycle of the CR Set or Verify sequence. Register Pin Name Function Key Name DQ0 DQ7 to DQ1 DQ15 to DQ8 CR Key 1 CR Key 1 should be set or read at 5th cycle of the CR Set or Verify sequence. Register Pin Name Function Key Description Name 00 DQ1, DQ0 PS Partial Size 01 10 11 000, 001 010 011 DQ4 to DQ2 BL Burst Length 100 101 110 111 0 DQ5 M Mode 1 00 DQ7, DQ6 DS Driver Size 01 10 11 DQ15 to DQ8 ⎯ ⎯ 1 32M-bit Partial 16M-bit Partial 64M-bit Partial Sleep [Default] Reserved for future use 8 words 16 words 32 words 64 words 128 words Reserved for future use Synchronous Mode (Burst Read/Write) Asynchronous Mode [Default] (Random Read/Write) + Reserved for future use − Center [Default] Unused bits must be 1 *2 *1 *1 *4 *5 *3 *3 *3 *3 *1 CRSV ⎯ ⎯ CR Set/Verify ⎯ ⎯ 0 1 1 1 CR Verify CR Set Reserved for future use Unused bits must be 1 *1 *2 Description Note Note 8 DS05-11454-1E MB82DBS08164D-70L CR Key 2 CR Key 2 should be set or read at 6th cycle of the CR Set or Verify sequence. Register Pin Name Function Key Description Name 000, 001 010 DQ2 to DQ0 RL Read Latency 011 100 DQ3 DQ4 DQ5 DQ6 ⎯ ⎯ ⎯ RA ⎯ ⎯ ⎯ Reset to Asynchronous 1 0 1 0 1 0 DQ7 WC Write Control 1 DQ15 to DQ8 ⎯ ⎯ 1 Reserved for future use 4 clocks 5 clocks 6 clocks *1 *2 *6 *2 *7 *3 Reserved for future use Reserved for future use Reserved for future use Reset to Asynchronous mode Remain the previous mode WE Single Clock Pulse Control without Write Suspend Function WE Level Control with Write Suspend Function Unused bits must be 1 *2 *1 Note 101 to 111 Reserved for future use *1 : It is prohibited to apply this key. *2 : Must be set to “1”. *3 : Sleep and Partial power down mode are effective only when RA = 1. *4 : If M = 0, all the registers must be set with appropriate Key input at the same time. *5 : If M = 1, PS and DS must be set with appropriate Key input at the same time. Except for PS and DS, all the other key inputs must be “1”. *6 : Must be set to "0". *7 : In case of RA = 0, CE2 brought to Low reset the device to asynchronous standby state regardless PS set value therefore Sleep and Partial power down mode are not available. DS05-11454-1E 9 MB82DBS08164D-70L • Power Down The Power Down is low power idle state controlled by CE2. CE2 Low drives the device in power down mode and maintains low power idle state as long as CE2 is kept Low. CE2 High resumes the device from power down mode. This device has four power down modes, Sleep, 16 M-bit Partial, 32 M-bit Partial, and 64 M-bit Partial. Those power down modes are effective when RA = 1. The selection of power down mode is set through CR Set sequence. Each mode has following data retention features. Mode Sleep [default] 16 M-bit Partial 32 M-bit Partial 64 M-bit Partial Data Retention Size No 16 M bits 32 M bits 64 M bits Retention Address N/A 000000h to 0FFFFFh 000000h to 1FFFFFh 000000h to 3FFFFFh The default state is Sleep and it is the lowest power consumption. However all data will be lost once CE2 is brought to Low for Power Down. It is not required to perform CR Set sequence to set to Sleep mode after powerup in case of asynchronous operation. When RA = 0, CE2 brought to Low reset the device to asynchronous standby state regardless PS set value. • Burst Read/Write Operation Synchronous burst read/write operation provides faster memory access that synchronized to the microcontroller or system bus frequency. Configuration Register(CR) Set is required to perform a burst read & write operation after power-up. Once CR Set sequence is performed to select the synchronous burst mode, the device is configured to synchronous burst read/write operation mode with corresponding RL and BL that is set through CR Set sequence together with the operation mode. 10 DS05-11454-1E MB82DBS08164D-70L • Burst Read Operation CLK Address Valid address ADV CE1 OE WE DQ High RL High-Z Q1 BL WAIT High-Z Q2 QBL • Burst Write Operation CLK Address Valid address ADV CE1 High OE WE RL-1 DQ High-Z D1 BL WAIT High-Z D2 DBL • CLK Input Function The CLK is input signal to synchronize the memory to the microcontroller or system bus frequency during synchronous burst read & write operation. The CLK input increments the device internal address counter and the valid edge of CLK is referred for latency counts from address latch, burst write data latch, and the burst read data output. During synchronous operation mode, CLK input must be supplied except for standby state and power down state. CLK is a “don't care” during asynchronous operation. DS05-11454-1E 11 MB82DBS08164D-70L • ADV Input Function The ADV is input signal to latch the valid address. It is applicable to the synchronous operation as well as asynchronous operation. ADV input is active during CE1 = L and CE1 = H disables ADV input. During synchronous burst read/write operation, ADV = H disables all address inputs. Once ADV is brought to High after the valid address latch, it is inhibited to bring ADV Low until the end of burst or until the burst operation is terminated. ADV Low pulse is mandatory for the synchronous burst read/write operation mode to latch the valid address input. During asynchronous operation, ADV = H also disables all address inputs. ADV can be tied to Low during asynchronous operations and it is not necessary to control ADV to High. • WAIT Output Function The WAIT is output signal to indicate the data bus status when the device is operating in the synchronous burst mode. During burst read operation, WAIT output is enabled after specified time duration from CE1 = L. WAIT output Low indicates data output at next clock cycle is invalid, and WAIT output becomes High one clock cycle prior to valid data output. During OE read suspend, WAIT output doesn’t indicate the data bus status but carries the same level from previous clock cycle (kept High). During burst write operation, WAIT output is enabled after specified time duration from CE1 = L. WAIT output to High level after specified time duration from WE = L or CE1 = L whichever occurs last and kept High for entire write cycles including WE write suspend. The actual write data latching starts on the appropriate clock edge with respect to Read Latency, and Burst Length. During WE write suspend, WAIT output doesn’t indicate the data bus status but carries the same level from previous clock cycle (kept High). This device doesn’t incur additional output delay against internal refresh operation. Therefore, the burst operation is always started after the fixed latency with respect to Read Latency. And there is no waiting cycle asserted in the middle of burst operation except for the burst read or write suspend by OE brought to High or WE brought to High. Thus, once WAIT output is enabled and brought to High, WAIT output keeps High level until the end of burst or until the burst operation is terminated. When the device is operating in the asynchronous mode, WAIT output is always in High Impedance. 12 DS05-11454-1E MB82DBS08164D-70L • Latency Read Latency (RL) is the number of clock cycles between the address being latched and first read data becoming available during synchronous burst read operation. It is set through CR Set sequence after power-up. Once specific RL is set through CR Set sequence, write latency, that is the number of clock cycles between address being latched and first write data being latched, is automatically set to RL-1. The burst operation is always started after the fixed latency with respect to Read Latency set in CR. CLK 0 Address 1 2 3 4 5 6 7 Valid address ADV CE1 OE or WE RL = 4 DQ [Output] WAIT DQ [Input] WAIT High-Z RL = 5 DQ [Output] WAIT DQ [Input] WAIT High-Z RL = 6 DQ [Output] WAIT DQ [Input] WAIT High-Z High-Z D1 D2 D3 Q1 Q2 High-Z D1 D2 D3 D4 Q1 Q2 Q3 High-Z D1 D2 D3 D4 D5 Q1 Q2 Q3 Q4 DS05-11454-1E 13 MB82DBS08164D-70L • Address Latch by ADV The ADV latches the valid address presence on address inputs. During synchronous burst read/write operation mode, all the addresses are determined on first rising edge when ADV = CE1 = L. The specified minimum value of ADV = L setup time and hold time against valid edge of clock where RL count is begun must be satisfied for appropriate RL counts. Valid address must be determined with specified setup time against valid clock edge. And the determined valid address must not be changed during ADV = L period. • Burst Length Burst Length is the number of word to be read or written during synchronous burst read/write operation as the result of a single address latch cycle. It can be set on 8, 16, 32, 64, 128 words boundary for entire address through CR Set sequence. The burst type is sequential that is incremental decoding scheme within a boundary address. Starting from an initial address being latched, the device internal address counter assigns +1 to the previous address until reaching the end of boundary address and then wrap round to least significant address (= 0). After completing read data output or write data latch for the set burst length, operation automatically ended. • Write Control The device has two types of WE signal control method, "WE Level Control" and "WE Single Clock Pulse Control", for synchronous burst write operation. It is configured through CR Set sequence. When device is operating in "WE Single Clock Pulse Control" mode, burst write operation is determined by WE = L at the rising edge of CLK. In case of "WE Level Control", WE can be High at address latching and WE = L enables burst write operation. CLK 0 Address 1 2 3 4 5 6 7 Valid address RL = 5 ADV CE1 WE Level WAIT Control tWLD WE DQ [Input] tWLTH WAIT High-Z D1 D2 D3 D4 WE Single Clock Pulse Control tWSCK WE tCKWH DQ [Input] WAIT High-Z tCLTH tWLTH D1 D2 D3 D4 14 DS05-11454-1E MB82DBS08164D-70L • Burst Read Suspend Burst read operation can be suspended by OE High pulse. During burst read operation, OE brought to High suspends the burst read operation. Once OE is brought to High with the specified setup time against clock where the data being suspended, the device internal counter is suspended, and the data output becomes high impedance after specified time duration. It is inhibited to suspend the first data output at the beginning of burst read. OE brought to Low resumes the burst read operation. Once OE is brought to Low, data output becomes valid after specified time duration, and the internal address counter is reactivated. The last data output being suspended as the result of OE = H and first data output as the result of OE = L are from the same address. In order to guarantee to output last data before suspension and first data after resumption, the specified minimum value of OE = L hold time and setup time against clock edge must be satisfied respectively. CLK tCKOH tOSCK OE tCKOH tOSCK tAC DQ tCKTV WAIT Q1 tCKQX tOHZ Q2 tAC Q2 tAC Q3 tAC Q4 tCKQX tCKQX • Burst Write Suspend Burst write operation can be suspended by WE High pulse. During burst write operation, WE brought to High suspends the burst write operation. Once WE is brought to High with the specified setup time against clock where the data being suspended, the device internal counter is suspended, data input is ignored. It is inhibited to suspend the first data input at the beginning of burst write. WE brought to Low resumes the burst write operations. Once WE is brought to Low, data input becomes valid after specified time duration, and the internal address counter is reactivated. The write address of the cycle where data being suspended and the first write address as the result of WE = L are the same address. In order to guarantee to latch the last data input before suspension and first data input after resumption, the specified minimum value of WE = L hold time and setup time against clock edge must be satisfied respectively. Burst write suspend function is available only when the device is operating in WE level controlled burst write. CLK tCKWH tWSCK WE tCKWH tWSCK tDSCK DQ D1 tDHCK WAIT High D2 tDSCK D2 tDSCK D3 tDSCK D4 tDHCK tDHCK DS05-11454-1E 15 MB82DBS08164D-70L • Burst Read Termination Burst read operation can be terminated by CE1 brought to High. It is inhibited to terminate the burst read before first data output is completed. In order to guarantee last data output, the specified minimum value of CE1 = L hold time from the clock edge must be satisfied. After termination, the specified minimum recovery time is required to start a new access. CLK Address ADV tCKCLH CE1 tCKOH OE WAIT DQ Q1 tAC High-Z Q1 tCKQX tAC tCKQX tOHZ tCP tCHZ Vaild tCHTZ Q2 • Burst Write Termination Burst write operation can be terminated by CE1 brought to High. It is inhibited to terminate the burst write before first data input is completed. In order to guarantee last write data being latched, the specified minimum values of CE1 = L hold time from the clock edge must be satisfied. After termination, the specified minimum recovery time is required to start a new access. CLK Address ADV tCKCLH tCKWH Vaild tCP tCHCK CE1 WE WAIT DQ tDSCK D1 tDSCK D2 tDHCK tCHTZ High-Z tDSCK D1 tDHCK tDHCK 16 DS05-11454-1E MB82DBS08164D-70L ■ ABSOLUTE MAXIMUM RATINGS Parameter Voltage of VDD Supply Relative to VSS * Voltage at Any Pin Relative to VSS * Short Circuit Output Current Storage Temperature * : All voltages are referenced to VSS = 0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Symbol VDD VIN, VOUT IOUT TSTG Rating Min − 0.5 − 0.5 − 50 − 55 Max + 2.3 + 2.3 + 50 + 125 Unit V V mA °C ■ RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage*1 Ground High Level Input Voltage* * Ambient Temperature *1 : All voltages are referenced to VSS = 0 V. *2 : Maximum DC voltage on input and I/O pins is VDD + 0.2 V. During voltage transitions, inputs may overshoot to VDD + 1.0 V for the periods of up to 5 ns. *3 : Minimum DC voltage on input and I/O pins is -0.3 V. During voltage transitions, inputs may undershoot VSS to -1.0 V for the periods of up to 5 ns. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 1, 2 Symbol VDD VSS VIH VIL TA Value Min 1.7 0 VDD × 0.8 − 0.3 0 Max 1.95 0 VDD + 0.2 VDD × 0.2 + 70 Unit V V V V °C Low Level Input Voltage*1, *3 ■ PIN CAPACITANCE (f = 1 MHz, TA = +25 °C) Parameter Address Input Capacitance Control Input Capacitance Data Input/Output Capacitance DS05-11454-1E Symbol CIN1 CIN2 CIO Test conditions VIN = 0 V VIN = 0 V VIO = 0 V Value Min ⎯ ⎯ ⎯ Typ ⎯ ⎯ ⎯ Max 5 5 8 Unit pF pF pF 17 MB82DBS08164D-70L ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level Symbol ILI ILO VOH VOL IDDPS VDD Power Down Current IDDP16 IDDP32 IDDP64 IDDS VDD = VDD (Max), VIN (including CLK) = VIH or VIL, CE1 = CE2 = VIH VDD = VDD (Max), T A ≤ + 70 ° C VIN (including CLK) = VDD or VSS, T A ≤ + 40 ° C CE1 = CE2 = VDD VDD = VDD (Max), tCK = tCK (Min) , VIN = VDD or VSS, CE1 = CE2 = VDD VDD = VDD (Max), VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA tRC/tWC = Min tRC/tWC = 1 μs VDD = VDD (Max), VIN = VDD or VSS, CE2 = VSS (At recommended operating conditions unless otherwise noted) Value Test Conditions Unit Min Max VSS ≤ VIN ≤ VDD 0 V ≤ VOUT ≤ VDD, Output Disable VDD = VDD (Min), IOH = − 0.5 mA IOL = 1 mA Sleep 16 M-bit Partial 32 M-bit Partial 64 M-bit Partial − 1.0 − 1.0 1.4 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ + 1.0 + 1.0 ⎯ 0.4 10 230 260 310 1.5 400 200 500 35 5 μA μA V V μA μA μA μA mA μA μA μA mA mA VDD Standby Current IDDS1 IDDS2 IDDA1 VDD Active Current IDDA2 VDD Burst Access Current IDDA4 VDD = VDD (Max), VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, tCK = tCK (Min), BL = 128, IOUT = 0 mA 24 mA Notes : • All voltages are referenced to VSS = 0 V. • IDD depends on the output termination, load conditions, and AC characteristics. • After power on, initialization following power-up timing is required. DC characteristics are guaranteed after the initialization. • IDDP16, IDDP32, IDDP64, IDDS and IDDS1 might be higher for up to 400 ms after power-up or power down/standby mode entry. 18 DS05-11454-1E MB82DBS08164D-70L 2. AC Characteristics (1) Asynchronous Read Operation Parameter Read Cycle Time CE1 Access Time OE Access Time Address Access Time ADV Access Time LB, UB Access Time Output Data Hold Time CE1 Low to Output Low-Z OE Low to Output Low-Z LB, UB Low to Output Low-Z CE1 High to Output High-Z OE High to Output High-Z LB, UB High to Output High-Z Address Setup Time to ADV Low Address Setup Time to CE1 Low Address Setup Time to OE Low ADV Low Pulse Width ADV High Pulse Width Address Hold Time from ADV High Address Invalid Time Address Hold Time from CE1 High Address Hold Time from OE High WE High to OE Low Time for Read CE1 High Pulse Width (At recommended operating conditions unless otherwise noted) Value Symbol Unit Notes Min Max tRC tCE tOE tAA tAV tBA tOH tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tASVL tASC tASO tVPL tVPH tAHV tAX tCHAH tOHAH tWHOL tCP 70 ⎯ ⎯ ⎯ ⎯ ⎯ 3 10 10 10 ⎯ ⎯ ⎯ −5 −5 0 7 10 5 ⎯ −5 −5 10 10 1000 70 40 70 70 30 ⎯ ⎯ ⎯ ⎯ 9.5 9.5 9.5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 10 ⎯ ⎯ 1000 ⎯ ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *9 *4, *7 *8 *6 *1, *2 *3 *3 *3, *4 *3 *3 *3 *5 *5 *5 *3 *3 *3 *6 *6 *1 : Maximum value is applicable if CE1 is kept at Low without change of address input. *2 : Address should not be changed within a minimum tRC. *3 : The output load 50 pF with 50 Ω termination to VDD × 0.5 V. *4 : Applicable when CE1 is kept at Low. *5 : The output load 5 pF without any other load. *6 : tVPL is specified from the falling edge of either CE1 or ADV whichever comes late. The sum of actual tVPL and tASVL (or tASC) must be equal or greater than the specified minimum value of tVPL. *7 : Applicable to address access when at least two of address inputs are switched from the previous state. *8 : tRC (Min) must be satisfied. *9 : If actual value of tWHOL is shorter than specified minimum values, the actual tAA of following Read may become longer by the amount of subtracting actual value from specified minimum value. DS05-11454-1E 19 MB82DBS08164D-70L (2) Asynchronous Write Operation (At recommended operating conditions unless otherwise noted) Value Symbol Unit Notes Min Max tWC tASVL tAS tVPL tVPH tAHV tCW tWP tBW tBS tBH tWR tCP tWHP tBHP tDS tDH tOHCL tOES 70 −5 0 7 10 5 45 45 45 −5 −5 0 10 10 10 15 0 −5 0 1000 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 1000 1000 ⎯ ⎯ ⎯ ⎯ ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *9 *10 *8 *8 *2, *4 *2, *4 *2, *4 *5 *6 *2, *7 *3 *1, *2 *3 Parameter Write Cycle Time Address Setup Time to ADV Low Address Setup Time ADV Low Pulse Width ADV High Pulse Width Address Hold Time from ADV High CE1 Write Pulse Width WE Write Pulse Width LB, UB Write Pulse Width LB, UB Byte Mask Setup Time LB, UB Byte Mask Hold Time Write Recovery Time CE1 High Pulse Width WE High Pulse Width LB, UB High Pulse Width Data Setup Time Data Hold Time OE High to CE1 Low Setup Time for Write OE High to Address Setup Time for Write *1 : Maximum value is applicable if CE1 is kept at Low without any address change. *2 : The sum of write pulse width (tCW, tWP or tBW) and actual write recovery time (tWR) must be equal or greater than specified minimum tWC. *3 : tVPL is specified from the falling edge of either CE1 or ADV whichever comes late. The sum of actual tVPL and tASVL must be equal or greater than the specified minimum value of tVPL. *4 : Write pulse width is defined from High to Low transition of CE1, WE, LB, or UB, whichever occurs last. *5 : Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1 or WE whichever occurs last. *6 : Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1 or WE whichever occurs first. *7 : Write recovery time is defined from Low to High transition of CE1, WE, LB, or UB, whichever occurs first. *8 : Maximum specification of tWHP and tBHP are applicable to Output Disable mode when CE = L, WE = OE = H after write operation. Refer to “(7) Asynchronous Write Timing 2 (WE Control)” in “ ■ TIMING DIAGRAMS”. *9 : If OE is Low after minimum tOHCL, read cycle is initiated. In other word, OE must be brought to High within 5 ns after CE1 is brought to Low. *10 : If OE is Low after a new address input, read cycle is initiated. In other word, OE must be brought to High at the same time or before a new address becomes valid. 20 DS05-11454-1E MB82DBS08164D-70L (3) Synchronous Operation - Clock Input (Burst Mode) (At recommended operating conditions unless otherwise noted) Value Parameter Symbol Unit Notes Min Max RL = 6 Clock Period Clock High Time Clock Low Time Clock Transition Time RL = 5 RL = 4 tCKH tCKL tCKT tCK 13 15 18 3 3 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 1.5 ns ns ns ns ns ns *2 *1 *1 *1 *1 : Clock period is defined between valid clock edges. *2 : Clock transition time is defined between VIH (Min) and VIL (Max) (4) Synchronous Operation - Address Latch (Burst Mode) (At recommended operating conditions unless otherwise noted) Value Parameter Symbol Unit Notes Min Max Address Setup Time to CLK Address Hold Time from CLK ADV Low Pulse Width ADV Low Setup Time to CLK CE1 Low Setup Time to CLK ADV Low Hold Time from CLK CE1 High Hold Time from CLK *1 : Applicable to the 1st rising clock edge. *2 : tVPL is specified from the falling edge of either CE1 or ADV whichever comes late. *3 : Applicable to the positive clock edge before address latching. RL = 6 RL = 4, 5 RL = 6 RL = 4, 5 tASCK tCKAH tVPL tVSCK tCLCK tCKVH tCKCH 3 1 7 3 5 3 5 1 1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns ns ns ns ns ns ns *1 *1 *2 *1 *1 *1 *3 DS05-11454-1E 21 MB82DBS08164D-70L (5) Synchronous Read Operation (Burst Mode) (At recommended operating conditions unless otherwise noted) Value Parameter Symbol Unit Notes Min Max Burst Read Cycle Time CLK Access Time Output Hold Time from CLK CE1 Low to WAIT Low CLK to WAIT Valid Time WAIT Valid Hold Time from CLK CE1 Low to Output Low-Z OE Low to Output Low-Z LB, UB Low to Output Low-Z CE1 High to Output High-Z OE High to Output High-Z LB, UB High to Output High-Z CE1 High to WAIT High-Z OE Low Setup Time to 1st Data-output LB, UB Setup Time to 1st Data-output OE Setup Time to CLK OE Hold Time from CLK Burst End CE1 Low Hold Time from CLK LB, UB Hold Time from CLK CE1 High Pulse Width RL = 6 RL = 4, 5 tRCB tAC tCKQX tCLTL tCKTV tCKTX tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tCHTZ tOLQ tBLQ tOSCK tCKOH tCKCLH tCKBH tCP ⎯ ⎯ ⎯ 2 5 ⎯ 2 10 10 10 ⎯ ⎯ ⎯ ⎯ 34 26 3 1 1 1 9.5 8000 6 9 ⎯ 15 6 ⎯ ⎯ ⎯ ⎯ 9.5 9.5 9.5 9.5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *4 *1 *1 *1 *1 *1 *1 *2 *2, *3 *2 *1 *1 *1 *1 *1 : The output load 50 pF with 50 Ω termination to VDD × 0.5 V. *2 : The output load 5 pF without any other load. *3 : tOLZ must not be applied after burst read suspend. *4 : Once LB, UB are determined, LB, UB must not be changed until the end of burst read. 22 DS05-11454-1E MB82DBS08164D-70L (6) Synchronous Write Operation (Burst Mode) (At recommended operating conditions unless otherwise noted) Value Parameter Symbol Unit Notes Min Max Burst Write Cycle Time Data Setup Time to CLK Data Hold Time from CLK WE Low Setup Time to 1st Data Input WE Setup Time to CLK WE Hold Time from CLK LB, UB Setup Time to CLK LB, UB Hold Time from CLK CE1 Low to WAIT High WE Low to WAIT High CE1 High to WAIT High-Z Burst End CE1 Low Hold Time from CLK Burst End CE1 High Setup Time to next CLK CE1 High Pulse Width tWCB tDSCK tDHCK tWLD tWSCK tCKWH tBSCK tCKBH tCLTH tWLTH tCHTZ tCKCLH tCHCK tCP ⎯ 3 1 45 3 1 3 1 5 ⎯ ⎯ 1 3 9.5 8000 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 15 15 9.5 ⎯ ⎯ ⎯ ns ns ns ns ns ns ns ns ns ns ns ns ns ns *1 *1 *2, *3 *2, *3 *2 *1 : tBSCK and tCKBH should be satisfied for byte mask control. *2 : The output load 50 pF with 50 Ω termination to VDD × 0.5 V. *3 : WAIT outputs Low-Z after tCLTH (Min) from CE1 = L. WAIT outputs to High level after tWLTH or tCLTH from WE = L or CE1 = L whichever occurs last. DS05-11454-1E 23 MB82DBS08164D-70L (7) Power Down Parameters (At recommended operating conditions unless otherwise noted) Value Symbol Unit Notes Min Max tCSP tC2LP tC2LPR tCHH tCHHP tCHS 10 70 70 300 70 0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns ns ns μs ns ns *1 *2 *3 *2 Parameter CE2 Low Setup Time for Power Down Entry CE2 Low Hold Time after Power Down Entry CE2 Low Hold Time for Reset to Asynchronous Mode CE1 High Hold Time following CE2 High after Power Down Exit [Sleep mode only] CE1 High Hold Time following CE2 High after Power Down Exit [not in Sleep mode] CE1 High Setup Time following CE2 High after Power Down Exit *2 : Applicable also to power-up. *1 : Applicable when RA = 0 (Reset to Asynchronous mode) . *3 : Applicable when Partial Power Down mode and Reset to Asynchronous mode are set. (8) Other Timing Parameters (At recommended operating conditions unless otherwise noted) Value Symbol Unit Notes Min Max tCHOX tCHWX tC2LH tCHH tT 0 0 50 300 1 ⎯ ⎯ ⎯ ⎯ 25 ns ns μs μs ns *2, *3 *1 Parameter CE1 High to OE Invalid Time for Standby Entry CE1 High to WE Invalid Time for Standby Entry CE2 Low Hold Time after Power-up CE1 High Hold Time following CE2 High after Power-up Input Transition Time (except for CLK) *1 : Some data might be written into any address location if tCHWX (Min) is not satisfied. *2 : Except for the CLK input transition time. *3 : The Input Transition Time (tT) at AC testing is 3 ns for Asynchronous operation and 1.5 ns for Synchronous operation respectively. If actual tT is longer than 3 ns or 1.5 ns specified as AC test condition, it may violate AC specification of some timing parameters. Refer to " (9) AC Test Conditions". 24 DS05-11454-1E MB82DBS08164D-70L (9) AC Test Conditions Description Input High Level Input Low Level Input Timing Measurement Level Input Transition Time Async. Sync. Symbol VIH VIL VREF tT Test Setup ⎯ ⎯ ⎯ Between VIL and VIH Value VDD × 0.8 VDD × 0.2 VDD × 0.5 3 1.5 Unit V V V ns ns Notes • AC MEASUREMENT OUTPUT LOAD CIRCUIT VDD 0.5 V VDD 0.1 μF VSS 50 Device under Test 50 pF Output DS05-11454-1E 25 MB82DBS08164D-70L ■ TIMING DIAGRAMS (1) Asynchronous Read Timing 1-1 (Basic Timing) tRC Address Address Valid ADV Low tASC tCHAH tASC tCE CE1 tOE tCP tCHZ OE tOHZ tBA LB, UB tBLZ tOLZ tOH tBHZ DQ (Output) Valid Data Output Note : This timing diagram assumes CE2 = H and WE = H. 26 DS05-11454-1E MB82DBS08164D-70L (2) Asynchronous Read Timing 1-2 (Basic Timing) tRC Address Address Valid tAHV tAV tASVL ADV tASVL tVPL tCE tVPH tASC CE1 tASC tOE tCP tCHZ OE tOHZ tBA LB, UB tBLZ tOLZ tBHZ DQ tCLZ (Output) tOH Valid Data Output Note : This timing diagram assumes CE2 = H and WE = H. DS05-11454-1E 27 MB82DBS08164D-70L (3) Asynchronous Read Timing 2 (OE Control & Address Access) tRC tAX tRC Address Address Valid Address Valid tAA tOHAH tAA CE1 Low tASO tOE OE LB, UB tOHZ tOLZ tOH Valid Data Output tOH Valid Data Output DQ (Output) Note : This timing diagram assumes CE2 = H, ADV = L and WE = H. 28 DS05-11454-1E MB82DBS08164D-70L (4) Asynchronous Read Timing 3 (LB, UB Byte Control Access) tAX tRC tAX Address tAA Address Valid CE1, OE Low tBA tBA LB tBA UB tBHZ tBLZ tOH tBLZ tBHZ tOH DQ7 to DQ0 (Output) Valid Data Output tBLZ Valid Data Output tBHZ tOH DQ15 to DQ8 (Output) Valid Data Output Note : This timing diagram assumes CE2 = H, ADV = L and WE = H. DS05-11454-1E 29 MB82DBS08164D-70L (5) Asynchronous Write Timing 1-1 (Basic Timing) tWC Address Address Valid ADV Low tAS tCW tWR tAS CE1 tAS tWP tWR tCP tAS WE tAS tBW tWR tWHP tAS LB, UB tOHCL tBHP OE tDS tDH (Input) Valid Data Input DQ Note : This timing diagram assumes CE2 = H. 30 DS05-11454-1E MB82DBS08164D-70L (6) Asynchronous Write Timing 1-2 (Basic Timing) tWC Address Address Valid tAHV tASVL tVPH tCW tAS ADV tASVL tAS tVPL CE1 tWP tCP WE tBW tWHP LB, UB tOHCL tBHP OE tDS tDH DQ (Input) Valid Data Input Note : This timing diagram assumes CE2 = H. DS05-11454-1E 31 MB82DBS08164D-70L (7) Asynchronous Write Timing 2 (WE Control) tWC tWC Address Address Valid Address Valid tOHAH CE1 Low tAS tWP tWR tAS tWP tWR WE tWHP LB, UB tOES OE tOHZ tDS tDH tDS tDH DQ (Input) Valid Data Input Valid Data Input Note : This timing diagram assumes CE2 = H and ADV = L. 32 DS05-11454-1E MB82DBS08164D-70L (8) Asynchronous Write Timing 3-1 (WE, LB, UB Byte Write Control) tWC tWC Address Address Valid Address Valid CE1 Low tAS tWP tAS tWP WE tWR tWHP tBS tBH LB tBS tBH tWR UB tDS tDH DQ7 to DQ0 (Input) tDS tDH DQ15 to DQ8 (Input) Valid Data Input Valid Data Input Note : This timing diagram assumes CE2 = H, ADV = L and OE = H. DS05-11454-1E 33 MB82DBS08164D-70L (9) Asynchronous Write Timing 3-2 (WE, LB, UB Byte Write Control) tWC tWC Address Address Valid Address Valid CE1 Low tWR tWR WE tAS tBW tWHP tBS tBH LB tBH tAS tBW tBS UB tDS tDH DQ7 to DQ0 (Input) tDS tDH DQ15 to DQ8 (Input) Valid Data Input Valid Data Input Note : This timing diagram assumes CE2 = H, ADV = L and OE = H. 34 DS05-11454-1E MB82DBS08164D-70L (10) Asynchronous Write Timing 3-3 (WE, LB, UB Byte Write Control) tWC tWC Address Address Valid Address Valid CE1 Low WE tAS tBW tWR tWHP tBS tBH LB tBS tBH tAS tBW tWR UB tDS tDH DQ7 to DQ0 (Input) tDS tDH DQ15 to DQ8 (Input) Valid Data Input Valid Data Input Note : This timing diagram assumes CE2 = H, ADV = L and OE = H. DS05-11454-1E 35 MB82DBS08164D-70L (11) Asynchronous Write Timing 3-4 (WE, LB, UB Byte Write Control) tWC tWC Address CE1 Low Address Valid Address Valid WE tAS LB tDS tDH tBW tWR tBHP tDS tDH tAS tBW tWR DQ7 to DQ0 (Input) tAS UB Valid Data Input Valid Data Input tBW tWR tBHP tDS tDH tAS tBW tDS tWR tDH DQ15 to DQ8 (Input) Valid Data Input Valid Data Input Note : This timing diagram assumes CE2 = H, ADV = L and OE = H. 36 DS05-11454-1E MB82DBS08164D-70L (12) Asynchronous Read/Write Timing 1-1 (CE1 Control) tWC tRC Address tCHAH CE1 tCP tAS Write Address tWR tCW tASC Read Address tCHAH tCE tCP WE LB, UB tOHCL OE tCHZ tOH DQ tDS tDH tCLZ tOH Read Data Output Write Data Input Read Data Output Notes : • This timing diagram assumes CE2 = H and ADV = L. • Write address is valid from either CE1 or WE of last falling edge. DS05-11454-1E 37 MB82DBS08164D-70L (13) Asynchronous Read/Write Timing 1-2 (CE1, WE, OE Control) tWC tRC Address tCHAH CE1 tCP tAS Write Address tWR tASC Read Address tCHAH tCE tCP tWP WE LB, UB tOHCL OE tCHZ tOH DQ tDS tDH tOLZ tOH tOE Read Data Output Write Data Input Read Data Output Notes : • This timing diagram assumes CE2 = H and ADV = L. • OE can be fixed Low during write operation if it is CE1 controlled write at Read-Write-Read sequence. 38 DS05-11454-1E MB82DBS08164D-70L (14) Asynchronous Read/Write Timing 2 (OE, WE Control) tWC tRC Address Write Address Read Address tAA tOHAH CE1 Low tAS WE tOES tWP tWR tOHAH LB, UB tASO OE tOHZ tOH DQ tDS tDH tWHOL tOLZ tOH tOHZ tOE Read Data Output Write Data Input Read Data Output Notes : • This timing diagram assumes CE2 = H and ADV = L. • CE1 can be tied to Low for WE and OE controlled operation. • Read data will be available after tAA from WE = H if read addresses are not changed from write address. DS05-11454-1E 39 MB82DBS08164D-70L (15) Asynchronous Read/Write Timing 3 (OE, WE, LB, UB Control) tWC tRC Address Write Address Read Address tAA tOHAH CE1 Low tOHAH WE tOES LB, UB tBHZ tASO tAS tBW tWR tBA OE tOH DQ tDS tDH tWHOL tBHZ tBLZ tOH Read Data Output Write Data Input Read Data Output Notes : • This timing diagram assumes CE2 = H and ADV = L. • CE1 can be tied to Low for WE and OE controlled operation. • Read data will be available after tAA from WE = H if read addresses are not changed from write address. 40 DS05-11454-1E MB82DBS08164D-70L (16) Clock Input Timing tCK CLK tCK tCKH tCKL tCKT tCKT Notes : • Stable clock input must be required during CE1 = L. • tCK is defined between rising clock edges. • tCKT is defined between VIH (Min) and VIL (Max). (17) Address Latch Timing (Synchronous Mode) CLK tASCK tCKAH Address Address Valid tVSCK tCKVH ADV tVPL tCKCH tCLCK CE1 Notes : • tVPL is specified from the falling edge of either CE1 or ADV whichever comes late. At least one rising clock edge must be input during ADV = L. • tASCK, tVSCK and tCLCK are applied to the 1st valid clock edge during ADV = L. • tCKCH is applied to the rising clock edge before address latching. DS05-11454-1E 41 MB82DBS08164D-70L (18) Synchronous Read Timing 1 (OE Control) RL=5 CLK tRCB Address Address Valid Address Valid tASCK tCKAH tVPL ADV tVSCK tCKCH CE1 tCP tCLTL OE tOHZ tOLZ WE High tBLQ LB, UB tBLZ WAIT High-Z tCKTX DQ High-Z tAC tAC Q1 tCKQX tAC QBL tCKQX tCKTV tBHZ tCHTZ tCKBH tOLQ tCKOH tCKVH tCLCK tCKCH tASCK tCKAH tVPL tVSCK tCKVH tCLCK tCLTL Note : This timing diagram assumes CE2 = H. 42 DS05-11454-1E MB82DBS08164D-70L (19) Synchronous Read Timing 2 (CE1 Control) RL=5 CLK tRCB Address Address Valid Address Valid tASCK tCKAH tVPL ADV tVSCK tCKCH CE1 tCKCLH tCLTL tCLZ OE tCP tCKVH tCLCK tCKCH tASCK tCKAH tVPL tVSCK tCKVH tCLCK tCLTL tCLZ WE High LB, UB tCKTV tCHTZ WAIT tCKTX DQ tAC tAC Q1 tCKQX tAC QBL tCKQX tCHZ Note : This timing diagram assumes CE2 = H. DS05-11454-1E 43 MB82DBS08164D-70L (20) Synchronous Write Timing 1 (WE Level Control) RL=5 CLK tWCB Address Address Valid Address Valid tASCK tCKAH tVPL ADV tVSCK tCKCH CE1 tCLTH OE High tWLTH tWLD WE tBSCK LB, UB tCHTZ WAIT High-Z tDSCK DQ D1 tDHCK tDSCK D2 tDSCK DBL tDHCK tCKBH tCKWH tCP tCKVH tCLCK tCKCLH tCKCH tCHCK tASCK tCKAH tVPL tVSCK tCKVH tCLCK Note : This timing diagram assumes CE2 = H. 44 DS05-11454-1E MB82DBS08164D-70L (21) Synchronous Write Timing 2 (WE Single Clock Pulse Control) RL=5 CLK tWCB Address Address Valid Address Valid tASCK tCKAH tVPL ADV tVSCK tCKCH CE1 tCP tCLTH OE High tWSCK tCKWH tCKVH tCLCK tCKCLH tCKCH tCHCK tASCK tCKAH tVPL tVSCK tCKVH tCLCK tCLTH tWSCK tCKWH WE tWLTH LB, UB tCHTZ WAIT High-Z tDSCK DQ D1 tDHCK tDSCK D2 tDSCK DBL tDHCK tBSCK tCKBH tWLTH Note : This timing diagram assumes CE2 = H. DS05-11454-1E 45 MB82DBS08164D-70L (22) Synchronous Write Timing 3 (LB, UB Byte Mask Control) RL=5 CLK tWCB Address Address Valid Address Valid tASCK tCKAH tVPL ADV tVSCK tCKCH CE1 tCLTH OE High tWLTH tWLD WE tCKBH LB tCKBH tCKWH tCP tCKVH tCLCK tCKCLH tCKCH tCHCK tASCK tCKAH tVPL tVSCK tCKVH tCLCK UB tBSCK tBSCK tBSCK tCHTZ WAIT High-Z tDSCK tDSCK DBL tDHCK tDSCK DQ7 to DQ0 D1 DQ15 to DQ8 D1 tDHCK D2 Note : This timing diagram assumes CE2 = H and WE Level Control. 46 DS05-11454-1E MB82DBS08164D-70L (23) Synchronous Read to Write Timing 1 (CE1 Control) RL = 5 CLK tWCB Address Address Valid tASCK tCKAH tVPL ADV tVSCK tCKVH tCLCK tCKCLH tCKCH CE1 tCKCLH tCP tCLTH OE WE tCKBH tBSCK LB,UB tCHTZ WAIT tAC tCHZ tDSCK tDSCK tDSCK tDSCK DQ QBL-1 tCKQX QBL tCKQX D1 tDHCK D2 tDHCK D3 tDHCK DBL tDHCK Note : This timing diagram assumes CE2 = H. DS05-11454-1E 47 MB82DBS08164D-70L (24) Synchronous Write to Read Timing 1 (CE1 Control) RL=5 CLK tRCB Address Address Valid tASCK tCKAH tVPL ADV tCHCK tVSCK tCKCH CE1 tCKCLH tCP tCLTL tCLZ OE tCKCLH tCKVH tCLCK WE LB, UB Low tCKTV tCHTZ WAIT tDSCK DQ DBL-1 tDHCK tDSCK DBL tDHCK tCKTX tAC tAC Q1 tCKQX tAC Q2 tCKQX QBL tCKQX Note : This timing diagram assumes CE2 = H. 48 DS05-11454-1E MB82DBS08164D-70L (25) Power-up Timing 1 CE1 tCHS tC2LH CE2 tCHH VDD 0V VDD (Min) Note : The tC2LH specifies after VDD reaches specified minimum level. (26) Power-up Timing 2 CE1 tCHH CE2 VDD 0V VDD (Min) Note : The tCHH specifies after VDD reaches specified minimum level and applicable to both CE1 and CE2. If transition time of VDD (from 0 V to VDD (Min)) is longer than 50 ms, (25) Power-up Timing 1 must be applied. DS05-11454-1E 49 MB82DBS08164D-70L (27) Power Down Entry and Exit Timing CE1 tCHS CE2 tCSP tC2LP High-Z tCHH (tCHHP) DQ Power Down Entry Power Down Mode Power Down Exit Notes : • Power Down mode can be also used as a reset timing if “Power-up Timing” above could not be satisfied and Power Down program was not performed prior to this reset. • CE2 can be brought to Low after the completion of previous Read/Write operation. • CE2 must be kept at High during the specified minimum time of tCP. (28) Standby Entry Timing after Read or Write CE1 tCHOX tCHWX OE WE Active (Read) Standby Active (Write) Standby Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. 50 DS05-11454-1E MB82DBS08164D-70L (29) Configuration Register Set Timing 1 (Asynchronous Operation) tRC tWC MSB*1 tWC MSB*1 tWC MSB*1 tWC MSB*1 tWC MSB*1 Address MSB*1 tCP tCP tCP tCP tCP tWC*6 CE1 OE WE LB, UB *2 *2 *2 *3 *3 *3 DQ RDa RDa RDa CR Key 0*4 CR Key 1*5 CR Key 2*5 Cycle #1 Cycle #2 Cycle #3 Cycle #4 Cycle #5 Cycle #6 *1 : The all address inputs must be High from Cycle #1 to #6. *2 : At least either LB or UB must be brought to Low during Cycle #1 to #3. *3 : LB must be brought to Low in order to input the CR Keys during Cycle #4 to #6. *4 : The CR Key 0 must be set “1” for the CR Set as specified in “■FUNCTIONAL DESCRIPTION”. *5 : The CR Keys must conform to the format specified in “■FUNCTIONAL DESCRIPTION”. If not, any operations and data are not guaranteed. *6 : After tWC following Cycle #6, the Configuration Register Set is completed and returned to the normal operation. DS05-11454-1E 51 MB82DBS08164D-70L (30) Configuration Register Verify Timing 1 (Asynchronous Operation) tRC tWC MSB*1 tWC MSB*1 tWC MSB*1 tRC MSB*1 tRC MSB*1 Address MSB*1 tCP tCP tCP tCP tCP tRC*6 CE1 OE WE LB, UB *2 *2 *2 *3 *3 *3 DQ*3 RDa RDa RDa CR Key 0*4 CR Key 1*5 CR Key 2*5 Cycle #1 Cycle #2 Cycle #3 Cycle #4 Cycle #5 Cycle #6 *1 : The all address inputs must be High from Cycle #1 to #6. *2 : At least either LB or UB must be brought to Low during Cycle #1 to #3. *3 : LB must be brought to Low in order to input or output the CR Keys during Cycle #4 to #6. *4 : The CR Key 0 must be set “0” for the CR Verify as specified in “■FUNCTIONAL DESCRIPTION”. *5 : The CR Keys must conform to the format specified in “■FUNCTIONAL DESCRIPTION”. If not, any operations and data are not guaranteed. *6 : After tRC following Cycle #6, the Configuration Register Verify is completed and returned to the normal operation. 52 DS05-11454-1E MB82DBS08164D-70L (31) Configuration Register Set Timing 2 (Synchronous Operation) CLK Address MSB * 1 MSB * 1 MSB * 1 MSB * 1 MSB * 1 MSB *1 tRCB tWCB tWCB tWCB tWCB tWCB ADV tCP tCP tCP tCP tCP * tWC 6 CE1 OE WE *2 *2 *2 *3 *3 *3 LB,UB RL RL-1 RDa RDa RL-1 RDa RL-1 CR Key 0 RL-1 CR Key 1 RL-1 CR Key 2 DQ Cycle #1 Cycle #2 Cycle #3 Cycle #4 *4 Cycle #5 *5 Cycle #6 *5 *1 : The all address inputs must be High from Cycle #1 to #6. *2 : At least either LB or UB must be brought to Low during Cycle #1 to #3. *3 : LB must be brought to Low in order to input the CR Keys during Cycle #4 to #6. *4 : The CR Key 0 must be set “1” for the CR Set as specified in “■ FUNCTIONAL DESCRIPTION”. *5 : The CR Keys must conform to the format specified in “■ FUNCTIONAL DESCRIPTION”. If not, any operations and data are not guaranteed. *6 : After tWC following Cycle #6, the Configuration Register Set is completed and returned to the normal operation. DS05-11454-1E 53 MB82DBS08164D-70L (32) Configuration Register Verify Timing 2 (Synchronous Operation) CLK Address MSB * 1 MSB * 1 MSB * 1 MSB * 1 MSB * 1 MSB *1 tRCB tRCB tRCB tRCB tRCB tRCB ADV tCP tCP tCP tCP tCP tRC* 6 CE1 OE WE *2 *2 *2 *3 *3 *3 LB,UB RL RL-1 RDa RDa RL-1 RDa RL-1 CR Key 0 RL CR Key 1 RL CR Key 2 DQ Cycle #1 Cycle #2 Cycle #3 Cycle #4 *4 Cycle #5 *5 Cycle #6 *5 *1 : The all address inputs must be High from Cycle #1 to #6. *2 : At least either LB or UB must be brought to Low during Cycle #1 to #3. *3 : LB must be brought to Low in order to input or output the CR Keys during Cycle #4 to #6. *4 : The CR Key 0 must be set “0” for the CR Verify as specified in “■FUNCTIONAL DESCRIPTION”. *5 : The CR Keys must conform to the format specified in “■FUNCTIONAL DESCRIPTION”. If not, any operations and data are not guaranteed. *6 : After tRC following Cycle #6, the Configuration Register Verify is completed and returned to the normal operation. 54 DS05-11454-1E MB82DBS08164D-70L ■ ORDERING INFORMATION Part Number MB82DBS08164D-70LTBG Package 71-ball plastic FBGA (BGA-71P-M03) DS05-11454-1E 55 MB82DBS08164D-70L ■ PACKAGE DIMENSIONS 71-ball plastic FBGA Ball pitch Package width × package length Lead shape Sealing method Ball size Mounting height 0.80 mm 7.00 × 11.00 mm Soldering ball Plastic mold ∅0.45 mm 1.20 mm Max. 0.14 g (BGA-71P-M03) Weight 71-ball plastic FBGA (BGA-71P-M03) 11.00±0.10(.433±.004) 0.20(.008) S B 1.09 .043 +0.11 –0.10 +.004 –.004 B (Seated height) 0.80(.031) REF A 0.40(.016) REF 0.80(.031) REF 8 7 6 5 4 3 2 1 MLKJHGFEDCBA 7.00±0.10 (.276±.004) 0.40(.016) REF 0.10(.004) S INDEX-MARK AREA S 0.39±0.10 (Stand off) (.015±.004) 0.20(.008) S A 71-ø0.45 +0.10 –0.05 71-ø.018 +.004 –.002 ø0.08(.003) M S AB 0.10(.004) S C ©2003-2008 FUJITSU MICROELECTRONICS LIMITED B71003S-c-1-2 2003 FUJITSU LIMITED B71003S-c-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest Package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 56 DS05-11454-1E MB82DBS08164D-70L MEMO DS05-11454-1E 57 MB82DBS08164D-70L MEMO 58 DS05-11454-1E MB82DBS08164D-70L MEMO DS05-11454-1E 59 MB82DBS08164D-70L FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department