MB82DS01181E

FUJITSU SEMICONDUCTOR DATA SHEET DS05-11434-1E MEMORY Mobile FCRAMTM CMOS 16 Mbit (1 M word × 16 bit) MB82DS01181E-70L-A ■ DESCRIPTION Mobile Phone Application Specific Memory MB82DS01181E is a Fast Cycle Random Access Memory (FCRAM) with asynchronous Static Random Access Memory (SRAM) interface containing 16,777,216 storages accessible in a 16-bit format. MB82DS01181E is suited for mobile applications such as Cellular Handset and PDA. Note: FCRAM is a trademark of Fujitsu Limited, Japan. ■ FEATURES • • • • • • • • • • • Asynchronous SRAM Interface 1 M word × 16-bit Organization Low-voltage Operating Conditions Wide Operating Temperature Read/Write Cycle Time Fast Random Access Time Active current Standby current Power down current Byte Control Shipping Form : VDD = +1.7 V to +1.95 V : TA = −30 °C to +85 °C : tRC = tWC = 80 ns Min : tAA = tCE = 70 ns Max : IDDA1 = 20 mA Max : IDDS1 = 100 µA Max : IDDPS = 10 µA Max : Wafer / Chip MB82DS01181E-70L-A ■ PIN DESCRIPTION Pin Name A19 to A0 CE1 CE2 WE OE LB UB DQ8 to DQ1 DQ16 to DQ9 VDD VSS Address Input Chip Enable 1 (Low Active) Chip Enable 2 (High Active) Write Enable (Low Active) Output Enable (Low Active) Lower Byte Control (Low Active) Upper Byte Control (Low Active) Lower Byte Data Input/Output Upper Byte Data Input/Output Power Supply Ground Description 2 MB82DS01181E-70L-A ■ BLOCK DIAGRAM VDD VSS A19 to A0 Address Latch & Buffer Row Decoder Memory Cell Array 16,777,216 bits DQ8 to DQ1 I/O Data DQ16 to DQ9 Input Data Latch & Control Sense / Switch Output Data Column Decoder Address Latch & Buffer CE2 Power control Timing control CE1 WE LB UB OE 3 MB82DS01181E-70L-A ■ FUNCTION TRUTH TABLE Mode Standby (Deselect) Output Disable*1 No Read Read (Upper Byte) Read (Lower Byte) Read (Word) No Write Write (Upper Byte) Write (Lower Byte) Write (Word) Power Down *2 L X X X L H H H L CE2 CE1 H WE X H OE X H LB X X H H L L H H L L X UB X X H L H L H L H L X A19 to A0 DQ8 to DQ1 DQ16 to DQ9 X *3 Valid Valid Valid Valid Valid Valid Valid Valid X High-Z High-Z High-Z High-Z Output Valid Output Valid Invalid Invalid Input Valid Input Valid High-Z High-Z High-Z High-Z Output Valid High-Z Output Valid Invalid Input Valid Invalid Input Valid High-Z IDDP No Yes IDD IDDS Data Retention L IDDA Note : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High impedance *1 : Should not be kept this logic condition longer than 1 µs. *2 : Power down mode can be entered from standby state and all DQ pins are in High-Z state. *3 : Can be either VIL or VIH but must be valid before read or write. 4 MB82DS01181E-70L-A ■ ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage* Input Voltage* Output voltage* Short Circuit Output Current Storage Temperature * : All voltages are referenced to VSS = 0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Symbol VDD VIN VOUT IOUT TSTG Rating Min −0.5 −0.5 −0.5 −50 −55 Max +3.6 +3.6 +3.6 +50 +125 Unit V V V mA °C ■ RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage *1 High Level Input Voltage *1, *2 Low Level Input Voltage *1, *3 Ambient Temperature *1 : All voltages are referenced to VSS = 0 V. *2 : Overshoot spec. (VIH (Max) = VDD + 1.0 V, pulse width ≤ 5.0 ns) *3 : Undershoot spec. (VIL (Min) = − 1.0 V, pulse width ≤ 5.0 ns) WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Symbol VDD VSS VIH VIL TA Value Min 1.7 0 VDD × 0.8 −0.3 −30 Max 1.95 0 VDD + 0.2 VDD × 0.2 + 85 Unit V V V V °C 5 MB82DS01181E-70L-A ■ PIN CAPACITANCE Parameter Pin name A19 to A0 Input Capacitance Input/Output Capacitance CE1, CE2, WE, OE, LB, UB DQ16 to DQ1 Symbol Conditions CIN1 CIN2 CIO VIN = 0 V VIN = 0 V VIO = 0 V (f = 1.0 MHz, TA = +25 °C) Value Unit Typ Max ⎯ ⎯ ⎯ 5 5 8 pF pF pF Min ⎯ ⎯ ⎯ ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics (At recommended operating conditions unless otherwise noted.) Parameter Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level VDD Power Down Current Symbol ILI ILO VOH VOL IDDPS IDDS VDD Standby Current IDDS1 IDDA1 VDD Active Current IDDA2 VSS ≤ VIN ≤ VDD VSS ≤ VOUT ≤ VDD, Output High impedance VDD = VDD Min, IOH = −0.5 mA IOL = 1 mA VDD = VDD Max, VIN = VIH or VIL, CE2 ≤ 0.2 V VDD = VDD Max, VIN = VIH or VIL, CE1 = CE2 = VIH VDD = VDD Max, VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, CE1 = CE2 ≥ VDD − 0.2 V VDD = VDD Max, VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA tRC / tWC = Min tRC / tWC = 1 µs Conditions Value Min −1.0 −1.0 1.4 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max +1.0 +1.0 ⎯ 0.4 10 1 Unit µA µA V V µA mA µA 100 20 mA 3.0 Notes: • All voltages are referenced to Vss = 0 V. • DC Characteristics are measured after following POWER-UP timing. • IOUT depends on the output load conditions. 6 MB82DS01181E-70L-A 2. AC Characteristics (1) Read Operation (At recommended operating conditions unless otherwise noted.) Parameter Read Cycle Time CE1 Access Time OE Access Time Address Access Time LB, UB Access Time Output Data Hold Time CE1 Low to Output Low-Z OE Low to Output Low-Z LB, UB Low to Output Low-Z CE1 High to Output High-Z OE High to Output High-Z LB, UB High to Output High-Z Address Setup Time to CE1 Low Address Setup Time to OE Low Address Invalid Time Address Hold Time from CE1 High Address Hold Time from OE High WE High to OE Low Time for Read CE1 High Pulse Width Symbol tRC tCE tOE tAA tBA tOH tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tASC tASO tAX tCHAH tOHAH tWHOL tCP Value Min 80 ⎯ ⎯ ⎯ ⎯ 5 5 0 0 ⎯ ⎯ ⎯ −5 10 ⎯ −5 −5 15 15 Max 1000 70 45 70 30 ⎯ ⎯ ⎯ ⎯ 20 20 20 ⎯ ⎯ 10 ⎯ ⎯ 1000 ⎯ Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *7 *5 *6 Notes *1, *2 *3 *3 *3, *5 *3 *3 *4 *4 *4 *3 *3 *3 *1 : Maximum value is applicable if CE1 is kept at Low without any address change. *2 : Address should not be changed within minimum tRC. *3 : The output load 50 pF with 50 Ω termination to VDD × 0.5 V. *4 : The output load 5 pF without any other load. *5 : Applicable when CE1 is kept at Low. *6 : tRC (Min) must be satisfied. *7 : If the actual value of tWHOL is shorter than specified minimum value, the actual tAA of following Read may become longer by the amount of subtracting actual value from specified minimum value. Note : AC characteristics are measured after following power-up timing. 7 MB82DS01181E-70L-A (2) Write Operation (At recommended operating conditions unless otherwise noted.) Value Parameter Write Cycle Time Address Setup Time CE1 Write Pulse Width WE Write Pulse Width LB, UB Write Pulse Width LB, UB Byte Mask Setup Time LB, UB Byte Mask Hold Time Write Recovery Time CE1 High Pulse Width WE High Pulse Width LB, UB High Pulse Width Data Setup Time Data Hold Time OE High to CE1 Low Setup Time for Write OE High to Address Setup Time for Write LB and UB Write Pulse Overlap Symbol Min tWC tAS tCW tWP tBW tBS tBH tWR tCP tWHP tBHP tDS tDH tOHCL tOES tBWO 80 0 45 45 45 −5 −5 0 15 15 15 20 0 −5 0 20 Max 1000 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 1000 1000 ⎯ ⎯ ⎯ ⎯ ⎯ ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *7 *8 *1, *2 *2 *3 *3 *3 *4 *5 *6 Unit Notes *1 : Maximum value is applicable if CE1 is kept at Low without any address change. *2 : Minimum value must be equal or greater than the sum of write pulse width (tCW, tWP or tBW) and write recovery time (tWR) . *3 : Write pulse width is defined from High to Low transition of CE1, WE, LB or UB, whichever occurs last. *4 : Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1 or WE whichever occurs last. *5 : Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1 or WE whichever occurs first. *6 : Write recovery time is defined from Low to High transition of CE1, WE, LB or UB, whichever occurs first. *7 : If OE is Low after minimum tOHCL, read cycle is initiated. In other words, OE must be brought to High within 5 ns after CE1 is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC is met. *8 : If OE is Low after new address input, read cycle is initiated. In other words, OE must be brought to High at the same time or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum tRC is met. Note : AC Characteristics are measured after following POWER-UP timing. 8 MB82DS01181E-70L-A (3) Power Down Parameters (At recommended operating conditions unless otherwise noted.) Parameter CE2 Low Setup Time for Power Down Entry CE2 Low Hold Time after Power Down Entry CE1 High Hold Time following CE2 High after Power Down Exit [SLEEP mode only] CE1 High Setup Time following CE2 High after Power Down Exit * : Applicable also to power-up. (4) Other Timing Parameters (At recommended operating conditions unless otherwise noted.) Parameter CE1 High to OE Invalid Time for Standby Entry CE1 High to WE Invalid Time for Standby Entry CE1 High Hold Time following CE2 High after Power-up Input Transition Time Symbol tCHOX tCHWX tCHH tT Value Min 10 10 300 1 Max ⎯ ⎯ ⎯ 25 Unit ns ns µs ns *2 *1 Notes Symbol tCSP tC2LP tCHH tCHS Value Min 10 80 300 0 Max ⎯ ⎯ ⎯ ⎯ Unit ns ns µs ns * Notes *1: Some data might be written into any address location if tCHWX (Min) is not satisfied. *2: The Input Transition Time (tT) at AC testing is 5 ns as shown in below. If actual tT is longer than 5 ns, it may violate AC specifications of some timing parameters. (5) AC Test Conditions Parameter Input High Level Input Low level Input Timing Measurement Level Input Transition Time Symbol VIH VIL VREF tT Conditions ⎯ ⎯ ⎯ Between VIL and VIH Measured Value VDD × 0.8 VDD × 0.2 VDD × 0.5 5 Unit V V V ns Notes (6) AC Measurement Output Load Circuit VDD × 0.5 V 50 Ω VDD 0.1 µF VSS Device Under Test 50 pF OUT 9 MB82DS01181E-70L-A ■ TIMING DIAGRAM 1. READ Timing 1 (Basic Timing) tRC Address tASC tCE Address Valid tCHAH tCP tOE tCHZ tASC CE1 OE tOHZ tBA LB, UB tBLZ tBHZ DQ tOLZ tCLZ (Output) Valid Data Output Note : This timing diagram assumes CE2 = “H” and WE = “H”. tOH 2. READ Timing 2 (OE & Address Access) tRC tAX tRC Address CE1 Address Valid tAA Low tASO tOE Address Valid tAA tOHAH OE LB, UB tOLZ tOH tOHZ tOH DQ (Output) Valid Data Output Note : This timing diagram assumes CE2 = “H” and WE = “H”. Valid Data Output 10 MB82DS01181E-70L-A 3. READ Timing 3 (LB, UB Byte Access) tAX tRC tAX Address tAA Address Valid Low tBA tBA CE1, OE LB tBA UB tBLZ tBHZ tOH tBLZ tBHZ tOH DQ8 to DQ1 (Output) Valid Data Output tBLZ DQ16 to DQ9 Valid Data Output tOH tBHZ (Output) Valid Data Output Note : This timing diagram assumes CE2 = “H” and WE = “H”. 4. WRITE Timing 1 (Basic Timing) tWC Address tAS Address Valid tCW tWR tCP tAS tWP tWR tWHP tAS tBW tWR tBHP tOHCL tAS tAS tAS CE1 WE LB, UB OE DQ tDS tDH (Input) Valid Data Input Note : This timing diagram assumes CE2 = “H”. 11 MB82DS01181E-70L-A 5. WRITE Timing 2 (WE Control) tWC tWC Address tOHAH Address Valid Address Valid CE1 Low tAS tWP tWR tWHP tAS tWP tWR WE LB, UB tOES OE tOHZ tDS tDH tDS tDH DQ (Input) Valid Data Input Note : This timing diagram assumes CE2 = “H”. Valid Data Input 6. WRITE Timing 3-1 (WE, LB, UB Byte Write Control) tWC tWC Address CE1 Low tAS Address Valid Address Valid tWP tWHP tWR tAS tWP WE tBS tBH LB tBS tBH tDS tDH tWR UB DQ8 to DQ1 (Input) DQ16 to DQ9 Valid Data Input tDS tDH (Input) Valid Data Input Note : This timing diagram assumes CE2 = “H” and OE = “H”. 12 MB82DS01181E-70L-A 7. WRITE Timing 3-2 (WE, LB, UB Byte Write Control) tWC tWC Address CE1 Low Address Valid Address Valid tWR tWR tWHP WE tAS tBW tBS tBH LB tBS tBH tDS tDH tAS tBW UB DQ8 to DQ1 (Input) DQ16 to DQ9 Valid Data Input tDS tDH (Input) Valid Data Input Note : This timing diagram assumes CE2 = “H” and OE = “H”. 8. WRITE Timing 3-3 (WE, LB, UB Byte Write Control) tWC tWC Address CE1 Low Address Valid Address Valid WE tAS tBW tWR tWHP tBS tBH LB tBS tBH tDS tDH tAS tBW tWR UB DQ8 to DQ1 (Input) DQ16 to DQ9 Valid Data Input tDS tDH (Input) Valid Data Input Note : This timing diagram assumes CE2 = “H” and OE = “H”. 13 MB82DS01181E-70L-A 9. WRITE Timing 3-4 (WE, LB, UB Byte Write Control) tWC tWC Address CE1 Low Address Valid Address Valid WE tAS tBW tWR tBHP tBWO tDS tDH tDS tDH tAS tBW tWR LB DQ8 to DQ1 (Input) tAS Valid Data Input tBW tWR tBHP tDS tDH tAS Valid Data Input tBWO tBW tDS tWR UB DQ16 to DQ9 tDH (Input) Valid Data Input Valid Data Input Note : This timing diagram assumes CE2 = “H” and OE = “H”. 10. READ/WRITE Timing 1-1 (CE1 Control) tWC tRC Address tCHAH tAS Write Address tCW tWR tASC Read Address tCE tCHAH CE1 tCP tCP WE UB, LB tOHCL OE tCHZ tOH tDS tDH tCLZ tOH DQ Valid Data Output Valid Data Input Note : This timing diagram assumes CE2 = “H”. Write address is valid from either CE1 or WE of last falling edge. 14 MB82DS01181E-70L-A 11. READ/WRITE Timing 1-2 (CE1, WE, OE Control) tWC tRC Address tCHAH tAS Write Address tWR tASC Read Address tCE tCHAH CE1 tCP tWP tCP WE UB, LB tOHCL tOE OE tCHZ tOH tDS tDH tOLZ tOH DQ Valid Data Output Valid Data Input Valid Data Output Note : This timing diagram assumes CE2 = “H”. OE can be fixed Low during write operation if it is CE1 controlled write at Read-Write-Read sequence. 12. READ/WRITE Timing 2 (OE, WE Control) tWC tRC Address tOHAH Write Address Read Address tAA tOHAH CE1 Low tAS tWP tWR WE tOES UB, LB tASO tOE tOHZ tOH OE tOHZ tOH tDS tDH tWHOL tOLZ DQ Valid Data Output Valid Data Input Valid Data Output Note : This timing diagram assumes CE2 = “H”. CE1 can be tied to Low for WE and OE controlled operation. 15 MB82DS01181E-70L-A 13. READ/WRITE Timing 3 (OE, WE, LB, UB Control) tWC tRC Address CE1 Write Address Read Address tAA tOHAH Low tOHAH WE tOES tAS tBW tWR tBA UB, LB tBHZ tASO tWHOL tOH tDS tDH tBLZ OE tBHZ tOH DQ Valid Data Output Valid Data Input Valid Data Output Note : This timing diagram assumes CE2 = “H”. CE1 can be tied to Low for WE and OE controlled operation. 14. POWER-UP Timing CE1 tCHH CE2 VDD 0V VDD (Min) Note : tCHH specifies after VDD reaches specified minimum level and applicable to both CE1 and CE2. 16 MB82DS01181E-70L-A 15. POWER DOWN Entry and Exit Timing CE1 tCHS CE2 tCSP tC2LP High-Z tCHH DQ Power Down Entry Power Down Mode Power Down Exit Note : This Power Down mode can be also used as a reset timing if POWER-UP timing above could not be satisfied and Power Down program was not performed prior to this reset. 16. Standby Entry Timing after Read or Write CE1 tCHOX tCHWX OE WE Active (Read) Standby Active (Write) Standby Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (Min) period for Standby mode from CE1 Low to High transition. 17 MB82DS01181E-70L-A ■ BONDING PAD INFORMATION Please contact local FUJITSU representative for pad layout and pad coordinate information. ■ ORDERING INFORMATION Part Number MB82DS01181E-70LWT-A Shipping Form Wafer Remarks 18 MB82DS01181E-70L-A FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. 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