MB85AS4MTPF-G-BCERE1

FUJITSU SEMICONDUCTOR DATA SHEET DS501-00045-1v0-E Memory ReRAM 4M (512 K × 8) Bit SPI MB85AS4MT ■ DESCRIPTION MB85AS4MT is a ReRAM (Resistive Random Access Memory) chip in a configuration of 524,288 words × 8 bits, using the resistance-variable memory process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. MB85AS4MT adopts the Serial Peripheral Interface (SPI). MB85AS4MT is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MB85AS4MT can be used for 1.2 × 106 rewrite operations. ■ FEATURES : 4 Mbits (524,288 words × 8 bits) : SPI (Serial Peripheral Interface) Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1) Write buffer size : 256 bytes Operating frequency : 5 MHz (Max) Data endurance : 1.2 × 106 times / byte Data retention : 10 years (+85 °C) Operating power supply voltage : 1.65 V to 3.6 V Operating power supply current : Rewrite current 1.3 mA (Typ) Read-out current 0.2 mA (Typ@5 MHz) Standby current 10 μA (Typ) Sleep current 2 μA (Typ) Operation ambient temperature range : -40 °C to +85 °C Package : 8-pin plastic SOP (FPT-8P-M11) RoHS compliant • Bit configuration • Serial Peripheral Interface • • • • • • • • Copyright 2016 FUJITSU SEMICONDUCTOR LIMITED 2016.12 MB85AS4MT ■ PIN ASSIGNMENT (TOP VIEW) CS 1 8 VDD SO 2 7 HOLD WP 3 6 SCK VSS 4 5 SI (FPT-8P-M11) ■ PIN FUNCTIONAL DESCRIPTIONS Pin No. Pin Name CS Chip Select pin This is an input pin to make chips select. When CS is “H” level, device is in deselect (standby) status and SO becomes High-Z. Inputs from other pins are ignored for this time. When CS is “L” level, device is in select (active) status. CS has to be “L” level before inputting op-code. WP Write Protect pin This is a pin to control writing to a status register. The writing of status register (see “■ STATUS REGISTER”) is protected in related with WP and WPEN. See “■ WRITING PROTECT” for detail. 7 HOLD Hold pin This pin is used to interrupt serial input/output without making chips deselect. When HOLD is “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become do not care. While the hold operation, CS has to be retained “L” level. 6 SCK Serial Clock pin This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge, SO is output synchronously to a falling edge. 5 SI Serial Data Input pin This is an input pin of serial data. This inputs op-code, address, and writing data. 2 SO Serial Data Output pin This is an output pin of serial data. Reading data of ReRAM memory cell array and status register data are output. This is High-Z during standby. 8 VDD Supply Voltage pin 4 VSS Ground pin 1 3 2 Functional description DS501-00045-1v0-E MB85AS4MT ■ BLOCK DIAGRAM Control Circuit SCK HOLD Row Decoder CS Address Counter Serial-Parallel Converter SI ReRAM Cell Array 524,288 ✕ 8 ReRAM Status Register Column Decoder/Sense Amp/ Write Amp WP Data Register SO Parallel-Serial Converter DS501-00045-1v0-E 3 MB85AS4MT ■ SPI MODE MB85AS4MT corresponds to the SPI mode 0 (CPOL = 0, CPHA = 0) , and SPI mode 3 (CPOL = 1, CPHA = 1) . CS SCK SI 7 6 5 MSB 4 3 2 1 0 LSB SPI Mode 0 CS SCK SI 7 6 5 4 MSB 3 2 1 0 LSB SPI Mode 3 4 DS501-00045-1v0-E MB85AS4MT ■ SERIAL PERIPHERAL INTERFACE (SPI) MB85AS4MT works as a slave of SPI. More than 2 devices can be connected by using microcontroller equipped with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus connected to use. SCK MOSI MISO SO SPI Microcontroller SI SO SCK MB85AS4MT CS SI SCK MB85AS4MT CS HOLD HOLD SS1 SS2 HOLD1 HOLD2 MOSI : Master Out Slave In MISO : Master In Slave Out SS : Slave Select System Configuration with SPI Port SO SI SCK Microcontroller MB85AS4MT CS HOLD System Configuration without SPI Port DS501-00045-1v0-E 5 MB85AS4MT ■ STATUS REGISTER Bit No. Bit Name Function WPEN Status Register Write Protect This is a bit composed of nonvolatile memories (ReRAM). WPEN protects writing to a status register (refer to “■ WRITING PROTECT”) relating with WP input. Writing with the WRSR command and reading with the RDSR command are possible. 6 to 4 ⎯ Not Used Bits These are bits composed of volatile memories, writing with the WRSR command is possible. These bits are not used but they are read with the RDSR command. 3 BP1 2 BP0 7 1 0 Block Protect This is a bit composed of nonvolatile memory. This defines size of write protect block for the WRITE command (refer to “■ BLOCK PROTECT”). Writing with the WRSR command and reading with the RDSR command are possible. WEL Write Enable Latch This indicates ReRAM Array and status register are writable. The WREN command is for setting, and the WRDI command is for resetting. With the RDSR command, reading is possible but writing is not possible with the WRSR command. WEL is reset after the following operations. After power ON. The rising edge of CS after WRDI command recognition. The end of writing process after WRSR command recognition. The end of writing process after WRITE command recognition. WIP Write In Progress This indicates ReRAM Array and status register are in writing process. During this writing process, any commands except RDSR will not be executed (refer to “2. WIP polling”). With the RDSR command, reading is possible but writing is not possible with the WRSR command. ■ OP-CODE MB85AS4MT accepts 8 kinds of command specified in op-code. Op-code is a code composed of 8 bits shown in the table below. Do not input invalid codes other than those codes. If CS is risen while inputting op-code, the command are not performed. Name Description Op-code WREN Set Write Enable Latch 0000 0110B WRDI Reset Write Enable Latch 0000 0100B RDSR Read Status Register 0000 0101B WRSR Write Status Register 0000 0001B READ Read Memory Code 0000 0011B WRITE Write Memory Code 0000 0010B Read Device ID 1001 1111B Sleep Mode 1011 1001B RDID SLEEP 6 DS501-00045-1v0-E MB85AS4MT ■ COMMAND • WREN The WREN command sets WEL (Write Enable Latch) . WEL has to be set with the WREN command before writing operation (WRSR command and WRITE command) . CS 0 1 2 3 4 5 6 7 SCK SI Invalid 0 0 0 0 0 1 1 Invalid 0 High-Z SO • WRDI The WRDI command resets WEL (Write Enable Latch) . Writing operation (WRSR command and WRITE command) are not performed when WEL is reset. CS 0 1 2 3 4 5 6 7 SCK SI Invalid SO DS501-00045-1v0-E 0 0 0 0 0 1 0 0 Invalid High-Z 7 MB85AS4MT • RDSR The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. In the RDSR command, repeated reading of status register is enabled by sending SCK continuously before rising of CS. CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 0 Invalid 1 Data Out High-Z SO Invalid MSB LSB • WRSR The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR command. A SI value correspondent to bit 1 is ignored. Bit 0 of the status register cannot be written. The SI value corresponding to bit 0 is ignored. WP signal level shall be fixed before performing WRSR command, and do not change the WP signal level until the end of command sequence. After rising edge of CS, MB85AS4MT starts writing operation to nonvolatile register and set WIP bit in status register to “1”. After this writing operation has finished, reset this WIP bit from “1” to “0”. Although the RDSR command is executable for WIP polling during this writing process, any other commands will not be performed. CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK Data In Instruction SI SO 8 0 0 0 0 0 0 0 1 7 MSB High-Z 6 5 4 3 2 1 0 LSB DS501-00045-1v0-E MB85AS4MT • READ The READ command reads ReRAM memory cell array data. Arbitrary 24 bits address and op-code of READ are input to SI. The 5-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ command is completed, but keeps on reading with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK 24-bit Address OP-CODE Invalid 5 4 3 2 1 0 0 0 0 0 0 0 1 1 X X X X X 18 17 16 Data Out MSB LSB MSB LSB High-Z 7 6 5 4 3 2 1 0 SI SO Invalid • WRITE The WRITE command writes data to ReRAM memory cell array. WRITE op-code, arbitrary 24 bits of address and 8 bits of writing data are input to SI. The 5-bit upper address bit is invalid. During the CS is low, input writing data are temporary saved in the data register. The maximum writing data size is 256 bytes during this CS = low period. If the input writing data are more than 8 bits, it is possible to continue writing with automatic address increment. When it reaches the most significant address, it rolls over to the starting address, and writing cycle can be continued up to 256 bytes (which is the size of data register). Data exceed 256 bytes can not be written. After rising edge of CS, MB85AS4MT starts writing operation to nonvolatile memory and set WIP bit in status register to “1”. After this writing operation has finished, reset this WIP bit from “1” to “0”. Although the RDSR command is executable for WIP polling during this writing process, any other commands will not be performed. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK SI Data In 24-bit Address OP-CODE 0 0 0 0 0 0 1 0 X X X X X 18 17 16 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB SO DS501-00045-1v0-E High-Z LSB MSB LSB 9 MB85AS4MT • RDID The RDID command reads fixed Device ID. After performing RDID op-code to SI, 32-cycle clock is input to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. The output is in order of Manufacturer ID (8bit)/Continuation code (8bit)/Product ID (1st Byte)/Product ID (2nd Byte). In the RDID command, SO holds the output state of the last bit in 32-bit Device ID until CS is risen. RDID command is applicable to “Up to 25 MHz operation”. CS 0 1 2 3 4 5 6 7 1 0 0 1 1 1 1 1 8 31 32 33 34 35 36 37 38 39 9 10 11 SCK SI Invalid Data Out SO High-Z Data Out 8 31 30 29 28 7 6 5 4 3 2 MSB 1 0 LSB bit Manufacturer ID Continuation code Product ID (1st Byte) Product ID (2nd Byte) 10 7 0 0 6 0 1 5 0 1 Proprietary use 1 1 0 0 0 4 0 1 3 0 1 0 1 2 1 1 1 0 1 0 0 1 Hex 04H Fujitsu 7FH Density 0 0 1 Hex C9H Density: 01001B = 4 Mbit 1 Hex 03H Proprietary use 0 0 0 0 1 DS501-00045-1v0-E MB85AS4MT • SLEEP The SLEEP command shifts the LSI to a low power mode called “SLEEP mode”. The transition to the SLEEP mode is carried out at the rising edge of CS after operation code in the SLEEP command. However, when at least one SCK clock is inputted before the rising edge of CS after operation code in the SLEEP command, this SLEEP command is canceled. After the SLEEP mode transition, SCK and SI inputs are ignored and SO changes to a Hi-Z state. Enter Sleep Mode CS 0 1 2 3 4 5 6 7 1 0 1 1 1 0 0 1 Invalid SCK SI Invalid Hi-Z SO Sleep Mode Entry Returning to an normal operation from the SLEEP mode is carried out after tREC (Max 400 μs) time from the falling edge of CS (see the figure below). It is possible to return CS to H level before tREC time. However, it is prohibited to bring down CS to L level again during tREC period. CS CS tREC From this time Command input enable Exit Sleep Mode Sleep Mode Exit DS501-00045-1v0-E 11 MB85AS4MT ■ WRITING OPERATION OF NONVOLATILE MEMORY Each input data is not written to the nonvolatile memory by unit of byte right after its data input. Multiple bytes up to maximum 256 bytes are temporarily saved to the data register. After the command input is finished and rising edge of CS, start writing operation from this data register to the nonvolatile memory. 1. Address counter control In case of memory access by WRITE and READ commands, after the end of op-code and address input, it is possible to keep on accessing (= reading or writing) with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 8 cycles while CS is low level. However, for the WRITE command, continuous writing is restricted by the limit of buffer size in the data register. When it reaches the most significant address, it rolls over to the starting address, and this automatic address increment will be continued by the address counter control. Over write protection to the nonvolatile memory is enabled by BP0 and BP1 bits in status register. When the memory address exceed it from write protected block to unprotected block by address counter control, write to the unprotected block only. Similarly, when memory address exceed it from unprotected block to protected block, does not write to the protected block. MSB 7 6 bit number 5 4 3 2 1 LSB 0 Start address Start address+1 Address Start address+2 Most significant address-5 Most significant address-4 Most significant address-3 Most significant address-2 Most significant address-1 Most significant address 2. WIP polling After the last writing data was input, writing to the nonvolatile memory needs tWC waiting time from the rising edge of CS. This tWC time becomes larger than a minimum clock cycle. Production variation and operating condition are considered, and this maximum tWC value is defined. In the usual operation, this tWC time is shorter than the maximum value. Therefore, MB85AS4MT supports WIP polling to improve memory access by optimizing the waiting time. After starting the data writing to nonvolatile memory, MB85AS4MT sets “1” to a volatile register related to the WIP bit in status register. After finished the writing operation, reset this WIP bit from “1” to “0”. Although the usual commands are not executable during this writing process, only the RDSR command is acceptable. RDSR command outputs the value of status register to SO. It is possible to confirm if the internal writing operation to nonvolatile memory is finished or not, by checking the corresponding bit to WIP in output data from SO. 12 DS501-00045-1v0-E MB85AS4MT CS WRSR RDSR SCK SI WPEN busy X X X BP1 BP0 X X (Write process situation) wip (Internal volatile register for WIP) wel (Internal volatile register for WEL) SO WPEN X X X BP1 BP0 WEL WIP WPEN X X X BP1 BP0 WEL WIP RDSR command also outputs the WPEN, BP1 and BP0 of status register to SO. In the polling after WRSR command, MB85AS4MT outputs the WPEN, BP1 and BP0 data which is set before the writing to nonvolatile memory is completed. On the other hand for WEL and WIP, MB85AS4MT outputs (WEL,WIP)=2'b11 when the writing to nonvolatile memory is not completed. When it is competed, outputs (WEL,WIP)=2'b00. If continuously sending clocks to SCK during CS = low, it is also possible to keep on outputting WPEN to WIP bits in status register in unit of 8 cycles since 17th clock. In case the WIP polling is applied, WIP and WEL bits in status register output to SO by RDSR command are updated regularly. Figure shows the example of RDSR command input with continuously sending clocks over 17 during CS = low, before the writing process of WRSR command is finished. DS501-00045-1v0-E 13 MB85AS4MT ■ BLOCK PROTECT Writing protect block for WRITE command is configured by the value of BP0 and BP1 in the status register. BP1 BP0 Protected Block 0 0 None 0 1 60000H to 7FFFFH (upper 1/4) 1 0 40000H to 7FFFFH (upper 1/2) 1 1 00000H to 7FFFFH (all) ■ WRITING PROTECT Writing operation of the WRITE command and the WRSR command are protected with the value of WEL, WPEN, WP as shown in the table. WEL WPEN WP Protected Blocks Unprotected Blocks Status Register 0 X X Protected Protected Protected 1 0 X Protected Unprotected Unprotected 1 1 0 Protected Unprotected Protected 1 1 1 Protected Unprotected Unprotected ■ HOLD OPERATION Hold status is retained without aborting a command if HOLD is “L” level while CS is “L” level. The timing for starting and ending hold status depends on the SCK to be “H” level or “L” level when a HOLD pin input is transited to the hold condition as shown in the diagram below. In case the HOLD pin transited to “L” level when SCK is “L” level, return the HOLD pin to “H” level at SCK being “L” level. In the same manner, in case the HOLD pin transited to “L” level when SCK is “H” level, return the HOLD pin to “H” level at SCK being “H” level. Arbitrary command operation is interrupted in hold status, SCK and SI inputs become do not care. And, SO becomes High-Z while reading command (RDSR, READ). CS shall be set to “L” level during hold status. CS SCK HOLD Hold Condition 14 Hold Condition DS501-00045-1v0-E MB85AS4MT ■ ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Min Max Unit Power supply voltage* VDD − 0.5 + 4.0 V Input voltage* VIN − 0.5 VDD + 0.5 V VOUT − 0.5 VDD + 0.5 V TA − 40 + 85 °C Tstg − 55 + 125 °C Output voltage* Operation ambient temperature Storage temperature *:These parameters are based on the condition that VSS is 0 V. WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Power supply voltage*1 Operation ambient temperature *2 Value Unit Min Typ Max VDD 1.65 3.3 3.6 V TA − 40 ⎯ + 85 °C *1: These parameters are based on the condition that VSS is 0 V. *2: Ambient temperature when only this device is working. Please consider it to be the almost same as the package surface temperature. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. DS501-00045-1v0-E 15 MB85AS4MT ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics (within recommended operating conditions) Parameter Symbol Condition Input leakage current |ILI| Output leakage current |ILO| Operating power supply current IDD Standby current Value Unit Min Typ Max CS, WP, SCK, SI, HOLD = 0 V to VDD ⎯ ⎯ 1 μA SO = 0 V to VDD ⎯ ⎯ 1 μA SCK = 5 MHz (read) ⎯ 0.2 0.5 mA SCK = 5 MHz (write) ⎯ 1.3 3.0 mA ISB SCK = SI = CS = VDD ⎯ 10 45 μA Sleep current IZZ CS = VDD All inputs VSS or VDD ⎯ 2 5 μA Input high voltage VIH VDD = 1.65 V to 3.6 V VDD × 0.8 ⎯ VDD + 0.5 V Input low voltage VIL VDD = 1.65 V to 3.6 V − 0.5 ⎯ VDD × 0.2 V Output high voltage VOH IOH = − 1.5 mA @VDD ≥ 1.8 V VDD − 0.5 IOH = − 1.2 mA @VDD < 1.8 V ⎯ ⎯ V Output low voltage VOL ⎯ 0.4 V 16 IOL = 1.5 mA @VDD ≥ 1.8 V IOL = 1.2 mA @VDD < 1.8 V ⎯ DS501-00045-1v0-E MB85AS4MT 2. AC Characteristics Parameter Symbol Value Min Typ Max Unit Condition SCK clock frequency fCK 0 ⎯ 5 MHz Clock high time tCH 60 ⎯ ⎯ ns Clock low time tCL 60 ⎯ ⎯ ns tCSUH 60 ⎯ ⎯ tCSUL 60 ⎯ ⎯ tCSHH 60 ⎯ ⎯ tCSHL 60 ⎯ ⎯ tCSH 50 ⎯ ⎯ Output disable time tOD ⎯ ⎯ 60 ns Output data valid time tODV ⎯ ⎯ 60 ns Output hold time tOH 0 ⎯ ⎯ ns Deselect time tD 160 ⎯ ⎯ ns Data rising time tR ⎯ ⎯ 50 ns Data falling time tF ⎯ ⎯ 50 ns Data set up time tSU 20 ⎯ ⎯ ns Data hold time tH 20 ⎯ ⎯ ns HOLD set uptime tHS 20 ⎯ ⎯ ns HOLD hold time tHH 20 ⎯ ⎯ ns HOLD output floating time tHZ ⎯ ⎯ 60 ns HOLD output active time tLZ ⎯ ⎯ 60 ns Write cycle time tWC ⎯ 8500 17000 μs @50% data turn over (0xAAAA => 0xCCCC) ⎯ 16000 25000 μs @100% data turn over ⎯ ⎯ 400 μs Chip select set up time Chip select hold time SLEEP recovery time tREC ns CS rising to SCK rising CS falling to SCK rising SCK rising to CS falling ns SCK rising to CS rising SCK falling to CS rising AC Test Condition Power supply voltage : 1.65 V to 3.6 V Operation ambient temperature : − 40 °C to + 85 °C Input voltage magnitude : VDD × 0.8 ≤ VIH ≤ VDD 0 ≤ VIL ≤ VDD × 0.2 Input rising time : 5 ns Input falling time : 5 ns Input judge level : VDD/2 Output judge level : VDD/2 DS501-00045-1v0-E 17 MB85AS4MT AC Load Equivalent Circuit 3.3 V 1.2 k Output 30 pF 0.95 k 3. Pin Capacitance Parameter Symbol Condition Output capacitance CO Input capacitance CI VDD = VIN = VOUT = 0 V, f = 1 MHz, TA = +25 °C 18 Value Unit Min Max ⎯ 8 pF ⎯ 6 pF DS501-00045-1v0-E MB85AS4MT ■ TIMING DIAGRAM • Serial Data Timing Mode0 tD tCSUL tCSHL CS tCSUH tCSHH tCL SCK tCH tCSH tSU tH SI tOD tODV Hi-Z SO tOH Mode3 tD tCSHL tCSUL CS tCSHH tCSUH tCL SCK tCH tSU tH tCSH SI 㼠㻻㻰 tODV Hi-Z SO tOH : Hor L • Hold Timing CS SCK tHS tHH tHS tHS tHH tHS tHH tHH HOLD High-Z SO tHZ DS501-00045-1v0-E tLZ High-Z tHZ tLZ 19 MB85AS4MT ■ POWER ON/OFF SEQUENCE tpd tf tr tpu VDD VDD VDD (Min) VDD (Min) VIH (Min) VIH (Min) 1.0 V 1.0 V VIL (Max) VIL (Max) GND GND CS >VDD  0.8  CS CS >VDD  0.8  CS : don't care CS * : CS (Max) < VDD + 0.5 V Parameter Symbol Value Min Max Unit CS level hold time at power OFF tpd 25 ⎯ ms CS level hold time at power ON tpu 400 ⎯ μs Power supply rising time tr 0.05 ⎯ ms/V Power supply falling time tf 0.1 ⎯ ms/V If the device does not operate within the specified conditions of read cycle, write cycle or power on/off sequence, memory data can not be guaranteed. ■ ReRAM CHARACTERISTICS Parameter Value Unit Remarks Min Max 1.2 × 106 ⎯ Times/byte Operation Ambient Temperature TA = + 85 °C Data Retention 10 ⎯ Years Operation Ambient Temperature TA = + 85 °C Retention time of the first reading/writing data right after shipment. Data register size ⎯ 256 byte Write Endurance ■ NOTE ON USE We recommend programming of the device after reflow. Data written before reflow cannot be guaranteed. 20 DS501-00045-1v0-E MB85AS4MT ■ ESD AND LATCH-UP Test DUT Value ESD HBM (Human Body Model) JESD22-A114 compliant ≥ |2000 V| ESD MM (Machine Model) JESD22-A115 compliant ≥ |200 V| ESD CDM (Charged Device Model) JESD22-C101 compliant ≥ |1000 V| Latch-Up (I-test) JESD78 compliant MB85AS4MTPF-G-BCERE1 ⎯ Latch-Up (Vsupply overvoltage test) JESD78 compliant ⎯ Latch-Up (Current Method) Proprietary method ⎯ Latch-Up (C-V Method) Proprietary method ≥ |200 V| • Current method of Latch-Up Resistance Test Protection Resistance A Test terminal IIN VIN VDD + DUT - VSS VDD (Max.Rating) V Reference terminal Note : The voltage VIN is increased gradually and the current IIN of 300 mA at maximum shall flow. Confirm the latch up does not occur under IIN = ± 300 mA. In case the specific requirement is specified for I/O and IIN cannot be 300 mA, the voltage shall be increased to the level that meets the specific requirement. DS501-00045-1v0-E 21 MB85AS4MT • C-V method of Latch-Up Resistance Test Protection Resistance A 1 Test 2 terminal SW + VIN V - C 200pF VDD DUT VDD (Max.Rating) VSS Reference terminal Note : Charge voltage alternately switching 1 and 2 approximately 2 sec interval. This switching process is considered as one cycle. Repeat this process 5 times. However, if the latch-up condition occurs before completing 5times, this test must be stopped immediately. ■ MB85AS4MTPF (8-pin plastic SOP) REFLOW CONDITIONS AND FLOOR LIFE [ JEDEC MSL ] : Moisture Sensitivity Level 3 (ISP/JEDEC J-STD-020D) ■ CURRENT STATUS ON CONTAINED RESTRICTED SUBSTANCES This product complies with the regulations of REACH Regulations, EU RoHS Directive and China RoHS. 22 DS501-00045-1v0-E MB85AS4MT ■ ORDERING INFORMATION Part number MB85AS4MTPF-G-BCERE1 DS501-00045-1v0-E Package Shipping form Minimum shipping quantity 8-pin plastic SOP (FPT-8P-M11) Embossed Carrier tape 500 23 MB85AS4MT ■ PACKAGE DIMENSION 8-pin plastic SOP 1.27 mm Lead pitch Package width × package length 5.3 mm × 5.65 mm Lead shape Gullwing Sealing method Plastic mold Mounting heigth 1.73 mm MAX Weight TBD g (FPT-8P-M11) 8-pin plastic SOP 㸦FPT-8P-M11㸧 Note 1) *1: These dimensions do not include resin protrution. Note 2) *2: These dimensions do not include resin protrution. 㹼 0$; 㹼  SLQ SLQ ™5 SLQ SLQ ͆)͇  +0.063 0.064 7\S   +0.034 0.017 㹋 㹼 s 㹼  s s r 㹼  s 0$; s  7\S 7\S s 'HWDLOVRI͆)͇SDUW C 24 2016 FUJITSU SEMICONDUCTOR LIMITED Dimenssions in mm DS501-00045-1v0-E MB85AS4MT ■ MARKING [MB85AS4MTPF-G-BCERE1] AS4T 11624 V01 [FPT-08P-M11] DS501-00045-1v0-E 25 MB85AS4MT ■ MAJOR CHANGES IN THIS EDITION A change on a page is indicated by a vertical line drawn on the left side of that page. Page Section Change Results 6 14 26 ■ STATUS REGISTER Bit 6 to 4: revised to volatile memory. WEL: revised the reset condition. ■ HOLD OPERATION Revised CS operation during hold status. DS501-00045-1v0-E MB85AS4MT MEMO DS501-00045-1v0-E 27 MB85AS4MT FUJITSU SEMICONDUCTOR LIMITED Shin-Yokohama Chuo Building, 2-100-45 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa 222-0033, Japan http://jp.fujitsu.com/fsl/en/ All Rights Reserved. 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Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs and safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures into your facility, equipments and products such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. The products and technical information described in this document are subject to the Foreign Exchange and Foreign Trade Control Law of Japan, and may be subject to export or import laws or regulations in U.S. or other countries. You are responsible for ensuring compliance with such laws and regulations relating to export or re-export of the products and technical information described herein. All company names, brand names and trademarks herein are property of their respective owners. Edited: System Memory Business Division