MB85R1002PFTN-GE1

FUJITSU SEMICONDUCTOR DATA SHEET DS05-13104-3E Memory FRAM CMOS 1 M Bit (64 K × 16) MB85R1002 ■ DESCRIPTIONS The MB85R1002 is an FRAM (Ferroelectric Random Access Memory) chip consisting of 65,536 words x 16 bits of non-volatile memory cells created using ferroelectric process and silicon gate CMOS process technologies. The MB85R1002 is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MB85R1002 can be used for at least 1010 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM. The MB85R1002 uses a pseudo-SRAM interface that is compatible with conventional asynchronous SRAM. ■ FEATURES • • • • • • • Bit configuration Read/write endurance Operating power supply voltage Operating temperature range Data retention LB and UB data byte control Package : 65,536 words × 16 bits : 1010 times/bit (Min) : 3.0 V to 3.6 V : − 20 °C to +85 °C : 10 years (+55 °C) : 48-pin plastic TSOP (1) : 48-pin plastic FBGA Copyright©2005-2007 FUJITSU LIMITED All rights reserved MB85R1002 ■ PIN ASSIGNMENT (TOP VIEW) A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE CE2 GND UB LB VCC NC A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC GND I/O16 I/O8 I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 VCC I/O12 I/O4 I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 OE GND CE1 A0 (FPT-48P-M25) (Continued) 2 MB85R1002 (Continued) Top View INDEX 1 2 3 4 5 6 Bottom View A B C D E F G H 6 5 4 3 2 1 1 A B C D E F G H LB I/O9 2 OE UB 3 A0 A3 A5 NC NC A14 A12 A9 4 A1 A4 A6 A7 NC A15 A13 A10 5 A2 CE1 I/O2 I/O4 I/O5 I/O6 WE A11 6 CE2 I/O1 I/O3 VCC GND I/O7 I/O8 NC A B C D E F G H 6 CE2 I/O1 I/O3 VCC GND I/O7 I/O8 NC 5 A2 CE1 I/O2 I/O4 I/O5 I/O6 WE A11 4 A1 A4 A6 A7 NC A15 A13 A10 3 A0 A3 A5 NC NC A14 A12 A9 2 OE UB 1 LB I/O9 I/O10 I/O11 GND I/O12 VCC I/O16 NC I/O13 NC A8 I/O15 I/O14 I/O11 I/O10 I/O12 GND I/O13 NC A8 VCC I/O16 NC I/O14 I/O15 (BGA-48P-M23) ■ PIN DESCRIPTION Pin name A0 to A15 I/O1 to I/O16 CE1 CE2 WE OE LB, UB VCC GND NC Address In Data Input/Output Chip Enable 1 in Chip Enable 2 in Write Enable in Output Enable in Data Byte Control in Power Supply Ground No Connection 3 Function MB85R1002 ■ BLOCK DIAGRAM A0 · · · Address Latch. to Row Dec. Ferro Capacitor Cell A15 Column Dec. intCE2 S/A CE2 intCEB LB UB WE OE CE1 intCEB I/O8 · · to I/O1 · · intCE2 intOE intWE intCE2 I/O1 to I/O8 I/O9 to I/O16 I/O16 to I/O9 4 MB85R1002 ■ FUNCTION TRUTH TABLE Mode CE1 CE2 WE OE LB UB I/O1 to I/O8 I/O9 to I/O16 Supply Current H Standby Pre-charge X X X Read X L X X H X X H X H X X H X L X X X H L L H L X X X H L H L L H L L H L L H L Dout Dout High-Z Dout Dout High-Z Din Din High-Z Din Din High-Z Dout High-Z Dout Dout High-Z Dout Din High-Z Din Din High-Z Din Operation (ICC) High-Z High-Z Standby (ISB) L Read (Pseudo-SRAM, OE control*1) L H H L H L Write H L L X L H L Write (Pseudo-SRAM, WE control*2) L H H L H Notes : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance : Latch address and latch data at falling edge, : Latch address and latch data at rising edge *1 : OE control of the Pseudo-SRAM means the valid address at the falling edge of OE to read. *2 : WE control of the Pseudo-SRAM means the valid address and data at the falling edge of WE to write. 5 MB85R1002 ■ ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage* Input Voltage* Output Voltage* Ambient Operating Temperature Storage Temperature * : All voltages are referenced to GND. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Symbol VCC VIN VOUT TA Tstg Rating Min −0.5 −0.5 −0.5 −20 −40 Max +4.0 VCC + 0.5 VCC + 0.5 +85 +125 Unit V V V o o C C ■ RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage* Input Voltage (high)* Input Voltage (low)* Ambient Operating Temperature * : All voltages are referenced to GND. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Symbol VCC VIH VIL TA Value Min 3.0 VCC × 0.8 −0.5 − 20 Typ 3.3 ⎯ ⎯ ⎯ Max 3.6 VCC + 0.5 +0.6 +85 Unit V V V o C 6 MB85R1002 ■ ELECTRICAL CHARACTERISTICS 1. DC CHARACTERISTICS Parameter Input Leakage Current Output Leakage Current Operating Power Supply Current Symbol |ILI| |ILO| ICC (within recommended operating conditions) Value Test Conditions Unit Min Typ Max VIN = 0 V to VCC VOUT = 0 V to VCC, CE1 = VIH or OE = VIH CE1 = 0.2 V, CE2 = VCC−0.2 V, Iout = 0 mA*1 CE1 ≥ VCC−0.2 V Standby Current ISB CE2 ≤ 0.2 V*2 OE ≥ VCC−0.2 V, WE ≥ VCC−0.2 V*2 LB ≥ VCC−0.2 V, UB ≥ VCC−0.2 V*2 Output Voltage (high) Output Voltage (low) VOH VOL IOH = −0.1 mA IOL = 2.0 mA VCC × 0.8 ⎯ ⎯ ⎯ ⎯ 0.4 V V ⎯ 10 50 µA ⎯ ⎯ ⎯ ⎯ ⎯ 10 10 10 15 µA µA mA *1 : During the measurement of ICC , the Address, Data In were taken to only change once per active cycle. Iout : output current *2 : All pins other than setting pins should be input at the CMOS level voltages such as H ≥ VCC − 0.2 V, L ≤ 0.2 V. 7 MB85R1002 2. AC TEST CONDITIONS Supply Voltage : 3.0 V to 3.6 V Operating Temperature : −20 oC to +85 oC Input Voltage Amplitude : 0.3 V to 2.7 V Input Rising Time : 5 ns Input Falling Time : 5 ns Input Evaluation Level : 2.0 V / 0.8 V Output Evaluation Level : 2.0 V / 0.8 V Output Impedance : 50 pF (1) Read Operation Parameter Read Cycle time CE1 Active Time CE2 Active Time OE Active Time LB, UB Active Time Pre-charge Time Address Setup Time Address Hold Time OE Setup Time LB, UB Setup Time Output Data Hold time Output Set Time CE1 Access Time CE2 Access Time OE Access Time Output Floating Time Symbol tRC tCA1 tCA2 tRP tBP tPC tAS tAH tES tBS tOH tLZ tCE1 tCE2 tOE tOHZ (within recommended operating conditions) Value Min 150 120 120 120 120 20 0 50 0 5 0 30 ⎯ ⎯ ⎯ ⎯ Max ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 100 100 100 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 MB85R1002 (2) Write Operation (within recommended operating conditions) Parameter Write Cycle Time CE1 Active Time CE2 Active Time LB, UB Active Time Pre-Charge Time Address Setup Time Address Hold Time LB, UB Setup Time Write Pulse Width Data Setup Time Data Hold Time Write Setup Time (3) Power ON/OFF Sequence (within recommended operating conditions) Parameter CE1 LEVEL hold time for Power OFF CE1 LEVEL hold time for Power ON Symbol tpd tpu Value Min 85 85 Typ ⎯ ⎯ Max ⎯ ⎯ Unit ns ns Symbol tWC tCA1 tCA2 tBP tPC tAS tAH tBS tWP tDS tDH tWS Value Min 150 120 120 120 20 0 50 5 120 0 50 0 Max ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns ns ns ns 3. Pin Capacitance (f = 1 MHz, TA = +25 oC) Parameter Input Capacitance Output Capacitance Symbol CIN COUT Test Condition VIN = GND VOUT = GND Value Min ⎯ ⎯ Typ ⎯ ⎯ Max 10 10 Unit pF pF 9 MB85R1002 ■ TIMING DIAGRAMS 1. Read Cycle Timing 1 (CE1, CE2 Control) tRC tCA1 CE1 tPC CE2 tBS LB, UB tAS A0 to A15 Valid tES OE tCE1, tCE2 I/O1 to I/O16 tLZ tAH tCA2 tBP H or L tRP tOHZ High-Z Invalid tOH Valid Invalid 2. Read Cycle Timing 2 (OE Control) tCA1 CE1 CE2 tBS LB, UB tAS A0 to A15 Valid tAH tCA2 tBP H or L tRC OE tRP tPC tOE tLZ I/O1 to I/O16 Invalid tOH Valid tOHZ High-Z Invalid 10 MB85R1002 3. Write Cycle Timing 1 (CE1, CE2 Control) tWC CE1 tCA1 tPC CE2 tBS LB, UB tAS A0 to A15 Valid tAH tCA2 tBP H or L tWS WE tWP tDS tDH High-Z Data In Valid H or L 4. Write Cycle Timing 2 (WE Control) tCA1 CE1 CE2 tBS LB, UB tAS A0 to A15 Valid tAH tCA2 tBP H or L tWC tWP tPC WE tDS tDH High-Z Data In Valid H or L 11 MB85R1002 ■ POWER ON/OFF SEQUENCE tpd tpu VCC CE2 3.0 V VIH (Min) VCC CE2 3.0 V VIH (Min) 1.0 V 1.0 V VIL (Max) VIL (Max) GND CE2 ≤ 0.2 V CE1 > VCC × 0.8* CE1 : Don't Care CE1 > VCC × 0.8* GND CE1 CE1 * : CE1 (Max) < VCC + 0.5 V Note : You can choose either of CE1 or CE2, or both for disenable control of the device. ■ NOTES ON USE Data that is written prior to IR reflow is not guaranteed to be retained after IR reflow. ■ ORDERING INFOMATION Part number MB85R1002PFTN-GE1 MB85R1002BGT-GE1 Package 48-pin plastic TSOP(1) (FPT-48P-M25) 48-pin plastic FBGA (BGA-48P-M23) 12 MB85R1002 ■ PACKAGE DIMENSIONS 48-pin plastic TSOP(1) Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 12.00 × 12.40 mm Gullwing Plastic mold 1.20 mm MAX 0.37 g P-TSOP(1)48-12×12.4-0.50 (FPT-48P-M25) Code (Reference) 48-pin plastic TSOP(1) (FPT-48P-M25) Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max). Note 2) *2 : These dimensions do not include resin protrusions. Note 3) Pin widths and pin thicknesses include plating thickness. Note 4) Pin widths do not include tie bar cutting burrs. 0.10±0.05 (Stand off) (.004±.002) LEAD No. 1 48 INDEX 0.50(.020) 0.22 –0.04 *1 12.00±0.10 +0.05 +.002 .009 –.002 0.10(.004) M (.472±.004) 24 25 14.00±0.20(.551±.008) *2 12.40±0.10(.488±.004) 1.13±0.07 (Mounting height) (.044±.003) Details of "A" part "A" 0˚~8˚ +0.05 +.002 0.08(.003) 0.145 –0.03 .006 –.001 0.25(.010) 0.60±0.15 (.024±.006) C 2003 FUJITSU LIMITED F48043S-c-2-2 Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html (Continued) 13 MB85R1002 (Continued) 48-pin plastic FBGA Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.75 mm 8.10 mm × 6.10 mm Ball Plastic mold 1.10 mm Max 0.08 g (BGA-48P-M23) 48-pin plastic FBGA (BGA-48P-M23) 5.25(.207) 8.10±0.20(.319±.008) 0.95 –0.10 .043 –.004 (Mounting height) 0.25±0.10(.010±.004) (Stand off) +0.15 +.006 0.75(.030)TYP B 6 A 6.10±0.20 (.240±.008) 3.75 (.148) 5 4 3 2 1 (INDEX AREA) S H G F E D C B M A SAB 48-ø0.35±0.05 (48-ø.014±.002) ø0.08(.003) 0.10(.004) C 2007 FUJITSU LIMITED B48023S-c-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 14 MB85R1002 FUJITSU LIMITED All Rights Reserved. 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