MB85R2001

FUJITSU SEMICONDUCTOR DATA SHEET DS05-13107-2E Memory FRAM CMOS 2 M Bit (256 K × 8) MB85R2001 ■ DESCRIPTIONS The MB85R2001 is an FRAM (Ferroelectric Random Access Memory) chip consisting of 262,144 words x 8 bits of non-volatile memory cells created using ferroelectric process and silicon gate CMOS process technologies. The MB85R2001 is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MB85R2001 can be used for at least 1010 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM. The MB85R2001 uses a pseudo-SRAM interface that is compatible with conventional asynchronous SRAM. ■ FEATURES • • • • • • Bit configuration Read/write endurance Operating power supply voltage Operating temperature range Data retention Package : 262,144 words × 8 bits : 1010 times/bit (Min) : 3.0 V to 3.6 V : − 20 °C to + 85 °C : 10 years ( + 55 °C) : 48-pin plastic TSOP (1) Copyright©2007 FUJITSU LIMITED All rights reserved MB85R2001 ■ PIN ASSIGNMENTS (TOP VIEW) A11 A9 NC A8 A13 WE CE2 A15 NC VCC NC NC GND NC NC VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 OE NC GND A10 CE1 NC I/O8 I/O7 I/O6 I/O5 I/O4 VCC NC I/O3 I/O2 I/O1 NC NC NC A0 A1 GND A2 A3 (FPT-48P-M25) ■ PIN DESCRIPTIONS Pin name A0 to A17 I/O1 to I/O8 CE1 CE2 WE OE VCC GND NC Address Input Data Input/Output Chip Enable 1 Input Chip Enable 2 Input Write Enable Input Output Enable Input Power Supply Ground No Connection Function 2 MB85R2001 ■ BLOCK DIAGRAM A0 · · · Address Latch. Row Dec. Ferro Capacitor Cell to A17 Column Dec. intCE2 S/A CE2 intCEB WE OE intCEB CE1 · · I/O8 to I/O1 intCE2 intOE intWE intCE2 I/O1 to I/O8 3 MB85R2001 ■ FUNCTION TRUTH TABLE Operation Mode Standby Pre-charge CE1 H X X Read Read (Pseudo-SRAM, OE control*1) Write L Write (Pseudo-SRAM, WE control*2) L H H L L H H CE2 X L X H WE X X H H H L H Din OE X X H L Dout Operation (ICC) High-Z Standby (ISB) I/O1 to I/O8 Supply Current L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance : Latch address and latch data at falling edge, : Latch address and latch data at rising edge *1 : OE control of the Pseudo-SRAM means the valid address at the falling edge of OE to read. *2 : WE control of the Pseudo-SRAM means the valid address and data at the falling edge of WE to write. 4 MB85R2001 ■ ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage* Input Voltage* Output Voltage* Ambient Operating Temperature Storage Temperature * : All voltages are referenced to GND = 0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Symbol VCC VIN VOUT TA Tstg Rating Min −0.5 −0.5 −0.5 −20 −40 Max +4.0 VCC+0.5 VCC+0.5 +85 +125 Unit V V V °C °C ■ RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage* Input Voltage (high)* Input Voltage (low)* Operating Temperature Symbol VCC VIH VIL TA Value Min 3.0 VCC x 0.8 −0.5 −20 Typ 3.3 ⎯ ⎯ ⎯ Max 3.6 VCC + 0.5 +0.8 +85 Unit V V V °C * : All voltages are referenced to GND = 0 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 5 MB85R2001 ■ ELECTRICAL CHARACTERISTICS 1. DC CHARACTERISTICS Parameter Input Leakage Current Output Leakage Current Supply Current Symbol |ILI| |ILO| ICC Test Condition VIN = 0 V to VCC VOUT = 0 V to VCC, CE1 = VIH or OE = VIH CE1 = 0.2 V, CE2 = VCC−0.2 V, IOUT = 0 mA*1 CE1 ≥ VCC−0.2 V Standby Current Output Voltage (high) Output Voltage (low) ISB VOH VOL CE2 ≤ 0.2 V*2 OE ≥ VCC−0.2 V, WE ≥ VCC−0.2 V*2 IOH = −0.1 mA IOL = 2.0 mA VCC x 0.8 ⎯ ⎯ ⎯ ⎯ 0.4 V V ⎯ 10 50 µA (within recommended operating conditions) Value Unit Min Typ Max ⎯ ⎯ ⎯ ⎯ ⎯ 10 10 10 15 µA µA mA *1 : During the measurement of ICC , the Address, Data In were taken to only change once per active cycle. IOUT : output current *2 : All pins other than setting pins should be input at the CMOS level voltages such as H ≥ VCC − 0.2 V, L ≤ 0.2 V. 6 MB85R2001 2. AC CHARACTERISTICS • AC TEST CONDITIONS Supply Voltage Operating Temperature Input Voltage Amplitude Input Rising Time Input Falling Time Input Evaluation Level Output Evaluation Level Output Impedance (1) Read Operation (within recommended operating conditions) Parameter Read Cycle Time CE1 Active Time OE Active Time Pre-charge Time Address Setup Time Address Hold Time OE Setup Time Output Hold Time Output Set Time CE1 Access Time CE2 Access Time OE Access Time Output Floating Time (2) Write Operation (within recommended operating conditions) Parameter Write Cycle Time CE1 Active Time CE2 Active Time Pre-charge Time Address Setup Time Address Hold Time Write Pulse Width Data Setup Time Data Hold Time Write Setup Time Symbol tWC tCA1 tCA2 tPC tAS tAH tWP tDS tDH tWS Value Min 150 120 120 20 5 50 120 0 50 5 Max ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns ns 7 Symbol tRC tCA1 tRP tPC tAS tAH tES tOH tLZ tCE1 tCE2 tOE tOHZ Value Min 150 120 120 20 5 50 5 0 30 ⎯ ⎯ ⎯ ⎯ Max ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 100 100 100 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns : 3.0 V to 3.6 V : −20 °C to +85 °C : 0.3 V to 2.7 V : 5 ns : 5 ns : 2.0 V / 0.8 V : 2.0 V / 0.8 V : 50 pF MB85R2001 (3) Power ON/OFF Sequence (within recommended operating conditions) Parameter CE1 level hold time for Power OFF CE1 level hold time for Power ON Symbol tpd tpu Value Min 85 85 Typ ⎯ ⎯ Max ⎯ ⎯ Unit ns ns 3. Pin Capacitance (f = 1 MHz, TA = +25 °C) Parameter Input Capacitance Output Capacitance Symbol CIN COUT Test Condition VIN = GND VOUT = GND Value Min ⎯ ⎯ Typ ⎯ ⎯ Max 10 10 Unit pF pF 8 MB85R2001 ■ TIMING DIAGRAMS 1. Read Cycle Timing 1 (CE1, CE2 Control) tRC tCA1 CE1 tCA2 tPC CE2 tAS A0 to A17 Valid tES OE tAH H or L tRP tCE1, tCE2 tOHZ High-Z Invalid I/O1 to I/O8 tLZ Invalid tOH Valid 2. Read Cycle Timing 2 (OE Control) tCA1 CE1 CE2 tCA2 tAS A0 to A17 Valid tAH H or L tRC OE tRP tPC tOE tLZ I/O1 to I/O8 Invalid tOH Valid tOHZ High-Z Invalid 9 MB85R2001 3. Write Cycle Timing 1 (CE1, CE2 Control) tWC tCA1 CE1 tPC CE2 tAH tCA2 tAS A0 to A17 Valid H or L tWS WE tWP tDS tDH High-Z Data In Valid H or L 4. Write Cycle Timing 2 (WE Control) tCA1 CE1 CE2 tCA2 tAS A0 to A17 Valid tAH H or L tWC tWP tPC WE tDS tDH High-Z Data In Valid H or L 10 MB85R2001 ■ POWER ON/OFF SEQUENCE tpd tpu VCC CE2 3.0 V VIH (Min) VCC CE2 3.0 V VIH (Min) 1.0 V 1.0 V VIL (Max) VIL (Max) CE2 ≤ 0.2 V GND GND CE1 > VCC × 0.8∗ CE1 : Don't Care CE1 > VCC × 0.8∗ CE1 CE1 * : CE1 (Max) < VCC + 0.5 V Note : You can choose either of CE1 or CE2, or both for disenable control of the device. ■ NOTES ON USE Data that is written prior to IR reflow is not guaranteed to be retained after IR reflow. ■ ORDERING INFOMATION Part number MB85R2001PFTN-GE1 Package 48-pin plastic TSOP(1) (FPT-48P-M25) 11 MB85R2001 ■ PACKAGE DIMENSIONS 48-pin plastic TSOP(1) Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 12.00 × 12.40 mm Gullwing Plastic mold 1.20 mm MAX 0.37 g P-TSOP(1)48-12×12.4-0.50 (FPT-48P-M25) Code (Reference) 48-pin plastic TSOP(1) (FPT-48P-M25) Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max). Note 2) *2 : These dimensions do not include resin protrusions. Note 3) Pin widths and pin thicknesses include plating thickness. Note 4) Pin widths do not include tie bar cutting burrs. 0.10±0.05 (Stand off) (.004±.002) LEAD No. 1 48 INDEX 0.50(.020) 0.22 –0.04 *1 12.00±0.10 (.472±.004) +0.05 +.002 .009 –.002 0.10(.004) M 24 25 14.00±0.20(.551±.008) *2 12.40±0.10(.488±.004) 1.13±0.07 (Mounting height) (.044±.003) Details of "A" part "A" 0˚~8˚ +0.05 +.002 0.08(.003) 0.145 –0.03 .006 –.001 0.25(.010) 0.60±0.15 (.024±.006) C 2003 FUJITSU LIMITED F48043S-c-2-2 Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 12 MB85R2001 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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