MB85R256G

FUJITSU SEMICONDUCTOR FACT SHEET NP501-00004-0v01-E FRAM MB85R256G MB85R256G is a 256K-bits FRAM LSI using the ferroelectric process and CMOS process technologies for forming the nonvolatile memory cells. Because FRAM is able to write high-speed even though a nonvolatile memory, it is suitable for the log management and the storage of the resume data, etc. MB85R256G uses a pseudo-SRAM interface compatible with conventional asynchronous SRAM. ■ FEATURES  Bit configuration ：32,768 words × 8 bits  Read/write endurance ：1010 times/bit  Peripheral circuit CMOS construction  Operating power supply voltage ：2.7 to 3.6V  Operating temperature range ：-40℃ to +85℃  Data retention ：10 years (+70℃)  Package ：28-pins, SOP flat package ：28-pins, TSOP(1) flat package ■ ORDERING INFORMATION Product name TBD Package Plastic・SOP,28-pins (FPT-28P-M17) 8.60mm×17.75mm,1.27mm pitch Plastic・TSOP,28-pins (FPT-28P-M19) 11.80mm×8.00mm,0.55mm pitch Plastic・SOP,28-pins (FPT-28P-M17) 8.60mm×17.75mm,1.27mm pitch Remarks - TBD - TBD Embossed Carrier tape ■ PACKAGE EXAMPLE OF REFERENCE Plastic ・ TSOP、28-pins (FPT-28P-M19) November, 2010 1/2 Copyright©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved MB85R256G PRELIMINARY ■ PIN ASSIGNMENT （TOP VIEW） A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 FPT-28P-M19 Pin No. 1 to 10, 21, 23 to 26 Pin name A0 to A14 I/O0 to I/O7 CE WE OE VCC GND Description Address input Data input/output Chip enable input Write enable input Output enable input Power supply (＋3.3V Typ.) Ground FPT-28P-M17 11 to 13, 15 to 19 20 27 22 28 14 ■ BLOCK DIAGRAM A14 to A10 Block decoder A14 to A0 Address latch A7 to A0 Row decoder FRAM array: 32,768 × 8 CE Pseudo-SRAM interface logic circuit A8, A9 Column decoder WE Control logic I/O latch bus driver I/O0-I/O7 I/O0 I/O7 to OE NP501-00004-0v01-E November, 2010 2/2 Copyright©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved