FUJITSU SEMICONDUCTOR
DATA SHEET
DS501-00006-3v1-E
Memory FRAM
4 M Bit (256 K × 16)
MB85R4002A
■ DESCRIPTIONS
The MB85R4002A is an FRAM (Ferroelectric Random Access Memory) chip consisting of 262,144 words ×
16 bits of nonvolatile memory cells fabricated using ferroelectric process and silicon gate CMOS process
technologies.
The MB85R4002A is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85R4002A can be used for 1010 read/write operations, which is a significant
improvement over the number of read and write operations supported by Flash memory and E2PROM.
The MB85R4002A uses a pseudo-SRAM interface that is compatible with conventional asynchronous SRAM.
■ FEATURES
•
•
•
•
•
•
Bit configuration
LB and UB data byte control
Read/write endurance
Data retention
Operating power supply voltage
Low power operation
: 262,144 words × 16 bits
: 1010 times / byte
: 10 years ( + 55 °C), 55 years ( + 35 °C)
: 3.0 V to 3.6 V
: Operating power supply current 15 mA (Typ)
Standby current 50 μA (Typ)
• Operation ambient temperature range : − 40 °C to + 85 °C
• Package
: 48-pin plastic TSOP (FPT-48P-M48)
RoHS compliant
Copyright©2011-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2013.4
MB85R4002A
■ PIN ASSIGNMENTS
(TOP VIEW)
A15
A14
A13
A12
A11
A10
A9
A8
NC
DNU
WE
CE2
VSS
UB
LB
VDD
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
VSS
I/O16
I/O8
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
VDD
I/O12
I/O4
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
OE
VSS
CE1
A0
(FPT-48P-M48)
■ PIN DESCRIPTIONS
2
Pin Number
Pin Name
Functional Description
1 to 8, 17 to 25, 48
A0 to A17
29 to 36, 38 to 45
I/O1 to I/O16
Data Input/Output pins
26
CE1
Chip Enable 1 Input pin
12
CE2
Chip Enable 2 Input pin
11
WE
Write Enable Input pin
28
OE
Output Enable Input pin
14, 15
LB, UB
16, 37
VDD
Supply Voltage pins
Connect all two pins to the power supply.
13, 27, 46
VSS
Ground pins
Connect all three pins to ground.
9, 47
NC
No Connect pins
Leave these pins open, or connect to VDD or
VSS.
10
DNU
Address Input pins
Data Byte Control Input pins
Do Not Use pin
Make sure to connect this pin to VDD.
DS501-00006-3v1-E
MB85R4002A
■ BLOCK DIAGRAM
Address Latch
Row Decoder
A0
A17
FRAM Array
262,144 × 16
Column Decoder
S/A
intWE
intOE
CE2
CE1
WE
OE
LB
UB
I/O1 to I/O8
I/O9 to I/O16
I/O16
I/O9
I/O8
I/O1
DS501-00006-3v1-E
3
MB85R4002A
■ FUNCTIONAL TRUTH TABLE
Mode
Standby Precharge
Supply
Current
Hi-Z
Hi-Z
Standby
(ISB)
L
Data Output
Data Output
L
H
Data Output
Hi-Z
H
L
Hi-Z
Data Output
L
L
Data Output
Data Output
L
H
Data Output
Hi-Z
H
L
Hi-Z
Data Output
L
L
Data Output
Data Output
L
H
Data Output
Hi-Z
H
L
Hi-Z
Data Output
L
L
Data Input
Data Input
L
H
Data Input
Hi-Z
H
L
Hi-Z
Data Input
L
L
Data Input
Data Input
L
H
Data Input
Hi-Z
H
L
Hi-Z
Data Input
L
L
Data Input
Data Input
L
H
Data Input
Hi-Z
H
L
Hi-Z
Data Input
WE
OE
LB
UB
H
X
X
X
X
X
X
L
X
X
X
X
X
X
H
H
X
X
X
X
X
X
H
H
L
H
L
Read
L
L
H
H
H
L
H
L
H
Write
L
Write
(Pseudo-SRAM,
WE control*2)
I/O9 to I/O16
CE2
H
Read
(Pseudo-SRAM,
OE control*1)
I/O1 to I/O8
CE1
L
L
H
Note: L = VIL, H = VIH, X can be either H, L,
H
H
or
Operation
(IDD)
, Hi-Z = High Impedance
: Latch address and latch data at falling edge,
: Latch address and latch data at rising edge
*1 : OE control of the Pseudo-SRAM means the valid address at the falling edge of OE to read.
*2 : WE control of the Pseudo-SRAM means the valid address and data at the falling edge of WE to write.
4
DS501-00006-3v1-E
MB85R4002A
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Min
Max
Unit
Power Supply Voltage*
VDD
−0.5
+4.0
V
Input Pin Voltage*
VIN
−0.5
VDD + 0.5 ( ≤ 4.0)
V
VOUT
−0.5
VDD + 0.5 ( ≤ 4.0)
V
TA
−40
+85
o
TSTG
−55
+125
o
Output Pin Voltage*
Operation Ambient Temperature
Storage Temperature
C
C
* : All voltages are referenced to VSS (ground 0 V).
WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without
limitation, voltage, current or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Value
Symbol
Min
Typ
Max
Unit
Power Supply Voltage*
VDD
3.0
3.3
3.6
V
High Level Input Voltage*
VIH
VDD × 0.8
⎯
VDD + 0.5
( ≤ 4.0)
V
Low Level Input Voltage*
VIL
−0.5
⎯
+0.6
TA
− 40
⎯
+85
Operation Ambient Temperature
V
o
C
* : All voltages are referenced to VSS (ground 0 V).
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of
device and could result in device failure.
No warranty is made with respect to any use, operating conditions or combinations not represented
on this data sheet. If you are considering application under any conditions other than listed herein,
please contact sales representatives beforehand.
DS501-00006-3v1-E
5
MB85R4002A
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter
Symbol
Condition
(within recommended operating conditions)
Value
Unit
Min
Typ
Max
Input Leakage Current*1
|ILI|
VIN = 0 V to VDD
⎯
⎯
10
μA
Output Leakage Current
|ILO|
VOUT = 0 V to VDD,
CE1 = VIH or OE = VIH
⎯
⎯
10
μA
Operating Power Supply
Current*2
IDD
CE1 = 0.2 V, CE2 = VDD − 0.2 V,
Iout = 0 mA
⎯
15
20
mA
⎯
50
150
μA
VDD × 0.8
⎯
⎯
V
⎯
⎯
0.4
V
CE1 ≥ VDD − 0.2 V
Standby Current*3
ISB
CE2 ≤ 0.2 V
OE ≥ VDD − 0.2 V, WE ≥ VDD − 0.2 V
LB ≥ VDD − 0.2 V, UB ≥ VDD − 0.2 V
High Level Output Voltage
VOH
IOH = − 1.0 mA
Low Level Output Voltage
VOL
IOL = 2.0 mA
*1 : This also applies to DNU pins.
*2 : During the measurement of IDD , the Address and Data In were taken to only change once per active cycle.
Iout : output current
*3 : All pins other than setting pins shall be input at the CMOS level voltages such as H ≥ VDD − 0.2 V, L ≤ 0.2 V.
6
DS501-00006-3v1-E
MB85R4002A
2. AC Characteristics
• AC Test Conditions
Power Supply Voltage
Operation Ambient Temperature
Input Voltage Amplitude
Input Rising Time
Input Falling Time
Input Evaluation Level
Output Evaluation Level
Output Load Capacitance
: 3.0 V to 3.6 V
: −40 oC to +85 oC
: 0.3 V to 2.7 V
: 5 ns
: 5 ns
: 2.0 V / 0.8 V
: 2.0 V / 0.8 V
: 50 pF
(1) Read Cycle
Parameter
Symbol
Value
Min
Max
Unit
Read Cycle time
tRC
150
⎯
ns
CE1 Active Time
tCA1
120
⎯
ns
CE2 Active Time
tCA2
120
⎯
ns
OE Active Time
tRP
120
⎯
ns
LB, UB Active Time
tBP
120
⎯
ns
Precharge Time
tPC
20
⎯
ns
Address Setup Time
tAS
0
⎯
ns
Address Hold Time
tAH
50
⎯
ns
OE Setup Time
tES
0
⎯
ns
LB, UB Setup Time
tBS
5
⎯
ns
Output Data Hold time
tOH
0
⎯
ns
Output Set Time
tLZ
30
⎯
ns
CE1 Access Time
tCE1
⎯
120
ns
CE2 Access Time
tCE2
⎯
120
ns
OE Access Time
tOE
⎯
120
ns
Output Floating Time
tOHZ
⎯
20
ns
DS501-00006-3v1-E
7
MB85R4002A
(2) Write Cycle
Parameter
Symbol
Value
Min
Max
Unit
Write Cycle Time
tWC
150
⎯
ns
CE1 Active Time
tCA1
120
⎯
ns
CE2 Active Time
tCA2
120
⎯
ns
LB, UB Active Time
tBP
120
⎯
ns
Precharge Time
tPC
20
⎯
ns
Address Setup Time
tAS
0
⎯
ns
Address Hold Time
tAH
50
⎯
ns
LB, UB Setup Time
tBS
5
⎯
ns
Write Pulse Width
tWP
120
⎯
ns
Data Setup Time
tDS
0
⎯
ns
Data Hold Time
tDH
50
⎯
ns
Write Setup Time
tWS
0
⎯
ns
3. Pin Capacitance
Parameter
Input Capacitance
Symbol
CIN
Output Capacitance
COUT
DNU Pin Input Capacitance
CDNU
8
Condition
VDD = VIN = VOUT = 0 V,
f = 1 MHz, TA = + 25 oC
Value
Unit
Min
Typ
Max
⎯
⎯
10
pF
⎯
⎯
10
pF
⎯
⎯
10
pF
DS501-00006-3v1-E
MB85R4002A
■ TIMING DIAGRAMS
1. Read Cycle Timing (CE1 Control)
tRC
tCA1
tPC
CE1
CE2
tBS
tBP
LB, UB
tAS
A0 to A17
tAH
Valid
H or L
tES
tRP
OE
tCE1
tOH
tLZ
I/O1 to I/O16
tOHZ
Hi-Z
Valid
Invalid
Invalid
:H or L
2. Read Cycle Timing (CE2 Control)
CE1
tRC
tPC
tCA2
CE2
tBS
tBP
LB, UB
tAS
A0 to A17
tAH
Valid
H or L
tES
tRP
OE
tCE2
tOH
tLZ
I/O1 to I/O16
tOHZ
Hi-Z
Valid
Invalid
Invalid
:H or L
DS501-00006-3v1-E
9
MB85R4002A
3. Read Cycle Timing (OE Control)
CE1
CE2
tBS
tBP
LB, UB
tAS
A0 to A17
tAH
Valid
H or L
tRC
tPC
tRP
OE
tOE
tOHZ
tOH
tLZ
I/O1 to I/O16
Hi-Z
Valid
Invalid
Invalid
:H or L
4. Write Cycle Timing (CE1 Control)
tWC
tCA1
tPC
CE1
CE2
tBS
tBP
LB, UB
tAS
A0 to A17
tAH
Valid
H or L
tWS
tWP
WE
tDS
tDH
Hi-Z
Valid
Data In
H or L
:H or L
10
DS501-00006-3v1-E
MB85R4002A
5. Write Cycle Timing (CE2 Control)
CE1
tWC
tPC
tCA2
CE2
tBS
tBP
LB, UB
tAS
A0 to A17
tAH
Valid
H or L
tWS
tWP
WE
tDH
tDS
Hi-Z
Valid
Data In
H or L
:H or L
6. Write Cycle Timing (WE Control)
CE1
CE2
tBS
tBP
LB, UB
tAS
A0 to A17
tAH
Valid
H or L
tWC
tWP
tPC
WE
tDS
tDH
Hi-Z
Data In
Valid
H or L
:H or L
DS501-00006-3v1-E
11
MB85R4002A
■ POWER ON/OFF SEQUENCE
tPD
tR
tPU
VDD
VDD
CE2
CE2
3.0 V
3.0 V
VIH (Min)
VIH (Min)
1.0 V
1.0 V
VIL (Max)
VIL (Max)
CE2 ≤ 0.2 V
0V
0V
CE1 > VDD × 0.8*
CE1 > VDD × 0.8*
CE1 : Don't Care
CE1
CE1
* : CE1 (Max) < VDD + 0.5 V
Parameter
Value
Symbol
Min
Typ
Max
Unit
CE1 level hold time for Power OFF
tPD
85
⎯
⎯
ns
CE1 level hold time for Power ON
tPU
85
⎯
⎯
ns
Power supply rising time
tR
0.05
⎯
200
ms
If the device does not operate within the specified conditions of read cycle, write cycle or power on/off
sequence, memory data can not be guaranteed.
In case the power is turned on or off, use the power supply reset IC and fix the CE2 to low level, to prevent
unexpected writing. Use either of CE1 or CE2, or both to disable control of the device.
■ FRAM CHARACTERISTICS
Item
Min
Max
Read/Write Endurance*1
1010
⎯
10
⎯
55
⎯
Data Retention*2
Unit
Parameter
Times/byte Operation Ambient Temperature TA = + 85 °C
Years
Operation Ambient Temperature TA = + 55 °C
Operation Ambient Temperature TA = + 35 °C
*1 : Total number of reading and writing defines the minimum value of endurance, as an FRAM memory operates
with destructive readout mechanism.
*2 : Minimun values define retention time of the first reading/writing data right after shipment, and these values
are calculated by qualification results.
■ NOTES ON USE
Data written before performing IR reflow is not guaranteed after IR reflow.
12
DS501-00006-3v1-E
MB85R4002A
■ ESD AND LATCH-UP
Test
DUT
Value
ESD HBM (Human Body Model)
JESD22-A114 compliant
≥ |2000 V|
ESD MM (Machine Model)
JESD22-A115 compliant
≥ |200 V|
ESD CDM (Charged Device Model)
JESD22-C101 compliant
⎯
Latch-Up (I-test)
JESD78 compliant
MB85R4002ANC-GE1
Latch-Up (Vsupply overvoltage test)
JESD78 compliant
⎯
⎯
Latch-Up (Current Method)
Proprietary method
≥ |300 mA|
Latch-Up (C-V Method)
Proprietary method
⎯
• Current method of Latch-Up Resistance Test
Protection Resistor
A
Test terminal
IIN
VIN
VDD
+
DUT
-
VSS
VDD
(Max.Rating)
V
Reference
terminal
Note : The voltage VIN is increased gradually and the current IIN of 300 mA at maximum shall flow.
Confirm the latch up does not occur under IIN = ± 300 mA.
In case the specific requirement is specified for I/O and IIN cannot be 300 mA, the voltage shall be
increased to the level that meets the specific requirement.
DS501-00006-3v1-E
13
MB85R4002A
• C-V method of Latch-Up Resistance Test
Protection Resistor
A
1
Test
2 terminal
SW
+
VIN
V
-
C
200pF
VDD
DUT
VDD
(Max.Rating)
VSS
Reference
terminal
Note : Charge voltage alternately switching 1 and 2 approximately 2 sec interval. This switching process is
considered as one cycle.
Repeat this process 5 times. However, if the latch-up condition occurs before completing 5 times, this
test must be stopped immediately.
14
DS501-00006-3v1-E
MB85R4002A
■ REFLOW CONDITIONS AND FLOOR LIFE
Item
Condition
Method
IR (infrared reflow) , Convection
Times
2
Before unpacking
Please use within 2 years after production.
From unpacking to 2nd reflow
Within 8 days
In case over period of floor life
Baking with 125 °C+/-3 °C for
24hrs+2hrs/-0hrs is required.
Then please use within 8 days.
(Please remember baking is up to 2 times)
Floor life
Floor life condition
Between 5 °C and 30 °C and also below 70%RH required.
(It is preferred lower humidity in the required temp range.)
Reflow Profile
260°C
255°C
Liquidous
Temperature
170 °C
to
190 °C
(b)
RT
(c)
(a)
(a) Average ramp-up rate
(b) Preheat & Soak
(c) Average ramp-up rate
(d) Peak temperature
(d’) Liquidous temperature
(e) Cooling
(d)
(e)
(d')
: 1 °C/s to 4 °C/s
: 170 °C to 190 °C, 60 s to 180 s
: 1 °C/s to 4 °C/s
: Temperature 260 °C Max; 255 °C within 10 s
: Up to 230 °C within 40 s or
Up to 225 °C within 60 s or
Up to 220 °C within 80 s
: Natural cooling or forced cooling
Note : Temperature on the top of the package body is measured.
DS501-00006-3v1-E
15
MB85R4002A
■ RESTRICTED SUBSTANCES
This product complies with the regulations below (Based on current knowledge as of November 2011).
• EU RoHS Directive (2002/95/EC)
• China RoHS (Administration on the Control of Pollution Caused by Electronic Information Products
(
))
• Vietnam RoHS (30/2011/TT-BCT)
Restricted substances in each regulation are as follows.
Substances
Threshold
Contain status*
Lead and its compounds
1,000 ppm
❍
Mercury and its compounds
1,000 ppm
❍
100 ppm
❍
Hexavalent chromium compound
1,000 ppm
❍
Polybrominated biphenyls (PBB)
1,000 ppm
❍
Polybrominated diphenyl ethers (PBDE)
1,000 ppm
❍
Cadmium and its compounds
* : The mark of “❍” shows below a threshold value.
16
DS501-00006-3v1-E
MB85R4002A
■ ORDERING INFORMATION
Part Number
MB85R4002ANC-GE1
DS501-00006-3v1-E
Package
Shipping form
Minimum shipping
quantity
48-pin plastic TSOP
(FPT-48P-M48)
Tray
1
17
MB85R4002A
■ PACKAGE DIMENSIONS
48-pin plastic TSOP
Lead pitch
0.50 mm
Package width ×
package length
12.00 mm × 12.40 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.20 mm MAX
Weight
0.36 g
(FPT-48P-M48)
Note 1) # : Resin protrusion. (Each side : +0.15 (.006) Max).
Note 2) * : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
48-pin plastic TSOP
(FPT-48P-M48)
0.10±0.05 (.004±.002)
(STAND OFF)
1
48
0.50(.020)
INDEX
#12.00±0.10
(.472±.004)
+0.05
0.22 –0.04
(.009 +.002
–.002 )
24
0.10(.004)
M
25
1.13±0.07 (.044±.003)
(MOUNTING HEIGHT)
Details of A part
14.00±0.20(.551±.008)
*12.40±0.10(.488±.004)
0.25(.010)
+0.05
0.145 –0.03
(.006 +.002
–.001 )
C
18
0.08(.003)
2010 FUJITSU SEMICONDUCTOR LIMITED F48048Sc-1-1
A
0.60±0.15
(.024±.006)
0~8
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
DS501-00006-3v1-E
MB85R4002A
■ MARKING
[MB85R4002A-GE1]
JAPAN
MB85R4002A
1150 E00
E1
[FPT-48P-M48]
DS501-00006-3v1-E
19
MB85R4002A
■ SHIPPING FORM
1. Tray
1.1 Tray Dimensions
TSOP48, 56 (I)
Maximum storage capacity
PKG code
pcs/tray
pcs/inner box
pcs/outer box
128
1280
5120
322.6
315
15 × 19.0 = 285
15
15
8-NO HOLES
7.62
1.27
7 × 14.9 = 104.3
135.9
15.8
FPT-48P-M48
25.4
13.564
12.2
10
8
1.27
1
1 1
1
10
R4.7
19
15.8
1 1
8
0.9
1.27
1
0.9
1.27
1.27
7.62
7.62
1
2
1.27
15.564
14.2
11.8
10
15
C
25.4
255.3
2
34.3
SEC.A-A
5
B
A
0.76
C3
2.54
A
15.8
B
14.9
SEC.B-B
2002-2010 FUJITSU SEMICONDUCTOR LIMITED TSOP (1) 12 x 14 : JHB-TS1-1214-1-D-3
(Dimensions in mm)
Material : Conductive polyphenyleneether
Heat proof temperature : 125 °C MAX
Weight : 133 g
20
DS501-00006-3v1-E
MB85R4002A
1.2 IEC (JEDEC) TRAY Dry Pack Packing Specifications
Product (IC)
Tray
Index mark
IC
Chamfered corner
Tray
*5
Humidity
indicator
Desiccant *5
Label I *1*4*5
*5
Dry pack
↓
Inner box
Heat seal
Binding band
or tape
Aluminum laminated bag *5
Filled tray + one empty tray
Cushioning material *5
Inner box *5
*5
Binding band
or tape
Label I *1*4*5
Cushioning material *5
Outer box
Outer box *2*3*5
Use adhesive tapes. *5
Label II-A *4*5
Label II-B *4*5
*1: For a product of witch part number is suffixed with "E1", a " G
bag and the inner boxes.
Pb
" marks is display to the moisture barrier
*2: The size of the outer box may be changed depending on the quantity of inner boxes.
*3: The space in the outer box will be filled with empty inner boxes, or cushions, etc.
*4: Please refer to an attached sheet about the indication label.
*5: The packing materials except tray may differ slightly from the color and dimensions depend on country of
manufacture.
Note: The packing specifications may not be applied when the product is delivered via a distributer.
DS501-00006-3v1-E
21
MB85R4002A
1.3 Product label indicators
Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping)
[C-3 Label (50mm x 100mm) Supplemental Label (20mm x 100mm)]
XXXXXXXXXXXXXX
(Customer part number or FJ part number)
C-3 Label
(LEAD FREE mark)
(3N)1 XXXXXXXXXXXXXX XXX
(Part number and quantity)
QC PASS
(3N)2 XXXXXXXXXX XXXXXX
(FJ control number)
XXX pcs
XXXXXXXXXXXXXX
(Quantity)
(Customer part number or FJ part number)
(Customer part number or FJ part number
bar code)
XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx
XXXXXXXXXXXXXX (Customer part number or FJ part number)
(FJ control number bar code)
XX/XX
XXXX-XXX XXX
(Package count)
XXXX-XXX XXX
XXXXXXXXXX (FJ control number ) (Lot Number and quantity)
XXXXXXXXXXXXXX (Comment)
Perforated line
Supplemental Label
Label II-A: Label on Outer box [D Label] (100mm x 100mm)
D Label
XXXXXXXXXXXXX (Customer Name)
(CUST.)
XXXXXXXXX (Delivery Address)
(DELIVERY POINT)
XXXXXXXXXXXXXX
(TRANS.NO.) (FJ control number)
XXXXXXXXXXXXXX
(PART NO.)
(Customer part number or
FJ part number)
XXX (FJ control number)
XXX (FJ control number)
XXX (FJ control number)
XXXXXXXXXXXXXX
(Part number)
(PART NAME) XXXXXXXXXXXXXX (Part number)
XXX/XXX
(Q’TY/TOTAL Q’TY)
(CUSTOMER'S
REMARKS)
XXXXXXXXXXXXXXXXXXXX
(3N)3 XXXXXXXXXXXXXX XXX
XX
(UNIT)
(PACKAGE COUNT)
XXX/XXX
(FJ control number + Product quantity)
(FJ control number + Product quantity
bar code)
(Part number + Product quantity)
(3N)4 XXXXXXXXXXXXXX XXX
(Part number + Product quantity bar code)
(3N)5 XXXXXXXXXX
(FJ control number)
(FJ control number bar code)
Label II-B: Outer boxes product indicate
XXXXXXXXXXXXXX
(Lot Number)
XXXX-XXX
XXXX-XXX
(Part number)
(Count)
X
X
(Quantity)
XXX
XXX
XXX
Note: Depending on shipment state, "Label II-A" and "Label II-B" on the external boxes might not be printed.
22
DS501-00006-3v1-E
MB85R4002A
1.4 Dimensions for Containers
(1) Dimensions for inner box
H
W
L
L
W
H
165
360
75
(Dimensions in mm)
(2) Dimensions for outer box
H
W
L
L
W
H
355
385
195
(Dimensions in mm)
DS501-00006-3v1-E
23
MB85R4002A
■ MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page
Section
Change Results
■ FEATURES
Revised the Data retention.
10 years ( + 55 °C)
→ 10 years ( + 55 °C), 55 years ( + 35 °C)
4
■ FUNCTIONAL TRUTH TABLE
Revised the table.
5
■ ABSOLUTE MAXIMUM RANGES
Revised the Storage Temperature.
− 40 °C → + 55 °C
■ POWER ON/OFF SEQUENCE
Deleted the following description:
“Because turning the power-on from an intermediate level
cause malfunction, when the power is turned on, VDD is required to be started from 0V (see the figure below).”
1
Moved the following description under the table:
“If the device does not operate within the specified conditions of read cycle, write cycle or power on/off sequence,
memory data can not be guaranteed. In case the power is
turned on or off, use the power supply reset IC and fix the
CE2 to low level, to prevent unexpected writing. Use either
of CE1 or CE2, or both to disable control of the device.”
12
■ FRAM CHARACTERISTICS
24
Revised the table and Note.
DS501-00006-3v1-E
MB85R4002A
MEMO
DS501-00006-3v1-E
25
MB85R4002A
MEMO
26
DS501-00006-3v1-E
MB85R4002A
MEMO
DS501-00006-3v1-E
27
MB85R4002A
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
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http://cn.fujitsu.com/fsp/
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the right to make changes to the information contained in this document without notice. Please contact your FUJITSU
SEMICONDUCTOR sales representatives before order of FUJITSU SEMICONDUCTOR device.
Information contained in this document, such as descriptions of function and application circuit examples is presented solely for
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Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs and
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