MB85RC128PNF-G-JNE1

FUJITSU SEMICONDUCTOR DATA SHEET DS05–13110–3E Memory FRAM 128 K (16 K × 8) Bit I2C MB85RC128 ■ DESCRIPTION The MB85RC128 is a FRAM (Ferroelectric Random Access Memory) Stand-Alone chip in a configuration of 16,384 words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. The MB85RC128 adopts the two-wire serial interface. Unlike SRAM, the MB85RC128 is able to retain data without using a data backup battery. The read/write endurance of the nonvolatile memory cells used for the MB85RC128 has improved to be at least 1010 cycles, significantly out performing Flash memory and E2PROM in the number. The MB85RC128 does not need a polling sequence after writing to the memory such as the case of Flash memory nor E2PROM. ■ FEATURES • • • • Bit configuration : 16,384 words × 8 bits Operating power supply voltage : 2.7 V to 3.6 V Operating frequency : 400 kHz (Max) Two-wire serial interface : I2C-bus specification ver. 2.1 compliant, supports Standard-mode/ Fast-mode. Fully controllable by two ports: serial clock (SCL) and serial data (SDA). Operating temperature range : − 40 °C to +85 °C Data retention : 10 years ( + 75 °C) Read/write endurance : 1010 times Package : Plastic / SOP, 8-pin (FPT-8P-M02) Low power consumption : Operating current 0.15 mA (Max: @400 kHz), Standby current 5 μA (Typ) • • • • • Copyright©2010-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2011.6 MB85RC128 ■ PIN ASSIGNMENT (TOP VIEW) A0 1 8 VDD A1 2 7 WP A2 3 6 SCL VSS 4 5 SDA (FPT-8P-M02) ■ PIN FUNCTIONAL DESCRIPTIONS Pin Number Pin Name Functional Description Device Address pins The MB85RC128 can be connected to the same data bus up to 8 devices. Device addresses are used in order to identify each of the devices. Connect these pins to VDD pin or VSS pin externally. Only if the combination of VDD and VSS pins matches a device, an address and a code inputted from the SDA pin, the device operates. In the open pin state, A0, A1, and A2 pins are pulled-down and recognized as “L”. Ground pin Serial Data I/O pin This is an I/O pin of serial data for performing bidirectional communication of address and writing or reading data of FRAM memory cell array. It is an open drain output that may be wired OR with other open drain or open collector signals on the bus, so a pull-up resistance is required to be connected to the external circuit. Serial Clock pin This is a clock input pin for input/output serial data. Data is sampled on the rising edge of the clock and output on the falling edge. Write Protect pin When Write Protect pin is “H”, writing operation is disabled. When Write Protect pin is “L”, the entire memory region can be overwritten. Reading operation is always enabled regardless of the Write Protect pin input level. The Write Protect pin is pulled down internally to VSS pin, therefore if the Write Protect pin is open, the pin status is detected as “L” (write enabled). Supply Voltage pin 1 to 3 A0 to A2 4 VSS 5 SDA 6 SCL 7 WP 8 VDD 2 DS05–13110–3E MB85RC128 ■ BLOCK DIAGRAM Serial/Parallel Converter SDA Row Decoder WP Control Logic SCL Address Counter FRAM Array 16,384 × 8 Column Decoder/Sense Amp/ Write Amp A0, A1, A2 ■ I2C (Inter-Integrated Circuit) The MB85RC128 has a two-wire serial interface, supports the I2C bus, and operates as a slave device. The I2C bus defines communication roles of “master” and “slave” devices, with the master side holding the authority to initiate control. Furthermore, a I2C bus connection is possible where a single master device is connected to multiple slave devices. In this case, it is necessary to assign a unique device address to the slave device, the master side starts communication after specifying the slave to communicate by addresses. • I2C Interface System Configuration Example VDD Pull-up Resistors SCL SDA I2C Bus Master I2C Bus MB85RC128 A2 0 A1 0 A0 0 I2C Bus MB85RC128 A2 0 A1 0 A0 1 I2C Bus MB85RC128 A2 0 A1 1 A0 0 ... Device address DS05–13110–3E 3 MB85RC128 ■ I2C COMMUNICATION PROTOCOL The I2C bus is a two wire serial interface that uses a bidirectional data bus (SDA) and serial clock (SCL). A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The SDA signal should change while SCL is Low. However, as an exception, when starting and stopping communication sequence, SDA is allowed to change while SCL is High. • Start Condition To start read or write operations by the I2C bus, change the SDA input from High to Low while the SCL input is in the high state. • Stop Condition To stop the I2C bus communication, change the SDA input from Low to High while the SCL input is in the high state. In the reading operation, inputting the stop condition finishes reading and enters the standby state. In the writing operation, inputting the stop condition finishes inputting the rewrite data. • Start Condition, Stop Condition SCL SDA Start Stop Note : The FRAM device does not need the programming wait time (tWC) after issuing the Stop Condition during the write operation. 4 DS05–13110–3E MB85RC128 ■ ACKNOWLEDGE (ACK) In the I2C bus, serial data including address or memory information is sent in units of 8 bits. The acknowledge signal indicates that every each 8 bits of the data is successfully sent and received. The information receiver side usually outputs “L” every time on the 9th SCL clock after each 8 bits are successfully transmitted. On the transmitter side, the bus is temporarily released to Hi-Z every time on this 9th clock to allow the acknowledge signal to be received and checked. During this Hi-Z-released period, the receiver side pulls the SDA line down to indicate “L” that the previous 8bits communication is successfully received. If the information receiver side detects Stop condition before driving the acknowledge “L”, the read operation ends and the I2C bus enters the standby state. If Stop condition is not sent, nor does the transmitter detect the acknowledge “L”, the bus remains in the released state “H” without doing anything. • Acknowledge timing overview diagram SCL 1 2 3 8 9 SDA The transmitter side should always release SDA on the 9th bit. At this time, the receiver side outputs a pull-down to indicate a successful byte transfer (ACK response). ACK Start DS05–13110–3E 5 MB85RC128 ■ DEVICE ADDRESS WORD (Slave address) Following the start condition, the bus master sends the 8bits device address word (Slave address) to start I2C communication. The device address word (8bits) consists of a device Type code (4bits), device address code (3bits), and a read/write code (1bit). • Device Type Code (4bits) The upper 4 bits of the device address word are a device type code that identifies the device type, and are fixed at “1010” for the MB85RC128. • Device Address Code (3bits) Following the device type code, the 3 bits of the device address code are input in order of A2, A1, and A0 pins. Each MB85RC128 is given a unique 3bits code on the device address pin (external hardware pin A2, A1, and A0). When the device address code is received by the slave device, the slave only responds if the hardware device address of which is equal to its unique 3bits code. • Read/Write Code (1bit) The 8th bit of the device address word is the R/W (read/write) code. When the R/W code is “L”, a write operation is enabled, and the R/W code is “H”, a read operation is enabled for the MB85RC128. 6 DS05–13110–3E MB85RC128 ■ DATA STRUCTURE In the I2C bus, the acknowledge “L” is output on the 9th bit after the 8 bits of the device and address word following the start condition. After confirming the acknowledge response at the slave, the I2C master outputs 8bits × 2 memory address to the I2C slave. When the memory address input ends, the slave again outputs the acknowledge “L”. After this operation, the I/O data follows in units of 8 bits, with the acknowledge “L” output after every 8bits. It is determined by the R/W code whether the data line is driven by the master or the slave. For a write operation the slave will accept 8bits from the master then send an acknowledge. If the master detects the acknowledge, the master will transfer the next 8bits. For a read operation the slave will place 8bits on the I2C bus, then wait for an acknowledge from the master. • Data Structure Diagram Start SCL 1 2 3 4 5 6 7 8 9 1 2 .. ACK SDA S 1 0 1 0 A2 A1 A0 R/W A .. Access from master Access from slave S Start Condition A ACK ■ FRAM ACKNOWLEDGE -- POLLING NOT REQUIRED The MB85RC128 performs write operations at the same speed as read operations, so any waiting time for an ACK polling* does not occur. The write cycle takes no additional time. *: As to E2PROM, the Acknowledge Polling is performed as a progress check in the write programming step. It places NAK condition on the bus as of “not acknowledged” during the writing programming period. The busy status for the write programming is given from 9th ACK bit. That “done” condition is placed onto I2C bus by E2PROM I2C device and your program had to poll the bus in order to sense that condition. ■ WRITE PROTECT (WP) The entire memory array can be write protected using the Write Protect pin. When the Write Protect is set to “H”, the entire memory map will be write protected. When the write protect pin is “L”, all addresses may be overwritten. Note : The Write Protect pin is pulled down internally to VSS pin, therefore if the Write Protect pin is open, the pin status is detected as Low (write enabled). DS05–13110–3E 7 MB85RC128 ■ COMMAND • Byte Write If the 8th bit of the device address word (R/W = 0) is sent following the start condition, the slave responds with an ACK. After this ACK, write addresses and data are sent in the same way, and the write ends by master, generating a stop condition at the end. S 1 0 1 0 A2 A1 A0 0 A Address High 8bits A Address Low 8bits A Write Data 8bits AP 00 XXXXXX X X X X X X XX Access from master MSB LSB Access from slave S Start Condition P Stop Condition A ACK Note : In the MB85RC128, input “00” as the upper 2 bits of the MSB. • Page Write If additional 8bits are sent after the same command as Byte Write, a page write is performed. If more bytes are sent than will fit up to the end of the address, the address rolls over to 0000H. Therefore, if more than 8KBytes are sent, the data is overwritten in order starting from the start of the FRAM memory address that was written first. Because FRAM performs write operations at bus speed, the data will be written to FRAM after the ACK response finishes immediately. Address High 8bits Address Low 8bits Write Data 8bits Write Data S 1 0 1 0 A2 A1 A0 0 A A A A ... AP Access from master Access from slave S Start Condition P Stop Condition A ACK Note : It is not necessary to take a period for internal write programming cycles from the buffer to the memory after the stop condition is generated. 8 DS05–13110–3E MB85RC128 • Current Address Read When the previous write or read operation finishes successfully up to the stop command and if the last accessed address is taken to be “n”, then the address at “n+1” is read by sending the following command unless turning the power off. If the end of the address range is reached internally, the address counter will roll over to 0000H. The current address is undefined immediately after the power is turned on. Access from master Access from slave (n+1) address S 1 0 1 0 A2 A1 A0 1 A Read Data 8bits NP S Start Condition P Stop Condition A ACK N NACK • Random Read The one byte of data at the address as saved in the buffer can be read out synchronously to SCL by specifying the address in the same way as for a write, and then issuing another start condition and sending the Control Byte (R/W = 1). The final NACK is issued by the receiver that receives the data. In this case, this bit is issued by the master side. n address S 1 0 1 0 A2 A1 A0 0 A Address High 8bits A Address Low 8bits AS 1 0 1 0 A2 A1 A0 1 A Read Data 8bits NP Access from master Access from slave S Start Condition P Stop Condition A ACK N NACK DS05–13110–3E 9 MB85RC128 • Sequential Read Data can be received continuously following the control byte after specifying the address the same as for Random Read. If the read exceeds the end of address for the MB85RC128, the internal read address automatically rolls over to 0000H. ... A Read Data 8bits A Read Data ... A Read Data 8bits NP Access from master Access from slave P Stop Condition A ACK N NACK 10 DS05–13110–3E MB85RC128 ■ ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage* Input pin voltage* Output pin voltage* Ambient temperature Storage temperature Symbol VCC VIN VOUT TA Tstg Rating Min − 0.5 − 0.5 − 0.5 − 40 − 40 Max +4.0 VCC + 0.5 ( ≤ 4.0) VCC + 0.5 ( ≤ 4.0) + 85 + 125 Unit V V V °C °C * : These parameters are based on the condition that VSS is 0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Power supply voltage* “H” level input voltage* “L” level input voltage* Ambient temperature Symbol VCC VIH VIL TA Value Min 2.7 VCC × 0.8 − 0.5 − 40 Typ 3.3 ⎯ ⎯ ⎯ Max 3.6 VCC + 0.5 ( ≤ 4.0) + 0.6 + 85 Unit V V V °C * : These parameters are based on the condition that VSS is 0 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. DS05–13110–3E 11 MB85RC128 ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics (within recommended operating conditions) Parameter Input leakage current Output leakage current Operating power supply current Standby current “L” level output voltage Symbol |ILI| |ILO| ICC ISB VOL Condition SCL, SDA = 0 V to VCC A0, A1, A2, WP = 0 V or VCC VOUT = 0 V to VDD SCL = 400 kHz SCL, SDA = VCC A0, A1, A2, WP = 0 V or VCC IOL = 2 mA Value Min ⎯ ⎯ ⎯ ⎯ ⎯ Typ ⎯ ⎯ 100 5 ⎯ Max 1 1 150 20 0.4 Unit μA μA μA μA V 2. AC Characteristics Parameter SCL clock frequency Clock high time Clock low time SCL/SDA rise time SCL/SDA fall time Start condition hold Start condition setup SDA input hold SDA input setup SDA output hold Stop condition setup SDA output access after SCL fall Pre-charge time Pulse width ignored (Input Filter on SCL and SDA) Symbol FSCL THIGH TLOW Tr Tf THD:STA TSU:STA THD:DAT TSU:DAT TDH:DAT TSU:STO TAA TBUF TSP Value Min 0 600 1300 ⎯ ⎯ 600 600 0 100 0 600 ⎯ 1300 ⎯ Max 400 ⎯ ⎯ 300 300 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 900 ⎯ 50 Unit kHz ns ns ns ns ns ns ns ns ns ns ns ns ns AC characteristics were measured under the following measurement conditions. Power supply voltage Operating temperature Input rise time Input fall time Input judge level Output judge level : 2.7 V to 3.6 V : − 40 °C to + 85 °C : 5 ns : 5 ns : VCC/2 : VCC/2 Input voltage magnitude : 0.3 V to 2.7 V 12 DS05–13110–3E MB85RC128 3. AC Timing Definitions TSU:DAT THD:DAT SCL VIH VIL VIH VIH VIL VIH VIL VIH VIL Start VIH VIL VIL Stop VIH VIL SDA VIH VIL VIH VIL TSU:STA THD:STA Tr THIGH TLOW VIH VIL VIH VIL Tf TSU:STO SCL VIH VIL VIH VIL Stop VIH VIL VIL Tbuf Start VIH VIL SDA VIH VIL VIH Tr Taa T TDH:DAT f VIH Tsp SCL VIL VIH VIL SDA VIL Valid VIH VIL VIL 1/FSCL 4. Pin capacitance Parameter I/O capacitance Input capacitance Symbol CI/O CIN Conditions VIN = VOUT = 0 V, f = 1 MHz, TA = + 25 °C Value Min ⎯ ⎯ Typ ⎯ ⎯ Max 15 15 Unit pF pF DS05–13110–3E 13 MB85RC128 5. AC Test Load Circuit 3.3 V 1 kΩ Output 100 pF 14 DS05–13110–3E MB85RC128 ■ POWER ON SEQUENCE tpd VCC tr tpu VCC 2.7 V VIH (Min) 2.7 V VIH (Min) 1.0 V 1.0 V VIL (Max) VIL (Max) 0V 0V SDA, SCL SDA, SCL >VCC × 0.8 * SDA, SCL : Don't care SDA, SCL >VCC × 0.8 * SDA, SCL * : SDA, SCL (Max) < VCC + 0.5 V Parameter SDA, SCL level hold time during power down SDA, SCL level hold time during power up Power supply rise time Symbol tpd tpu tr Value Min 85 85 10 Max ⎯ ⎯ ⎯ Unit ns ns μs ■ NOTES ON USE • Data written before performing IR reflow is not guaranteed. • VDD pin is required to be rising from 0 V because turning the power on from an intermediate level may cause malfunctions, when the power is turned on. During the access period from the start condition to the stop condition, keep the level of WP, A0, A1, and A2 pins to “H” or “L”. DS05–13110–3E 15 MB85RC128 ■ ORDERING INFORMATION Part number MB85RC128PNF-G-JNE1 MB85RC128PNF-G-JNERE1 Package 8-pin, plastic SOP (FPT-8P-M02) 8-pin, plastic SOP (FPT-8P-M02) Embossed Carrier tape Remarks 16 DS05–13110–3E MB85RC128 ■ PACKAGE DIMENSION 8-pin plastic SOP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 1.27 mm 3.9 mm × 5.05 mm Gullwing Plastic mold 1.75 mm MAX 0.06 g (FPT-8P-M02) 8-pin plastic SOP (FPT-8P-M02) Note 1) *1 : These dimensions include resin protrusion. Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. +.010 *1 5.05 –0.20 .199 –.008 8 +0.25 0.22 –0.07 5 +0.03 +.001 .009 –.003 *2 3.90±0.30 6.00±0.40 (.154±.012) (.236±.016) Details of "A" part 45° 1.55±0.20 (Mounting height) (.061±.008) 0.25(.010) 0.40(.016) 1 4 "A" 0~8° 1.27(.050) 0.44±0.08 (.017±.003) 0.13(.005) M 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.15±0.10 (.006±.004) (Stand off) 0.10(.004) C 2002-2010 FUJITSU SEMICONDUCTOR LIMITED F08004S-c-4-9 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ DS05–13110–3E 17 MB85RC128 MEMO 18 DS05–13110–3E MB85RC128 MEMO DS05–13110–3E 19 MB85RC128 FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 902 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fsk/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fss/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. 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