MB85RC16PNF-G-JNERE1

FUJITSU SEMICONDUCTOR DATA SHEET DS501-00001-2v0-E Memory FRAM 16 K (2 K × 8) Bit I2C MB85RC16 ■ DESCRIPTION The MB85RC16 is an FRAM (Ferroelectric Random Access Memory) chip in a configuration of 2,048 words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. Unlike SRAM, the MB85RC16 is able to retain data without using a data backup battery. The memory cells used in the MB85RC16 have at least 1010 Read/Write operation endurance per bit, which is a significant improvement over the number of read and write operations supported by other nonvolatile memory products. The MB85RC16 can provide writing in one byte units because the long writing time is not required unlike Flash memory and E2PROM. Therefore, the writing completion waiting sequence like a write busy state is not required. ■ FEATURES • • • • • • • • • Bit configuration : 2,048 words × 8 bits Operating power supply voltage : 2.7 V to 3.6 V Operating frequency : 1 MHz (Max) Two-wire serial interface : Fully controllable by two ports: serial clock (SCL) and serial data (SDA). Operating temperature range : − 40 °C to + 85 °C Data retention : 10 years ( + 75 °C) Read/Write endurance : 1010 times Package : Plastic / SOP, 8-pin (FPT-8P-M02) Low power consumption : Operating current 0.1mA (Max: @1 MHz), Standby current 0.1 μA (Typ) Copyright©2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2011.6 MB85RC16 ■ PIN ASSIGNMENT (TOP VIEW) NC 1 8 VDD NC 2 7 WP NC 3 6 SCL VSS 4 5 SDA (FPT-8P-M02) ■ PIN FUNCTIONAL DESCRIPTIONS 2 Pin Number Pin Name 1 to 3 NC Unconnected pins Leave it unconnected. 4 VSS Ground pin 5 SDA Serial Data I/O pin This is an I/O pin of serial data for performing bidirectional communication of memory address and writing or reading data. It is possible to connect some devices. It is an open drain output, so a pull-up resistance is required to be connected to the external circuit. 6 SCL Serial Clock pin This is a clock input pin for input/output timing serial data. Data is sampled on the rising edge of the clock and output on the falling edge. 7 WP Write Protect pin When Write Protect pin is “H” level, writing operation is disabled. When Write Protect pin is “L” level, the entire memory region can be overwritten. Reading operation is always enabled regardless of the Write Protect pin state. The write protect pin is internally pulled down to VSS pin, and that is recognized as “L” level (the state that writing is enabled) when the pin is the open state. 8 VDD Supply Voltage pin Functional Description DS501-00001-2v0-E MB85RC16 ■ BLOCK DIAGRAM Control circuit SCL WP Row Decoder Serial/Parallel Converter Memory Address Counter SDA FRAM Array 2,048 × 8 Column Decoder/Sense Amp/ Write Amp ■ I2C (Inter-Integrated Circuit) The MB85RC16 has the two-wire serial interface and the I2C bus, and operates as a slave device. The I2C bus defines communication roles of “master” and “slave” devices, with the master side holding the authority to initiate control. Furthermore, a I2C bus connection is possible where a single master device is connected to multiple slave devices in a party-line configuration. • I2C Interface System Configuration Example VDD Pull-up Resistors SCL SDA I2C Bus Master DS501-00001-2v0-E I2C Bus MB85RC16 I2C Bus Other slave 3 MB85RC16 ■ I2C COMMUNICATION PROTOCOL The I2C bus provides communication by two wires only, therefore, the SDA input should change while SCL is the “L” level. However, when starting and stopping the communication sequence, SDA is allowed to change while SCL is the “H” level. • Start Condition To start read or write operations by the I2C bus, change the SDA input from the “H” level to the “L” level while the SCL input is in the “H” level. • Stop Condition To stop the I2C bus communication, change the SDA input from the “L” level to the “H” level while the SCL input is in the “H” level. In the reading operation, inputting the stop condition finishes reading and enters the standby state. In the writing operation, inputting the stop condition finishes inputting the rewrite data. • Start Condition, Stop Condition SCL SDA Start Stop Note : The FRAM device does not need the programming wait time (tWC) after issuing the Stop Condition during the write operation. 4 DS501-00001-2v0-E MB85RC16 ■ ACKNOWLEDGE (ACK) In the I2C bus, serial data including memory address or memory information is sent in units of 8 bits. The acknowledge signal indicates that every 8 bits of the data is successfully sent and received. The receiver side usually outputs the “L” level every time on the 9th SCL clock after every 8 bits are successfully transmitted. On the transmitter side, the bus is temporarily released on this 9th clock to allow the acknowledge signal to be received and checked. During this released period, the receiver side pulls the SDA line down to indicate that the communication works correctly. If the receiver side receives the stop condition before transmitting the acknowledge “L” level, the read operation ends and the I2C bus enters the standby state. If the acknowledge “L” level is not detected, and the Stop condition is not sent, the bus remains in the released state without doing anything. • Acknowledge timing overview diagram 1 SCL 2 3 8 SDA 9 ACK Start The transmitter side should always release SDA on the 9th bit. At this time, the receiver side outputs a pull-down if the receive of the previous 8 bit works correctly (ACK response). ■ MEMORY ADDRESS STRUCTURE The MB85RC16 has the memory address buffer to store the 11-bit information for the memory address. As for byte write, page write and random read commands, the complete 11-bit memory address is configured by inputting the memory upper address (3 bits) and the memory lower address (8 bits), and saving to the memory address buffer and access to the memory is performed. As for a current address read command, the complete 11-bit memory address is configured by inputting the memory upper address (3 bits) and by the memory address lower 8-bit which has saved in the memory address buffer, and saving to the memory address buffer and access to the memory is performed. DS501-00001-2v0-E 5 MB85RC16 ■ DEVICE ADDRESS WORD Following the start condition, the 8 bit device address word is input. Inputting the device address word decides whether the master or the slave drives the data line. However, the clock is always driven by the master. The device address word (8bits) consists of a device Type code (4bits), memory upper address code (3bits), and a Read/Write code (1bit). • Device Type Code (4bits) The upper 4 bits of the device address word are a device type code that identifies the device type, and are fixed at “1010” for the MB85RC16. • Memory Upper Address Code (3bits) Following the device type code, the 3 bits of the memory upper address code are input. The slave address selection is not performed by the external pin setting on this device. These 3 bits are not the setting bits for the slave address, but the upper 3-bit setting bits for the memory address. • Read/Write Code (1bit) The 8th bit of the device address word is the R/W (Read/Write) code. When the R/W code is “0” input, a write operation is enabled, and the R/W code is “1” input, a read operation is enabled for the MB85RC16. If the device code is not “1010”, the Read/Write operation is not performed and the standby state is chosen. 6 DS501-00001-2v0-E MB85RC16 ■ DATA STRUCTURE The master inputs the device address word (8 bits) following the start condition, and then the slave outputs the Acknowledge “L” level on the ninth bit. After confirming the Acknowledge response, the sequential 8-bit memory lower address is input, to the byte write, page write and random read commands. As for the current address read command, inputting the memory lower address is not performed, and the address buffer lower 8-bit is used as the memory lower address. When inputting the memory lower address finishes, the slave outputs the Acknowledge “L” level on the ninth bit again. Afterwards, the input and the output data continue in 8-bit units, and then the Acknowledge “L” level is output for every 8-bit data. • Device Address Word Start 1 2 3 4 5 6 7 8 9 1 2 .. SCL SDA ACK S 1 0 1 Device code 0 A2 A1 A0 Memory Upper Address R/W A .. Read/Write code Access from master Access from slave S Start Condition A ACK (SDA is the "L" level) DS501-00001-2v0-E 7 MB85RC16 ■ FRAM ACKNOWLEDGE -- POLLING NOT REQUIRED The MB85RC16 performs the high speed write operations, so any waiting time for an ACK* by the acknowledge polling does not occur. *: In E2PROM, the Acknowledge Polling is performed as a progress check whether rewriting is executed or not. It is normal to judge by the 9th bit of Acknowledge whether rewriting is performed or not after inputting the start condition and then the device address word (8 bits) during rewriting. ■ WRITE PROTECT (WP) The entire memory array can be write protected by setting the WP pin to the “H” level. When the WP pin is set to the “L” level, the entire memory array will be rewritten. Reading is allowed regardless of the WP pin's “H” level or “L” level. Do not change the WP signal level during the communication period from the start condition to the stop condition. Note : The WP pin is pulled down internally to VSS pin, therefore if the WP pin is open, the pin status is detected as the “L” level (write enabled). 8 DS501-00001-2v0-E MB85RC16 ■ COMMAND • Byte Write If the device address word (R/W “0” input) is sent after the start condition, an ACK responds from the slave. After this ACK, write memory addresses and write data are sent in the same way, and the write ends by generating a stop condition at the end. S 1 0 1 0 A2 A1 A0 0 A XXX Address Low 8bits A Write Data 8bits A P X X X X X X XX Access from master MSB LSB Access from slave S Start Condition P Stop Condition A ACK (SDA is the "L" level) • Page Write If data is continuously sent after the following address when the same command (expect stop condition) as Byte Write was sent, a page write is performed. The memory address rolls over to first memory address (000H) at the end of the address. Therefore, if more than 2 Kbytes are sent, the data is overwritten in order starting from the start of the memory address that was written first. S 1 0 1 0 A2 A1 A0 0 A Address Low 8bits A Write Data 8bits A Write Data ... A P Access from master Access from slave S Start Condition P Stop Condition A ACK (SDA is the "L" level) DS501-00001-2v0-E 9 MB85RC16 • Current Address Read If the last write or read operation finishes correctly up to the end of stop condition, the memory address that was accessed last remains in the memory address buffer (the length is 11 bits). When sending this command without turning the power off, it is possible to read from the memory address n+1 which adds 1 to the total 11-bit memory address n, which consists of the memory upper address 3-bit from the device address word input and the lower 8-bit of the memory address buffer. If the memory address n is the last address, it is possible to read with rolling over to the head of the memory address (000H). The current address (address that the memory address buffer indicates) is undefined immediately after turning the power on. Access from master Access from slave (n+1) memory address S Start Condition Read Data 8bits P Stop Condition 1 0 1 0 A2 A1 A0 1 A S N P A ACK (SDA is the "L"level) N NACK (SDA is the "H" level) • Random Read The one byte of data from the memory address as saved in the memory address buffer can be read out synchronously to SCL by specifying the address in the same way as for a write, and then issuing another start condition and sending the Device Address Word (R/W “1” input). Setting values for the first and the second memory upper address codes should be the same. The final NACK (SDA is the “H” level) is issued by the receiver that receives the data. In this case, this bit is issued by the master side. n address S 1 0 1 0 A2 A1 A0 0 A (Input example) when reading memory address 16FH: 001B Address Low 8bits 01101111B A S 1 0 1 0 A2 A1 A0 1 A Read Data 8bits N P 001B Access from master Access from slave S Start Condition P Stop Condition A ACK (SDA is the "L" level) N NACK (SDA is the "H" level) 10 DS501-00001-2v0-E MB85RC16 • Sequential Read Data can be received continuously following the Device address word (R/W “1” input) after specifying the address in the same way as for Random Read. If the read reaches the end of address for the MB85RC16, the read address automatically rolls over to first memory address (000H). ... A Read Data 8bits A Read Data ... A Read Data 8bits N P Access from master Access from slave P Stop Condition A ACK (SDA is the "L" level) N NACK (SDA is the "H" level) DS501-00001-2v0-E 11 MB85RC16 ■ ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Min Max Unit Power supply voltage* VDD − 0.5 + 4.0 V Input voltage* VIN − 0.5 VDD + 0.5 ( ≤ 4.0) V VOUT − 0.5 VDD + 0.5 ( ≤ 4.0) V Ambient temperature TA − 40 + 85 °C Storage temperature Tstg − 40 + 125 °C Output voltage* *: These parameters are based on the condition that VSS is 0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Min Typ Max Unit Power supply voltage* VDD 2.7 3.3 3.6 V “H” level input voltage* VIH VDD × 0.8 ⎯ VDD + 0.5 ( ≤ 4.0) V “L” level input voltage* VIL − 0.5 ⎯ + 0.6 V Ambient temperature TA − 40 ⎯ + 85 °C *: These parameters are based on the condition that VSS is 0 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 12 DS501-00001-2v0-E MB85RC16 ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics (within recommended operating conditions) Parameter Symbol Condition Value Min Typ Max Unit |ILI| VIN = 0 V to VDD ⎯ ⎯ 1 μA Output leakage current* |ILO| VOUT = 0 V to VDD ⎯ ⎯ 1 μA Operating power supply current ICC SCL = 1 MHz -⎯ 70 100 μA Standby current ISB SCL, SDA = VDD WP = 0V or VDD or OPEN TA = + 25 °C ⎯ 0.1 1 μA “L” level output voltage VOL IOL = 2 mA ⎯ ⎯ 0.4 V Input resistance for WP pin RIN VIN = VIL (Max) 50 ⎯ ⎯ kΩ VIN = VIH (Min) 1 ⎯ ⎯ MΩ Input leakage current*1 2 *1: Applicable pin: SCL,SDA *2: Applicable pin: SDA DS501-00001-2v0-E 13 MB85RC16 2. AC Characteristics (within recommended operating conditions) Value Parameter Symbol STANDARD MODE FAST MODE Min Max Min Max Unit SCL clock frequency FSCL 0 400 0 1000 kHz Clock high time THIGH 600 ⎯ 400 ⎯ ns Clock low time TLOW 1300 ⎯ 600 ⎯ ns SCL/SDA rise time Tr ⎯ 300 ⎯ 300 ns SCL/SDA fall time Tf ⎯ 300 ⎯ 100 ns Start condition hold THD:STA 600 ⎯ 250 ⎯ ns Start condition setup TSU:STA 600 ⎯ 250 ⎯ ns SDA input hold THD:DAT 0 ⎯ 0 ⎯ ns SDA input setup TSU:DAT 100 ⎯ 100 ⎯ ns SDA output hold TDH:DAT 0 ⎯ 0 ⎯ ns Stop condition setup TSU:STO 600 ⎯ 250 ⎯ ns SDA output access after SCL fall TAA ⎯ 900 ⎯ 550 ns Pre-charge time TBUF 1300 ⎯ 500 ⎯ ns Noise suppression time constant on SCL, SDA TSP ⎯ 50 ⎯ 50 ns AC characteristics were measured under the following measurement conditions. 14 Power supply voltage : 2.7 V to 3.6 V Operating temperature : − 40 °C to + 85 °C Input voltage amplitude : 0.3 V to 2.7 V Input rise time : 5 ns Input fall time : 5 ns Input judge level : VDD/2 Output judge level : VDD/2 DS501-00001-2v0-E MB85RC16 3. AC Timing Definitions TSU:DAT SCL VIH Start VIL SDA THD:DAT VIH VIH VIH VIH VIL VIL VIL VIL VIH VIH VIH VIH VIL VIL VIL VIL TSU:STA THD:STA TSU:STO Tr THIGH SCL Stop VIH Tf TLOW VIH VIL VIL VIH VIH VIL VIL VIH SDA Stop VIH VIL Start VIH VIL VIH VIL VIL Tbuf Tr T TDH:DAT f Taa Tsp VIH SCL VIL VIL VIH SDA VIL Valid VIH VIL VIL 1/FSCL 4. Pin capacitance Parameter Symbol Conditions I/O capacitance CI/O Input capacitance CIN VDD = VIN = VOUT = 0V, f = 1 MHz, TA = + 25 °C Value Min Typ Max Unit ⎯ ⎯ 15 pF ⎯ ⎯ 15 pF 5. AC Test Load Circuit 3.3 V Output 100 pF DS501-00001-2v0-E 15 MB85RC16 ■ POWER ON SEQUENCE tpd tf tOFF tr tpu VDD VDD 2.7 V 2.7 V VIH (Min) VIH (Min) 1.0 V 1.0 V VIL (Max) VIL (Max) 0V 0V SDA, SCL SDA, SCL > VDD × 0.8 * SDA, SCL : Don't care SDA, SCL > VDD × 0.8 * SDA, SCL * : SDA, SCL (Max) < VDD + 0.5 V Parameter Symbol SDA, SCL level hold time during power down SDA, SCL level hold time during power up Value Unit Min Max tpd 85 ⎯ ns tpu 85 ⎯ ns Power supply rise time tr 0.01 50 ms Power supply fall time tf 0.01 50 ms tOFF 50 ⎯ ms Power off time ■ NOTES ON USE • Data written before performing IR reflow is not guaranteed after IR reflow. • VDD is required to be rising from 0 V because turning the power on from an intermediate level may cause malfunctions, when the power is turned on. 16 DS501-00001-2v0-E MB85RC16 ■ ORDERING INFORMATION Part number Package MB85RC16PNF-G-JNE1 8-pin, plastic SOP (FPT-8P-M02) MB85RC16PNF-G-JNERE1 8-pin, plastic SOP (FPT-8P-M02) DS501-00001-2v0-E Remarks Embossed Carrier tape 17 MB85RC16 ■ PACKAGE DIMENSION 8-pin plastic SOP Lead pitch 1.27 mm Package width × package length 3.9 mm × 5.05 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.75 mm MAX Weight 0.06 g (FPT-8P-M02) 8-pin plastic SOP (FPT-8P-M02) +0.25 Note 1) *1 : These dimensions include resin protrusion. Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. +.010 +0.03 *1 5.05 –0.20 .199 –.008 0.22 –0.07 +.001 .009 –.003 8 5 *2 3.90±0.30 6.00±0.40 (.154±.012) (.236±.016) Details of "A" part 45° 1.55±0.20 (Mounting height) (.061±.008) 0.25(.010) 0.40(.016) 1 "A" 4 1.27(.050) 0.44±0.08 (.017±.003) 0.13(.005) 0~8° M 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.15±0.10 (.006±.004) (Stand off) 0.10(.004) C 2002-2010 FUJITSU SEMICONDUCTOR LIMITED F08004S-c-4-9 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 18 DS501-00001-2v0-E MB85RC16 MEMO DS501-00001-2v0-E 19 MB85RC16 FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://sg.fujitsu.com/semiconductor/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. 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