MB85RC64APNF-G-JNERE1

FUJITSU SEMICONDUCTOR DATA SHEET DS501-00019-2v0-E Memory FRAM 64 K (8 K × 8) Bit I2C MB85RC64A ■ DESCRIPTION The MB85RC64A is an FRAM (Ferroelectric Random Access Memory) chip in a configuration of 8,192 words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. Unlike SRAM, the MB85RC64A is able to retain data without using a data backup battery. The read/write endurance of the nonvolatile memory cells used for the MB85RC64A has improved to be at least 1012 cycles, significantly outperforming Flash memory and E2PROM in the number. The MB85RC64A does not need a polling sequence after writing to the memory such as the case of Flash memory or E2PROM. ■ FEATURES : 8,192 words × 8 bits : Fully controllable by two ports: serial clock (SCL) and serial data (SDA). : 1 MHz (Max) : 1012 times / byte : 10 years ( + 85 °C), 95 years ( + 55 °C), over 200 years ( + 35 °C) : 2.7 V to 3.6 V : Operating power supply current 250 μA (Typ @1 MHz) Standby current 5 μA (Typ) • Operation ambient temperature range : − 40 °C to + 85 °C • Package : 8-pin plastic SOP (FPT-8P-M02) RoHS compliant • • • • • • • Bit configuration Two-wire serial interface Operating frequency Read/write endurance Data retention Operating power supply voltage Low power consumption Copyright©2012-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2013.2 MB85RC64A ■ PIN ASSIGNMENT (TOP VIEW) A0 1 8 VDD A1 2 7 WP A2 3 6 SCL VSS 4 5 SDA (FPT-8P-M02) ■ PIN FUNCTIONAL DESCRIPTIONS Pin Number 2 Pin Name Functional Description 1 to 3 A0 to A2 Device Address pins The MB85RC64A can be connected to the same data bus up to 8 devices. Device addresses are used in order to identify each of these devices. Connect these pins to VDD pin or VSS pin externally. Only if the combination of VDD and VSS pins matches a Device Address Code inputted from the SDA pin, the device operates. In the open pin state, A0, A1, and A2 pins are internally pulleddown and recognized as the “L” level. 4 VSS Ground pin 5 SDA Serial Data I/O pin This is an I/O pin which performs bidirectional communication for both memory address and writing/reading data. It is possible to connect multiple devices. It is an open drain output, so a pull-up resistor is required to be connected to the external circuit. 6 SCL Serial Clock pin This is a clock input pin for input/output timing serial data. Data is sampled on the rising edge of the clock and output on the falling edge. 7 WP Write Protect pin When the Write Protect pin is the “H” level, the writing operation is disabled. When the Write Protect pin is the “L” level, the entire memory region can be overwritten. The reading operation is always enabled regardless of the Write Protect pin input level. The write protect pin is internally pulled down to VSS pin, and that is recognized as the “L” level (write enabled) when the pin is the open state. 8 VDD Supply Voltage pin DS501-00019-2v0-E MB85RC64A ■ BLOCK DIAGRAM Control Logic SCL WP Row Decoder Serial/Parallel Converter Address Counter SDA FRAM Array 8,192 × 8 Column Decoder/Sense Amp/ Write Amp A0, A1, A2 ■ I2C (Inter-Integrated Circuit) The MB85RC64A has the two-wire serial interface; the I2C bus,and operates as a slave device. The I2C bus defines communication roles of “master” and “slave” devices, with the master side holding the authority to initiate control. Furthermore, an I2C bus connection is possible where a single master device is connected to multiple slave devices in a party-line configuration. In this case, it is necessary to assign a unique device address to the slave device, the master side starts communication after specifying the slave to communicate by addresses. • I2C Interface System Configuration Example VDD Pull-up Resistors SCL SDA I2C Bus Master I2C Bus MB85RC64A A2 0 A1 0 A0 0 I2C Bus MB85RC64A A2 0 A1 0 A0 1 I2C Bus MB85RC64A A2 0 A1 1 ... A0 0 Device address DS501-00019-2v0-E 3 MB85RC64A ■ I2C COMMUNICATION PROTOCOL The I2C bus is a two wire serial interface that uses a bidirectional data bus (SDA) and serial clock (SCL). A data transfer can only be initiated by the master, which will also provide the serial clock for synchronization. The SDA signal should change while SCL is the “L” level. However, as an exception, when starting and stopping communication sequence, SDA is allowed to change while SCL is the “H” level. • Start Condition To start read or write operations by the I2C bus, change the SDA input from the “H” level to the “L” level while the SCL input is in the “H” level. • Stop Condition To stop the I2C bus communication, change the SDA input from the “L” level to the “H” level while the SCL input is in the “H” level. In the reading operation, inputting the stop condition finishes reading and enters the standby state. In the writing operation, inputting the stop condition finishes inputting the rewrite data and enters the standby state. • Start Condition, Stop Condition SCL SDA “H” or “L” Start Stop Note : At the write operation, the FRAM device does not need the programming wait time (tWC) after issuing the Stop Condition. 4 DS501-00019-2v0-E MB85RC64A ■ ACKNOWLEDGE (ACK) In the I2C bus, serial data including address or memory information is sent in units of 8 bits. The acknowledge signal indicates that every 8 bits of the data is successfully sent and received. The receiver side usually outputs the “L” level every time on the 9th SCL clock after each 8 bits are successfully transmitted and received. On the transmitter side, the bus is temporarily released to Hi-Z every time on this 9th clock to allow the acknowledge signal to be received and checked. During this Hi-Z-released period, the receiver side pulls the SDA line down to indicate the “L” level that the previous 8 bits communication is successfully received. In case the slave side receives Stop condition before sending or receiving the ACK “L” level, the slave side stops the operation and enters to the standby state. On the other hand, the slave side releases the bus state after sending or receiving the NACK “H” level. The master side generates Stop condition or Start condition in this released bus state. • Acknowledge timing overview diagram 1 SCL 2 3 8 SDA 9 ACK Start DS501-00019-2v0-E The transmitter side should always release SDA on the 9th bit. At this time, the receiver side outputs a pull-down if the previous 8 bits data are received correctly (ACK response). 5 MB85RC64A ■ DEVICE ADDRESS WORD (Slave address) Following the start condition, the master sends the 8 bits device address word to start I2C communication. The device address word (8 bits) consists of a device Type code (4 bits), device address code (3 bits), and a read/write code (1 bit). • Device Type Code (4 bits) The upper 4 bits of the device address word are a device type code that identifies the device type, and are fixed at “1010” for the MB85RC64A. • Device Address Code (3 bits) Following the device type code, the 3 bits of the device address code are input in order of A2, A1, and A0. The device address code identifies one device from up to eight devices connected to the bus. Each MB85RC64A is given a unique 3 bits code on the device address pin (external hardware pin A2, A1, and A0). The slave only responds if the received device address code is equal to this unique 3 bits code. • Read/Write Code (1 bit) The 8th bit of the device address word is the R/W (read/write) code. When the R/W code is “0”, a write operation is enabled, and the R/W code is “1”, a read operation is enabled for the MB85RC64A. It turns to a stand-by state if the device code is not “1010” or device address code does not equal to pins A2, A1, and A0. • Device Address Word Start 1 2 3 4 5 6 7 8 9 1 2 .. SCL SDA ACK S 1 0 1 Device Code 0 A2 A1 A0 R/W A .. Device Address Code Read/Write Code Access from master Access from slave S Start Condition A ACK (SDA is the "L" level) 6 DS501-00019-2v0-E MB85RC64A ■ DATA STRUCTURE In the I2C bus, the acknowledge “L” level is output on the 9th bit by a slave, after the 8 bits of the device address word following the start condition are input by a master. After confirming the acknowledge response by the master, the master outputs 8bits × 2 memory address to the slave. When the each memory address input ends, the slave again outputs the acknowledge “L” level. After this operation, the I/O data follows in units of 8 bits, with the acknowledge “L” level output after every 8 bits. It is determined by the R/W code whether the data line is driven by the master or the slave. However, the clock line shall be driven by the master. For a write operation, the slave will accept 8 bits from the master, then send an acknowledge. If the master detects the acknowledge, the master will transfer the next 8 bits. For a read operation, the slave will place 8 bits on the data line, then wait for an acknowledge from the master. ■ FRAM ACKNOWLEDGE -- POLLING NOT REQUIRED The MB85RC64A performs write operations at the same speed as read operations, so any waiting time for an ACK polling* does not occur. The write cycle takes no additional time. *: In E2PROM, the Acknowledge Polling is performed as a progress check whether rewriting is executed or not. It is normal to judge by the 9th bit of Acknowledge whether rewriting is performed or not after inputting the start condition and then the device address word (8 bits) during rewriting. ■ WRITE PROTECT (WP) The entire memory array can be write protected using the Write Protect pin. When the Write Protect pin is set to the “H” level, the entire memory array will be write protected. When the Write Protect pin is the “L” level, entire memory array will be rewritten. Reading is allowed regardless of the WP pin's “H” level or “L” level. Note : The Write Protect pin is pulled down internally to VSS pin, therefore if the Write Protect pin is open, the pin status is detected as the “L” level (write enabled). DS501-00019-2v0-E 7 MB85RC64A ■ COMMAND • Byte Write If the device address word (R/W “0” input ) is sent following the start condition, the slave responds with an ACK. After this ACK, write addresses and data are sent in the same way, and the write ends by generating a stop condition at the end. S 1 0 1 0 A2 A1 A0 0 A Address High 8bits A 0 00XXXXX Address Low 8bits A Write Data 8bits A P X X X X X X XX Access from master MSB LSB Access from slave S Start Condition P Stop Condition A ACK (SDA is the "L" level) Note : In the MB85RC64A, input “000” as the upper 3 bits of the MSB. • Page Write If additional 8 bits are continuously sent after the same command (except stop condition) as Byte Write, a page write is performed. The memory address rolls over to first memory address (0000H) at the end of the address. Therefore, if more than 8 Kbytes are sent, the data is overwritten in order starting from the start of the memory address that was written first. Because FRAM performs the high-speed write operations, the data will be written to FRAM right after the ACK response finished. S 1 0 1 0 A2 A1 A0 0 A Address High 8bits A Address Low 8bits A Write Data 8bits A Write Data ... A P Access from master Access from slave S Start Condition P Stop Condition A ACK (SDA is the "L" level) Note : It is not necessary to take a period for internal write operation cycles from the buffer to the memory after the stop condition is generated. 8 DS501-00019-2v0-E MB85RC64A • Current Address Read When the previous write or read operation finishes successfully up to the stop condition and assumes the last accessed address is “n”, then the address at “n+1” is read by sending the following command unless turning the power off. If the memory address is last address, the address counter will roll over to 0000H. The current address in memory address buffer is undefined immediately after the power is turned on. Access from master Access from slave S Start Condition (n+1) address S 1 0 1 0 A2 A1 A0 1 A Read Data 8bits N P P Stop Condition A ACK(SDA is the "L" level) N NACK (SDA is the "H" level) • Random Read The one byte of data from the memory address saved in the memory address buffer can be read out synchronously to SCL by specifying the address in the same way as for a write, and then issuing another start condition and sending the Device Address Word (R/W “1” input). The final NACK is issued by the receiver that receives the data. In this case, this bit is issued by the master side. S 1 0 1 0 A2 A1 A0 0 A Address High 8bits A Address Low 8bits A S 1 0 1 0 A2 A1 A0 1 A Read Data 8bits N P Access from master Access from slave S Start Condition P Stop Condition A ACK (SDA is the "L" level) N NACK (SDA is the "H" level) DS501-00019-2v0-E 9 MB85RC64A • Sequential Read Data can be received continuously following the Device address word (R/W “1” input) after specifying the address in the same way as for Random Read. If the read reaches the end of address, the internal read address automatically rolls over to first memory address 0000H and keeps reading. ... A Read Data 8bits A Read Data ... A Read Data 8bits N P Access from master Access from slave P Stop Condition A ACK (SDA is the "L" level) N NACK (SDA is the "H" level) ■ SOFTWARE RESET SEQUENCE OR COMMAND RETRY In case the malfunction has occurred after power on, the master side stopped the I2C communication during processing, or unexpected malfunction has occurred, execute the following (1) software recovery sequence just before each command, or (2) retry command just after failure of each command. (1) Software Reset Sequence Since the slave side may be outputting “L” level, do not force to drive “H” level, when the master side drives the SDA port. This is for preventing a bus conflict. The additional hardware is not necessary for this software reset sequence. 9 set of “Start Conditions and one “1” data” SCL SDA Hi-Z state by pull up Resistor Send “Start Condition and one data “1”” . Repeat these 9 times just before Write or Read command. (2) Command Retry Command retry is useful to recover from failure response during I2C communication. 10 DS501-00019-2v0-E MB85RC64A ■ ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Min Max Unit Power supply voltage* VDD − 0.5 +4.0 V Input voltage* VIN − 0.5 VDD + 0.5 ( ≤ 4.0) V VOUT − 0.5 VDD + 0.5 ( ≤ 4.0) V TA − 40 + 85 °C Tstg − 55 + 125 °C Output voltage* Operation ambient temperature Storage temperature *: These parameters are based on the condition that VSS is 0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Min Typ Max Unit Power supply voltage* VDD 2.7 3.3 3.6 V “H” level input voltage* VIH VDD × 0.8 ⎯ VDD + 0.5 ( ≤ 4.0) V “L” level input voltage* VIL − 0.5 ⎯ + 0.6 V Operation ambient temperature TA − 40 ⎯ + 85 °C *: These parameters are based on the condition that VSS is 0 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. DS501-00019-2v0-E 11 MB85RC64A ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics (within recommended operating conditions) Parameter Symbol Value Condition Min Typ Max Unit Input leakage current |ILI| SCL, SDA = 0 V to VDD ⎯ ⎯ 1 μA Output leakage current |ILO| SDA = 0 V to VDD ⎯ ⎯ 1 μA Operating power supply current IDD SCL = 1 MHz ⎯ 250 375 μA Standby current ISB SCL, SDA = VDD A0, A1, A2, WP = 0 V or VDD ⎯ 5 20 μA “L” level output voltage VOL IOL = 3 mA ⎯ ⎯ 0.4 V Input resistance for WP, A0, A1 and A2 RIN VIN = VIL (Max) 50 ⎯ ⎯ kΩ VIN = VIH (Min) 1 ⎯ ⎯ MΩ 2. AC Characteristics Value Parameter Symbol Standard Mode Fast Mode Fast Mode Plus Unit Min Max Min Max Min Max SCL clock frequency FSCL 0 100 0 400 0 1000 kHz Clock high time THIGH 4000 ⎯ 600 ⎯ 400 ⎯ ns Clock low time TLOW 4700 ⎯ 1300 ⎯ 600 ⎯ ns SCL/SDA rising time Tr ⎯ 1000 ⎯ 300 ⎯ 300 ns SCL/SDA falling time Tf ⎯ 300 ⎯ 300 ⎯ 100 ns Start condition hold THD:STA 4000 ⎯ 600 ⎯ 250 ⎯ ns Start condition setup TSU:STA 4700 ⎯ 600 ⎯ 250 ⎯ ns SDA input hold THD:DAT 0 ⎯ 0 ⎯ 0 ⎯ ns SDA input setup TSU:DAT 250 ⎯ 100 ⎯ 100 ⎯ ns SDA output hold TDH:DAT 0 ⎯ 0 ⎯ 0 ⎯ ns Stop condition setup TSU:STO 4000 ⎯ 600 ⎯ 250 ⎯ ns SDA output access after SCL falling TAA ⎯ 3000 ⎯ 900 ⎯ 550 ns Pre-charge time TBUF 4700 - 1300 - 500 ⎯ ns ⎯ 50 ns Noise suppression time TSP ⎯ 50 ⎯ 50 (SCL and SDA) AC characteristics were measured under the following measurement conditions. Power supply voltage : 2.7 V to 3.6 V Operation ambient temperature : − 40 °C to + 85 °C 12 Input voltage magnitude : 0.3 V to 2.7 V Input rising time : 5 ns Input falling time : 5 ns Input judge level : VDD/2 Output judge level : VDD/2 DS501-00019-2v0-E MB85RC64A 3. AC Timing Definitions TSU:DAT SCL VIH Start VIL SDA THD:DAT VIH VIH VIH VIH VIL VIL VIL VIL VIH VIH VIH VIH VIL VIL VIL VIL TSU:STA THD:STA TSU:STO Tr THIGH SCL Stop VIH Tf TLOW VIH VIL VIL VIH VIH VIL VIL VIH SDA Stop VIH VIL Start VIH VIL VIH VIL VIL TBUF Tr T TDH:DAT f TAA Tsp VIH SCL VIL VIL VIH SDA VIL Valid VIH VIL VIL 1/FSCL 4. Pin Capacitance Parameter Symbol Conditions I/O capacitance CI/O Input capacitance CIN VDD = VIN = VOUT = 0 V, f = 1 MHz, TA = + 25 °C Value Unit Min Typ Min ⎯ ⎯ 15 pF ⎯ ⎯ 15 pF 5. AC Test Load Circuit 3.3 V 1.1 kΩ Output 100 pF DS501-00019-2v0-E 13 MB85RC64A ■ POWER ON/OFF SEQUENCE If VDD falls down below 2.0V, VDD is required to be started from 0V to prevent malfunctions when the power is turned on again. tr tpd tpu VDD VDD 2.7 V 2.7 V VIH (Min) VIH (Min) 1.0 V 1.0 V VIL (Max) VIL (Max) 0V 0V SDA, SCL >VDD × 0.8 * SDA, SCL SDA, SCL : Don't care SDA, SCL >VDD × 0.8 * SDA, SCL * : SDA, SCL (Max) < VDD + 0.5 V Parameter Symbol SDA, SCL level hold time during power down SDA, SCL level hold time during power up Power supply rising time Value Unit Min Max tpd 85 ⎯ ns tpu 85 ⎯ ns tr 10 ⎯ μs If the device does not operate within the specified conditions of read cycle, write cycle or power on/off sequence, memory data can not be guaranteed. ■ FRAM CHARACTERISTICS Item Min Read/Write Endurance* 2 Data Retention* 1 Max Unit Parameter ⎯ Times/byte Operation Ambient Temperature TA = + 85 °C 10 ⎯ Operation Ambient Temperature TA = + 85 °C 95 ⎯ ≥ 200 ⎯ 10 12 Years Operation Ambient Temperature TA = + 55 °C Operation Ambient Temperature TA = + 35 °C *1 : Total number of reading and writing defines the minimum value of endurance, as an FRAM memory operates with destructive readout mechanism. *2 : Minimun values define retention time of the first reading/writing data right after shipment, and these values are calculated by qualification results. ■ NOTE ON USE • Data written before performing IR reflow is not guaranteed after IR reflow. • During the access period from the start condition to the stop condition, keep the level of WP, A0, A1, and A2 pins to the “H” level or the “L” level. 14 DS501-00019-2v0-E MB85RC64A ■ ESD AND LATCH-UP Test DUT Value ESD HBM (Human Body Model) JESD22-A114 compliant ≥ |2000 V| ESD MM (Machine Model) JESD22-A115 compliant ≥ |200 V| ESD CDM (Charged Device Model) JESD22-C101 compliant ⎯ Latch-Up (I-test) JESD78 compliant MB85RC64APNF-G-JNE1 ⎯ Latch-Up (Vsupply overvoltage test) JESD78 compliant ⎯ Latch-Up (Current Method) Proprietary method ⎯ Latch-Up (C-V Method) Proprietary method ⎯ • Current method of Latch-Up Resistance Test Protection Resistance A IIN VIN Test terminal VDD + DUT - VSS VDD (Max.Rating) V Reference terminal Note : The voltage VIN is increased gradually and the current IIN of 300 mA at maximum shall flow. Confirm the latch up does not occur under IIN = ± 300 mA. In case the specific requirement is specified for I/O and IIN cannot be 300 mA, the voltage shall be increased to the level that meets the specific requirement. DS501-00019-2v0-E 15 MB85RC64A • C-V method of Latch-Up Resistance Test Protection Resistance A 1 Test 2 terminal SW + VIN V - C 200pF VDD DUT VDD (Max.Rating) VSS Reference terminal Note 16 Charge voltage alternately switching 1 and 2 approximately 2 sec interval. This switching process is considered as one cycle. Repeat this process 5 times. However, if the latch-up condition occurs before completing 5 times, this test must be stopped immediately. DS501-00019-2v0-E MB85RC64A ■ REFLOW CONDITIONS AND FLOOR LIFE Item Condition Method IR (infrared reflow) , Convection Times 2 Before unpacking Please use within 2 years after production. From unpacking to 2nd reflow Within 8 days In case over period of floor life Baking with 125 °C+/-3 °C for 24hrs+2hrs/-0hrs is required. Then please use within 8 days. (Please remember baking is up to 2 times) Floor life Floor life condition Between 5 °C and 30 °C and also below 70%RH required. (It is preferred lower humidity in the required temp range.) Reflow Profile 260°C 255°C Liquidous Temperature 170 °C to 190 °C (b) RT (c) (a) (a) Average ramp-up rate (b) Preheat & Soak (c) Average ramp-up rate (d) Peak temperature (d’) Liquidous temperature (e) Cooling (d) (e) (d') : 1 °C/s to 4 °C/s : 170 °C to 190 °C, 60 s to 180 s : 1 °C/s to 4 °C/s : Temperature 260 °C Max; 255 °C within 10 s : Up to 230 °C within 40 s or Up to 225 °C within 60 s or Up to 220 °C within 80 s : Natural cooling or forced cooling Note : Temperature on the top of the package body is measured. DS501-00019-2v0-E 17 MB85RC64A ■ RESTRICTED SUBSTANCES This product complies with the regulations below (Based on current knowledge as of November 2011). • EU RoHS Directive (2002/95/EC) • China RoHS (Administration on the Control of Pollution Caused by Electronic Information Products ( )) • Vietnam RoHS (30/2011/TT-BCT) Restricted substances in each regulation are as follows. Substances Threshold Contain status* Lead and its compounds 1,000 ppm ❍ Mercury and its compounds 1,000 ppm ❍ 100 ppm ❍ Hexavalent chromium compound 1,000 ppm ❍ Polybrominated biphenyls (PBB) 1,000 ppm ❍ Polybrominated diphenyl ethers (PBDE) 1,000 ppm ❍ Cadmium and its compounds * : The mark of “❍” shows below a threshold value. 18 DS501-00019-2v0-E MB85RC64A ■ ORDERING INFORMATION Package Shipping form Minimum shipping quantity MB85RC64APNF-G-JNE1 8-pin, plastic SOP (FPT-8P-M02) Tube 1 MB85RC64APNF-G-JNERE1 8-pin, plastic SOP (FPT-8P-M02) Embossed Carrier tape 1500 Part number DS501-00019-2v0-E 19 MB85RC64A ■ PACKAGE DIMENSION 8-pin plastic SOP Lead pitch 1.27 mm Package width × package length 3.9 mm × 5.05 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.75 mm MAX Weight 0.06 g (FPT-8P-M02) 8-pin plastic SOP (FPT-8P-M02) +0.25 Note 1) *1 : These dimensions include resin protrusion. Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. +.010 +0.03 *1 5.05 –0.20 .199 –.008 0.22 –0.07 +.001 .009 –.003 8 5 *2 3.90±0.30 6.00±0.20 (.154±.012) (.236±.008) Details of "A" part 45° 1.55±0.20 (Mounting height) (.061±.008) 0.25(.010) 0.40(.016) 1 "A" 4 1.27(.050) 0.44±0.08 (.017±.003) 0.13(.005) 0~8° M 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.15±0.10 (.006±.004) (Stand off) 0.10(.004) C 2002-2012 FUJITSU SEMICONDUCTOR LIMITED F08004S-c-5-10 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 20 DS501-00019-2v0-E MB85RC64A ■ MARKING [MB85RC64APNF-G-JNE1] [MB85RC64APNF-G-JNERE1] RC64A E11000 300 [FPT-8P-M02] DS501-00019-2v0-E 21 MB85RC64A ■ PACKING INFORMATION 1. Tube 1.1 Tube Dimensions • Tube/stopper shape Tube Transparent polyethylene terephthalate (treated to antistatic) Stopper (treated to antistatic) Tube length: 520 mm Tube cross-sections and Maximum quantity Maximum quantity Package form Package code FPT-8P-M02 SOP, 8, plastic (2) pcs/ tube pcs/inner box pcs/outer box 95 7600 30400 1.8 2.6 7.4 6.4 4.4 ©2006-2010 FUJITSU SEMICONDUCTOR LIMITED C 2006 FUJITSU LIMITED F08008-SET1-PET:FJ99L-0022-E0008-1-K-1 F08008-SET1-PET:FJ99L-0022-E0008-1-K-3 t = 0.5 Transparent polyethylene terephthalate (Dimensions 22 in mm) DS501-00019-2v0-E MB85RC64A 1.2 Tube Dry pack packing specifications IC Tube Stopper For SOP Index mark Label I *1*3 Aluminum Iaminated bag Heat seal Dry pack Desiccant Humidity indicater Aluminum Iaminated bag (tubes inside) Inner box Cushioning material Inner box Label I *1*3 Cushioning material Outer box*2 Outer box Use adhesive tapes. Label II-A *3 Label II-B *3 *1: For a product of witch part number is suffixed with “E1”, a “ G bag and the inner boxes. Pb ” marks is display to the moisture barrier *2: The space in the outer box will be filled with empty inner boxes, or cushions, etc. *3: Please refer to an attached sheet about the indication label. Note: The packing specifications may not be applied when the product is delivered via a distributer. DS501-00019-2v0-E 23 MB85RC64A 1.3 Product label indicators Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm × 100mm) Supplemental Label (20mm × 100mm)] XXXXXXXXXXXXXX (Customer part number or FJ part number) C-3 Label (LEAD FREE mark) (3N)1 XXXXXXXXXXXXXX XXX (Part number and quantity) QC PASS (3N)2 XXXXXXXXXX XXXXXX (FJ control number) XXX pcs XXXXXXXXXXXXXX (Quantity) (Customer part number or FJ part number) (Customer part number or FJ part number bar code) XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx XXXXXXXXXXXXXX (Customer part number or FJ part number) (FJ control number bar code) XX/XX XXXX-XXX XXX (Package count) XXXX-XXX XXX XXXXXXXXXX (FJ control number ) (Lot Number and quantity) XXXXXXXXXXXXXX (Comment) Perforated line Supplemental Label Label II-A: Label on Outer box [D Label] (100mm × 100mm) D Label XXXXXXXXXXXXX (Customer Name) (CUST.) XXXXXXXXX (Delivery Address) (DELIVERY POINT) XXXXXXXXXXXXXX (TRANS.NO.) (FJ control number) XXXXXXXXXXXXXX (PART NO.) (Customer part number or FJ part number) XXX (FJ control number) XXX (FJ control number) XXX (FJ control number) XXXXXXXXXXXXXX (Part number) (PART NAME) XXXXXXXXXXXXXX (Part number) XXX/XXX (Q’TY/TOTAL Q’TY) (CUSTOMER'S REMARKS) XXXXXXXXXXXXXXXXXXXX (3N)3 XXXXXXXXXXXXXX XXX XX (UNIT) (PACKAGE COUNT) XXX/XXX (3N)4 XXXXXXXXXXXXXX XXX (FJ control number + Product quantity) (FJ control number + Product quantity bar code) (Part number + Product quantity) (3N)5 XXXXXXXXXX (FJ control number) (Part number + Product quantity bar code) (FJ control number bar code) Label II-B: Outer boxes product indicate XXXXXXXXXXXXXX (Lot Number) XXXX-XXX XXXX-XXX (Part number) (Count) X X (Quantity) XXX XXX XXX Note: Depending on shipment state, “Label II-A” and “Label II-B” on the external boxes might not be printed. 24 DS501-00019-2v0-E MB85RC64A 1.4 Dimensions for Containers (1) Dimensions for inner box H W L L W H 540 125 75 (Dimensions in mm) (2) Dimensions for outer box H W L L W H 565 270 180 (Dimensions in mm) DS501-00019-2v0-E 25 MB85RC64A 2. Emboss Tape 2.1 Tape Dimensions PKG code FPT-8P-M02 Maximum storage capacity Reel No 3 pcs/reel pcs/inner box pcs/outer box 1500 1500 10500 ø1.5 +0.1 –0 8±0.1 1.75±0.1 2±0.05 4±0.1 B 0.3±0.05 A B A 5.5±0.1 12 +0.3 –0.1 5.5±0.05 ø1.5 +0.1 –0 SEC.B-B 2.1±0.1 6.4±0.1 0.4 3.9±0.2 SEC.A-A C 2012 FUJITSU SEMICONDUCTOR LIMITED SOL8-EMBOSSTAPE9 : NFME-EMB-X0084-1-P-1 (Dimensions in mm) Material : Conductive polystyrene Heat proof temperature : No heat resistance. Package should not be baked by using tape and reel. 26 DS501-00019-2v0-E MB85RC64A 2.2 IC orientation Index mark • ER type (User Direction of Feed) (Reel side) (User Direction of Feed) 2.3 Reel dimensions Reel cutout dimensions E ∗ D C B A W1 W2 r W3 ∗: Reel No Hub unit width dimensions 1 2 3 4 5 6 7 8 Tape width 8 12 16 24 Symbol A 254 ± 2 254 ± 2 330 ± 2 254 ± 2 330 ± 2 254 ± 2 330 ± 2 32 C 13 ± 0.2 D 21 ± 0.8 E 10 11 44 12 13 56 12 Dimensions in mm 14 15 16 24 330 ± 2 100 +2 -0 100 +2 -0 B 9 150 +2 -0 100 +2 -0 150 +2 -0 100 +2 -0 100 ± 2 13 +0.5 -0.2 20.5 +1 -0.2 2 ± 0.5 W1 8.4 +2 -0 W2 less than 14.4 12.4 +2 -0 less than 18.4 less than 22.4 less than 30.4 less than 38.4 less than 50.4 less than 62.4 less than 18.4 less than 22.4 less than 30.4 W3 7.9 ~ 10.9 11.9 ~ 15.4 15.9 ~ 19.4 23.9 ~ 27.4 31.9 ~ 35.4 43.9 ~ 47.4 55.9 ~ 59.4 12.4 ~ 14.4 16.4 ~ 18.4 24.4 ~ 26.4 r DS501-00019-2v0-E 16.4 +2 -0 24.4 +2 -0 32.4 +2 -0 44.4 +2 -0 +0.1 56.4 +2 12.4 +1 16.4 +1 -0 -0 -0 24.4 -0 1.0 27 MB85RC64A 2.4 Taping (φ330mm Reel) Dry Pack Packing Specifications Outside diameter: φ 330mm reel Label I *1, *4 Embossed tapes Label I *1, *4 Desiccant Humidity indicator Aluminum laminated bag Dry pack Label I *1, *4 Heat seal Inner box Inner box Label I *1, *4 Taping Outer box *2, *3 Outer box Use adhesive tapes. Label II-A *4 Label II-B *4 *1: For a product of witch part number is suffixed with “E1”, a “ G bag and the inner boxes. Pb ” marks is display to the moisture barrier *2: The size of the outer box may be changed depending on the quantity of inner boxes. *3: The space in the outer box will be filled with empty inner boxes, or cushions, etc. *4: Please refer to an attached sheet about the indication label. Note: The packing specifications may not be applied when the product is delivered via a distributer. 28 DS501-00019-2v0-E MB85RC64A 2.5 Product label indicators Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm × 100mm) Supplemental Label (20mm × 100mm)] XXXXXXXXXXXXXX (Customer part number or FJ part number) C-3 Label (LEAD FREE mark) (3N)1 XXXXXXXXXXXXXX XXX (Part number and quantity) QC PASS (3N)2 XXXXXXXXXX XXXXXX (FJ control number) XXX pcs XXXXXXXXXXXXXX (Quantity) (Customer part number or FJ part number) (Customer part number or FJ part number bar code) XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx XXXXXXXXXXXXXX (Customer part number or FJ part number) (FJ control number bar code) XX/XX XXXX-XXX XXX (Package count) XXXX-XXX XXX XXXXXXXXXX (FJ control number ) (Lot Number and quantity) XXXXXXXXXXXXXX (Comment) Perforated line Supplemental Label Label II-A: Label on Outer box [D Label] (100mm × 100mm) D Label XXXXXXXXXXXXX (Customer Name) (CUST.) XXXXXXXXX (Delivery Address) (DELIVERY POINT) XXXXXXXXXXXXXX (TRANS.NO.) (FJ control number) XXXXXXXXXXXXXX (PART NO.) (Customer part number or FJ part number) XXX (FJ control number) XXX (FJ control number) XXX (FJ control number) XXXXXXXXXXXXXX (Part number) (PART NAME) XXXXXXXXXXXXXX (Part number) XXX/XXX (Q’TY/TOTAL Q’TY) (CUSTOMER'S REMARKS) XXXXXXXXXXXXXXXXXXXX (3N)3 XXXXXXXXXXXXXX XXX XX (UNIT) (PACKAGE COUNT) XXX/XXX (3N)4 XXXXXXXXXXXXXX XXX (FJ control number + Product quantity) (FJ control number + Product quantity bar code) (Part number + Product quantity) (3N)5 XXXXXXXXXX (FJ control number) (Part number + Product quantity bar code) (FJ control number bar code) Label II-B: Outer boxes product indicate XXXXXXXXXXXXXX (Lot Number) XXXX-XXX XXXX-XXX (Part number) (Count) X X (Quantity) XXX XXX XXX Note: Depending on shipment state, “Label II-A” and “Label II-B” on the external boxes might not be printed. DS501-00019-2v0-E 29 MB85RC64A 2.6 Dimensions for Containers (1) Dimensions for inner box H W L Tape width L W H 12, 16 24, 32 44 40 365 50 345 65 56 75 (Dimensions in mm) (2) Dimensions for outer box H W L L W H 415 400 315 (Dimensions in mm) 30 DS501-00019-2v0-E MB85RC64A ■ MAJOR CHANGES IN THIS EDITION A change on a page is indicated by a vertical line drawn on the left side of that page. Page Section Change Results ■ FEATURES Revised the Data retention 10 years ( + 85 °C) →10 years ( + 85 °C), 95 years ( + 55 °C), over 200 years ( + 35 °C) ■ POWER ON/OFF SEQUENCE Revised the following description: “POWER ON SEQUENCE” → “POWER ON/OFF SEQUENCE” 1 Added the following description: “If the device does not operate within the specified conditions of read cycle, write cycle or power on/off sequence, memory data can not be guaranteed.” 14 Revised the following description: “VDD pin is required to be rising from 0 V because turning the power on from an intermediate level may cause malfunctions, when the power is turned on” →“If VDD falls down below 2.0V, VDD is required to be started from 0V to prevent malfunctions when the power is turned on again.” ■ FRAM CHARACTERISTICS DS501-00019-2v0-E Revised the table and Note 31 MB85RC64A FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://sg.fujitsu.com/semiconductor/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. 30F, Kerry Parkside, 1155 Fang Dian Road, Pudong District, Shanghai 201204, China Tel : +86-21-6146-3688 Fax : +86-21-6146-3660 http://cn.fujitsu.com/fss/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 902 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fsk/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 2/F, Green 18 Building, Hong Kong Science Park, Shatin, N.T., Hong Kong Tel : +852-2736-3232 Fax : +852-2314-4207 http://cn.fujitsu.com/fsp/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department