FUJITSU SEMICONDUCTOR
DATA SHEET
DS501-00044-2v0-E
Memory FRAM
64 K (8 K × 8) Bit I2C
MB85RC64TA
■ DESCRIPTION
The MB85RC64TA is an FRAM (Ferroelectric Random Access Memory) chip in a configuration of 8,192
words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the
nonvolatile memory cells.
Unlike SRAM, the MB85RC64TA is able to retain data without using a data backup battery.
The read/write endurance of the nonvolatile memory cells used for the MB85RC64TA has improved to be
at least 1013 cycles, significantly outperforming Flash memory and E2PROM in the number.
The MB85RC64TA does not need a polling sequence after writing to the memory such as the case of Flash
memory or E2PROM.
■ FEATURES
: 8,192 words × 8 bits
: Fully controllable by two ports: serial clock (SCL) and serial data (SDA).
: 3.4 MHz (Max @HIGH SPEED MODE)
1 MHz (Max @FAST MODE PLUS)
Read/write endurance
: 1013 times / byte
Data retention
: 10 years ( + 85 °C), 95 years ( + 55 °C), over 200 years ( + 35 °C)
Operating power supply voltage : 1.8 V to 3.6 V
Low power consumption
: Operating power supply current 170 μA (Typ @3.4 MHz)
Standby current 8 μA (Typ)
Sleep current 4 μA (Typ)
Operation ambient temperature range : − 40 °C to + 85 °C
Package
: 8-pin plastic SOP (FPT-8P-M09)
8-pin plastic SON (LCC-8P-M04)
RoHS compliant
• Bit configuration
• Two-wire serial interface
• Operating frequency
•
•
•
•
•
•
Copyright 2016 FUJITSU SEMICONDUCTOR LIMITED
2016.10
MB85RC64TA
■ PIN ASSIGNMENT
(TOP VIEW)
(TOP VIEW)
1
A0
8
VDD
A1
2
7
WP
A2
3
6
SCL
4
VSS
5
A0
1
8
VDD
A1
2
7
WP
A2
3
6
SCL
VSS
4
5
SDA
SDA
(FPT-8P-M09)
(LCC-8P-M04)
■ PIN FUNCTIONAL DESCRIPTIONS
Pin
Number
2
Pin Name
Functional Description
1 to 3
A0 to A2
Device Address pins
The MB85RC64TA can be connected to the same data bus up to 8 devices.
Device addresses are used in order to identify each of these devices. Connect
these pins to VDD pin or VSS pin externally. Only if the combination of VDD and
VSS pins matches a Device Address Code inputted from the SDA pin, the
device operates. In the open pin state, A0, A1 and A2 pins are internally pulleddown and recognized as the “L” level.
4
VSS
Ground pin
5
SDA
Serial Data I/O pin
This is an I/O pin which performs bidirectional communication for both memory
address and writing/reading data. It is possible to connect multiple devices. It is
an open drain output, so a pull-up resistor is required to be connected to the external circuit.
6
SCL
Serial Clock pin
This is a clock input pin for input/output serial data. Data is sampled on the rising edge of the clock and output on the falling edge.
7
WP
Write Protect pin
When the Write Protect pin is the “H” level, the writing operation is disabled.
When the Write Protect pin is the “L” level, the entire memory region can be
overwritten. The reading operation is always enabled regardless of the Write
Protect pin input level. The Write Protect pin is internally pulled down to VSS
pin, and that is recognized as the “L” level (write enabled) when the pin is the
open state.
8
VDD
Supply Voltage pin
DS501-00044-2v0-E
MB85RC64TA
■ BLOCK DIAGRAM
Control Logic
SCL
WP
Row Decoder
Serial/Parallel Converter
Address Counter
SDA
FRAM Array
8,192 × 8
Column Decoder/Sense Amp/
Write Amp
A0, A1, A2
■ I2C (Inter-Integrated Circuit)
The MB85RC64TA has the two-wire serial interface; the I2C bus, and operates as a slave device.
The I2C bus defines communication roles of “master” and “slave” devices, with the master side holding the
authority to initiate control. Furthermore, an I2C bus connection is possible where a single master device is
connected to multiple slave devices in a party-line configuration. In this case, it is necessary to assign a
unique device address to the slave device, the master side starts communication after specifying the slave
to communicate by addresses.
• I2C Interface System Configuration Example
VDD
Pull-up
Resistors
SCL
SDA
I2C Bus
Master
I2C Bus
MB85RC64TA
A2
0
A1
0
A0
0
I2C Bus
MB85RC64TA
A2
0
A1
0
A0
1
I2C Bus
MB85RC64TA
A2
0
A1
1
...
A0
0
Device address
DS501-00044-2v0-E
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MB85RC64TA
■ I2C COMMUNICATION PROTOCOL
The I2C bus is a two wire serial interface that uses a bidirectional data bus (SDA) and serial clock (SCL). A
data transfer can only be initiated by the master, which will also provide the serial clock for synchronization.
The SDA signal should change while the SCL is the “L” level. However, as an exception, when starting and
stopping communication sequence, the SDA is allowed to change while the SCL is the “H” level.
• Start Condition
To start read or write operations by the I2C bus, change the SDA input from the “H” level to the “L” level while
the SCL input is in the “H” level.
• Stop Condition
To stop the I2C bus communication, change the SDA input from the “L” level to the “H” level while the SCL
input is in the “H” level. In the reading operation, inputting the stop condition finishes reading and enters the
standby state. In the writing operation, inputting the stop condition finishes inputting the rewrite data and
enters the standby state.
• Start Condition, Stop Condition
SCL
SDA
“H” or “L”
Start
Stop
Note : At the write operation, the FRAM device does not need the programming wait time (tWC) after issuing the
Stop Condition.
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MB85RC64TA
■ ACKNOWLEDGE (ACK)
In the I2C bus, serial data including address or memory information is sent in units of 8 bits. The acknowledge
signal indicates that every 8 bits of the data is successfully sent and received. The receiver side usually
outputs the “L” level every time on the 9th SCL clock after each 8 bits are successfully transmitted and
received. On the transmitter side, the bus is temporarily released to Hi-Z every time on this 9th clock to allow
the acknowledge signal to be received and checked. During this Hi-Z-released period, the receiver side pulls
the SDA line down to indicate the “L” level that the previous 8 bits communication is successfully received.
In case the slave side receives Stop condition before sending or receiving the ACK “L” level, the slave side
stops the operation and enters to the standby state. On the other hand, the slave side releases the bus state
after sending or receiving the NACK “H” level. The master side generates Stop condition or Start condition
in this released bus state.
• Acknowledge timing overview diagram
1
SCL
2
3
8
SDA
9
ACK
Start
DS501-00044-2v0-E
The transmitter side should always release SDA on the
9th bit. At this time, the receiver side outputs a pull-down if
the previous 8 bits data are received correctly (ACK response).
5
MB85RC64TA
■ DEVICE ADDRESS WORD (Slave address)
Following the start condition, the master sends the 8 bits device address word to start I2C communication.
The device address word (8 bits) consists of a device Type code (4 bits), device address code (3 bits), and
a read/write code (1 bit).
• Device Type Code (4 bits)
The upper 4 bits of the device address word are a device type code that identifies the device type, and are
fixed at “1010” for the MB85RC64TA.
• Device Address Code (3 bits)
Following the device type code, the 3 bits of the device address code are input in order of A2, A1 and A0.
The device address code identifies one device from up to eight devices connected to the bus.
Each MB85RC64TA is given a unique 3 bits code on the device address pin (external hardware pin A2, A1
and A0). The slave only responds if the received device address code is equal to this unique 3 bits code.
• Read/Write Code (1 bit)
The 8th bit of the device address word is the R/W (read/write) code. When the R/W code is “0”, a write
operation is enabled, and the R/W code is “1”, a read operation is enabled for the MB85RC64TA.
It turns to a stand-by state if the device code is not “1010” or device address code does not equal to pins
A2, A1 and A0.
• Device Address Word
Start
1
2
3
4
5
6
7
8
9
1
2
..
SCL
SDA
ACK
S
1
0
1
Device Code
0
A2
A1
A0
R/W
A
..
Device Address Code Read/Write Code
Access from master
Access from slave
S Start Condition
A ACK (SDA is the "L" level)
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MB85RC64TA
■ DATA STRUCTURE
In the I2C bus, the acknowledge “L” level is output on the 9th bit by a slave, after the 8 bits of the device
address word following the start condition are input by a master. After confirming the acknowledge response
by the master, the master outputs 8 bits × 2 memory address to the slave. When the each memory address
input ends, the slave again outputs the acknowledge “L” level. After this operation, the I/O data follows in
units of 8 bits, with the acknowledge “L” level output after every 8 bits.
It is determined by the R/W code whether the data line is driven by the master or the slave. However, the
clock line shall be driven by the master. For a write operation, the slave will accept 8 bits from the master,
then send an acknowledge. If the master detects the acknowledge, the master will transfer the next 8 bits.
For a read operation, the slave will place 8 bits on the data line, then wait for an acknowledge from the master.
■ FRAM ACKNOWLEDGE -- POLLING NOT REQUIRED
The MB85RC64TA performs write operations at the same speed as read operations, so any waiting time for
an ACK polling* does not occur. The write cycle takes no additional time.
*: In E2PROM, the Acknowledge Polling is performed as a progress check whether rewriting is executed or not.
It is normal to judge by the 9th bit of Acknowledge whether rewriting is performed or not after inputting the
start condition and then the device address word (8 bits) during rewriting.
■ WRITE PROTECT (WP)
The entire memory array can be write protected using the Write Protect pin. When the Write Protect pin is
set to the “H” level, the entire memory array will be write protected. When the Write Protect pin is the “L”
level, entire memory array will be rewritten. Reading is allowed regardless of the WP pin's “H” level or “L” level.
Note : The Write Protect pin is pulled down internally to VSS pin, therefore if the Write Protect pin is open, the
pin status is detected as the “L” level (write enabled).
DS501-00044-2v0-E
7
MB85RC64TA
■ COMMAND
• Byte Write
If the device address word (R/W “0” input) is sent following the start condition, the slave responds with an
ACK. After this ACK, write addresses and data are sent in the same way, and the write ends by generating
a stop condition at the end.
S
1 0 1 0 A2 A1 A0 0 A
Address
High 8bits
A
0 00XXXXX
Address
Low 8bits
A
Write
Data 8bits
A P
X X X X X X XX
Access from master
MSB
LSB
Access from slave
S Start Condition
P Stop Condition
A ACK (SDA is the "L" level)
Note : In the MB85RC64TA, input “000” as the upper 3 bits of the MSB.
• Page Write
If additional 8 bits are continuously sent after the same command (except stop condition) as Byte Write, a
page write is performed. The memory address rolls over to first memory address (0000H) at the end of the
address. Therefore, if more than 8 Kbytes are sent, the data is overwritten in order starting from the start of
the memory address that was written first. Because FRAM performs the high-speed write operations, the
data will be written to FRAM right after the ACK response finished.
S
1 0 1 0 A2 A1 A0 0 A
Address
High 8bits
A
Address
Low 8bits
A
Write
Data 8bits
A
Write
Data
...
A P
Access from master
Access from slave
S Start Condition
P Stop Condition
A ACK (SDA is the "L" level)
Note : It is not necessary to take a period for internal write operation cycles from the buffer to the memory after
the stop condition is generated.
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DS501-00044-2v0-E
MB85RC64TA
• Current Address Read
When the previous write or read operation finishes successfully up to the stop condition and assumes the
last accessed address is “n”, then the address at “n+1” is read by sending the following command unless
turning the power off. If the memory address is last address, the address counter will roll over to 0000H. The
current address in memory address buffer is undefined immediately after the power is turned on.
Access from master
Access from slave
S Start Condition
(n+1) address
S
1 0 1 0 A2 A1 A0 1 A
Read
Data 8bits
N P
P Stop Condition
A
ACK(SDA is the "L" level)
N NACK (SDA is the "H" level)
• Random Read
The one byte of data from the memory address saved in the memory address buffer can be read out
synchronously to SCL by specifying the address in the same way as for a write, and then issuing another
start condition and sending the Device Address Word (R/W “1” input).
The final NACK is issued by the receiver that receives the data. In this case, this bit is issued by the master
side.
S
1 0 1 0 A2 A1 A0 0 A
Address
High 8bits
A
Address
Low 8bits
A S
1 0 1 0 A2 A1 A0 1 A
Read
Data 8bits
N P
Access from master
Access from slave
S Start Condition
P Stop Condition
A
ACK (SDA is the "L" level)
N NACK (SDA is the "H" level)
DS501-00044-2v0-E
9
MB85RC64TA
• Sequential Read
Data can be received continuously following the Device address word (R/W “1” input) after specifying the
address in the same way as for Random Read. If the read reaches the end of address, the internal read
address automatically rolls over to first memory address 0000H and keeps reading.
...
A
Read
Data 8bits
A
Read
Data
...
A
Read
Data 8bits
N P
Access from master
Access from slave
P Stop Condition
A ACK (SDA is the "L" level)
N NACK (SDA is the "H" level)
10
DS501-00044-2v0-E
MB85RC64TA
• High Speed Mode
MB85RC64TA supports High Speed mode up to 3.4 MHz. By sending an entry command (0000 1XXX) after
start condition from the master side, it informs to the slave that the data transmission with High Speed mode
will start.
Since there is no slave side which is allowed to respond to this entry command, NACK response continues
from the slave side. After the master side recognizes this NACK response, the master side changes its state
to High Speed mode and enables the bidirectional communication up to 3.4 MHz.
By sending Stop condition, it exits out of the state in High Speed communication.
Byte Write @High Speed Mode
S
0 0 0 0 1 X X X N S
1 0 1 0 A2 A1 A0 0 A
Address
High 8bits
A
Address
Low 8bits
A
Write
Data 8bits
A P
Address
High 8bits
A
Address
Low 8bits
A
Write
Data 8bits
A
Read
Data 8bits
N P
Page Write @High Speed Mode
S 0 0 0 0 1 X X X N S 1 0 1 0 A2 A1 A0 0 A
Write
Data
...
A P
Current Address Read @High Speed Mode
S
0 0 0 0 1 X X X N S
1 0 1 0 A2 A1 A0 1 A
Random Address Read @High Speed Mode
S
0 0 0 0 1 X X X N S 1 0 1 0 A2 A1 A0 0 A
Address
High 8bits
A
Address
Low 8bits
A S
1 0 1 0 A2 A1 A0 1 A
Read
Data 8bits
N P
Address
High 8bits
A
Address
Low 8bits
A S
1 0 1 0 A2 A1 A0 1 A
Read
Data 8bits
A
Sequential Read @High Speed Mode
S
0 0 0 0 1 X X X N S 1 0 1 0 A2 A1 A0 0 A
...
A
Read
Data 8bits
A
Read
Data
...
A
Read
Data 8bits
...
N P
Access from master
Standard Mode
Fast Mode
Fast Mode Plus
DS501-00044-2v0-E
High Speed Mode
Access from slave
S
Start Condition
P
Stop Condition
ACK(SDA is the “L” level)
NACK(SDA is the “H” level)
A
A
N
N
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MB85RC64TA
• Sleep Mode
MB85RC64TA provides Sleep mode which reduces less current consumption than Standby mode, by stooping the internal regulator circuits. Following sequences enable the Sleep mode transition.
a) The master sends start condition followed by F8H.
b) After ACK response from slave, the master sends the device address word.
In this device address word, Read/Write code are Don't care.
c) After ACK response from slave, the master re-sends the start condition followed by 86H.
d) The slave moves to Sleep mode after ACK response to the master.
S 1 1 1 1 1 0 0 0 A 1 0 1 0 A2 A1 A0 R/W A S 1 0 0 0 0 1 1 0 A P
Access from master
Access from slave
S
Start Condition
P
Stop Condition
A
ACK(SDA is the “L” level)
Even if the MB85RC64TA stays in the Sleep mode, SDA and SCL signals are monitored. Following sequences
enable the transition to Standby mode after recovery time (tREC) of internal regulator circuits.
a) The master sends start condition followed by device address word.
In this device address word, Read/Write code are Don't care.
b) At the rising edge of 9th clock from start condition, an internal regulator starts to operate its recovery
sequence.
c) After the recovery time (tREC) passed, standby mode enabled.
After returning to Standby mode, reading and writing are enabled by sending each command starts with start
condition.
S 1 0 1 0 A2 A1 A0 R/W X
Recovery
operation
S 1 0 1 0 A2 A1 A0 R/W A ͐
Access from master
Start recovery operation
Access from slave
12
S
Start Condition
A
ACK(SDA is the “L” level)
DS501-00044-2v0-E
MB85RC64TA
• Device ID
The Device ID command reads fixed Device ID. The size of Device ID is 3 bytes and consists of manufacturer
ID and product ID. The Device ID is read-only and can be read out by following sequences.
a) The master sends the Reserved Slave ID F8H after the START condition.
b) The master sends the device address word after the ACK response from the slave.
In this device address word, R/W code are “Don't care”.
c) The master re-sends the START condition followed by the Reserved Slave ID F9H after the ACK response
from the slave.
d) The master read out the Device ID succeedingly in order of Data Byte 1st / 2nd / 3rd after the ACK
response from the slave.
e) The master responds the NACK (SDA is the “H” level) after reading 3 bytes of the Device ID.
In case the master respond the ACK after reading 3 bytes of the Device ID, the master re-reading the
Device ID from the 1st byte.
Reserved
Reserved
R
S Slave ID A 1 0 1 0 A2 A1 A0 / A S Slave ID A Data Byte A Data Byte A Data Byte N P
W
1st
2nd
3rd
(F9H)
(F8H)
Access from master
Access from slave
S Start Condition
P Stop Condition
A ACK (SDA is the "L" level)
N NACK (SDA is the "H" level)
Data Byte 1st
Manufacture ID = 00AH
Data Byte 2nd
Data Byte 3rd
Product ID = 358H
11 10
9
8 7 6 5 4 3
Fujitsu Semiconductor
2
1
0
11 10 9 8
Density = 3H
7
6
5 4 3 2
Proprietary use
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
DS501-00044-2v0-E
0
0
0
0
1
0
1
1
1
1
0
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MB85RC64TA
■ SOFTWARE RESET SEQUENCE OR COMMAND RETRY
In case the malfunction has occurred after power on, the master side stopped the I2C communication during
processing, or unexpected malfunction has occurred, execute the following (1) software recovery sequence
just before each command, or (2) retry command just after failure of each command.
(1) Software Reset Sequence
Since the slave side may be outputting “L” level, do not force to drive “H” level, when the master side drives
the SDA port. This is for preventing a bus conflict. The additional hardware is not necessary for this software
reset sequence.
9 set of “Start Conditions and one “1” data”
SCL
SDA
Hi-Z state by pull up Resistor
Send “Start Condition and one data “1””.
Repeat these 9 times just before Write or Read command.
(2) Command Retry
Command retry is useful to recover from failure response during I2C communication.
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DS501-00044-2v0-E
MB85RC64TA
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Min
Max
Unit
Power supply voltage*
VDD
− 0.5
+ 4.0
V
Input voltage*
VIN
− 0.5
VDD + 0.5 ( ≤ 4.0)
V
VOUT
− 0.5
VDD + 0.5 ( ≤ 4.0)
V
TA
− 40
+ 85
°C
Tstg
− 55
+ 125
°C
Output voltage*
Operation ambient temperature
Storage temperature
*: These parameters are based on the condition that VSS is 0 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Min
Typ
Max
Unit
Power supply voltage*1
VDD
1.8
3.3
3.6
V
Operation ambient temperature*2
TA
− 40
⎯
+ 85
°C
*1: These parameters are based on the condition that VSS is 0 V.
*2: Ambient temperature when only this device is working. Please consider it to be the almost same as the
package surface temperature.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
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15
MB85RC64TA
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(within recommended operating conditions)
Parameter
Symbol
Input leakage current*1
Output leakage current*
2
Operating power supply
current
Condition
Value
Min
Typ
Max
Unit
|ILI|
VIN = 0 V to VDD
⎯
⎯
1
μA
|ILO|
VOUT = 0 V to VDD
⎯
⎯
1
μA
SCL = 0.1 MHz
⎯
35
⎯
μA
SCL = 1 MHz
⎯
80
100
μA
SCL = 3.4 MHz
⎯
170
190
μA
⎯
8
10
μA
4
6
μA
IDD
Standby current
ISB
SCL, SDA = VDD
A0, A1, A2, WP = 0 V or
VDD or Open
Under Stop Condition
Sleep current
IZZ
SCL, SDA = VDD
A0, A1, A2, WP = 0 V
“H” level input voltage
VIH
VDD = 1.8 V to 3.6 V
VDD × 0.7
⎯
VDD
V
“L” level input voltage
VIL
VDD = 1.8 V to 3.6 V
VSS
⎯
VDD × 0.3
V
“L” level output voltage
VOL
IOL = 3 mA
⎯
⎯
0.4
V
Input resistance for
WP, A0, A1 and A2 pins
RIN
VIN = VIL (Max)
50
⎯
⎯
kΩ
VIN = VIH (Min)
1
⎯
⎯
MΩ
*1: Applicable pin: SCL,SDA
*2: Applicable pin: SDA
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MB85RC64TA
2. AC Characteristics
Value
STANDARD
MODE
FAST MODE
FAST MODE
PLUS
Min
Max
Min
Max
Min
Max
Min
Max
0
100
0
400
0
4000
⎯
600
⎯
TLOW
4700
⎯
1300
⎯
SCL/SDA rising time
Tr
⎯
1000
⎯
SCL/SDA falling time
Tf
⎯
300
Start condition hold
THD:STA
4000
Start condition setup
TSU:STA
SDA input hold
Parameter
Symbol
SCL clock frequency
Unit
1000
0
3400
kHz
*1
⎯
60
⎯
ns
*2
500
⎯
160
⎯
ns
300
⎯
300
⎯
80
ns
⎯
300
⎯
120
⎯
80
ns
⎯
600
⎯
250
⎯
160
⎯
ns
4700
⎯
600
⎯
250
⎯
160
⎯
ns
THD:DAT
0
⎯
0
⎯
0
⎯
0
⎯
ns
SDA input setup
TSU:DAT
250
⎯
100
⎯
50
⎯
15*4
⎯
ns
SDA output hold
TDH:DAT
0
⎯
0
⎯
0
⎯
0
⎯
ns
Stop condition setup
TSU:STO
4000
⎯
600
⎯
250
⎯
160
⎯
ns
SDA output access after SCL falling
TAA
⎯
3000
⎯
900
⎯
450*3
⎯
130
ns
Pre-charge time
TBUF
4700
⎯
1300
⎯
500
⎯
300
⎯
ns
Noise suppression
time
(SCL and SDA)
TSP
⎯
50
⎯
50
⎯
50
⎯
5
ns
Clock high time
Clock low time
FSCL
HIGH SPEED
MODE
THIGH
260
*1: 300 ns @VDD ≤ 2.7 V
*2: 600 ns @VDD ≤ 2.7 V
*3: 550 ns @VDD ≤ 2.7 V
*4: 20 ns @VDD ≤ 2.7 V
AC characteristics were measured under the following measurement conditions.
Power supply voltage
: 1.8 V to 3.6 V
Operation ambient temperature : − 40 °C to + 85 °C
Input voltage magnitude
: Vss to VDD
Input rising time
: 5 ns
Input falling time
: 5 ns
Input judge level
: VDD/2
Output judge level
: VDD/2
Output load capacitance
: 100 pF
DS501-00044-2v0-E
17
MB85RC64TA
3. AC Timing Definitions
TSU:DAT
SCL
VIH
VIL
SDA
Start
THD:DAT
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
TSU:STA THD:STA
TSU:STO
Tr
THIGH
SCL
Stop
VIH
Tf
TLOW
VIH
VIL
VIL
VIH
VIH
VIL
VIL
VIH
SDA
Stop
VIH
VIL
Start
VIH
VIL
VIH
VIL
VIL
TBUF
Tr
T
TDH:DAT f
TAA
Tsp
VIH
SCL
VIL
VIL
VIH
SDA
VIL
Valid
VIH
VIL
VIL
1/FSCL
4. Pin Capacitance
Parameter
Symbol
Conditions
I/O capacitance
CI/O
Input capacitance
CIN
VDD = 3.3 V,
f = 1 MHz, TA = + 25 °C
Value
Unit
Min
Typ
Max
⎯
⎯
8
pF
⎯
⎯
8
pF
5. AC Test Load Circuit
3.3 V
1.1 kΩ
Output
100 pF
18
DS501-00044-2v0-E
MB85RC64TA
■ POWER ON/OFF SEQUENCE
tf
tpd
tr
tpu
VDD
VDD
VDD (Min)
VDD (Min)
VIH (Min)
VIH (Min)
VIL (Max)
VIL (Max)
0V
0V
SDA, SCL > VDD × 0.8 *
SDA, SCL
SDA, SCL : Don't care
SDA, SCL > VDD × 0.8 *
SDA, SCL
* : SDA, SCL (Max) < VDD + 0.5 V
Parameter
Symbol
Value
Min
Max
Unit
SDA, SCL level hold time during power down
tpd
85
⎯
ns
SDA, SCL level hold time during power up
tpu
250
⎯
μs
Power supply rising time
tr
0.05
⎯
ms/V
Power supply falling time
tf
0.1
⎯
ms/V
tREC
⎯
400
μs
Internal regulator recovery time
If the device does not operate within the specified conditions of read cycle, write cycle or power on/off
sequence, memory data can not be guaranteed.
■ FRAM CHARACTERISTICS
Item
Min
Max
Read/Write Endurance*1
1013
⎯
Times/byte Operation Ambient Temperature TA = + 85 °C
10
⎯
Operation Ambient Temperature TA = + 85 °C
95
⎯
≥ 200
⎯
2
Data Retention*
Unit
Years
Parameter
Operation Ambient Temperature TA = + 55 °C
Operation Ambient Temperature TA = + 35 °C
*1 : Total number of reading and writing defines the minimum value of endurance, as an FRAM memory operates
with destructive readout mechanism.
*2 : Minimum values define retention time of the first reading/writing data right after shipment, and these values
are calculated by qualification results.
DS501-00044-2v0-E
19
MB85RC64TA
■ NOTE ON USE
• We recommend programming of the device after reflow. Data written before reflow cannot be guaranteed.
• During the access period from the start condition to the stop condition, keep the level of WP, A0, A1 and
A2 pins to the “H” level or the “L” level.
■ ESD AND LATCH-UP
Test
DUT
Value
ESD HBM (Human Body Model)
JESD22-A114 compliant
≥ |2000 V|
ESD MM (Machine Model)
JESD22-A115 compliant
≥ |200 V|
ESD CDM (Charged Device Model)
JESD22-C101 compliant
≥ |1000 V|
Latch-Up (I-test)
JESD78 compliant
MB85RC64TAPNF-G-BDE1
⎯
Latch-Up (Vsupply overvoltage test)
JESD78 compliant
⎯
Latch-Up (Current Method)
Proprietary method
⎯
Latch-Up (C-V Method)
Proprietary method
≥ |200 V|
• Current method of Latch-Up Resistance Test
Protection Resistance
A
IIN
VIN
Test terminal
VDD
+
DUT
-
VSS
VDD
(Max.Rating)
V
Reference
terminal
Note : The voltage VIN is increased gradually and the current IIN of 300 mA at maximum shall flow. Confirm the
latch up does not occur under IIN = ± 300 mA.
In case the specific requirement is specified for I/O and IIN cannot be 300 mA, the voltage shall be
increased to the level that meets the specific requirement.
20
DS501-00044-2v0-E
MB85RC64TA
• C-V method of Latch-Up Resistance Test
Protection Resistance
A
1
Test
2 terminal
SW
+
VIN
V
-
C
200pF
VDD
DUT
VDD
(Max.Rating)
VSS
Reference
terminal
Note
Charge voltage alternately switching 1 and 2 approximately 2 sec interval. This switching process is
considered as one cycle.
Repeat this process 5 times. However, if the latch-up condition occurs before completing 5 times, this
test must be stopped immediately.
■ REFLOW CONDITIONS AND FLOOR LIFE
[ JEDEC MSL ] : Moisture Sensitivity Level 3 (ISP/JEDEC J-STD-020D)
■ CURRENT STATUS ON CONTAINED RESTRICTED SUBSTANCES
This product complies with the regulations of REACH Regulations, EU RoHS Directive and China RoHS.
DS501-00044-2v0-E
21
MB85RC64TA
■ ORDERING INFORMATION
Package
Shipping form
Minimum shipping
quantity
MB85RC64TAPNF-G-BDE1
8-pin, plastic SOP
(FPT-8P-M09)
Tube
⎯*
MB85RC64TAPNF-G-BDERE1
8-pin, plastic SOP
(FPT-8P-M09)
Embossed Carrier tape
1500
MB85RC64TAPN-G-AMEWE1
8-pin, plastic SON
(LCC-8P-M04)
Embossed Carrier tape
1500
Part number
*: Please contact our sales office about minimum shipping quantity.
22
DS501-00044-2v0-E
MB85RC64TA
■ PACKAGE DIMENSION
8-pin plastic SOP
1.27 mm
Lead pitch
Package width ×
package length
3.9 mm × 4.89 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting heigth
1.73 mm MAX
Weight
0.08 g
(FPT-8P-M09)
8-pin plastic SOP
㸦FPT-8P-M09㸧
Note 1) *1: These dimensions do not include resin protrution.
Note 2) *2: These dimensions do not include resin protrution.
5pin
8pin
㹼
0.17MAX
3.81㹼3.99*2
0.12MAX
“F”
4×R0.05
1pin
4pin
1.27(Typ)
+0.063
0.42 -0.064
5.30MAX
0.22 -0.017
+0.034
0.102㹼0.254
1.55㹼1.73
1.5(Typ)
4.80㹼4.98*1
0.406㹼0.889
Details of “F” part
C
2015 FUJITSU SEMICONDUCTOR LIMITED F08-17Sc
Dimenssions in mm
(Continued)
DS501-00044-2v0-E
23
MB85RC64TA
(Continued)
8-pin plastic SON
Lead pitch
0.5 mm
Package width ×
package length
2.0 mm × 3.0 mm
Sealing method
Plastic mold
Mounting height
0.75 mm MAX
Weight
0.015g
(LCC-8P-M04)
8-pin plastic SON
(LCC-8P-M04)
1.6±0.10
(.063±.004)
2.00±0.07
(.079±.003)
0.40±0.07
(.016±.003)
3.00±0.07
(.118±.003)
1.40±0.10
(.055±.004)
INDEX AREA
1PIN CORNER
(C0.30(C.012))
0.50(.020)
TYP
0.05(.002) MAX
C
24
0.25±0.05
(.010±.002)
0.70±0.05
(.028±.002)
0.15(.006)
2011 FUJITSU SEMICONDUCTOR LIMITED HMbC8-04Sc-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
DS501-00044-2v0-E
MB85RC64TA
■ MARKING
[MB85RC64TAPNF-G-BDE1]
[MB85RC64TAPNF-G-BDERE1]
C 6 4 TA
11547
701
[FPT-8P-M09]
[MB85RC64TAPN-G-AMEWE1]
Y Y WW
C64 TA
0XX
[LCC-8P-M04]
DS501-00044-2v0-E
25
MB85RC64TA
■ MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page
Section
Change Results
26
1
■ FEATURES
Added Data retention under 85 °C.
19
■ FRAM CHARACTERISTICS
Added Data retention under 85 °C.
DS501-00044-2v0-E
MB85RC64TA
MEMO
DS501-00044-2v0-E
27
MB85RC64TA
FUJITSU SEMICONDUCTOR LIMITED
Shin-Yokohama Chuo Building, 2-100-45 Shin-Yokohama,
Kohoku-ku, Yokohama, Kanagawa 222-0033, Japan
http://jp.fujitsu.com/fsl/en/
All Rights Reserved.
FUJITSU SEMICONDUCTOR LIMITED, its subsidiaries and affiliates (collectively, "FUJITSU SEMICONDUCTOR") reserves
the right to make changes to the information contained in this document without notice. Please contact your FUJITSU
SEMICONDUCTOR sales representatives before order of FUJITSU SEMICONDUCTOR device.
Information contained in this document, such as descriptions of function and application circuit examples is presented solely for
reference to examples of operations and uses of FUJITSU SEMICONDUCTOR device. FUJITSU SEMICONDUCTOR disclaims
any and all warranties of any kind, whether express or implied, related to such information, including, without limitation, quality,
accuracy, performance, proper operation of the device or non-infringement. If you develop equipment or product incorporating the
FUJITSU SEMICONDUCTOR device based on such information, you must assume any responsibility or liability arising out of or
in connection with such information or any use thereof. FUJITSU SEMICONDUCTOR assumes no responsibility or liability for any
damages whatsoever arising out of or in connection with such information or any use thereof.
Nothing contained in this document shall be construed as granting or conferring any right under any patents, copyrights, or any other
intellectual property rights of FUJITSU SEMICONDUCTOR or any third party by license or otherwise, express or implied.
FUJITSU SEMICONDUCTOR assumes no responsibility or liability for any infringement of any intellectual property rights or other
rights of third parties resulting from or in connection with the information contained herein or use thereof.
The products described in this document are designed, developed and manufactured as contemplated for general use including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and
manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high levels of safety is secured,
could lead directly to death, personal injury, severe physical damage or other loss (including, without limitation, use in nuclear
facility, aircraft flight control system, air traffic control system, mass transport control system, medical life support system and
military application), or (2) for use requiring extremely high level of reliability (including, without limitation, submersible repeater
and artificial satellite). FUJITSU SEMICONDUCTOR shall not be liable for you and/or any third party for any claims or damages
arising out of or in connection with above-mentioned uses of the products.
Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs and
safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures into your
facility, equipments and products such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal
operating conditions.
The products and technical information described in this document are subject to the Foreign Exchange and Foreign Trade Control
Law of Japan, and may be subject to export or import laws or regulations in U.S. or other countries. You are responsible for ensuring
compliance with such laws and regulations relating to export or re-export of the products and technical information described herein.
All company names, brand names and trademarks herein are property of their respective owners.
Edited: System Memory Business Division
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