FUJITSU SEMICONDUCTOR
DATA SHEET
DS501-00043-2v0-E
Memory FRAM
4 M (512 K × 8) Bit Quad SPI
MB85RQ4ML
■ DESCRIPTION
MB85RQ4ML is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 524,288
words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the
nonvolatile memory cells.
MB85RQ4ML adopts the Quad Serial Peripheral Interface (QSPI) which can realize a high bandwidth such
as Read and Write at 54 MB/s using four bi-directional pins (Quad I/O).
The MB85RQ4ML is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85RQ4ML can be used for 1013 read/write operations, which is a significant
improvement over the number of read and write operations supported by Flash memory and E2PROM.
MB85RQ4ML does not take long time to write data like Flash memories or E2PROM.
MB85RQ4ML is able to write data at a high bandwidth without any waiting time and fits perfectly into
Networking, Gaming, Industrial computing, Camera, RAID controllers, etc.
■ FEATURES
: 524,288 words × 8 bits
: SPI (Serial Peripheral Interface) / Quad SPI
Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)
Write supports
: Single data input / Quad data input / Quad address and data input /
QPI mode
Read supports
: Single data output / Fast single data output / Fast quad data output /
Fast quad address input and data output / QPI mode / XIP mode
Operating frequency
: 108 MHz (Except normal READ command)
High endurance
: 1013 Read/Write per byte
Data retention
: 10 years (+85 °C), 95 years ( + 55 °C), over 200 years ( + 35 °C)
Operating power supply voltage : 1.7 V to 1.95 V (Single power supply)
Power consumption
: Operating power supply current 20.0 mA (Typ@Quad I/O 108 MHz)
Standby current 70 μA (Typ), 400 μA (Max)
Operation ambient temperature range : -40 °C to +85 °C
Package
: 16-pin plastic SOP (FPT-16P-M24)
RoHS compliant
• Bit configuration
• Serial Peripheral Interface
•
•
•
•
•
•
•
•
•
Copyright 2016 FUJITSU SEMICONDUCTOR LIMITED
2016.10
MB85RQ4ML
■ PIN ASSIGNMENT
(TOP VIEW)
SCK
HOLD (IO3)
SI (IO0)
VDD
NC
NC
NC
NC
NC
NC
NC
NC
CS
VSS
SO (IO1)
WP (IO2)
(FPT-16P-M24)
NC: Non connect pin
■ PIN FUNCTIONAL DESCRIPTIONS
Pin No. Pin Name
Functional description
CS
Chip Select pin
This is an input pin to make chips select. When CS is “H” level, device is in deselect
(standby) status and SO becomes High-Z. Inputs from other pins are ignored for this
time. When CS is “L” level, device is in select (active) status. CS has to be “L” level before
inputting op-code. The Chip Select pin is pulled up internally to the VDD pin via a resistor.
WP
(IO2)
Write Protect pin except in Quad SPI mode
This is a pin to control writing to a status register. The writing of status register (see “■
STATUS REGISTER”) is protected in related with WP and WPEN bit of the status
register. See “■ WRITING PROTECT” for detail.
(Serial Data Input Output 2 in Quad SPI mode)
1
HOLD
(IO3)
Hold pin except in Quad SPI mode
This pin is used to interrupt serial input/output without making chips deselect. When
HOLD is “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become
“don’t care”. While the hold operation, CS has to be retained “L” level.
(Serial Data Input Output 3 in Quad SPI mode)
16
SCK
Serial Clock pin
This is a clock input pin to input/output serial data. Inputs data are latched synchronously
to a rising edge, Outputs data occur synchronously to a falling edge.
15
SI
(IO0)
Serial Data Input pin except in Quad SPI mode
This is an input pin of serial data. This inputs op-code, addresses and writing data.
(Serial Data Input Output 0 in Quad SPI mode)
8
SO
(IO1)
Serial Data Output pin except in Quad SPI mode
This is an output pin of serial data. Reading data of FRAM memory cell array and status
register data are output. This is High-Z during standby.
(Serial Data Input Output 1 in Quad SPI mode)
2
VDD
Supply Voltage pin
10
VSS
Ground pin
7
9
* When using Quad SPI mode instructions, the SI, SO, WP and HOLD pins become bidirectional IO0, IO1, IO2
and IO3 pins.
2
DS501-00043-2v0-E
MB85RQ4ML
■ BLOCK DIAGRAM
SO (IO1)
Decoder
Control Circuit
Serial I/O Interface
CS
SI (IO0)
Address Counter
SCK
HOLD (IO3)
FRAM Cell Array
524,288 ✕ 8
Sense Amp/Write Amp
Data Register
WP (IO2)
FRAM
Status Register
■ SPI MODE
MB85RQ4ML corresponds to the SPI mode 0 (CPOL = 0, CPHA = 0) , and SPI mode 3 (CPOL = 1, CPHA = 1) .
CS
SCK
SI
7
6
5
MSB
4
3
2
1
0
LSB
SPI Mode 0
CS
SCK
SI
7
6
5
4
MSB
3
2
1
0
LSB
SPI Mode 3
DS501-00043-2v0-E
3
MB85RQ4ML
■ SERIAL PERIPHERAL INTERFACE (SPI)
• SPI
MB85RQ4ML works as a slave of SPI. SPI uses the SI serial input pin to write op-code, addresses or data
to the device on the rising edge of SCK. The SO serial output pin is used to read data or status register
from the device on the falling edge of SCK.
• Quad SPI
MB85RQ4ML works as a slave of Quad SPI. MB85RQ4ML supports Quad SPI mode using the “FRQO”,
“FRQAD”, “WQD” and “WQAD” commands, QPI mode using the “EQPI” and “DQPI” commands and XIP
mode. When using Quad SPI mode instructions, the SI, SO, WP and HOLD pins become bidirectional IO0,
IO1, IO2 and IO3 pins.
■ STATUS REGISTER
Bit No.
Bit Name
Function
WPEN
Status Register Write Protect
This is a bit composed of nonvolatile memory (FRAM). WPEN protects
writing to a status register (refer to “■ WRITING PROTECT”) relating with
WP input. Writing with the WRSR command and reading with the RDSR
command are possible.
6
QPI
QPI mode bit
This is a volatile bit and “0” after power-on and defines QPI mode
enabled/disabled.
1 = QPI mode enabled, set by the EQPI command
0 = QPI mode disabled, reset by the DQPI command
The QPI bit cannot be changed with the WRSR command. Reading with
the RDSR command is possible.
5
LC1
4
LC0
3
BP1
2
BP0
7
4
1
WEL
0
0
LC (Latency Control) mode bit
These are bits composed of nonvolatile memories.
These define number of dummy cycles for the FRQO and FRQAD commands (refer to “■ LC Mode”).
Writing with the WRSR command and reading with the RDSR
command are possible.
Block Protect
These are bits composed of nonvolatile memories. These define size of
write protect block for the WRITE, WQD and WQAD commands (refer to
“■ BLOCK PROTECT”). Writing with the WRSR command and reading
with the RDSR command are possible.
Write Enable Latch
This is a volatile bit and “0” after power-on and indicates FRAM Array and
status register are writable.
1 = writable, set by the WREN command
0 = unwritable, reset by the WRDI command
With the RDSR command, reading is possible but writing is impossible
with the WRSR command.
WEL is reset after the following operations.
After power-on.
After the WRDI command recognition.
At the rising edge of CS after WRSR command recognition.
At the rising edge of CS after WRITE command recognition.
At the rising edge of CS after WQD command recognition.
At the rising edge of CS after WQAD command recognition.
This is a bit fixed to “0”.
DS501-00043-2v0-E
MB85RQ4ML
■ OP-CODE
MB85RQ4ML accepts 8 kinds of SPI Mode command, 4 kinds of Quad SPI Mode command and 2 kinds
of QPI Mode command specified in op-code. Op-code is a code composed of 8 bits shown in the table
below. Do not input invalid codes other than those codes. If CS is risen while inputting op-code, the command
are not performed.
Mode Name
Description
Op-code
Max Freq. (MHz)
QPI
XIP
SPI
WREN
Set Write Enable Latch
0000 0110B
108
Yes
No
WRDI
Reset Write Enable Latch
0000 0100B
108
Yes
No
RDSR
Read Status Register
0000 0101B
108
Yes
No
WRSR
Write Status Register
0000 0001B
108
No
No
READ
Read
0000 0011B
40
No
No
WRITE Write
0000 0010B
108
No
No
Read Device ID
1001 1111B
108
No
No
FSTRD Fast Read Memory Code
0000 1011B
108
No
Yes
FRQO
Fast Read Quad Output
0110 1011B
108*
No
Yes
FRQAD Fast Read Quad Address and Data
1110 1011B
108*
Yes
Yes
0011 0010B
108
No
No
0001 0010B
108
Yes
No
RDID
Quad
SPI
WQD
Write Quad Data
WQAD Write Quad Address and Data
QPI
EQPI
Enable QPI mode
0011 1000B
108
No
No
DQPI
Disable QPI mode
1111 1111B
108
Yes
No
*: The frequency when the number of dummy cycles is default value of 6 (see “■ LC MODE”).
Notes
1. “Yes”: Commands are supported in this mode, “No”: Commands are not supported.
2. FRQAD command cannot be issued as 1st command after power-on. Any other command shall be issued
at least once before FRQAD command.
3-1. Single Input Address (3bytes)
SI= X, X, X, X, X, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0
(Upper 5bit = any)
3-2. Quad Input Address (3bytes)
IO0=X, A16, A12, A8, A4, A0
IO1=X, A17, A13, A9, A5, A1
IO2=X, A18, A14, A10, A6, A2
IO3=X, X, A15, A11, A7, A3
(Upper 5bit = any)
4-1. Single I/O Data
SI (or SO)=D7, D6, D5, D4, D3, D2, D1, D0
4-2. Quad I/O Data
IO0=D4, D0
IO1=D5, D1
IO2=D6, D2
IO3=D7, D3
DS501-00043-2v0-E
5
MB85RQ4ML
■ COMMAND
• WREN
The WREN command sets WEL (Write Enable Latch) . WEL has to be set with the WREN command before
writing operation (WRSR, WRITE, WQD and WQAD commands) . The maximum clock frequency for the
WREN command is 108 MHz.
CS
0
1
2
3
4
5
6
7
SCK
SI
Invalid
0
0
0
0
0
1
1
0
Invalid
High-Z
SO
WREN Command Sequence
CS
0
1
SCK
OPCODE
IO0
0
0
IO1
0
1
IO2
0
1
IO3
0
0
WREN Command Sequence (QPI mode)
6
DS501-00043-2v0-E
MB85RQ4ML
• WRDI
The WRDI command resets WEL (Write Enable Latch) . Writing operation (WRSR, WRITE, WQD and WQAD
commands) are not performed when WEL is reset. The maximum clock frequency for the WRDI command
is 108 MHz.
CS
0
1
2
3
4
5
6
7
SCK
SI
Invalid
0
0
0
0
0
1
0
0
Invalid
High-Z
SO
WRDI Command Sequence
CS
0
1
SCK
OPCODE
IO0
0
0
IO1
0
0
IO2
0
1
IO3
0
0
WRDI Command Sequence (QPI mode)
DS501-00043-2v0-E
7
MB85RQ4ML
• RDSR
The RDSR command reads status register data. After driving CS low, op-code of RDSR is input to SI and
more 8-cycle clock is input to SCK, and then driving CS high. The SI value is invalid for this time. SO is
output synchronously to a falling edge of SCK. In the RDSR command, repeated reading of status register
is enabled by sending SCK continuously before rising of CS. The maximum clock frequency for the RDSR
command is 108 MHz.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
Invalid
1
Data Out
SO
High-Z
Invalid
MSB
LSB
RDSR Command Sequence
CS
0
1
2
3
4
5
6
7
8
9
1
0
SCK
OPCODE
IO0
0
High-Z
1
Data out
IO1
0
0
IO2
0
1
IO3
0
0
7
MSB
6
5
4
3
2
High-Z
LSB
High-Z
RDSR Command Sequence (QPI mode)
8
DS501-00043-2v0-E
MB85RQ4ML
• WRSR
The WRSR command writes data to the nonvolatile memory bit of status register. After driving CS low,
op-code of WRSR and 8 writing data bits are input to SI, and then driving CS high. QPI mode bit is not able to be
written with WRSR command. A SI value corresponding to bit 6 is ignored. Bit 4 and Bit 5 shall be set to “0”. WEL
(Write Enable Latch) is not able to be written with WRSR command. A SI value correspondent to bit 1 is
ignored. Bit 0 of the status register is fixed to “0” and cannot be written. The SI value corresponding to bit 0
is ignored. The WP signal level shall be fixed before performing WRSR command, and not be changed until
the end of command sequence. The maximum clock frequency for the WRSR command is 108 MHz.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Data In
SI
0
0
SO
DS501-00043-2v0-E
0
0
0
0
0
1
7
MSB
High-Z
6
5
4
3
2
1
0
LSB
9
MB85RQ4ML
• READ
The READ command reads FRAM memory cell array data. After driving CS low, READ op-code and arbitrary
24 address bits are input to SI. The 5 upper address bits are ignored. Then, 8 clock cycles are input to SCK.
SO outputs 8 data bits synchronously to the falling edge of SCK. While reading, the SI value is invalid. When
CS is risen, the READ command is completed, otherwise it keeps on reading with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it
reaches the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely.
The maximum clock frequency for the READ command is 40 MHz.
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
24-bit Address
OP-CODE
Invalid
5 4 3 2 1 0
0 0 0 0 0 0 1 1 X X X X X 18 17 16
Data Out
MSB
LSB MSB
LSB
High-Z
7 6 5 4 3 2 1 0
SI
SO
Invalid
• WRITE
The WRITE command writes data to FRAM memory cell array. After driving CS low, WRITE op-code, arbitrary
24 address bits and 8 writing data bits are input to SI. The 5-bit upper address bits are ignored. When 8
writing data bits are input, data is written to FRAM memory cell array. Risen CS will terminate the WRITE
command. However, if you continue sending the writing data for 8 bits each before CS rising, it is possible
to continue writing with automatic address increment. When it reaches the most significant address, it rolls
over to the starting address, and writing cycle keeps on infinitely. The maximum clock frequency for the
WRITE command is 108 MHz.
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
SI
Data In
24-bit Address
OP-CODE
0 0 0 0 0 0 1 0 X X X X X 18 17 16
5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB
SO
10
High-Z
LSB MSB
LSB
DS501-00043-2v0-E
MB85RQ4ML
• FSTRD
The FSTRD command reads FRAM memory cell array data. After driving CS low, FSTRD op-code and a
arbitrary 24 address bits are input to SI, followed by 8 mode bits. The 5 upper address bits are ignored.
Then, 8 clock cycles are input to SCK. SO outputs 8 data bits synchronously to the falling edge of SCK.
While reading, the SI value is invalid. When CS is risen, the FSTRD command is completed, otherwise it
keeps on reading with automatic address increment which is enabled by continuously sending clocks to SCK
in unit of 8 cycles before CS rising. When it reaches the most significant address, it rolls over to the starting
address, and reading cycle keeps on infinitely. The maximum clock frequency for the FSTRD command is
108 MHz.
Address jumps can be done without the need for additional FSTRD command. This is controlled through
the setting of the Mode bits after the address sequence. This added feature, which is called “XIP mode”,
removes the need for the command sequence. If the Mode bits equal EFH or AFH, then the device remains
in FSTRD mode and the next address can be entered (after CS is raised high and then asserted low) without
requiring the FSTRD command, thus eliminating 8 cycles for the command sequence. If the Mode bits are
any value other than EFH and AFH, then the next time CS is raised high the device will be released from
FSTRD mode. After that, the device can accept SPI commands. CS should not be driven high during mode
bits as this may make the mode bits indeterminate.
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 1415
29 30 31 32 33
38 39 40 41 42 43 44 45 46 47
24-bit Address
OP-CODE
0 0 0 0 1 0 1 1 X X X X X 18 17 16
Mode bits
1 0 Invalid
2 1 0 7 6
Data Out LSB
LSB MSB
LSB MSB
7 6 5 4 3 2 1 0
SCK
SI
MSB
High-Z
SO
Invalid
FSTRD Command Sequence
CS
0 1 2 3 4 5 6 7
21 22 23 24 25
30 31 32 33 34 35 36 37 38 39
24-bit Address
X X X X X 18 17 16
Mode bits
Invalid
1 0
2 1 0 7 6
Data Out LSB
LSB MSB
LSB MSB
7 6 5 4 3 2 1 0
SCK
SI
MSB
SO
High-Z
Invalid
FSTRD Command Sequence (XIP mode)
DS501-00043-2v0-E
11
MB85RQ4ML
• RDID
The RDID command reads fixed Device ID. After driving CS low, RDID op-code is input to SI and more 32
clock cycles are input to SCK, and then driving CS high. The SI value is invalid during this time. SO is output
synchronously to a falling edge of SCK. The output order is: Manufacturer ID (8bit)/Continuation code (8bit)/
Product ID (1st Byte)/Product ID (2nd Byte). In the RDID command, SO holds the output state of the last bit
in 32-bit Device ID until CS is risen. The maximum clock frequency for the RDID command is 108 MHz.
CS
0
1
2
3
4
5
6
7
1
0
0
1
1
1
1
1
8
31 32 33 34 35 36 37 38 39
9 10 11
SCK
SI
Invalid
Data Out
SO
High-Z
Data Out
8
31 30 29 28
7
6
5
4
3
2
MSB
1
0
LSB
bit
7
0
0
Manufacturer ID
Continuation code
6
0
1
5
0
1
Proprietary use
0
0
1
Product ID (1st Byte)
Product ID (2nd Byte)
1
0
0
4
0
1
3
0
1
2
1
1
0
Density
1
0
0
Proprietary use
0
0
1
1
0
1
0
0
0
1
Hex
04H Fujitsu
7FH
1
Hex
29H Density: 01001B = 4 Mbit
1
Hex
85H
■ LC MODE
The following read commands have a variable latency period between the end of mode bit and the beginning
of read data.
• FRQO
• FRQAD
This nonvolatile configuration bit (LC1, LC0) sets the number of dummy cycles(= latency period) to be used
in advance, therefore MB85RQ4ML can start to read immediately with an appropriate dummy cycles.
Dummy Cycles vs. SCK Frequency
12
LC1
LC0
Number of Dummy Cycles
Frequency Limit of SCK (MHz)
0
0
6 (Default)
108
0
1
4
78
1
0
2
46
1
1
0
15
DS501-00043-2v0-E
MB85RQ4ML
■ QUAD SPI MODE COMMAND
• FRQO (Fast Read Quad Output)
The FRQO command is similar to the FSTRD command, except that the data is shifted out 4 bits at one time
using 4 I/O pins (IO0 (SI), IO1 (SO), IO2 (WP) and IO3 (HOLD)) instead of 1 bit, at a maximum frequency
of 108 MHz. The data transfer rate of the FRQO command is four times higher than the FSTRD command.
After driving CS low, FRQO op-code and arbitrary 24 address bits are input to IO0. The 5 upper address
bits are ignored. Then 8 mode bits are input to 4 I/O pins for 2 cycles, followed by dummy cycles. The number
of dummy cycles is defined beforehand by the frequency of SCK, and configured by the latency bit of LC1
and LC0. The op-code, the address and the mode bits are latched on the rising edge of SCK. After that,
FRAM memory cell array data are shifted out 4 bits at one time through 4 I/O pins synchronously to the
falling edge of SCK. When CS is risen, the FRQO command is completed, otherwise it keeps on reading
with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 2 cycles
before CS rising. When it reaches the most significant address, it rolls over to the starting address, and
reading cycle keeps on infinitely.
Address jumps can be done without the need for additional FRQO command. This is controlled through the
setting of the Mode bits after the address sequence. This added feature, which is called “XIP mode”, removes
the need for the command sequence. If the Mode bits equal EFH or AFH, then the device remains in FRQO
mode and the next address can be entered (after CS is raised high and then asserted low) without requiring
the FRQO command, thus eliminating 8 cycles for the command sequence. If the Mode bits are any value
other than EFH and AFH, then the next time CS is raised high the device will be released from FRQO mode.
After that, the device can accept SPI commands. CS should not be driven high during mode or dummy bits
as this may make the mode bits indeterminate.
It is important that the I/O pins are set to high-impedance prior to the falling edge of the first data out clock.
The FRQO command is terminated by driving CS high at any time during data output.
IO switches from Input to Output
CS
嵣嵣嵣
0
1
2
3
4
5
6
7
8
9
10
11
12
13
30
31
32
33
34
35
嵣嵣嵣
SCK
OPCODE
IO0
嵣嵣嵣
29
0
1
1
0
嵣嵣嵣
Mode bits
24bit Address
1
0
1
1
X
X
X
MSB
X
X
18
IO2
High
IO3
High
2
1
0
Data out
4
0
Don’t care 嵣嵣嵣
4
0
4
0
4
5
1
Don’t care 嵣嵣嵣
5
1
5
1
5
6
2
Don’t care 嵣嵣嵣
6
2
6
2
6
7
3
Don’t care 嵣嵣嵣
7
3
7
3
7
LSB
High-Z
IO1
嵣嵣嵣
Dummy cycles (max 6)
嵣嵣嵣
嵣嵣嵣
嵣嵣嵣
Byte 1
Byte 2
FRQO Command Sequence
CS
嵣嵣嵣
0
1
2
3
4
5
21
22
IO switches from Input to Output
嵣嵣嵣
23 24 25 26 27
嵣嵣嵣
SCK
嵣嵣嵣
Mode bits
24bit Address
IO0
X
MSB
IO1
X
X
X
High-Z
IO2
IO3
High
High
X
18
嵣嵣嵣
2
1
0
Dummy cycles (max 6)
Data out
4
0
Don’t care 嵣嵣嵣
4
0
4
0
4
5
1
Don’t care 嵣嵣嵣
5
1
5
1
5
6
2
Don’t care 嵣嵣嵣
6
2
6
2
6
7
3
Don’t care 嵣嵣嵣
7
3
7
3
7
LSB
嵣嵣嵣
嵣嵣嵣
嵣嵣嵣
Byte 1
Byte 2
FRQO Command Sequence (XIP mode)
DS501-00043-2v0-E
13
MB85RQ4ML
• FRQAD (Fast Read Quad Address and Data)
The FRQAD command is similar to the FRQO command, except that it further improves throughput by
allowing input of the address bits (A23-A0) using 4 bits per SCK via 4 I/O pins (IO0 (SI), IO1 (SO), IO2 (WP)
and IO3 (HOLD)), at a maximum frequency of 108 MHz.
After driving CS low, FRQAD op-code is input to IO0. Then 24 address bits and 8 mode bits are input to
4 I/O pins for total 8 cycles, followed by dummy cycles. The 5 upper address bits are ignored. The number
of dummy cycles is defined beforehand by the frequency of SCK, and configured by the latency bit of LC1
and LC0. The op-code, the address and the mode bits are latched on the rising edge of SCK. After that,
FRAM memory cell array data are shifted out 4 bits at one time through 4 I/O pins synchronously to the
falling edge of SCK. When CS is risen, the FRQAD command is completed, otherwise it keeps on reading
with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 2 cycles
before CS rising. When it reaches the most significant address, it rolls over to the starting address, and
reading cycle keeps on infinitely.
FRQAD command cannot be issued soon after power-on. Any other command shall be issued at least once
before FRQAD command.
Address jumps can be done without the need for additional FRQAD command. This is controlled through
the setting of the Mode bits after the address sequence. This added feature, which is called “XIP mode”,
removes the need for the command sequence. If the Mode bits equal EFH or AFH, then the device remains
in FRQAD mode and the next address can be entered (after CS is raised high and then asserted low) without
requiring the FRQAD command, thus eliminating 8 cycles for the command sequence. If the Mode bits are
any value other than EFH and AFH, then the next time CS is raised high the device will be released from
FRQAD mode. After that, the device can accept SPI/Quad SPI commands. CS should not be driven high
during mode or dummy bits as this may make the mode bits indeterminate.
It is important that the I/O pins are set to high-impedance prior to the falling edge of the first data out clock.
The FRQAD command is terminated by driving CS high at any time during data output.
In QPI Mode, which is set by the EQPI command and is reset by the DQPI command, the FRQAD command
can be sent 4 bits per SCK rising edge.
IO switches from Input to Output
CS
嵣嵣嵣
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
嵣嵣嵣
SCK
1
1
1
0
Mode bits
24bit Address
OPCODE
IO0
17
1
0
1
1
X
16
12
8
4
0
Dummy cycles (max 6)
Data out
4
0
Don’t care 嵣嵣嵣
4
0
4
0
4
LSB
IO1
High-Z
IO2
High
IO3
High
X
17
13
9
5
1
5
1
Don’t care 嵣嵣嵣
5
1
5
1
5
X
18
14
10
6
2
6
2
Don’t care 嵣嵣嵣
6
2
6
2
6
X
X
15
11
7
3
7
3
Don’t care 嵣嵣嵣
7
3
7
3
7
MSB
Byte 1
Byte 2
FRQAD Command Sequence
14
DS501-00043-2v0-E
MB85RQ4ML
IO switches from Input to Output
CS
嵣嵣嵣
0
1
2
3
4
5
6
7
8
9
10
嵣嵣嵣
SCK
Mode bits
24bit Address
IO0
X
16
8
12
4
0
Dummy cycles (max 6)
Data out
4
0
Don’t care
嵣嵣嵣
4
0
4
0
4
LSB
IO1
X
17
13
9
5
1
5
1
Don’t care
嵣嵣嵣
5
1
5
1
5
IO2
X
18
14
10
6
2
6
2
Don’t care
嵣嵣嵣
6
2
6
2
6
X
X
15
11
7
3
7
3
Don’t care
嵣嵣嵣
7
3
7
3
7
IO3
MSB
Byte 1
Byte 2
FRQAD Command Sequence (XIP mode)
IO switches from Input to Output
CS
嵣嵣嵣
0
1
2
3
4
5
6
7
8
9
10
11
12
嵣嵣嵣
SCK
OPCODE
IO0
0
1
Mode bits
24bit Address
X
16
12
8
4
0
Dummy cycles (max 6)
Data out
4
0
Don’t care
嵣嵣嵣
4
0
4
0
4
LSB
IO1
1
1
X
17
13
9
5
1
5
1
Don’t care
嵣嵣嵣
5
1
5
1
5
IO2
1
0
X
18
14
10
6
2
6
2
Don’t care
嵣嵣嵣
6
2
6
2
6
IO3
1
1
X
X
15
11
7
3
7
3
Don’t care
嵣嵣嵣
7
3
7
3
7
MSB
Byte 1
Byte 2
FRQAD Command Sequence (QPI mode)
DS501-00043-2v0-E
15
MB85RQ4ML
• WQD (Write Quad Data)
The WQD command is similar to the WRITE command, except that the data is input to 4 I/O pins (IO0 (SI),
IO1 (SO), IO2 (WP) and IO3 (HOLD)) at one time instead of 1 input pin (SI), at a maximum frequency of
108 MHz. The data transfer rate of the WQD command is four times higher than the WRITE command.
After driving CS low, WQD op-code and arbitrary 24 address bits are input to IO0. The 5 upper address bits
are ignored. When 8 writing data bits are input to 4 I/O pins for 2 cycles, data is written to FRAM memory
cell array. The op-code, the address and the data are latched on the rising edge of SCK. Risen CS will
terminate the WQD command. However, if you continue sending the writing data for 8 bits each in unit of 2
cycles before CS rising, it is possible to continue writing with automatic address increment. When it reaches
the most significant address, it rolls over to the starting address, and writing cycle keeps on infinitely.
CS
嵣嵣嵣
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0
0
1
1
0
0
1
0
X
MSB
IO1
IO2
IO3
30
31
32
34
35
2
1
0
4
0
4
0
4
5
1
5
1
5
6
2
6
2
6
7
3
7
3
Byte 2
7
24bit Address
OPCODE
IO0
29
33
嵣嵣嵣
SCK
X
X
X
High-Z
High
High
X
18
嵣嵣嵣
Data in
LSB
嵣嵣嵣
嵣嵣嵣
嵣嵣嵣
Byte 1
WQD Command Sequence
16
DS501-00043-2v0-E
MB85RQ4ML
• WQAD (Write Quad Address and Data)
The WQAD command is similar to the WQD command, except that it further improves throughput by allowing
input of the address bits (A23-A0) using 4 bits per SCK via 4 I/O pins (IO0 (SI), IO1 (SO), IO2 (WP) and
IO3 (HOLD)), at a maximum frequency of 108 MHz.
After driving CS low, WQAD op-code is input to IO0. Then 24 address bits are input to 4 I/O pins for 6 cycles.
The 5 upper address bits are ignored. When 8 writing data bits are input to 4 I/O pins for 2cycles, data is
written to FRAM memory cell array. The opcode, the address and the data are latched on the rising edge of
SCK. Risen CS will terminate the WQAD command. However, if you continue sending the writing data for 8
bits each in unit of 2 cycles before CS rising, it is possible to continue writing with automatic address
increment. When it reaches the most significant address, it rolls over to the starting address, and writing
cycle keeps on infinitely.
In QPI Mode, which is set by the EQPI command and is reset by the DQPI command, the WQAD command
can be sent 4 bits per SCK rising edge.
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SCK
0
0
0
1
Data in
24bit Address
OPCODE
IO0
0
0
1
0
X
16
12
8
4
0
4
0
4
0
4
LSB
High-Z
IO1
IO2
High
IO3
High
X
17
13
9
5
1
5
1
5
1
5
X
18
14
10
6
2
6
2
6
2
6
X
X
15
11
7
3
7
3
7
3
Byte 2
7
MSB
Byte 1
WQAD Command Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
11
SCK
OPCODE
IO0
1
0
24bit Address
X
16
12
8
4
Data in
0
4
0
4
0
4
LSB
IO1
0
1
X
17
13
9
5
1
5
1
5
1
5
IO2
0
0
X
18
14
10
6
2
6
2
6
2
6
IO3
0
0
X
X
15
11
7
3
7
3
7
3
Byte 2
7
MSB
Byte 1
WQAD Command Sequence (QPI mode)
DS501-00043-2v0-E
17
MB85RQ4ML
■ QPI MODE COMMAND
QPI Mode can shorten op-code input cycle from 8 cycles to 2 cycles with 4 I/O pins. The device enters QPI
Mode with the EQPI Command. When in QPI Mode, the Status Register bit 6 is set to “1” and will reset to
“0” either when the device exits from the QPI Mode with the DQPI command or at power-off. After poweron, QPI mode is disabled.
Mode
SPI
Quad
SPI
QPI
The command list supported in QPI mode
Description
Op-code
Max Freq. (MHz)
Name
QPI
XIP
WREN
Set Write Enable Latch
0000 0110B
108
Yes
No
WRDI
Reset Write Enable Latch
0000 0100B
108
Yes
No
RDSR
Read Status Register
0000 0101B
108
Yes
No
FRQAD Fast Read Quad Address and Data
1110 1011B
108*
Yes
Yes
WQAD Write Quad Address and Data
0001 0010B
108
Yes
No
1111 1111B
108
Yes
No
DQPI
Disable QPI mode
*: The frequency when the number of dummy cycles is default value of 6 (see “■ LC MODE”).
• EQPI (Enable QPI mode)
The EQPI command is used for the device to enter QPI mode, at a maximum frequency of 108 MHz.
After driving CS low, the op-code is input to SI(IO0). The command is terminated by driving CS high. When
in QPI Mode, the Status Register bit 6 is set to “1” and the device stays in QPI mode until power-off or the
DQPI command is issued.
CS
0
1
2
3
4
5
6
7
0
0
1
OPCODE
1
1
0
0
0
SCK
SI
EQPI Command Sequence
18
DS501-00043-2v0-E
MB85RQ4ML
• DQPI (Disable QPI mode)
The Disable QPI command is used for the device to exit from QPI mode and return to the SPI mode and set
the Status Register bit 6 to “0”, at a maximum frequency of 108 MHz.
After driving CS low, the op-code is input to 4 I/O pins for 2 cycles. The command is terminated by driving
CS high.
CS
0
1
IO0
1
1
IO1
1
1
IO2
1
1
IO3
1
1
SCK
DQPI Command Sequence
DS501-00043-2v0-E
19
MB85RQ4ML
■ BLOCK PROTECT
Writing protect block for WRITE, WQD and WQAD commands are configured by the value of BP0 and BP1
in the status register.
BP1
BP0
Protected Block
0
0
None
0
1
60000H to 7FFFFH (upper 1/4)
1
0
40000H to 7FFFFH (upper 1/2)
1
1
00000H to 7FFFFH (all)
■ WRITING PROTECT
Writing operation of WRITE, WQD, WQAD and the WRSR commands are protected with the value of WEL,
WPEN, WP as shown in the table.
WEL
WPEN
WP
Protected Blocks
Unprotected Blocks
Status Register
0
X
X
Protected
Protected
Protected
1
0
X
Protected
Unprotected
Unprotected
1
1
0
Protected
Unprotected
Protected
1
1
1
Protected
Unprotected
Unprotected
■ HOLD OPERATION
Hold status is retained without aborting a command if HOLD is “L” level while CS is “L” level. The timing for
starting and ending hold status depends on the SCK to be “H” level or “L” level when a HOLD pin input is
transited to the hold condition as shown in the diagram below. In case the HOLD pin transited to “L” level
when SCK is “L” level, return the HOLD pin to “H” level at SCK being “L” level. In the same manner, in case
the HOLD pin transited to “L” level when SCK is “H” level, return the HOLD pin to “H” level at SCK being “H”
level. Arbitrary command operation is interrupted in hold status, SCK and SI inputs become do not care.
And, SO becomes High-Z while reading command (RDSR, READ, FSTRD). If CS is rising during hold status,
a command is aborted. In case the command is aborted before its recognition, WEL holds the value before
transition to hold status.
Note: The HOLD operation is disabled during Quad SPI Mode (FRQO, FRQAD, WQD, WQAD) and QPI mode.
CS
SCK
HOLD
Hold Condition
20
Hold Condition
DS501-00043-2v0-E
MB85RQ4ML
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Min
Max
Unit
Power supply voltage*
VDD
− 0.5
+ 2.5
V
Input voltage*
VIN
− 0.5
VDD + 0.5
V
VOUT
− 0.5
VDD + 0.5
V
TA
− 40
+ 85
°C
Tstg
− 55
+ 125
°C
Output voltage*
Operation ambient temperature
Storage temperature
*:These parameters are based on the condition that VSS is 0 V.
WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without
limitation, voltage, current or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Power supply voltage*1
Operation ambient temperature
*2
Value
Unit
Min
Typ
Max
VDD
1.7
1.8
1.95
V
TA
− 40
⎯
+ 85
°C
*1: These parameters are based on the condition that VSS is 0 V.
*2: Ambient temperature when only this device is working. Please consider it to be the almost same as the
package surface temperature.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of
device and could result in device failure.
No warranty is made with respect to any use, operating conditions or combinations not represented
on this data sheet. If you are considering application under any conditions other than listed herein,
please contact sales representatives beforehand.
DS501-00043-2v0-E
21
MB85RQ4ML
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(within recommended operating conditions)
Parameter
Input leakage current
Output leakage current
Operating power supply current
Symbol
|ILI|
|ILO|
IDD
Condition
Value
Unit
Min
Typ
Max
0 ≤ CS< VDD
⎯
⎯
200
CS = VDD
⎯
⎯
1
WP, HOLD, SCK,
SI = 0 V to VDD
⎯
⎯
1
SO = 0 V to VDD
⎯
⎯
1
μA
SCK = 20 MHz
(SPI)
⎯
1.3
⎯
mA
SCK = 40 MHz
(SPI)
⎯
2.6
⎯
mA
SCK = 108 MHz
(SPI)
⎯
6.8
15
mA
SCK = 20 MHz
(Quad SPI)
⎯
3.6
⎯
mA
SCK = 40 MHz
(Quad SPI)
⎯
7.4
⎯
mA
SCK = 108 MHz
(Quad SPI)
⎯
20.0
30
mA
⎯
70
400
μA
μA
Standby current
ISB
SCK = SI = CS = WP
= HOLD = VDD
Input high voltage
VIH
VDD = 1.7 V to 1.95 V VDD × 0.8
⎯
VDD + 0.3
V
Input low voltage
VIL
VDD = 1.7 V to 1.95 V
− 0.5
⎯
VDD × 0.2
V
Output high voltage
VOH
IOH = − 2 mA
VDD − 0.5
⎯
⎯
V
Output low voltage
VOL
IOL = 2 mA
⎯
⎯
0.4
V
Pull up resistance for CS
RP
⎯
18
33
80
kΩ
22
DS501-00043-2v0-E
MB85RQ4ML
2. AC Characteristics
Parameter
Symbol
Condition
Valu
Unit
Min
Max
except READ command*2
0
108*3
MHz
for READ command
0
40
MHz
except READ command
4
⎯
ns
for READ command
11
⎯
ns
except READ command
4
⎯
ns
for READ command
11
⎯
ns
SCK clock frequency
fCK
Clock high time
tCH
Clock low time
tCL
Chip select set up time
tCSU
5
⎯
ns
Chip select hold time
tCSH
5
⎯
ns
tOD
⎯
7
ns
tODV
⎯
7
ns
tOH
0
⎯
ns
After Write cycle
40
⎯
ns
After Write cycle in QPI mode
80
⎯
ns
After Read cycle
40
⎯
ns
After Read cycle in QPI mode
except terminated in the specific
address*1
80
⎯
ns
After Read cycle in XIP mode
except terminated in the specific
address*1
100
⎯
ns
Output disable time*2
Output data valid time
*2
Output hold time
Deselect time
tD
Data set up time
tSU
3
⎯
ns
Data hold time
tH
4
⎯
ns
HOLD set up time
tHS
4
⎯
ns
HOLD hold time
tHH
4
⎯
ns
HOLD output floating time
tHZ
⎯
7
ns
HOLD output active time
tLZ
⎯
7
ns
*1 : tD after read cycle normally equals 40ns. But in QPI mode or XIP mode, tD will be longer (80ns or 100ns)
due to internal cycle time unless read operation is terminated by driving CS high in the specific address. In
case the read operation is terminated either in A1=1 and other address = “don’t care” during QPI mode or
in A1=1, A0=1 and other address = “don’t care” during XIP mode, tD=40ns can be kept.
*2 : Use “AC Load Equivalent Circuit 2” for these condition or parameters. Others are tested under “AC Load
Equivalent Circuit 1”.
*3 : For the frequency of FRQO and FRQAD commands, the number of dummy cycles is default value of 6.
(see “■ LC MODE”)
DS501-00043-2v0-E
23
MB85RQ4ML
AC Test Condition
Power supply voltage
: 1.7 V to 1.95 V
Operation ambient temperature : − 40 °C to + 85 °C
Input voltage magnitude
: VIH = VDD
VIL = 0 V
Input rising time
: 2 ns
Input falling time
: 2 ns
Input judge level
: VDD/2
Output judge level
: VDD/2
AC Load Equivalent Circuit 1
1.8 V
1.2 k
Output
0.95 k
30 pF
AC Load Equivalent Circuit 2
Output
50
30 pF
VT=VDD/2
3. Pin Capacitance
Parameter
I/O capacitance
Input capacitance
24
Symbol
Condition
CI/O
VDD = VIN = VOUT = 0 V,
f = 1 MHz, TA = +25 °C
CI
Value
Unit
Min
Max
⎯
4
pF
⎯
4
pF
DS501-00043-2v0-E
MB85RQ4ML
■ TIMING DIAGRAM
• Serial Data Timing
tD
CS
tCSH
tCSU
tCH
SCK
tSU
tCL
tCH
tH
Valid in
SI or IO
tODV
SO or IO
tOH
tOD
High-Z
High-Z
Valid out
Invalid
: H or L
• Hold Timing
CS
SCK
tHS
tHH
tHS
tHS
tHH
tHS
tHH
tHH
HOLD
High-Z
SO or IO
tHZ
DS501-00043-2v0-E
tLZ
High-Z
tHZ
tLZ
25
MB85RQ4ML
■ POWER ON/OFF SEQUENCE
tpd
tf
tr
tpu
VDD
VDD
VDD (Min)
VDD (Min)
VIH (Min)
VIH (Min)
1.0 V
1.0 V
VIL (Max)
VIL (Max)
GND
GND
CS >VDD 0.8
CS
CS >VDD 0.8
CS : don't care
CS
* : CS (Max) < VDD + 0.3 V
Parameter
Symbol
Value
Min
Max
Unit
CS level hold time at power OFF
tpd
400
⎯
ns
CS level hold time at power ON
tpu
250
⎯
μs
Power supply rising time
tr
0.05
⎯
ms/V
Power supply falling time
tf
0.1
⎯
ms/V
If the device does not operate within the specified conditions of read cycle, write cycle or power on/off
sequence, memory data can not be guaranteed.
■ FRAM CHARACTERISTICS
Parameter
Read/Write Endurance*1
2
Data Retention*
Value
Min
Max
1013
⎯
10
⎯
95
⎯
≥ 200
⎯
Unit
Remarks
Times/byte
Operation Ambient Temperature TA = + 85 °C
Operation Ambient Temperature TA = + 85 °C
Years
Operation Ambient Temperature TA = + 55 °C
Operation Ambient Temperature TA = + 35 °C
*1 : Total number of reading and writing defines the minimum value of endurance, as an FRAM memory operates
with destructive readout mechanism.
*2: Minimum values define retention time of the first reading/writing data right after shipment, and these values
are calculated by qualification results.
■ NOTE ON USE
We recommend programming of the device after reflow. Data written before reflow cannot be guaranteed.
26
DS501-00043-2v0-E
MB85RQ4ML
■ ESD AND LATCH-UP
Test
DUT
Value
ESD HBM (Human Body Model)
JESD22-A114 compliant
≥ |2000 V|
ESD MM (Machine Model)
JESD22-A115 compliant
≥ |200 V|
ESD CDM (Charged Device Model)
JESD22-C101 compliant
≥ |1000 V|
Latch-Up (I-test)
JESD78 compliant
MB85RQ4MLPF-G-BCE1
MB85RQ4MLPF-G-BCERE1
⎯
Latch-Up (Vsupply overvoltage test)
JESD78 compliant
⎯
Latch-Up (Current Method)
Proprietary method
⎯
Latch-Up (C-V Method)
Proprietary method
≥ |200 V|
• Current method of Latch-Up Resistance Test
Protection Resistance
A
Test terminal
IIN
VIN
VDD
+
DUT
-
VSS
VDD
(Max.Rating)
V
Reference
terminal
Note : The voltage VIN is increased gradually and the current IIN of 300 mA at maximum shall flow.
Confirm the latch up does not occur under IIN = ± 300 mA.
In case the specific requirement is specified for I/O and IIN cannot be 300 mA, the voltage shall be
increased to the level that meets the specific requirement.
DS501-00043-2v0-E
27
MB85RQ4ML
• C-V method of Latch-Up Resistance Test
Protection Resistance
A
1
Test
2 terminal
SW
+
VIN
V
-
C
200pF
VDD
DUT
VDD
(Max.Rating)
VSS
Reference
terminal
Note : Charge voltage alternately switching 1 and 2 approximately 2 sec interval. This switching process is
considered as one cycle. Repeat this process 5 times. However, if the latch-up condition occurs before
completing 5times, this test must be stopped immediately.
■ REFLOW CONDITIONS AND FLOOR LIFE
[ JEDEC MSL ] : Moisture Sensitivity Level 3 (ISP/JEDEC J-STD-020D)
■ CURRENT STATUS ON CONTAINED RESTRICTED SUBSTANCES
This product complies with the regulations of REACH Regulations, EU RoHS Directive and China RoHS.
28
DS501-00043-2v0-E
MB85RQ4ML
■ ORDERING INFORMATION
Package
Shipping form
Minimum shipping
quantity
MB85RQ4MLPF-G-BCE1
16-pin plastic SOP
(FPT-16P-M24)
Tray
⎯*
MB85RQ4MLPF-G-BCERE1
16-pin plastic SOP
(FPT-16P-M24)
Embossed Carrier tape
500
Part number
* : Please contact our sales office about minimum shipping quantity.
DS501-00043-2v0-E
29
MB85RQ4ML
■ PACKAGE DIMENSION
16-pin plastic SOP
Lead pitch
1.27mm
Package width ×
package length
7.5 × 10.3 mm
Lead shape
Gullwing
Plastic mold
Sealing method
2.66mm MAX
Mounting height
TBD g
Weight
(FPT-16P-M24)
16-pin plastic SOP
㸦FPT-16P-M24㸧
Note 1) *1 does not include Mold flash.
Note 2) *2 does not include Mold flash.
Note 3) *3 does not include TRIM offset.
s
s
s
͆)͇
5
7 W\S
s
W\S
W\S
W\S
PD[
Detail of “F” part.
㹼
C
30
2015 FUJITSU SEMICONDUCTOR LIMITED F16-24Sc
Dimensions in mm.
DS501-00043-2v0-E
MB85RQ4ML
■ MARKING
[MB85RQ4MLPF-G-BCE1]
[MB85RQ4MLPF-G-BCERE1]
MB85RQ4ML
1550 V00
E1
[FPT-16P-M24]
DS501-00043-2v0-E
31
MB85RQ4ML
■ MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page
Section
Change Results
32
1
■ FEATURES
Added Data retention under 85 °C.
26
■ FRAM CHARACTERISTICS
Added Data retention under 85 °C.
DS501-00043-2v0-E
MB85RQ4ML
MEMO
DS501-00043-2v0-E
33
MB85RQ4ML
MEMO
34
DS501-00043-2v0-E
MB85RQ4ML
MEMO
DS501-00043-2v0-E
35
MB85RQ4ML
FUJITSU SEMICONDUCTOR LIMITED
Shin-Yokohama Chuo Building, 2-100-45 Shin-Yokohama,
Kohoku-ku, Yokohama, Kanagawa 222-0033, Japan
http://jp.fujitsu.com/fsl/en/
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the right to make changes to the information contained in this document without notice. Please contact your FUJITSU
SEMICONDUCTOR sales representatives before order of FUJITSU SEMICONDUCTOR device.
Information contained in this document, such as descriptions of function and application circuit examples is presented solely for
reference to examples of operations and uses of FUJITSU SEMICONDUCTOR device. FUJITSU SEMICONDUCTOR disclaims
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without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and
manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high levels of safety is secured,
could lead directly to death, personal injury, severe physical damage or other loss (including, without limitation, use in nuclear
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Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs and
safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures into your
facility, equipments and products such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal
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Edited: System Memory Business Division
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