MB85RS128TYPNF-G-BCERE1

FUJITSU SEMICONDUCTOR MEMORY SOLUTION DATA SHEET DS501-00048-6v1-E Memory FRAM 128K (16K  8) Bit SPI MB85RS128TY(AEC-Q100 Compliant)  DESCRIPTION MB85RS128TY is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 16,384 words  8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. This product is specifically targeted for high-temperature environment such as automotive applications. MB85RS128TY adopts the Serial Peripheral Interface (SPI). The MB85RS128TY is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MB85RS128TY can be used for 1013 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM. As MB85RS128TY does not need any waiting time in writing process, the write cycle time of MB85RS128TY is much shorter than that of Flash memories or E2PROM.  FEATURES • Bit configuration • Serial Peripheral Interface • Operating frequency • High endurance • Data retention : 16,384 words  8 bits : SPI (Serial Peripheral Interface) Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1) : 40 MHz (Max) : 1013 times / byte : 40.2 years (+85 C), 10.9 years (+105 C) 3.38 years (+125 C) or more Under evaluation for more than 3.38 year(+125 C) : 1.8 V to 3.6 V : Operating power supply current 2.5 mA (Max@40 MHz) Standby current 45 A (Max) Sleep current 12 A (Max) • Operation ambient temperature range :  40 C to +125 C • Package : 8-pin plastic SOP AEC-Q100 Grade 1 compliant RoHS compliant • Operating power supply voltage • Low power consumption Copyright 2020 FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED 2020.05 MB85RS128TY(AEC-Q100 Compliant)  PIN ASSIGNMENT (TOP VIEW) CS 1 8 VDD SO 2 7 HOLD WP 3 6 SCK VSS 4 5 SI (8-pin plastic SOP)  PIN FUNCTIONAL DESCRIPTIONS Pin No. Pin Name CS Chip Select pin This is an input pin to make chips select. When CS is “H” level, device is in deselect (standby) status and SO becomes High-Z. Inputs from other pins are ignored for this time. When CS is “L” level, device is in select (active) status. CS has to be “L” level before inputting op-code. The Chip Select pin is pulled up internally to the VDD pin. WP Write Protect pin This is a pin to control writing to a status register. The writing of status register (see “ STATUS REGISTER”) is protected in related with WP and WPEN. See “ WRITING PROTECT” for detail. 7 HOLD Hold pin This pin is used to interrupt serial input/output without making chips deselect. When HOLD is “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become do not care. “ HOLD OPERATION” for detail. 6 SCK Serial Clock pin This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge, SO is output synchronously to a falling edge. 5 SI Serial Data Input pin This is an input pin of serial data. This inputs op-code, address, and writing data. 2 SO Serial Data Output pin This is an output pin of serial data. Reading data of FRAM memory cell array and status register data are output. This is High-Z during standby. 8 VDD Supply Voltage pin 4 VSS Ground pin 1 3 2 Functional description DS501-00048-6v1-E MB85RS128TY(AEC-Q100 Compliant)  BLOCK DIAGRAM Control Circuit SCK HOLD Row Decoder CS Address Counter Serial-Parallel Converter SI FRAM Cell Array 16,384 ✕ 8 FRAM Status Register Column Decoder/Sense Amp/ Write Amp WP Data Register SO Parallel-Serial Converter DS501-00048-6v1-E 3 MB85RS128TY(AEC-Q100 Compliant)  SPI MODE MB85RS128TY corresponds to the SPI mode 0 (CPOL  0, CPHA  0) , and SPI mode 3 (CPOL  1, CPHA  1) . CS SCK SI 7 6 5 MSB 4 3 2 1 0 LSB SPI Mode 0 CS SCK SI 7 6 5 4 MSB 3 2 1 0 LSB SPI Mode 3 4 DS501-00048-6v1-E MB85RS128TY(AEC-Q100 Compliant)  SERIAL PERIPHERAL INTERFACE (SPI) MB85RS128TY works as a slave of SPI. More than 2 devices can be connected by using microcontroller equipped with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus connected to use. SCK MOSI MISO SO SPI Microcontroller SI SO SCK SI SCK MB85RS128TY MB85RS128TY CS CS HOLD HOLD SS1 SS2 HOLD1 HOLD2 MOSI : Master Out Slave In MISO : Master In Slave Out SS : Slave Select System Configuration with SPI Port SO SI SCK Microcontroller MB85RS128TY CS HOLD System Configuration without SPI Port DS501-00048-6v1-E 5 MB85RS128TY(AEC-Q100 Compliant)  STATUS REGISTER Bit No. Bit Name Function WPEN Status Register Write Protect This is a bit composed of nonvolatile memories (FRAM). WPEN protects writing to a status register (refer to “ WRITING PROTECT”) relating with WP input. Writing with the WRSR command and reading with the RDSR command are possible. 6 to 4  Not Used Bits These are bits composed of nonvolatile memories, writing with the WRSR command is possible. These bits are not used but they are read with the RDSR command. 3 BP1 2 BP0 7 1 WEL 0 0 Block Protect This is a bit composed of nonvolatile memory. This defines size of write protect block for the WRITE command (refer to “ BLOCK PROTECT”). Writing with the WRSR command and reading with the RDSR command are possible. Write Enable Latch This indicates FRAM Array and status register are writable. The WREN command is for setting, and the WRDI command is for resetting. With the RDSR command, reading is possible but writing is not possible with the WRSR command. WEL is reset after the following operations. After power ON. After WRDI command recognition. After return from SLEEP mode. Achieving continuous writing mode, WEL is not reset after following operations making it possible to execute writing commands continuously. After WRSR command recognition. After WRITE command recognition. This is a bit fixed to “0”.  OP-CODE MB85RS128TY accepts 8 kinds of command specified in op-code. Op-code is a code composed of 8 bits shown in the table below. Do not input invalid codes other than those codes. If CS is risen while inputting op-code, the command are not performed. Name Description Op-code WREN Set Write Enable Latch 0000 0110B WRDI Reset Write Enable Latch 0000 0100B RDSR Read Status Register 0000 0101B WRSR Write Status Register 0000 0001B READ Read Memory Code 0000 0011B WRITE Write Memory Code 0000 0010B Read Device ID 1001 1111B Sleep Mode 1011 1001B RDID SLEEP 6 DS501-00048-6v1-E MB85RS128TY(AEC-Q100 Compliant)  COMMAND  WREN The WREN command sets WEL (Write Enable Latch) bit to 1. WEL has to be set with the WREN command before writing operation (WRSR command and WRITE command) . CS 0 1 2 3 4 5 6 7 SCK SI Invalid 0 0 0 0 0 1 1 Invalid 0 High-Z SO  WRDI The WRDI command resets WEL (Write Enable Latch) bit to 0. Writing operation (WRSR command and WRITE command) are not performed when WEL is reset.. CS 0 1 2 3 4 5 6 7 SCK SI Invalid SO DS501-00048-6v1-E 0 0 0 0 0 1 0 0 Invalid High-Z 7 MB85RS128TY(AEC-Q100 Compliant)  RDSR The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. In the RDSR command, repeated reading of status register is enabled by sending SCK continuously before rising of CS. CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 0 Invalid 1 Data Out High-Z SO Invalid LSB MSB  WRSR The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR command. A SI value correspondent to bit 1 is ignored. Bit 0 of the status register is fixed to “0” and cannot be written. The SI value corresponding to bit 0 is ignored. WP signal level shall be fixed before performing WRSR command, and do not change the WP signal level until the end of command sequence. CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK Data In Instruction SI SO 8 0 0 0 0 0 0 0 1 7 MSB High-Z 6 5 4 3 2 1 0 LSB DS501-00048-6v1-E MB85RS128TY(AEC-Q100 Compliant)  READ The READ command reads FRAM memory cell array data. Arbitrary 16 bits address and op-code of READ are input to SI. The upper two address bits are invalid. Then, 8-cycle clock is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ command is completed, but keeps on reading with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCK SI SO 16-bit Address OP-CODE 0 0 0 0 0 0 1 1 X X 13 12 11 10 5 4 MSB High-Z 3 2 1 Invalid 0 LSB MSB 7 6 Data Out 5 4 3 2 1 LSB 0 Invalid  WRITE The WRITE command writes data to FRAM memory cell array. WRITE op-code, arbitrary 16 bits of address and 8 bits of writing data are input to SI. The upper two address bits are invalid. When 8 bits of writing data is input, data is written to FRAM memory cell array. Risen CS will terminate the WRITE command, but if you continue sending the writing data for 8 bits each before CS rising, it is possible to continue writing with automatic address increment. When it reaches the most significant address, it rolls over to the starting address, and writing cycle can be continued infinitely. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCK SI SO 16-bit Address OP-CODE 0 0 0 0 0 0 1 0 X X 13 12 11 10 5 4 MSB High-Z DS501-00048-6v1-E Data In 3 2 1 0 7 6 LSB MSB 5 4 3 2 1 0 LSB 9 MB85RS128TY(AEC-Q100 Compliant)  RDID The RDID command reads fixed Device ID. After performing RDID op-code to SI, 32-cycle clock is input to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. The output is in order of Manufacturer ID (8bit)/Continuation code (8bit)/Product ID (1st Byte)/Product ID (2nd Byte). In the RDID command, 32-bit Device ID is output by continuously sending SCK clock, and SO holds the output state of the last bit until CS is risen. CS 0 1 2 3 4 5 6 7 1 0 0 1 1 1 1 1 8 31 32 33 34 35 36 37 38 39 9 10 11 SCK SI Invalid Data Out SO High-Z Data Out 8 7 6 1 0 1 0 0 1 Hex 04H Fujitsu 7FH Density 1 0 0 Hex 24H Density: 00100B  128Kbit 1 Hex 03H 31 30 29 28 5 4 3 MSB 2 1 0 LSB bit Manufacturer ID Continuation code Product ID (1st Byte) Product ID (2nd Byte) 10 7 0 0 6 0 1 5 0 1 Proprietary use 0 0 1 0 0 4 0 1 3 0 1 0 0 2 1 1 Proprietary use 0 0 0 0 1 DS501-00048-6v1-E MB85RS128TY(AEC-Q100 Compliant)  SLEEP The SLEEP command shifts the LSI to a low power mode called “SLEEP mode”. The transition to the SLEEP mode is carried out at the rising edge of CS after operation code in the SLEEP command. However, when at least one SCK clock is inputted before the rising edge of CS after operation code in the SLEEP command, this SLEEP command is canceled. After the SLEEP mode transition, SCK and SI inputs are logically ignored and SO changes to a High-Z state. If input pin(s) other than CS pin is (are) not fixed to VSS or VDD, flow-throw current may flow. Enter Sleep Mode CS 0 1 2 3 4 5 6 7 1 0 1 1 1 0 0 1 Invalid SCK SI Invalid High-Z SO Sleep Mode Entry Returning to an normal operation from the SLEEP mode is carried out after tREC (Max 400 s) time from the falling edge of CS (see the figure below). It is possible to return CS to H level before tREC time. However, it is prohibited to bring down CS to L level again during tREC period. CS CS tREC From this time Command input enable Exit Sleep Mode Sleep Mode Exit DS501-00048-6v1-E 11 MB85RS128TY(AEC-Q100 Compliant)  BLOCK PROTECT Writing protect block for WRITE command is configured by the value of BP0 and BP1 in the status register. BP1 BP0 Protected Block 0 0 None 0 1 3000H to 3FFFH (upper 1/4) 1 0 2000H to 3FFFH (upper 1/2) 1 1 0000H to 3FFFH (all)  WRITING PROTECT Writing operation of the WRITE command and the WRSR command are protected with the value of WEL, WPEN, WP as shown in the table. WEL WPEN WP Protected Blocks Unprotected Blocks Status Register 0 X X Protected Protected Protected 1 0 X Protected Unprotected Unprotected 1 1 0 Protected Unprotected Protected 1 1 1 Protected Unprotected Unprotected  HOLD OPERATION Hold status is retained without aborting a command if HOLD is “L” level while CS is “L” level. The timing for starting and ending hold status depends on the SCK to be “H” level or “L” level when a HOLD pin input is transited to the hold condition as shown in the diagram below. In case the HOLD pin transited to “L” level when SCK is “L” level, return the HOLD pin to “H” level at SCK being “L” level. In the same manner, in case the HOLD pin transited to “L” level when SCK is “H” level, return the HOLD pin to “H” level at SCK being “H” level. Arbitrary command operation is interrupted in hold status, SCK and SI inputs become do not care. And, SO becomes High-Z while reading command (RDSR, READ). If CS is rising during hold status, a command is aborted. In case the command is aborted before its recognition, WEL holds the value before transition to hold status. CS SCK HOLD Hold Condition 12 Hold Condition DS501-00048-6v1-E MB85RS128TY(AEC-Q100 Compliant)  ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Min Max Unit Power supply voltage* VDD  0.5  4.0 V Input voltage* VIN  0.5 VDD  0.5(  4.0) V VOUT  0.5 VDD  0.5(  4.0) V TA  40  125 C Tstg  55  150 C Output voltage* Operation ambient temperature Storage temperature *: These parameters are based on the condition that VSS is 0 V. WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.  RECOMMENDED OPERATING CONDITIONS Parameter Symbol Power supply voltage*1 Operation ambient temperature* 2 Value Unit Min Typ Max VDD 1.8 3.3 3.6 V TA  40   125 C *1: These parameters are based on the condition that VSS is 0 V. *2: Ambient temperature when only this device is working. Please consider it to be the almost same as the package surface temperature. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. DS501-00048-6v1-E 13 MB85RS128TY(AEC-Q100 Compliant)  ELECTRICAL CHARACTERISTICS 1. DC Characteristics (within recommended operating conditions) Parameter Symbol Value Condition Min Typ Max   200 25 C   1 125 C   2 25 C   1 125 C   2 25 C   1 125 C   2 0  CS< VDD Input leakage current* 1 CS  VDD |ILI| WP, HOLD, SCK SI  0 V to VDD SO  0 V to VDD Unit A A Output leakage current*2 |ILO| Operating power supply current*3 IDD SCK  40MHz  2.1 2.5 mA Standby current ISB SCK  SI  CS  WP  HOLD  VDD  20 45 A Sleep current IZZ CS  VDD All inputs VSS or VDD  6 12 A Input high voltage VIH VDD = 1.8 V to 3.6 V VDD  0.8  VDD  0.5 V Input low voltage VIL VDD = 1.8 V to 3.6 V  0.5  VDD  0.2 V Output high voltage VOH IOH   2 mA VDD  0.5   V Output low voltage VOL IOL  2 mA   0.4 V Pull up resistance for CS RP  18 33 80 k *1 : Applicable pin : CS, WP, HOLD, SCK, SI *2 : Applicable pin : SO *3 : Input voltage magnitude : VDD  0.2 V or VSS 14 DS501-00048-6v1-E MB85RS128TY(AEC-Q100 Compliant) 2. AC Characteristics Parameter Symbol Value Min Max 0 33 0 40 13  11  13  11  Unit Condition VDD 1.8V to 2.7V SCK clock frequency fCK Clock high time tCH Clock low time tCL Chip select set up time tCSU 10  ns  Chip select hold time tCSH 10  ns  Output disable time tOD  16 ns  Output data valid time tODV  13  9 Output hold time tOH 0  ns  Deselect time tD 40  ns  Data in rising time tR  50 ns  Data falling time tF  50 ns  Data set up time tSU 5  ns  Data hold time tH 5  ns  HOLD set uptime tHS 10  ns  HOLD hold time tHH 10  ns  HOLD output floating time tHZ  20 ns  HOLD output active time tLZ  20 ns  SLEEP recovery time tREC  400 s  MHz ns ns ns 2.7V to 3.6V 1.8V to 2.7V 2.7V to 3.6V 1.8V to 2.7V 2.7V to 3.6V 1.8V to 2.7V 2.7V to 3.6V AC Test Condition Power supply voltage : 1.8 V to 3.6 V Operation Operation ambient temperature :  40 C to  125 C Input voltage magnitude : VDD  0.8  VIH  VDD 0  VIL  VDD  0.2 Input rising time : 5 ns Input falling time : 5 ns Input judge level : VDD/2 Output judge level : VDD/2 DS501-00048-6v1-E 15 MB85RS128TY(AEC-Q100 Compliant) AC Load Equivalent Circuit VDD Output 30 pF 3. Pin Capacitance Parameter Symbol Condition Output capacitance CO Input capacitance CI VDD  3.3 V, VIN  VOUT  0 V to VDD, f  1 MHz, TA  +25 C 16 Value Unit Min Max  8 pF  6 pF DS501-00048-6v1-E MB85RS128TY(AEC-Q100 Compliant)  TIMING DIAGRAM  Serial Data Timing tD CS tCSH tCSU tCH tCL tCH SCK tSU tH Valid in SI tODV SO tOH tOD High-Z High-Z : H or L  Hold Timing CS SCK tHS tHH tHS tHS tHH tHS tHH tHH HOLD High-Z SO tHZ DS501-00048-6v1-E tLZ High-Z tHZ tLZ 17 MB85RS128TY(AEC-Q100 Compliant)  POWER ON/OFF SEQUENCE tpd tr tf tpu VDD VDD VDD (Min) VDD (Min) VIH (Min) VIH (Min) 1.0 V 1.0 V VIL (Max) VIL (Max) VSS VSS CS >VDD × 0.8 ∗ CS CS >VDD × 0.8 ∗ CS : don't care CS * : CS (Max) < VDD  0.5 V Parameter Symbol Value Min Max 400  0  Condition Unit VDD 1.8V to 2.7V CS level hold time at power OFF tpd CS level hold time at power ON tpu 250  s  Power supply rising time tr 0.05  ms/V  Power supply falling time tf 0.1  ms/V  ns 2.7V to 3.6V If the device does not operate within the specified conditions of read cycle, write cycle or power on/off sequence, memory data can not be guaranteed.  FRAM CHARACTERISTICS Parameter Read/Write Endurance*1 Data Retention*2 Value Min Max 1013  3.38 or more*3  10.9  40.2  Unit Remarks Times/byte Total number of reading and writing. Operation Ambient Temperature TA   125 C Operation Ambient Temperature TA   125 C Years Operation Ambient Temperature TA   105 C Operation Ambient Temperature TA   85 C *1 : Total number of reading and writing defines the minimum value of endurance, as an FRAM memory operates with destructive readout mechanism. *2: Minimum values define retention time of the first reading/writing data right after shipment, and these values are calculated by qualification results. *3: Under evaluation for more than 3.38 years(+125 C). 18 DS501-00048-6v1-E MB85RS128TY(AEC-Q100 Compliant)  NOTE ON USE We recommend programming of the device after reflow. Data written before reflow cannot be guaranteed.  ESD AND LATCH-UP Test DUT ESD HBM (Human Body Model) JESD22-A114 compliant ESD CDM (Charged Device Model) JESD22-C101 compliant Latch-Up (I-test) JESD78 compliant Value  |2000 V| MB85RS128TYPNF-GS-AWE2 MB85RS128TYPNF-GS-BCE1 MB85RS128TYPNF-GS-AWERE2 MB85RS128TYPNF-GS-BCERE1 Latch-Up (Vsupply overvoltage test) JESD78 compliant  |1000 V|  |125 mA|  5.4V  REFLOW CONDITIONS AND FLOOR LIFE [ JEDEC MSL ] : Moisture Sensitivity Level 3 (IPC/JEDEC J-STD-020D)  Current status on Contained Restricted Substances This product complies with the regulations of REACH Regulations, EU RoHS Directive and China RoHS.　 DS501-00048-6v1-E 19 MB85RS128TY(AEC-Q100 Compliant)  ORDERING INFORMATION Part number MB85RS128TYPNF-GS-AWE2 MB85RS128TYPNF-GS-BCE1 MB85RS128TYPNF-GS-AWRE2 MB85RS128TYPNF-GS-BCERE1 Package Shipping form Minimum shipping quantity 8-pin plastic SOP Tube * 8-pin plastic SOP Embossed Carrier tape 1500 * : Please contact our sales office about minimum shipping quantity. Note:MB85RS128TYPNF-GS has two basic part numbers, “-AW” and “-BC”, corresponding to each assembly site. 20 DS501-00048-6v1-E MB85RS128TY(AEC-Q100 Compliant)  PACKAGE DIMENSION (1) MB85RS128TYPNF-GS-AWE2/MB85RS128TYPNF-GS-AWERE2 8-pin plastic SOP 1.27 mm Lead pitch Package width × package length 3.9 mm × 4.9 mm Lead shape Gullwing Sealing method Plastic mold Mounting heigth 1.75 mm MAX MB85RS128TYPNF-GS-AWE2, MB85RS128TYPNF-GS-AWERE2 8-pin plastic SOP 㸦)3730 Note *: These dimensions do not include resin protrution. Pins width not do ninclude tie bar cutting remaindar. 5pin 1pin “A” s 3.90s* 8pin 4pin 1.27 0.10㹼0.25 0.10(Min) 1.75(Max) 4.90±0.1 * 1.25(Min) 0.41±0.1 0.4(Min) Details of “A” part Dimensions in mm DS501-00048-6v1-E 21 MB85RS128TY(AEC-Q100 Compliant) (2) MB85RS128TYPNF-GS-BCE1/MB85RS128TYPNF-GS-BCERE1 8-pin plastic SOP 1.27 mm Lead pitch Package width × package length 3.9 mm × 4.89 mm Lead shape Gullwing Sealing method Plastic mold Mounting heigth 1.73 mm MAX MB85RS128TYPNF-GS-BCE1, MB85RS128TYPNF-GS-BCERE1 8-pin plastic SOP Note *: These dimensions do not include resin protrution. Pins width not do ninclude tie bar cutting remaindar. 3.81㹼3.99* 1pin 㹼 5pin 8pin “F” 4pin 1.27(Typ) +0.063 0.42 -0.064 0.22 -0.017 +0.034 0.102㹼0.254 1.55㹼1.73 1.5(Typ) 4.80 㹼 4.98* 0.406㹼0.889 Details of “F” part Dimenssions in mm 22 DS501-00048-6v1-E MB85RS128TY(AEC-Q100 Compliant)  MARKING (Example) (1) MB85RS128TYPNF-GS-AWE2/MB85RS128TYPNF-GS-AWERE2 [MB85RS128TYPNF-GS-AWE2] [MB85RS128TYPNF-GS-AWERE2] S12TY A1907 R01 S12TY: Product name A1907 : A(CS code) + 1907(Year and Week code) R01 : Trace code DS501-00048-6v1-E 23 MB85RS128TY(AEC-Q100 Compliant) (2) MB85RS128TYPNF-GS-BCE1/MB85RS128TYPNF-GS-BCERE1 [MB85RS128TYPNF-GS-BCE1] [MB85RS128TYPNF-GS-BCERE1] S12TY A1907 V01 S12TY : Product name A1907 : A(CS code) + 1907(Year + Week code) V01 : Trace code 24 DS501-00048-6v1-E MB85RS128TY(AEC-Q100 Compliant)  PACKING INFORMATION (1) MB85RS128TYPNF-GS-AWE2/MB85RS128TYPNF-GS-AWERE2 1. Tube (MB85RS128TYPNF-GS-AWE2) 1.1 Tube Dimensions • Tube/stopper shape (example) Tube Stopper • Tube cross-sections and Maximum quantity Maximum quantity pcs/tube pcs/inner box 85 4,250 pcs/outer box 25,500 3.9 8.0 No heat resistance. Package should not be baked by using tube. (Dimensions in mm) • Direction of index in tube Index mark DS501-00048-6v1-E 25 MB85RS128TY(AEC-Q100 Compliant) 1.2 Product label indicators (example) Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm  100mm) Supplemental Label (20mm  100mm)] XXXXXXXXXXXXXX (Customer part number or FJ part number) C-3 Label (3N)1 XXXXXXXXXXXXXX XXX (LEAD FREE mark) (Part number and quantity) QC PASS (3N)2 XXXXXXXXXX XXXXXX (FJ control number) XXX pcs XXXXXXXXXXXXXX (Quantity) (Customer part number or FJ part number) (Customer part number or FJ part number bar code) XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx XXXXXXXXXXXXXX (Customer part number or FJ part number) (FJ control number bar code) XX/XX XXXX-XXX XXX (Package count) XXXX-XXX XXX XXXXXXXXXX (FJ control number ) (Lot Number and quantity) XXXXXXXXXXXXXX (Comment) 26 Perforated line Supplemental Label DS501-00048-6v1-E MB85RS128TY(AEC-Q100 Compliant) 1.3 Dimensions for Containers (1) Dimensions for inner box H W L L W H 549 125 81 (Dimensions in mm) (2) Dimensions for outer box H W L L W H 567 272 269 (Dimensions in mm) DS501-00048-6v1-E 27 MB85RS128TY(AEC-Q100 Compliant) 2. Emboss Tape (MB85RS128TYPNF-GS-AWERE2) 2.1 Tape Dimensions (not drawn to scale) (8-pin plastic SOP) Maximum storage capacity pcs/reel(Φ330mm) pcs/inner box pcs/outer box 1500 1500 (1 pack/inner box) 9000 (6 inner boxes/outer box:Max.) 8.0 1.75 2.0 4.0 0.3 A B A 5.4 12.0 5.5 B SEC.B-B 1.7 6.4 SEC.A-A (Dimension in mm) Heat proof temperature : No heat resistance. Package should not be baked by using tape and reel. 28 DS501-00048-6v1-E MB85RS128TY(AEC-Q100 Compliant) 2.2 IC orientation • example Index mark (User Direction of Feed) (Feed Side) (User Direction of Feed) 2.3 Reel dimensions C B A Reel cutout dimensions W1 W2 Dimensions in mm A B C W1 W2 300 100 13 13.5 17.5 DS501-00048-6v1-E 29 MB85RS128TY(AEC-Q100 Compliant) 2.4 Product label indicators (examples) Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm  100mm) Supplemental Label (20mm  100mm)] XXXXXXXXXXXXXX (Customer part number or FJ part number) C-3 Label (LEAD FREE mark) (3N)1 XXXXXXXXXXXXXX XXX (Part number and quantity) QC PASS (3N)2 XXXXXXXXXX XXXXXX (FJ control number) XXX pcs XXXXXXXXXXXXXX (Quantity) (Customer part number or FJ part number) (Customer part number or FJ part number bar code) XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx XXXXXXXXXXXXXX (Customer part number or FJ part number) (FJ control number bar code) XX/XX XXXX-XXX XXX (Package count) XXXX-XXX XXX XXXXXXXXXX (FJ control number ) (Lot Number and quantity) XXXXXXXXXXXXXX (Comment) Perforated line Supplemental Label Label II:Moisture Barrier Bag (It sticks it on the Aluminum laminated bag) [MSL Label (100mm  70mm)] MSL label 30 DS501-00048-6v1-E MB85RS128TY(AEC-Q100 Compliant) 2.5 Dimensions for Containers (1) Dimensions for inner box H W L Tape width L W H 12 350 335 35 (Dimensions in mm) (2) Dimensions for outer box H W L L W H 384 368 225 (Dimensions in mm) DS501-00048-6v1-E 31 MB85RS128TY(AEC-Q100 Compliant) (2) MB85RS128TYPNF-GS-BCE1/MB85RS128TYPNF-GS-BCERE1 1. Tube (MB85RS128TYPNF-GS-BCE1) 1.1 Tube Dimensions • Tube/stopper shape (example) Tube Stopper • Tube cross-sections and Maximum quantity Maximum quantity pcs/tube(500mm) pcs/inner box pcs/outer box 85 4,250 17,000 4 9.5 No heat resistance. Package should not be baked by using tube. (Dimensions in mm) • Direction of index in tube Index mark 32 DS501-00048-6v1-E MB85RS128TY(AEC-Q100 Compliant) 1.2 Product label indicators (example) Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm  100mm) Supplemental Label (20mm  100mm)] XXXXXXXXXXXXXX (Customer part number or FJ part number) C-3 Label (LEAD FREE mark) (3N)1 XXXXXXXXXXXXXX XXX (Part number and quantity) QC PASS (3N)2 XXXXXXXXXX XXXXXX (FJ control number) XXX pcs XXXXXXXXXXXXXX (Quantity) (Customer part number or FJ part number) (Customer part number or FJ part number bar code) XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx XXXXXXXXXXXXXX (Customer part number or FJ part number) (FJ control number bar code) XX/XX XXXX-XXX XXX (Package count) XXXX-XXX XXX XXXXXXXXXX (FJ control number ) (Lot Number and quantity) XXXXXXXXXXXXXX (Comment) DS501-00048-6v1-E Perforated line Supplemental Label 33 MB85RS128TY(AEC-Q100 Compliant) 1.3 Dimensions for Containers (1) Dimensions for inner box H W L L W H 533 124 73 (Dimensions in mm) (2) Dimensions for outer box H W L L W H 549 277 180 (Dimensions in mm) 34 DS501-00048-6v1-E MB85RS128TY(AEC-Q100 Compliant) 2. Emboss Tape (MB85RS128TYPNF-GS-BCERE1) 2.1 Tape Dimensions (not drawn to scale) (8-pin plastic SOP) Maximum storage capacity pcs/reel(Φ330mm) pcs/inner box pcs/uter boxo 1500 1500 (1 pack/inner box) 9000 (6 inner boxes/outer box:Max) 8.0 1.75 2.0 4.0 0.3 A B A 5.2 12.0 5.5 B SEC.B-B 2.1 6.1 SEC.A-A (Dimensions in mm) Heat proof temperature : No heat resistance. Package should not be baked by using tape and reel. DS501-00048-6v1-E 35 MB85RS128TY(AEC-Q100 Compliant) 2.2 IC orientation • example Index mark (User Direction of Feed) (Feed Side) (User Direction of Feed) 2.3 Reel dimensions C B A Reel cutout dimensions W1 W2 Dimensions in mm 36 A B C W1 W2 254 100 13 13.5 17.5 DS501-00048-6v1-E MB85RS128TY(AEC-Q100 Compliant) 2.4 Product label indicators (examples) Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm  100mm) Supplemental Label (20mm  100mm)] XXXXXXXXXXXXXX (Customer part number or FJ part number) C-3 Label (3N)1 XXXXXXXXXXXXXX XXX (LEAD FREE mark) (Part number and quantity) QC PASS (3N)2 XXXXXXXXXX XXXXXX (FJ control number) XXX pcs XXXXXXXXXXXXXX (Quantity) (Customer part number or FJ part number) (Customer part number or FJ part number bar code) XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx XXXXXXXXXXXXXX (Customer part number or FJ part number) (FJ control number bar code) XX/XX XXXX-XXX XXX (Package count) XXXX-XXX XXX XXXXXXXXXX (FJ control number ) (Lot Number and quantity) XXXXXXXXXXXXXX (Comment) Perforated line Supplemental Label Label II:Moisture Barrier Bag (It sticks it on the Aluminum laminated bag) [MSL Label (100mm  70mm)] MSL label DS501-00048-6v1-E 37 MB85RS128TY(AEC-Q100 Compliant) 2.5 Dimensions for Containers (1) Dimensions for inner box H W L Tape width L W H 12 265 262 51 (Dimensions in mm) (2) Dimensions for outer box H W L L W H 549 277 180 (Dimensions in mm) 38 DS501-00048-6v1-E MB85RS128TY(AEC-Q100 Compliant)  MAJOR CHANGES IN THIS EDITION A change on a page is indicated by a vertical line drawn left side of that page. Page Section Change Results Data retention is prolonged. 1 FEATURES 2.5years(125 C), 8.2years(105 C), 30years(85 C) -> 3.38years(125 C), 10.9years(105 C), 40.2years(85 C) Data retention is prolonged. 18 FRAM CHARACTERISTICS 2.5years(125 C), 8.2years(105 C), 30years(85 C) -> 3.38years(125 C), 10.9years(105 C), 40.2years(85 C) New part numbers are added. 20 ORDERING INFORMATION MB85RS128TYPNF-GS-AWE2 MB85RS128TYPNF-GS-AWERE2 New package dimension is added. 21 PACKAGE DIMENSION MB85RS128TYPNF-GS-AWE2 MB85RS128TYPNF-GS-AWERE2 Marking for new package is added. 23 MARKING MB85RS128TYPNF-GS-AWE2 MB85RS128TYPNF-GS-AWERE2 Packing information for new package is added. 25 to31 PACKING INFORMATION MB85RS128TYPNF-GS-AWE2 MB85RS128TYPNF-GS-AWERE2 37 PACKING INFORMATION 2.4 Product Label indicators Label II: Moisture Barrier Bag DS501-00048-6v1-E MSL Label is revised. 39 MB85RS128TY(AEC-Q100 Compliant) FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED Shin-Yokohama TECH Building, 3-9-1 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa 222-0033, Japan https://www.fujitsu.com/jp/fsm/en/ All Rights Reserved. FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED, its subsidiaries and affiliates (collectively, "FUJITSU SEMICONDUCTOR MEMORY SOLUTION ") reserves the right to make changes to the information contained in this document without notice. Please contact your FUJITSU SEMICONDUCTOR MEMORY SOLUTION sales representatives before order of FUJITSU SEMICONDUCTOR MEMORY SOLUTION device. Information contained in this document, such as descriptions of function and application circuit examples is presented solely for reference to examples of operations and uses of FUJITSU SEMICONDUCTOR MEMORY SOLUTION device. FUJITSU SEMICONDUCTOR MEMORY SOLUTION disclaims any and all warranties of any kind, whether express or implied, related to such information, including, without limitation, quality, accuracy, performance, proper operation of the device or non-infringement. If you develop equipment or product incorporating the FUJITSU SEMICONDUCTOR MEMORY SOLUTION device based on such information, you must assume any responsibility or liability arising out of or in connection with such information or any use thereof. FUJITSU SEMICONDUCTOR MEMORY SOLUTION assumes no responsibility or liability for any damages whatsoever arising out of or in connection with such information or any use thereof. Nothing contained in this document shall be construed as granting or conferring any right under any patents, copyrights, or any other intellectual property rights of FUJITSU SEMICONDUCTOR MEMORY SOLUTION or any third party by license or otherwise, express or implied. FUJITSU SEMICONDUCTOR MEMORY SOLUTION assumes no responsibility or liability for any infringement of any intellectual property rights or other rights of third parties resulting from or in connection with the information contained herein or use thereof. The products described in this document are designed, developed and manufactured as contemplated for general use including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high levels of safety is secured, could lead directly to death, personal injury, severe physical damage or other loss (including, without limitation, use in nuclear facility, aircraft flight control system, air traffic control system, mass transport control system, medical life support system and military application), or (2) for use requiring extremely high level of reliability (including, without limitation, submersible repeater and artificial satellite). FUJITSU SEMICONDUCTOR MEMORY SOLUTION shall not be liable for you and/or any third party for any claims or damages arising out of or in connection with above-mentioned uses of the products. Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs and safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures into your facility, equipments and products such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. The products and technical information described in this document are subject to the Foreign Exchange and Foreign Trade Control Law of Japan, and may be subject to export or import laws or regulations in U.S. or other countries. You are responsible for ensuring compliance with such laws and regulations relating to export or re-export of the products and technical information described herein. All company names, brand names and trademarks herein are property of their respective owners. Edited: Marketing Division Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Fujitsu Semiconductor: MB85RS128TYPNF-GS-BCERE1