FUJITSU SEMICONDUCTOR
DATA SHEET
DS501-00032-3v0-E
Memory FRAM
2 M (256 K 8) Bit SPI
MB85RS2MTA
DESCRIPTION
MB85RS2MTA is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 262,144
words 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the
nonvolatile memory cells.
MB85RS2MTA adopts the Serial Peripheral Interface (SPI).
The MB85RS2MTA is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85RS2MTA can be used for 1013 read/write operations, which is a significant
improvement over the number of read and write operations supported by Flash memory and E2PROM.
MB85RS2MTA does not take long time to write data like Flash memories or E2PROM, and MB85RS2MTA
takes no wait time.
FEATURES
• Bit configuration : 262,144 words 8 bits
• Serial Peripheral Interface : SPI (Serial Peripheral Interface)
Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)
• Operating frequency : 40MHz (Max)
•
•
•
•
High endurance : 1013 times / byte
Data retention
: 10 years (+85 C), 95 years(+55 C), over 200 years(+35 C)
Operating power supply voltage : 1.8 V to 3.6 V
Low power consumption :
Operating power supply current 2.3mA (Max@40 MHz)
Standby current 50 A (Max)
Sleep current 10 A (Max)
• Operation ambient temperature range : -40 C to +85 C
• Package
: 8-pin plastic SOP (FPT-8P-M09)
8-pin plastic DIP (DIP-8P-M03)
RoHS compliant
Copyright 2018 FUJITSU SEMICONDUCTOR LIMITED
2018.03
MB85RS2MTA
PIN ASSIGNMENT
(TOP VIEW)
(TOP VIEW)
CS
1
8
VDD
CS
1
8
VDD
SO
2
7
HOLD
SO
2
7
HOLD
WP
3
6
SCK
WP
3
6
SCK
VSS
4
5
SI
VSS
4
5
SI
(DIP-8P-M03)
(FPT-8P-M09)
PIN FUNCTIONAL DESCRIPTIONS
Pin No. Pin Name
CS
Chip Select pin
This is an input pin to make chips select. When CS is “H” level, device is in deselect
(standby) status and SO becomes High-Z. Inputs from other pins are ignored for this
time. When CS is “L” level, device is in select (active) status. CS has to be “L” level before
inputting op-code. The Chip Select pin is pulled up internally to the VDD pin.
WP
Write Protect pin
This is a pin to control writing to a status register. The writing of status register (see “?
STATUS REGISTER”) is protected in related with WP and WPEN. See “?WRITING PROTECT” for detail.
7
HOLD
Hold pin
This pin is used to interrupt serial input/output without making chips deselect. When
HOLD is “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become
do not care. While the hold operation, CS has to be retained “L” level.
6
SCK
Serial Clock pin
This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising
edge, SO is output synchronously to a falling edge.
5
SI
Serial Data Input pin
This is an input pin of serial data. This inputs op-code, address, and writing data.
2
SO
Serial Data Output pin
This is an output pin of serial data. Reading data of FRAM memory cell array and status
register data are output. This is High-Z during standby.
8
VDD
Supply Voltage pin
4
VSS
Ground pin
1
3
2
Functional description
DS501-00032-3v0-E
MB85RS2MTA
BLOCK DIAGRAM
Control Circuit
SCK
HOLD
Row Decoder
CS
Address Counter
Serial-Parallel Converter
SI
FRAM Cell Array
262,144 ✕ 8
FRAM
Status Register
Column Decoder/Sense Amp/
Write Amp
WP
Data Register
SO
Parallel-Serial Converter
DS501-00032-3v0-E
3
MB85RS2MTA
SPI MODE
MB85RS2MTA corresponds to the SPI mode 0 (CPOL 0, CPHA 0) , and SPI mode 3 (CPOL 1, CPHA
1) .
CS
SCK
SI
7
6
5
MSB
4
3
2
1
0
LSB
SPI Mode 0
CS
SCK
SI
7
6
5
4
MSB
3
2
1
0
LSB
SPI Mode 3
4
DS501-00032-3v0-E
MB85RS2MTA
SERIAL PERIPHERAL INTERFACE (SPI)
MB85RS2MTA works as a slave of SPI. More than 2 devices can be connected by using microcontroller
equipped with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus
connected to use.
SCK
MOSI
MISO
SO
SPI
Microcontroller
SI
SO
SCK
MB85RS2MTA
CS
SI
SCK
MB85RS2MTA
CS
HOLD
HOLD
SS1
SS2
HOLD1
HOLD2
MOSI : Master Out Slave In
MISO : Master In Slave Out
SS
: Slave Select
System Configuration with SPI Port
SO
SI
SCK
Microcontroller
MB85RS2MTA
CS
HOLD
System Configuration without SPI Port
DS501-00032-3v0-E
5
MB85RS2MTA
STATUS REGISTER
Bit No.
Bit Name
Function
WPEN
Status Register Write Protect
This is a bit composed of nonvolatile memories (FRAM). WPEN protects
writing to a status register (refer to “?WRITING PROTECT”) relating with
WP input. Writing with the WRSR command and reading with the RDSR
command are possible.
6 to 4
Not Used Bits
These are bits composed of nonvolatile memories, writing with the WRSR
command is possible. These bits are not used but they are read with the
RDSR command.
3
BP1
2
BP0
7
1
WEL
0
0
Block Protect
This is a bit composed of nonvolatile memory. This defines size of write
protect block for the WRITE command (refer to “?BLOCK PROTECT”).
Writing with the WRSR command and reading with the RDSR command
are possible.
Write Enable Latch
This indicates FRAM Array and status register are writable. The WREN
command is for setting, and the WRDI command is for resetting. With the
RDSR command, reading is possible but writing is not possible with the
WRSR command. WEL is reset after the following operations.
After power ON.
After WRDI command recognition.
This device supports continual programming mode. After the following operations, without reseting WEL, this device can be programmed continually.
After WRSR command.
After WRITE command.
This is a bit fixed to “0”.
OP-CODE
MB85RS2MTA accepts 9 kinds of command specified in op-code. Op-code is a code composed of 8 bits
shown in the table below. Do not input invalid codes other than those codes. If CS is risen while inputting
op-code, the command are not performed.
Name
Description
Op-code
WREN
Set Write Enable Latch
0000 0110B
WRDI
Reset Write Enable Latch
0000 0100B
RDSR
Read Status Register
0000 0101B
WRSR
Write Status Register
0000 0001B
READ
Read Memory Code
0000 0011B
WRITE
Write Memory Code
0000 0010B
Read Device ID
1001 1111B
FSTRD
Fast Read Memory Code
0000 1011B
SLEEP
Sleep Mode
1011 1001B
RDID
6
DS501-00032-3v0-E
MB85RS2MTA
COMMAND
WREN
The WREN command sets WEL (Write Enable Latch) . WEL has to be set with the WREN command before
writing operation (WRSR command and WRITE command) .
CS
0
1
2
3
4
5
6
7
SCK
SI
Invalid
0
0
0
0
0
1
1
Invalid
0
High-Z
SO
WRDI
The WRDI command resets WEL (Write Enable Latch) . Writing operation (WRSR command and WRITE
command) are not performed when WEL is reset.
CS
0
1
2
3
4
5
6
7
SCK
SI
Invalid
SO
DS501-00032-3v0-E
0
0
0
0
0
1
0
0
Invalid
High-Z
7
MB85RS2MTA
RDSR
The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input
to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. In the
RDSR command, repeated reading of status register is enabled by sending SCK continuously before rising
of CS.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
Invalid
1
Data Out
High-Z
SO
Invalid
LSB
MSB
WRSR
The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR
op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR
command. A SI value correspondent to bit 1 is ignored. Bit 0 of the status register is fixed to “0” and cannot
be written. The SI value corresponding to bit 0 is ignored. WP signal level shall be fixed before performing
WRSR command, and do not change the WP signal level until the end of command sequence.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Data In
Instruction
SI
SO
8
0
0
0
0
0
0
0
1
7
MSB
High-Z
6
5
4
3
2
1
0
LSB
DS501-00032-3v0-E
MB85RS2MTA
READ
The READ command reads FRAM memory cell array data. Arbitrary 24 bits address and op-code of READ
are input to SI. The 6-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output
synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ
command is completed, but keeps on reading with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant
address, it rolls over to the starting address, and reading cycle keeps on infinitely.
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
24-bit Address
OP-CODE
Invalid
5 4 3 2 1 0
0 0 0 0 0 0 1 1 X X X X X X 17 16
Data Out
MSB
LSB MSB
LSB
High-Z
7 6 5 4 3 2 1 0
SI
SO
Invalid
WRITE
The WRITE command writes data to FRAM memory cell array. WRITE op-code, arbitrary 24 bits of address
and 8 bits of writing data are input to SI. The 6-bit upper address bit is invalid. When 8 bits of writing data is
input, data is written to FRAM memory cell array. Risen CS will terminate the WRITE command, but if you
continue sending the writing data for 8 bits each before CS rising, it is possible to continue writing with
automatic address increment. When it reaches the most significant address, it rolls over to the starting
address, and writing cycle can be continued infinitely.
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
SI
Data In
24-bit Address
OP-CODE
0 0 0 0 0 0 1 0 X X X X X X 17 16
5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB
SO
DS501-00032-3v0-E
High-Z
LSB MSB
LSB
9
MB85RS2MTA
FSTRD
The FSTRD command reads FRAM memory cell array data. Arbitrary 24 bits address and op-code of FSTRD
are input to SI followed by 8 bits dummy. The 6-bit upper address bit is invalid. Then, 8-cycle clock is input
to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When
CS is risen, the FSTRD command is completed, but keeps on reading with automatic address increment
which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches
the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely.
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 1415
29 30 31 32 33
24-bit Address
OP-CODE
0 0 0 0 1 0 1 1 X X X X X X 17 16
8-bit Dummy
X X
2 1 0 X X
38 39 40 41 42 43 44 45 46 47
SCK
SI
MSB
LSB
High-Z
SO
Invalid
MSB
Data Out LSB
7 6 5 4 3 2 1 0
Invalid
RDID
The RDID command reads fixed Device ID. After performing RDID op-code to SI, 32-cycle clock is input to
SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. The output
is in order of Manufacturer ID (8bit)/Continuation code (8bit)/Product ID (1st Byte)/Product ID (2nd Byte).
In the RDID command, SO holds the output state of the last bit in 32-bit Device ID until CS is risen.
CS
0
1
2
3
4
5
6
7
1
0
0
1
1
1
1
1
8
31 32 33 34 35 36 37 38 39
9 10 11
SCK
SI
Invalid
Data Out
SO
High-Z
Data Out
8
31 30 29 28
7
6
5
4
3
2
MSB
1
0
LSB
bit
Manufacturer ID
Continuation code
Product ID (1st Byte)
Product ID (2nd Byte)
10
7
0
0
6
0
1
5
0
1
Proprietary use
0
1
0
0
0
0
4
0
1
3
0
1
2
1
1
0
Density
1
0
0
Proprietary use
0
0
0
1
0
1
1
0
0
1
Hex
04H Fujitsu
7FH
0
Hex
48H Density: 01000B 2 Mbit
1
Hex
03H
DS501-00032-3v0-E
MB85RS2MTA
SLEEP
The SLEEP command shifts the LSI to a low power mode called “SLEEP mode”. The transition to the SLEEP
mode is carried out at the rising edge of CS after operation code in the SLEEP command. However, when
at least one SCK clock is inputted before the rising edge of CS after operation code in the SLEEP command,
this SLEEP command is canceled.
After the SLEEP mode transition, SCK and SI inputs are ignored and SO changes to a Hi-Z state.
Enter Sleep Mode
CS
0
1
2
3
4
5
6
7
1
0
1
1
1
0
0
1 Invalid
SCK
SI Invalid
Hi-Z
SO
Sleep Mode Entry
Returning to an normal operation from the SLEEP mode is carried out after tREC (Max 400 s) time from the
falling edge of CS (see the figure below). It is possible to return CS to H level before tREC time. However, it
is prohibited to bring down CS to L level again during tREC period.
CS
CS
tREC
From this time
Command input enable
Exit Sleep Mode
Sleep Mode Exit
DS501-00032-3v0-E
11
MB85RS2MTA
BLOCK PROTECT
Writing protect block for WRITE command is configured by the value of BP0 and BP1 in the status register.
BP1
BP0
Protected Block
0
0
None
0
1
30000H to 3FFFFH (upper 1/4)
1
0
20000H to 3FFFFH (upper 1/2)
1
1
00000H to 3FFFFH (all)
WRITING PROTECT
Writing operation of the WRITE command and the WRSR command are protected with the value of WEL,
WPEN, WP as shown in the table.
Protected Blocks
Unprotected Blocks
Status Register
WEL
WPEN
WP
0
X
X
Protected
Protected
Protected
1
0
X
Protected
Unprotected
Unprotected
1
1
0
Protected
Unprotected
Protected
1
1
1
Protected
Unprotected
Unprotected
HOLD OPERATION
Hold status is retained without aborting a command if HOLD is “L” level while CS is “L” level. The timing for
starting and ending hold status depends on the SCK to be “H” level or “L” level when a HOLD pin input is
transited to the hold condition as shown in the diagram below. In case the HOLD pin transited to “L” level
when SCK is “L” level, return the HOLD pin to “H” level at SCK being “L” level. In the same manner, in case
the HOLD pin transited to “L” level when SCK is “H” level, return the HOLD pin to “H” level at SCK being “H”
level. Arbitrary command operation is interrupted in hold status, SCK and SI inputs become do not care.
And, SO becomes High-Z while reading command (RDSR, READ). If CS is rising during hold status, a
command is aborted. In case the command is aborted before its recognition, WEL holds the value before
transition to hold status.
CS
SCK
HOLD
Hold Condition
12
Hold Condition
DS501-00032-3v0-E
MB85RS2MTA
ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Min
Max
Unit
Power supply voltage*
VDD
0.5
4.0
V
Input voltage*
VIN
0.5
VDD 0.5 ( 4.0)
V
VOUT
0.5
VDD 0.5 ( 4.0)
V
TA
40
85
C
Tstg
55
125
C
Output voltage*
Operation ambient temperature
Storage temperature
*:These parameters are based on the condition that VSS is 0 V.
WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without
limitation, voltage, current or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Min
Typ
Max
Unit
Power supply voltage*1
VDD
1.8
3.3
3.6
V
Operation ambient temperature*2
TA
40
85
C
*1: These parameters are based on the condition that VSS is 0 V.
*2: Ambient temperature when only this device is working. Please consider it to be the almost same as the
package surface temperature.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of
device and could result in device failure.
No warranty is made with respect to any use, operating conditions or combinations not represented
on this data sheet. If you are considering application under any conditions other than listed herein,
please contact sales representatives beforehand.
DS501-00032-3v0-E
13
MB85RS2MTA
ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(within recommended operating conditions)
Parameter
Input leakage current*1
Output leakage current*2
Operating power supply current
Symbol
Condition
|ILI|
|ILO|
IDD
Value
Min
Typ
Max
0 CS< VDD
200
CS VDD
1
WP, HOLD, SCK
SI 0 V to VDD
1
SO 0 V to VDD
1
SCK 1MHz
0.16
SCK 33 MHz
1.6
2.0
SCK 40 MHz
1.9
2.3
Unit
A
A
mA
Standby current
ISB
SCK SI CS VDD
50
A
Sleep current
IZZ
CS VDD
All inputs VSS or VDD
10
A
Input high voltage
VIH
VDD 1.8 V to 3.6 V
VDD 0.7
VDD 0.5
V
Input low voltage
VIL
VDD 1.8 V to 3.6 V
0.5
VDD 0.3
V
Output high voltage
VOH
IOH 2 mA
VDD 0.5
V
Output low voltage
VOL
IOL 2 mA
0.4
V
Pull up resistance for CS
RP
18
33
80
k
*1 : Applicable pin : CS, WP, HOLD, SCK, SI
*2 : Applicable pin : SO
14
DS501-00032-3v0-E
MB85RS2MTA
2. AC Characteristics
Value
Parameter
Symbol
VDD 1.8 V to 2.7 V
VDD 2.7 V to 3.6 V
Min
Max
Min
Max
Unit
SCK clock frequency
fCK
0
33
0
40
MHz
Clock high time
tCH
13
11
ns
Clock low time
tCL
13
11
ns
Chip select set up time
tCSU
10
10
ns
Chip select hold time
tCSH
10
10
ns
Output disable time
tOD
12
-
12
ns
Output data valid time
tODV
13
-
9
ns
Output hold time
tOH
0
0
ns
Deselect time
tD
40
40
ns
Data in rising time
tR
50
-
50
ns
Data falling time
tF
50
-
50
ns
Data set up time
tSU
5
5
ns
Data hold time
tH
5
5
ns
HOLD set uptime
tHS
10
10
ns
HOLD hold time
tHH
10
10
ns
HOLD output floating time
tHZ
20
20
ns
HOLD output active time
tLZ
20
20
ns
SLEEP recovery time
tREC
400
400
s
AC Test Condition
Power supply voltage : 1.8 V to 3.6 V
Operation ambient temperature : 40 C to 85 C
Input voltage magnitude : VDD 0.7 VIH VDD
0 VIL VDD 0.3
Input rising time : 5 ns
Input falling time : 5 ns
Input judge level : VDD/2
Output judge level : VDD/2
DS501-00032-3v0-E
15
MB85RS2MTA
AC Load Equivalent Circuit
VDD
Output
30 pF
3. Pin Capacitance
Parameter
Symbol
Condition
Output capacitance
CO
Input capacitance
CI
VDD VIN VOUT 0 V,
f 1 MHz, TA +25 C
16
Value
Unit
Min
Max
8
pF
6
pF
DS501-00032-3v0-E
MB85RS2MTA
TIMING DIAGRAM
Serial Data Timing
tD
CS
tCSH
tCSU
tCH
tCL
tCH
SCK
tSU
tH
Valid in
SI
tODV
SO
tOH
tOD
High-Z
High-Z
: H or L
Hold Timing
CS
SCK
tHS
tHH
tHS
tHS
tHH
tHS
tHH
tHH
HOLD
High-Z
SO
tHZ
DS501-00032-3v0-E
tLZ
High-Z
tHZ
tLZ
17
MB85RS2MTA
POWER ON/OFF SEQUENCE
tpd
tf
tr
tpu
VDD
VDD
VDD (Min)
VDD (Min)
VIH (Min)
VIH (Min)
1.0 V
1.0 V
VIL (Max)
VIL (Max)
VSS
VSS
CS
CS >VDD × 0.7 ∗
CS >VDD × 0.7 ∗
CS : don't care
CS
* : CS (Max) < VDD 0.5 V
Parameter
Symbol
Value
Min
Max
0
400
Unit
CS level hold time at power OFF
tpd
CS level hold time at power ON
tpu
250
s
Power supply rising time
tr
0.05
ms/V
Power supply falling time
tf
0.1
ms/V
ns
Parameters
VDD 2.7V to 3.6V
VDD 1.8V to 2.7V
If the device does not operate within the specified conditions of read cycle, write cycle or power on/off
sequence, memory data can not be guaranteed.
FRAM CHARACTERISTICS
Parameter
Read/Write Endurance
Data Retention
Value
Min
Max
1013
10
95
≥200
Unit
Remarks
Times/byte
Operation Ambient Temperature TA 85 C
Operation Ambient Temperature TA 85 C
Years
Operation Ambient Temperature TA 55 C
Operation Ambient Temperature TA 35 C
*1 : Total number of reading and writing defines the minimum value of endurance, as an FRAM memory operates
with destructive readout mechanism.
*2: Minimum values define retention time of the first reading/writing data right after shipment, and the these
values are calculated by qualification results.
*
NOTE ON USE
18
DS501-00032-3v0-E
MB85RS2MTA
We recommend programming of the device after reflow. Data written before reflow cannot be guaranteed.
ESD AND LATCH-UP
Test
DUT
Value
ESD HBM (Human Body Model)
JESD22-A114 compliant
|1000 V|
ESD CDM (Charged Device Model)
JESD22-C101 compliant
|1000 V|
Latch-Up (I-test)
JESD78 compliant
MB85RS2MTAPNF-G-BDE1
MB85RS2MTAPH-G-JNE2
Latch-Up (Vsupply overvoltage test)
JESD78 compliant
Latch-Up (Current Method)
Proprietary method
Latch-Up (C-V Method)
Proprietary method
|200 V|
• Current method of Latch-Up Resistance Test
Protection Resistance
A
Test terminal
IIN
VIN
VDD
+
DUT
-
VSS
VDD
(Max.Rating)
V
Reference
terminal
Note : The voltage VIN is increased gradually and the current IIN of 300 mA at maximum shall flow.
Confirm the latch up does not occur under IIN 300 mA.
In case the specific requirement is specified for I/O and IIN cannot be 300 mA, the voltage shall be
increased to the level that meets the specific requirement.
DS501-00032-3v0-E
19
MB85RS2MTA
• C-V method of Latch-Up Resistance Test
Protection Resistance
A
1
Test
2 terminal
SW
+
VIN
V
-
C
200pF
VDD
DUT
VDD
(Max.Rating)
VSS
Reference
terminal
Note : Charge voltage alternately switching 1 and 2 approximately 2 sec interval. This switching process is
considered as one cycle. Repeat this process 5 times. However, if the latch-up condition occurs before
completing 5times, this test must be stopped immediately.
MB85RS2MTAPNF (8-pin plastic SOP) REFLOW CONDITIONS AND FLOOR LIFE
[ JEDEC MSL ] : Moisture Sensitivity Level 3 (ISP/JEDEC J-STD-020D)
CURRENT STATUS ON CONTAINED RESTRICTED SUBSTANCES
This product complies with the regulations of REACH Regulations, EU RoHS Directive and China RoHS.
20
DS501-00032-3v0-E
MB85RS2MTA
ORDERING INFORMATION
Package
Shipping form
Minimum shipping
quantity
MB85RS2MTAPNF-G-BDE1
8-pin plastic SOP
(FPT-8P-M09)
Tube
*
MB85RS2MTAPNF-G-BDERE1
8-pin plastic SOP
(FPT-8P-M09)
Embossed Carrier tape
1500
MB85RS2MTAPH-G-JNE2
8-pin plastic DIP
(DIP-8P-M03)
Tube
*
Part number
* : Please contact our sales office about minimum shipping quantity.
DS501-00032-3v0-E
21
MB85RS2MTA
PACKAGE DIMENSION
8-pin plastic SOP
1.27 mm
Lead pitch
Package width ×
package length
3.9 mm × 4.89 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting heigth
1.73 mm MAX
Weight
0.08 g
(FPT-8P-M09)
8-pin plastic SOP
（FPT-8P-M09）
Note 1) *1: These dimensions do not include resin protrution.
Note 2) *2: These dimensions do not include resin protrution.
5pin
8pin
5.84～6.20
0.17MAX
3.81～3.99*2
0.12MAX
“F”
4×R0.05
1pin
4pin
1.27(Typ)
+0.063
0.42 -0.064
5.30MAX
0.22 -0.017
+0.034
0.102～0.254
1.55～1.73
1.5(Typ)
4.80～4.98*1
0.406～0.889
Details of “F” part
C
2015 FUJITSU SEMICONDUCTOR LIMITED F08-17Sc
Dimenssions in mm
(Continued)
22
DS501-00032-3v0-E
MB85RS2MTA
(Continued)
8-pin plastic DIP
Lead pitch
2.54 mm
Sealing method
Plastic mold
Weight
0.46 g
(DIP-8P-M03)
8-pin plastic DIP
(DIP-8P-M03)
9.40
.370
8
+0.40
–0.30
+.016
–.012
5
INDEX
6.35±0.25
(.250±.010)
1
4
7.62(.300)
TYP.
4.36(.172)MAX
0.50(.020)
MIN
0.25±0.05
(.010±.002)
3.00(.118)MIN
+0.35
0.46±0.08
(.018±.003)
0.89 –0.30
+.014
.035 –.012
+0.30
0.99 –0
+.012
.039 –0
C
+0.30
1.52 –0
2006-2010 FUJITSU SEMICONDUCTOR LIMITED D08008S-c-1-4
DS501-00032-3v0-E
15° MAX
+.012
.060 –0
2.54(.100)
TYP.
Dimensions in mm (inches).
Note: The values in parentheses are reference values
23
MB85RS2MTA
MARKING
[MB85RS2MTAPNF-G-BDE1]
[MB85RS2MTAPNF-G-BDERE1]
S 2 M TA
11600
700
[FPT-08P-M09]
[MB85RS2MTAPH-G-JNE2]
RS2MTA
E21600
300
[DIP-08P-M03]
24
DS501-00032-3v0-E
MB85RS2MTA
PACKING INFORMATION
1. Tube
1.1 Tube Dimensions
• Tube/stopper shape
Tube
Transparent polyethylene terephthalate
(treated to antistatic)
Stopper
(treated to antistatic)
Tube length: 500 mm
Tube cross-sections and Maximum quantity
Maximum quantity
Package form
Package code
SOP, 8, plastic (2)
FPT-8P-M09
pcs/
tube
pcs/inner
box
pcs/outer
box
85
4250
17000
9.5
4.5
1.4
3
1.8
1
4
2
3.9
3.9
t 0.6
Transparent polyethylene terephthalate
(Dimensions
in mm)
DS501-00032-3v0-E
25
MB85RS2MTA
1.2 Tube Dry pack packing specifications
IC
Tube
Stopper
For SOP
Index mark
Label I *1*3
Aluminum Iaminated bag
Heat seal
Dry pack
Desiccant
Humidity indicater
Aluminum Iaminated bag
(tubes inside)
Inner box
Cushioning material
Inner box
Label I *1*3
Cushioning material
Outer box*2
Outer box
Use adhesive tapes.
Label II-A *3
Label II-B *3
*1: For a product of witch part number is suffixed with “E1”, a “ G
bag and the inner boxes.
Pb ” marks is display to the moisture barrier
*2: The space in the outer box will be filled with empty inner boxes, or cushions, etc.
*3: Please refer to an attached sheet about the indication label.
Note: The packing specifications may not be applied when the product is delivered via a distributor.
26
DS501-00032-3v0-E
MB85RS2MTA
1.3 Product label indicators
Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping)
[C-3 Label (50mm 100mm) Supplemental Label (20mm 100mm)]
XXXXXXXXXXXXXX
(Customer part number or FJ part number)
C-3 Label
(LEAD FREE mark)
(3N)1 XXXXXXXXXXXXXX XXX
(Part number and quantity)
QC PASS
(3N)2 XXXXXXXXXX XXXXXX
(FJ control number)
XXX pcs
XXXXXXXXXXXXXX
(Quantity)
(Customer part number or FJ part number)
(Customer part number or FJ part number
bar code)
XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx
XXXXXXXXXXXXXX (Customer part number or FJ part number)
(FJ control number bar code)
XX/XX
XXXX-XXX XXX
(Package count)
XXXX-XXX XXX
XXXXXXXXXX (FJ control number ) (Lot Number and quantity)
XXXXXXXXXXXXXX (Comment)
Perforated line
Supplemental Label
Label II-A: Label on Outer box [D Label] (100mm 100mm)
D Label
XXXXXXXXXXXXX (Customer Name)
(CUST.)
XXXXXXXXX (Delivery Address)
(DELIVERY POINT)
XXXXXXXXXXXXXX
(TRANS.NO.) (FJ control number)
XXXXXXXXXXXXXX
(PART NO.)
(Customer part number or
FJ part number)
XXX (FJ control number)
XXX (FJ control number)
XXX (FJ control number)
XXXXXXXXXXXXXX
(Part number)
(PART NAME) XXXXXXXXXXXXXX (Part number)
XXX/XXX
(Q’TY/TOTAL Q’TY)
(CUSTOMER'S
REMARKS)
XXXXXXXXXXXXXXXXXXXX
(3N)3 XXXXXXXXXXXXXX XXX
XX
(UNIT)
(PACKAGE COUNT)
XXX/XXX
(3N)4 XXXXXXXXXXXXXX XXX
(FJ control number + Product quantity)
(FJ control number + Product quantity
bar code)
(Part number + Product quantity)
(3N)5 XXXXXXXXXX
(FJ control number)
(Part number + Product quantity bar code)
(FJ control number bar code)
Label II-B: Outer boxes product indicate
XXXXXXXXXXXXXX
(Lot Number)
XXXX-XXX
XXXX-XXX
(Part number)
(Count)
X
X
(Quantity)
XXX
XXX
XXX
Note: Depending on shipment state, “Label II-A” and “Label II-B” on the external boxes might not be printed.
DS501-00032-3v0-E
27
MB85RS2MTA
1.4 Dimensions for Containers
(1) Dimensions for inner box
H
L
W
L
W
H
540
125
75
(Dimensions in mm)
(2) Dimensions for outer box
H
W
L
L
W
H
565
270
180
(Dimensions in mm)
28
DS501-00032-3v0-E
MB85RS2MTA
2. Emboss Tape (FPT-8P-M09)
2.1 Tape Dimensions
Maximum storage capacity
PKG code
Reel No
FPT-8P-M09
2
pcs/reel
pcs/inner box
pcs/uter boxo
1500
1500
9000
ø1.5 +0.1
–0
8±0.1
1.75±0.1
2±0.05
4±0.1
B
0.3±0.05
A
B
A
5.2+0.4
–0.2
12.0±0.3
5.5±0.05
ø1.5 +0.1
–0
SEC.B-B
2.1±0.1
6.1+0.4
–0.2
0.4
3.9±0.2
SEC.A-A
C
2012 FUJITSU SEMICONDUCTOR LIMITED SOL8-EMBOSSTAPE9 : NFME-EMB-X0084-1-P-1
(Dimensions in mm)
Material : Conductive polystyrene
Heat proof temperature : No heat resistance.
Package should not be baked
by using tape and reel.
DS501-00032-3v0-E
29
MB85RS2MTA
2.2 IC orientation
• ER type
(User Direction of Feed)
Index mark
(Reel side)
(User Direction of Feed)
2.3 Reel dimensions
Reel cutout dimensions
E
∗
W2
D
C
B
A
W1
r
W3
∗:
Hub unit width dimensions
Dimensions in mm
Reel No
2
Tape width
Symbol
A
B
C
D
E
W1
W2
W3
r
30
12
254 ± 2
+2
100 -0
13 ± 0.2
21 ± 0.8
2 ± 0.5
12.4 +2
-0
less than
18.4
11.9 ~ 15.4
1.0
DS501-00032-3v0-E
MB85RS2MTA
2.4 Taping (254mm Reel) Dry Pack Packing Specifications
Outside diameter: φ 254mm reel
Label I *1, *4
Embossed
tapes
Label I *1, *4
Desiccant
Humidity indicator
Dry pack
Aluminum laminated bag
Label I *1, *4
Heat seal
Inner box
Inner box
Label I *1, *4
Taping
Outer box *2, *3
Outer box
Use adhesive tapes.
Label II-A *4
Label II-B *4
*1: For a product of witch part number is suffixed with “E1”, a “ G
bag and the inner boxes.
Pb
” marks is display to the moisture barrier
*2: The size of the outer box may be changed depending on the quantity of inner boxes.
*3: The space in the outer box will be filled with empty inner boxes, or cushions, etc.
*4: Please refer to an attached sheet about the indication label.
Note: The packing specifications may not be applied when the product is delivered via a distributor.
DS501-00032-3v0-E
31
MB85RS2MTA
2.5 Product label indicators
Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping)
[C-3 Label (50mm 100mm) Supplemental Label (20mm 100mm)]
XXXXXXXXXXXXXX
(Customer part number or FJ part number)
C-3 Label
(3N)1 XXXXXXXXXXXXXX XXX
(LEAD FREE mark)
(Part number and quantity)
QC PASS
(3N)2 XXXXXXXXXX XXXXXX
(FJ control number)
XXX pcs
XXXXXXXXXXXXXX
(Quantity)
(Customer part number or FJ part number)
(Customer part number or FJ part number
bar code)
XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx
XXXXXXXXXXXXXX (Customer part number or FJ part number)
(FJ control number bar code)
XX/XX
XXXX-XXX XXX
(Package count)
XXXX-XXX XXX
XXXXXXXXXX (FJ control number ) (Lot Number and quantity)
XXXXXXXXXXXXXX (Comment)
Perforated line
Supplemental Label
Label II-A: Label on Outer box [D Label] (100mm 100mm)
D Label
XXXXXXXXXXXXX (Customer Name)
(CUST.)
XXXXXXXXX (Delivery Address)
(DELIVERY POINT)
XXXXXXXXXXXXXX
(TRANS.NO.) (FJ control number)
XXXXXXXXXXXXXX
(PART NO.)
(Customer part number or
FJ part number)
XXX (FJ control number)
XXX (FJ control number)
XXX (FJ control number)
XXXXXXXXXXXXXX
(Part number)
(PART NAME) XXXXXXXXXXXXXX (Part number)
XXX/XXX
(Q’TY/TOTAL Q’TY)
(CUSTOMER'S
REMARKS)
XXXXXXXXXXXXXXXXXXXX
(3N)3 XXXXXXXXXXXXXX XXX
XX
(UNIT)
(PACKAGE COUNT)
XXX/XXX
(FJ control number + Product quantity)
(FJ control number + Product quantity
bar code)
(Part number + Product quantity)
(3N)4 XXXXXXXXXXXXXX XXX
(Part number + Product quantity bar code)
(3N)5 XXXXXXXXXX
(FJ control number)
(FJ control number bar code)
Label II-B: Outer boxes product indicate
XXXXXXXXXXXXXX
(Lot Number)
XXXX-XXX
XXXX-XXX
(Part number)
(Count)
X
X
(Quantity)
XXX
XXX
XXX
Note: Depending on shipment state, “Label II-A” and “Label II-B” on the external boxes might not be printed.
32
DS501-00032-3v0-E
MB85RS2MTA
2.6 Dimensions for Containers
(1) Dimensions for inner box
H
W
L
Tape width
L
W
12, 16
24, 32
44
H
40
365
345
56
50
65
75
(Dimensions in mm)
(2) Dimensions for outer box
H
W
L
L
W
H
415
400
315
(Dimensions in mm)
DS501-00032-3v0-E
33
MB85RS2MTA
MAJOR CHANGES IN THIS EDITION
Changes on pages are indicated by vertical lines drawn on the left side of that pages.
Page
Section
Change Results
1
18
25-33
34
FEATURES
Data retention
FRAM CHARACTERISTICS
95 years(+55 C), over 200 years(+35 C)
95 years(+55 C), over 200 years(+35 C)
Data retention
PACKING INFORMATION
FPT-8P-M09
DS501-00032-3v0-E
MB85RS2MTA
FUJITSU SEMICONDUCTOR LIMITED
Shin-Yokohama Chuo Building, 2-100-45 Shin-Yokohama,
Kohoku-ku, Yokohama, Kanagawa 222-0033, Japan
http://jp.fujitsu.com/fsl/en/
All Rights Reserved.
FUJITSU SEMICONDUCTOR LIMITED, its subsidiaries and affiliates (collectively, "FUJITSU SEMICONDUCTOR") reserves
the right to make changes to the information contained in this document without notice. Please contact your FUJITSU
SEMICONDUCTOR sales representatives before order of FUJITSU SEMICONDUCTOR device.
Information contained in this document, such as descriptions of function and application circuit examples is presented solely for
reference to examples of operations and uses of FUJITSU SEMICONDUCTOR device. FUJITSU SEMICONDUCTOR disclaims
any and all warranties of any kind, whether express or implied, related to such information, including, without limitation, quality,
accuracy, performance, proper operation of the device or non-infringement. If you develop equipment or product incorporating the
FUJITSU SEMICONDUCTOR device based on such information, you must assume any responsibility or liability arising out of or
in connection with such information or any use thereof. FUJITSU SEMICONDUCTOR assumes no responsibility or liability for any
damages whatsoever arising out of or in connection with such information or any use thereof.
Nothing contained in this document shall be construed as granting or conferring any right under any patents, copyrights, or any other
intellectual property rights of FUJITSU SEMICONDUCTOR or any third party by license or otherwise, express or implied.
FUJITSU SEMICONDUCTOR assumes no responsibility or liability for any infringement of any intellectual property rights or other
rights of third parties resulting from or in connection with the information contained herein or use thereof.
The products described in this document are designed, developed and manufactured as contemplated for general use including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and
manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high levels of safety is secured,
could lead directly to death, personal injury, severe physical damage or other loss (including, without limitation, use in nuclear
facility, aircraft flight control system, air traffic control system, mass transport control system, medical life support system and
military application), or (2) for use requiring extremely high level of reliability (including, without limitation, submersible repeater
and artificial satellite). FUJITSU SEMICONDUCTOR shall not be liable for you and/or any third party for any claims or damages
arising out of or in connection with above-mentioned uses of the products.
Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs and
safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures into your
facility, equipments and products such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal
operating conditions.
The products and technical information described in this document are subject to the Foreign Exchange and Foreign Trade Control
Law of Japan, and may be subject to export or import laws or regulations in U.S. or other countries. You are responsible for ensuring
compliance with such laws and regulations relating to export or re-export of the products and technical information described herein.
All company names, brand names and trademarks herein are property of their respective owners.
Edited: System Memory Company
Mouser Electronics
Authorized Distributor
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MB85RS2MTAPH-G-JNE2
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