FUJITSU SEMICONDUCTOR
DATA SHEET
DS501-00023-0v01-E
Memory FRAM
2 M (256 K × 8) Bit SPI
MB85RS2MT
■ DESCRIPTION
MB85RS2MT is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 262,144
words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the
nonvolatile memory cells.
MB85RS2MT adopts the Serial Peripheral Interface (SPI).
The MB85RS2MT is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85RS2MT can be used for 1013 read/write operations, which is a significant
improvement over the number of read and write operations supported by Flash memory and E2PROM.
MB85RS2MT does not take long time to write data like Flash memories or E2PROM, and MB85RS2MT takes
no wait time.
■ FEATURES
: 262,144 words × 8 bits
: SPI (Serial Peripheral Interface)
Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)
Operating frequency
: 25 MHz (Max)
For FSTRD command 2.7 V to 3.6 V, 40 MHz (Max)
High endurance
: 1013 times / byte
Data retention
: 10 years (+85 °C)
Operating power supply voltage : 1.8 V to 3.6 V
Low power consumption
: Operating power supply current 10.6 mA (Max@25 MHz) (TBD)
Standby current 150 μA (Max) (TBD)
Sleep current 10 μA (Max) (TBD)
Operation ambient temperature range : -40 °C to +85 °C
Package
: 8-pin plastic SOP (FPT-8P-M08)
8-pin plastic DIP (DIP-8P-M03)
RoHS compliant
• Bit configuration
• Serial Peripheral Interface
•
•
•
•
•
•
•
Copyright©2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2013.3
MB85RS2MT
■ PIN ASSIGNMENT
(TOP VIEW)
CS
1
8
7
2
SO
(TOP VIEW)
VDD
CS
1
8
VDD
SO
2
7
HOLD
WP
3
6
SCK
VSS
4
5
SI
HOLD
WP
3
6
SCK
VSS
4
5
SI
(DIP-8P-M03)
(FPT-8P-M08)
■ PIN FUNCTIONAL DESCRIPTIONS
Pin No. Pin Name
CS
Chip Select pin
This is an input pin to make chips select. When CS is “H” level, device is in deselect
(standby) status and SO becomes High-Z. Inputs from other pins are ignored for this
time. When CS is “L” level, device is in select (active) status. CS has to be “L” level before
inputting op-code.
WP
Write Protect pin
This is a pin to control writing to a status register. The writing of status register (see “■
STATUS REGISTER”) is protected in related with WP and WPEN. See “■ WRITING
PROTECT” for detail.
7
HOLD
Hold pin
This pin is used to interrupt serial input/output without making chips deselect. When
HOLD is “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become
do not care. While the hold operation, CS has to be retained “L” level.
6
SCK
Serial Clock pin
This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising
edge, SO is output synchronously to a falling edge.
5
SI
Serial Data Input pin
This is an input pin of serial data. This inputs op-code, address, and writing data.
2
SO
Serial Data Output pin
This is an output pin of serial data. Reading data of FRAM memory cell array and status
register data are output. This is High-Z during standby.
8
VDD
Supply Voltage pin
4
VSS
Ground pin
1
3
2
Functional description
DS501-00023-0v01-E
MB85RS2MT
■ BLOCK DIAGRAM
Control Circuit
CS
SCK
HOLD
Row Decoder
Serial-Parallel Converter
Address Counter
SI
FRAM Cell Array
262,144 ✕ 8
FRAM
Status Register
Column Decoder/Sense Amp/
Write Amp
WP
Data Register
SO
Parallel-Serial Converter
DS501-00023-0v01-E
3
MB85RS2MT
■ SPI MODE
MB85RS2MT corresponds to the SPI mode 0 (CPOL = 0, CPHA = 0) , and SPI mode 3 (CPOL = 1, CPHA = 1) .
CS
SCK
SI
7
6
5
MSB
4
3
2
1
0
LSB
SPI Mode 0
CS
SCK
SI
7
6
5
4
MSB
3
2
1
0
LSB
SPI Mode 3
4
DS501-00023-0v01-E
MB85RS2MT
■ SERIAL PERIPHERAL INTERFACE (SPI)
MB85RS2MT works as a slave of SPI. More than 2 devices can be connected by using microcontroller
equipped with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus
connected to use.
SCK
MOSI
MISO
SO
SPI
Microcontroller
SI
SO
SCK
SCK
MB85RS2MT
MB85RS2MT
CS
SI
CS
HOLD
HOLD
SS1
SS2
HOLD1
HOLD2
MOSI : Master Out Slave In
MISO : Master In Slave Out
SS
: Slave Select
System Configuration with SPI Port
SO
SI
SCK
Microcontroller
MB85RS2MT
CS
HOLD
System Configuration without SPI Port
DS501-00023-0v01-E
5
MB85RS2MT
■ STATUS REGISTER
Bit No.
Bit Name
Function
WPEN
Status Register Write Protect
This is a bit composed of nonvolatile memories (FRAM). WPEN protects
writing to a status register (refer to “■ WRITING PROTECT”) relating with
WP input. Writing with the WRSR command and reading with the RDSR
command are possible.
6 to 4
⎯
Not Used Bits
These are bits composed of nonvolatile memories, writing with the WRSR
command is possible. These bits are not used but they are read with the
RDSR command.
3
BP1
2
BP0
7
1
WEL
0
0
Block Protect
This is a bit composed of nonvolatile memory. This defines size of write
protect block for the WRITE command (refer to “■ BLOCK PROTECT”).
Writing with the WRSR command and reading with the RDSR command
are possible.
Write Enable Latch
This indicates FRAM Array and status register are writable. The WREN
command is for setting, and the WRDI command is for resetting. With the
RDSR command, reading is possible but writing is not possible with the
WRSR command. WEL is reset after the following operations.
After power ON.
After WRDI command recognition.
The rising edge of CS after WRSR command recognition.
The rising edge of CS after WRITE command recognition.
This is a bit fixed to “0”.
■ OP-CODE
MB85RS2MT accepts 9 kinds of command specified in op-code. Op-code is a code composed of 8 bits
shown in the table below. Do not input invalid codes other than those codes. If CS is risen while inputting
op-code, the command are not performed.
Name
Description
Op-code
WREN
Set Write Enable Latch
0000 0110B
WRDI
Reset Write Enable Latch
0000 0100B
RDSR
Read Status Register
0000 0101B
WRSR
Write Status Register
0000 0001B
READ
Read Memory Code
0000 0011B
WRITE
Write Memory Code
0000 0010B
Read Device ID
1001 1111B
FSTRD
Fast Read Memory Code
0000 1011B
SLEEP
Sleep Mode
1011 1001B
RDID
6
DS501-00023-0v01-E
MB85RS2MT
■ COMMAND
• WREN
The WREN command sets WEL (Write Enable Latch) . WEL has to be set with the WREN command before
writing operation (WRSR command and WRITE command) . WREN command is applicable to “Up to
25 MHz operation”.
CS
0
1
2
3
4
5
6
7
SCK
SI
Invalid
0
0
0
0
0
1
1
Invalid
0
High-Z
SO
• WRDI
The WRDI command resets WEL (Write Enable Latch) . Writing operation (WRSR command and WRITE
command) are not performed when WEL is reset. WRDI command is applicable to “Up to 25 MHz operation”.
CS
0
1
2
3
4
5
6
7
SCK
SI
Invalid
SO
DS501-00023-0v01-E
0
0
0
0
0
1
0
0
Invalid
High-Z
7
MB85RS2MT
• RDSR
The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input
to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. In the
RDSR command, repeated reading of status register is enabled by sending SCK continuously before rising
of CS. RDSR command is applicable to “Up to 25 MHz operation”.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
Invalid
1
Data Out
High-Z
SO
Invalid
MSB
LSB
• WRSR
The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR
op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR
command. A SI value correspondent to bit 1 is ignored. Bit 0 of the status register is fixed to “0” and cannot
be written. The SI value corresponding to bit 0 is ignored. WP signal level shall be fixed before performing
WRSR command, and do not change the WP signal level until the end of command sequence. WRSR
command is applicable to “Up to 25 MHz operation”.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Data In
Instruction
SI
SO
8
0
0
0
0
0
0
0
1
7
MSB
High-Z
6
5
4
3
2
1
0
LSB
DS501-00023-0v01-E
MB85RS2MT
• READ
The READ command reads FRAM memory cell array data. Arbitrary 24 bits address and op-code of READ
are input to SI. The 6-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output
synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ
command is completed, but keeps on reading with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant
address, it rolls over to the starting address, and reading cycle keeps on infinitely. READ command is
applicable to “Up to 25 MHz operation”.
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
24-bit Address
OP-CODE
Invalid
5 4 3 2 1 0
0 0 0 0 0 0 1 1 X X X X X X 17 16
Data Out
MSB
LSB MSB
LSB
High-Z
7 6 5 4 3 2 1 0
SI
SO
Invalid
• WRITE
The WRITE command writes data to FRAM memory cell array. WRITE op-code, arbitrary 24 bits of address
and 8 bits of writing data are input to SI. The 6-bit upper address bit is invalid. When 8 bits of writing data is
input, data is written to FRAM memory cell array. Risen CS will terminate the WRITE command, but if you
continue sending the writing data for 8 bits each before CS rising, it is possible to continue writing with
automatic address increment. When it reaches the most significant address, it rolls over to the starting
address, and writing cycle can be continued infinitely. WRITE command is applicable to “Up to 25 MHz
operation”.
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
SI
Data In
24-bit Address
OP-CODE
0 0 0 0 0 0 1 0 X X X X X X 17 16
5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB
SO
DS501-00023-0v01-E
High-Z
LSB MSB
LSB
9
MB85RS2MT
• FSTRD
The FSTRD command reads FRAM memory cell array data. Arbitrary 24 bits address and op-code of FSTRD
are input to SI followed by 8 bits dummy. The 6-bit upper address bit is invalid. Then, 8-cycle clock is input
to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When
CS is risen, the FSTRD command is completed, but keeps on reading with automatic address increment
which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches
the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely. FSTRD
command is applicable to “Up to 25 MHz (1.8 V to 2.7 V) and 40 MHz (2.7 V to 3.6 V) operation”.
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 1415
29 30 31 32 33
38 39 40 41 42 43 44 45 46 47
24-bit Address
OP-CODE
0 0 0 0 1 0 1 1 X X X X X X 17 16
8-bit Dummy
X X
2 1 0 X X
SCK
SI
MSB
LSB
High-Z
SO
Invalid
MSB
Data Out LSB
7 6 5 4 3 2 1 0
Invalid
• RDID
The RDID command reads fixed Device ID. After performing RDID op-code to SI, 32-cycle clock is input to
SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. The output
is in order of Manufacturer ID (8bit)/Continuation code (8bit)/Product ID (1st Byte)/Product ID (2nd Byte).
In the RDID command, SO holds the output state of the last bit after 32-bit Device ID output by continuously
sending SCK clock before CS is risen. RDID command is applicable to “Up to 25 MHz operation”.
CS
0
1
2
3
4
5
6
7
1
0
0
1
1
1
1
1
8
31 32 33 34 35 36 37 38 39
9 10 11
SCK
SI
Invalid
Data Out
SO
High-Z
Data Out
8
31 30 29 28
7
6
5
4
3
2
MSB
1
0
LSB
bit
Manufacturer ID
Continuation code
Product ID (1st Byte)
Product ID (2nd Byte)
10
7
0
0
6
0
1
5
0
1
Proprietary use
0
0
1
0
0
0
4
0
1
3
0
1
2
1
1
0
Density
1
0
0
Proprietary use
0
0
0
1
0
1
1
0
0
1
Hex
04H Fujitsu
7FH
0
Hex
28H Density: 01000B = 2 Mbit
1
Hex
03H
DS501-00023-0v01-E
MB85RS2MT
• SLEEP
The SLEEP command shifts the LSI to a low power mode called “SLEEP mode”. The transition to the SLEEP
mode is carried out at the rising edge of CS after operation code in the SLEEP command. However, when
at least one SCK clock is inputted before the rising edge of CS after operation code in the SLEEP command,
this SLEEP command is canceled.
After the SLEEP mode transition, SCK and SI inputs are ignored and SO changes to a Hi-Z state.
Enter Sleep Mode
CS
0
1
2
3
4
5
6
7
1
0
1
1
1
0
0
1 Invalid
SCK
SI Invalid
Hi-Z
SO
Sleep Mode Entry
Returning to an normal operation from the SLEEP mode is carried out after tREC (Max 400 μs) time from the
falling edge of CS (see the figure below). It is possible to return CS to H level before tREC time. However, it
is prohibited to bring down CS to L level again during tREC period.
CS
CS
tREC
From this time
Command input enable
Exit Sleep Mode
Sleep Mode Exit
DS501-00023-0v01-E
11
MB85RS2MT
■ BLOCK PROTECT
Writing protect block for WRITE command is configured by the value of BP0 and BP1 in the status register.
BP1
BP0
Protected Block
0
0
None
0
1
30000H to 3FFFFH (upper 1/4)
1
0
20000H to 3FFFFH (upper 1/2)
1
1
00000H to 3FFFFH (all)
■ WRITING PROTECT
Writing operation of the WRITE command and the WRSR command are protected with the value of WEL,
WPEN, WP as shown in the table.
WEL
WPEN
WP
Protected Blocks
Unprotected Blocks
Status Register
0
X
X
Protected
Protected
Protected
1
0
X
Protected
Unprotected
Unprotected
1
1
0
Protected
Unprotected
Protected
1
1
1
Protected
Unprotected
Unprotected
■ HOLD OPERATION
Hold status is retained without aborting a command if HOLD is “L” level while CS is “L” level. The timing for
starting and ending hold status depends on the SCK to be “H” level or “L” level when a HOLD pin input is
transited to the hold condition as shown in the diagram below. In case the HOLD pin transited to “L” level
when SCK is “L” level, return the HOLD pin to “H” level at SCK being “L” level. In the same manner, in case
the HOLD pin transited to “L” level when SCK is “H” level, return the HOLD pin to “H” level at SCK being “H”
level. Arbitrary command operation is interrupted in hold status, SCK and SI inputs become do not care.
And, SO becomes High-Z while reading command (RDSR, READ). If CS is rising during hold status, a
command is aborted. In case the command is aborted before its recognition, WEL holds the value before
transition to hold status.
CS
SCK
HOLD
Hold Condition
12
Hold Condition
DS501-00023-0v01-E
MB85RS2MT
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Min
Max
Unit
Power supply voltage*
VDD
− 0.5
+ 4.0
V
Input voltage*
VIN
− 0.5
VDD + 0.5
V
VOUT
− 0.5
VDD + 0.5
V
TA
− 40
+ 85
°C
Tstg
− 55
+ 125
°C
Output voltage*
Operation ambient temperature
Storage temperature
*:These parameters are based on the condition that VSS is 0 V.
WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without
limitation, voltage, current or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Min
Typ
Max
Unit
Power supply voltage*
VDD
1.8
3.3
3.6
V
Input high voltage*
VIH
VDD × 0.7
⎯
VDD + 0.5
V
Input low voltage*
VIL
− 0.5
⎯
VDD × 0.3
V
Operation ambient temperature
TA
− 40
⎯
+ 85
°C
*:These parameters are based on the condition that VSS is 0 V.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of
device and could result in device failure.
No warranty is made with respect to any use, operating conditions or combinations not represented
on this data sheet. If you are considering application under any conditions other than listed herein,
please contact sales representatives beforehand.
DS501-00023-0v01-E
13
MB85RS2MT
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(within recommended operating conditions)
Parameter
Input leakage current*1
Symbol
Condition
|ILI|
Value(TBD)
Min
Typ
Max
0 ≤ CS< VDD
⎯
⎯
200
CS = VDD
⎯
⎯
1
WP, HOLD, SCK
SI = 0 V to VDD
⎯
⎯
1
Unit
μA
Output leakage current*2
|ILO|
SO = 0 V to VDD
⎯
⎯
1
μA
Operating power supply current
IDD
SCK = 25 MHz
⎯
⎯
10.6
mA
Standby current
ISB
All inputs VSS or
SCK = SI = CS = VDD
⎯
35
150
μA
Sleep current
IZZ
CS = VDD
All inputs VSS or VDD
⎯
⎯
10
μA
Output high voltage
VOH
IOH = − 2 mA
VDD − 0.5
⎯
⎯
V
Output low voltage
VOL
IOL = 2 mA
⎯
⎯
0.4
V
*1 : Applicable pin : CS, WP, HOLD, SCK, SI
*2 : Applicable pin : SO
14
DS501-00023-0v01-E
MB85RS2MT
2. AC Characteristics
Value (TBD)
Parameter
Symbol
Up to 25 MHz operation*
VDD = 1.8 V to 2.7 V
VDD = 2.7 V to 3.6 V
Min
Max
Min
Max
Unit
SCK clock frequency
(All commands except
FSTRD command)
fCK
0
25
0
25
MHz
SCK clock frequency
(for FSTRD command)
fCK
0
25
0
40
MHz
Clock high time
tCH
15
⎯
11
⎯
ns
Clock low time
tCL
15
⎯
11
⎯
ns
Chip select set up time
tCSU
10
⎯
10
⎯
ns
Chip select hold time
tCSH
10
⎯
10
⎯
ns
Output disable time
tOD
⎯
12
-
12
ns
Output data valid time
tODV
⎯
18
-
9
ns
Output hold time
tOH
0
⎯
0
⎯
ns
Deselect time
tD
40
⎯
40
⎯
ns
Data in rising time
tR
⎯
50
-
50
ns
Data falling time
tF
⎯
50
-
50
ns
Data set up time
tSU
5
⎯
5
⎯
ns
Data hold time
tH
5
⎯
5
⎯
ns
HOLD set uptime
tHS
10
⎯
10
⎯
ns
HOLD hold time
tHH
10
⎯
10
⎯
ns
HOLD output floating time
tHZ
⎯
20
⎯
20
ns
HOLD output active time
tLZ
⎯
20
⎯
20
ns
SLEEP recovery time
tREC
⎯
400
⎯
400
μs
* : All commands except FSTRD are applicable to “Up to 25 MHz operation”.
AC Test Condition
Power supply voltage
: 1.8 V to 3.6 V
Operation ambient temperature : − 40 °C to + 85 °C
Input voltage magnitude
: VDD × 0.7 ≤ VIH ≤ VDD
0 ≤ VIL ≤ VDD × 0.3
Input rising time
: 5 ns
Input falling time
: 5 ns
Input judge level
: VDD/2
Output judge level
: VDD/2
DS501-00023-0v01-E
15
MB85RS2MT
AC Load Equivalent Circuit
3.3 V
1.2 k
Output
30 pF
0.95 k
3. Pin Capacitance
Parameter
Symbol
Condition
Output capacitance
CO
Input capacitance
CI
VDD = VIN = VOUT = 0 V,
f = 1 MHz, TA = +25 °C
16
Value
Unit
Min
Max
⎯
6
pF
⎯
8
pF
DS501-00023-0v01-E
MB85RS2MT
■ TIMING DIAGRAM
• Serial Data Timing
tD
CS
tCSH
tCSU
tCH
tCL
tCH
SCK
tSU
tH
Valid in
SI
tODV
SO
tOH
tOD
High-Z
High-Z
: H or L
• Hold Timing
CS
SCK
tHS
tHH
tHS
tHS
tHH
tHS
tHH
tHH
HOLD
High-Z
SO
tHZ
DS501-00023-0v01-E
tLZ
High-Z
tHZ
tLZ
17
MB85RS2MT
■ POWER ON/OFF SEQUENCE
tpd
tf
tr
tpu
VDD
VDD
3.0 V
3.0 V
VIH (Min)
VIH (Min)
1.0 V
1.0 V
VIL (Max)
VIL (Max)
GND
GND
CS >VDD × 0.8*
CS
CS >VDD × 0.8*
CS : do not care
CS
* : CS (Max) < VDD + 0.5 V
Parameter
Symbol
Value
Min
Max
Unit
CS level hold time at power OFF
tpd
0
⎯
ns
CS level hold time at power ON
tpu
250
⎯
ns
Power supply rising time
tr
0.05
⎯
ms/V
Power supply falling time
tf
0.1
⎯
ms/V
If the device does not operate within the specified conditions of read cycle, write cycle or power on/off
sequence, memory data can not be guaranteed.
■ FRAM CHARACTERISTICS
Parameter
Read/Write Endurance
Data Retention
Value
Unit
Remarks
⎯
Times/byte
Operation Ambient Temperature TA = + 85 °C
Total numbers of reading and writing
⎯
Years
Operation Ambient Temperature TA = + 85 °C
Retention time of the first reading/writing data
right after shipment
Min
Max
1013
10
Note : Total number of reading and writing defines the minimum value of endurance, as an FRAM memory
operates with destructive readout mechanism.
■ NOTE ON USE
We recommend programming of the device after reflow. Data written before reflow cannot be guaranteed.
18
DS501-00023-0v01-E
MB85RS2MT
■ ESD AND LATCH-UP
Test
DUT
Value
ESD HBM (Human Body Model)
JESD22-A114 compliant
⎯
ESD MM (Machine Model)
JESD22-A115 compliant
⎯
ESD CDM (Charged Device Model)
JESD22-C101 compliant
⎯
Latch-Up (I-test)
JESD78 compliant
MB85RS2MTPF-G-JNE2
MB85RS2MTPH-G-JNE1
⎯
Latch-Up (Vsupply overvoltage test)
JESD78 compliant
⎯
Latch-Up (Current Method)
Proprietary method
⎯
Latch-Up (C-V Method)
Proprietary method
⎯
• Current method of Latch-Up Resistance Test
Protection Resistance
A
Test terminal
IIN
VIN
VDD
+
DUT
-
VSS
VDD
(Max.Rating)
V
Reference
terminal
Note : The voltage VIN is increased gradually and the current IIN of 300 mA at maximum shall flow.
Confirm the latch up does not occur under IIN = ± 300 mA.
In case the specific requirement is specified for I/O and IIN cannot be 300 mA, the voltage shall be
increased to the level that meets the specific requirement.
DS501-00023-0v01-E
19
MB85RS2MT
• C-V method of Latch-Up Resistance Test
Protection Resistance
A
1
Test
2 terminal
SW
+
VIN
V
-
C
200pF
VDD
DUT
VDD
(Max.Rating)
VSS
Reference
terminal
Note : Charge voltage alternately switching 1 and 2 approximately 2 sec interval. This switching process is
considered as one cycle. Repeat this process 5 times. However, if the latch-up condition occurs before
completing 5times, this test must be stopped immediately.
20
DS501-00023-0v01-E
MB85RS2MT
■ MB85RS2MTPF (8-pin plastic SOP) REFLOW CONDITIONS AND FLOOR LIFE
Item
Condition
Method
IR (infrared reflow) , Convection
Times
2
Before unpacking
Please use within 2 years after production.
From unpacking to 2nd reflow
Within 8 days
In case over period of floor life
Baking with 125 °C+/-3 °C for
24hrs+2hrs/-0hrs is required.
Then please use within 8 days.
(Please remember baking is up to 2 times)
Floor life
Floor life condition
Between 5 °C and 30 °C and also below 70%RH required.
(It is preferred lower humidity in the required temp range.)
Reflow Profile
260°C
255°C
Liquidous
Temperature
170 °C
to
190 °C
(b)
RT
(c)
(a)
(a) Average ramp-up rate
(b) Preheat & Soak
(c) Average ramp-up rate
(d) Peak temperature
(d’) Liquidous temperature
(e) Cooling
(d)
(e)
(d')
: 1 °C/s to 4 °C/s
: 170 °C to 190 °C, 60 s to 180 s
: 1 °C/s to 4 °C/s
: Temperature 260 °C Max; 255 °C within 10 s
: Up to 230 °C within 40 s or
Up to 225 °C within 60 s or
Up to 220 °C within 80 s
: Natural cooling or forced cooling
Note : Temperature on the top of the package body is measured.
DS501-00023-0v01-E
21
MB85RS2MT
■ RESTRICTED SUBSTANCES
This product complies with the regulation below (Based on current knowledge as of November 2011).
• EU RoHS Directive (2002/95/EC)
• China RoHS (Administration on the Control of Pollution Caused by Electronic Information Products
(
))
• Vietnam RoHS (30/2011/TT-BCT)
Restricted substances in each regulation are as follows.
Substances
Threshold
Contain status*
Lead and its compounds
1,000 ppm
❍
Mercury and its compounds
1,000 ppm
❍
100 ppm
❍
Hexavalent chromium compound
1,000 ppm
❍
Polybrominated biphenyls (PBB)
1,000 ppm
❍
Polybrominated diphenyl ethers (PBDE)
1,000 ppm
❍
Cadmium and its compounds
* : The mark of “❍” shows below a threshold value.
22
DS501-00023-0v01-E
MB85RS2MT
■ ORDERING INFORMATION
Package
Shipping form
Minimum shipping
quantity
MB85RS2MTPF-G-JNE2
8-pin plastic SOP
(FPT-8P-M08)
Tube
1
MB85RS2MTPF-G-JNERE2
8-pin plastic SOP
(FPT-8P-M08)
Embossed Carrier tape
2000
MB85RS2MTPH-G-JNE1
8-pin plastic DIP
(DIP-8P-M03)
Tube
1
Part number
DS501-00023-0v01-E
23
MB85RS2MT
■ PACKAGE DIMENSION
8-pin plastic SOP
Lead pitch
1.27 mm
Package width ×
package length
5.30 mm × 5.24 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
2.10 mm Max
(FPT-8P-M08)
8-pin plastic SOP
(FPT-8P-M08)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) # : These dimensions do not include resin protrusion.
#5.24±0.10
(.206±.004)
8
5
"A"
BTM E-MARK
#5.30±0.10
(.209±.004)
INDEX
7.80
.307
+0.45
–0.10
+.018
–.004
Details of "A" part
2.10(.083)
MAX
(Mounting height)
1
1.27(.050)
4
0.43±0.05
(.017±.002)
0.20±0.05
(.008±.002)
0~8°
+0.15
0.10 –0.05
+.006
–.002
.004
(Stand off)
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED F08016S-c-1-2
+0.10
0.75 –0.20
+.004
.030 –.008
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
24
DS501-00023-0v01-E
MB85RS2MT
(Continued)
8-pin plastic DIP
Lead pitch
2.54 mm
Sealing method
Plastic mold
(DIP-8P-M03)
8-pin plastic DIP
(DIP-8P-M03)
9.40
.370
8
+0.40
–0.30
+.016
–.012
5
INDEX
6.35±0.25
(.250±.010)
1
4
7.62(.300)
TYP.
4.36(.172)MAX
0.50(.020)
MIN
0.25±0.05
(.010±.002)
3.00(.118)MIN
+0.35
0.46±0.08
(.018±.003)
0.89 –0.30
+.014
.035 –.012
+0.30
0.99 –0
.039
C
+.012
–0
+0.30
1.52 –0
15° MAX
+.012
.060 –0
2.54(.100)
TYP.
2006-2010 FUJITSU SEMICONDUCTOR LIMITED D08008S-c-1-4
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS501-00023-0v01-E
25
MB85RS2MT
■ MARKING
[MB85RS2MTPF-G-JNE2]
[MB85RS2MTPF-G-JNERE2]
RS2MT
E21300
300
[FPT-08P-M08]
[MB85RS2MTPH-G-JNE1]
RS2MT
E11300
300
[DIP-08P-M03]
26
DS501-00023-0v01-E
MB85RS2MT
MEMO
DS501-00023-0v01-E
27
MB85RS2MT
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
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FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
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#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://sg.fujitsu.com/semiconductor/
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Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
30F, Kerry Parkside, 1155 Fang Dian Road, Pudong District,
Shanghai 201204, China
Tel : +86-21-6146-3688 Fax : +86-21-6146-3660
http://cn.fujitsu.com/fss/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
902 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fsk/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
2/F, Green 18 Building, Hong Kong Science Park,
Shatin, N.T., Hong Kong
Tel : +852-2736-3232 Fax : +852-2314-4207
http://cn.fujitsu.com/fsp/
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FUJITSU SEMICONDUCTOR LIMITED, its subsidiaries and affiliates (collectively, "FUJITSU SEMICONDUCTOR") reserves
the right to make changes to the information contained in this document without notice. Please contact your FUJITSU
SEMICONDUCTOR sales representatives before order of FUJITSU SEMICONDUCTOR device.
Information contained in this document, such as descriptions of function and application circuit examples is presented solely for
reference to examples of operations and uses of FUJITSU SEMICONDUCTOR device. FUJITSU SEMICONDUCTOR disclaims
any and all warranties of any kind, whether express or implied, related to such information, including, without limitation, quality,
accuracy, performance, proper operation of the device or non-infringement. If you develop equipment or product incorporating the
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The products described in this document are designed, developed and manufactured as contemplated for general use including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and
manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high levels of safety is secured,
could lead directly to death, personal injury, severe physical damage or other loss (including, without limitation, use in nuclear
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and artificial satellite). FUJITSU SEMICONDUCTOR shall not be liable for you and/or any third party for any claims or damages
arising out of or in connection with above-mentioned uses of the products.
Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs and
safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures into your
facility, equipments and products such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal
operating conditions.
The products and technical information described in this document are subject to the Foreign Exchange and Foreign Trade Control
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