MB85RS64PNF-G-JNE1

FUJITSU SEMICONDUCTOR DATA SHEET DS501-00012-0v01-E Memory FRAM 64 K (8 K  8) Bit SPI MB85RS64 ■ DESCRIPTION MB85RS64 is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 8,192 words  8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. MB85RS64 adopts the Serial Peripheral Interface (SPI). The MB85RS64 is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MB85RS64 can be used for 1010 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM. MB85RS64 does not take long time to write data unlike Flash memories nor E2PROM, and MB85RS64 takes no wait time. ■ FEATURES : 8,192 words  8 bits : SPI (Serial Peripheral Interface) Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1) Operating frequency : 20 MHz (Max) High endurance : 10 Billion Read/writes Data retention : 10 years (+85 C) Operating power supply voltage : 2.7 V to 3.6 V Low power consumption : Operating power supply current 1.5(TBD)mA (Typ@20 MHz) Standby current 10 A(TBD) (Typ) Operation ambient temperature range :  40 C to +85 C Package : 8-pin plastic SOP (FPT-8P-M02) RoHS compliant • Bit configuration • Serial Peripheral Interface • • • • • • • Copyright©2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2011.10 MB85RS64 ■ PIN ASSIGNMENT (TOP VIEW) CS 1 8 VDD SO 2 7 HOLD WP 3 6 SCK GND 4 5 SI (FPT-8P-M02) ■ PIN FUNCTIONAL DESCRIPTIONS Pin No. Pin Name 2 Functional description 1 CS Chip Select pin This is an input pin to make chips select. When CS is the “H” level, device is in deselect (standby) status as long as device is not write status internally, and SO becomes HighZ. Inputs from other pins are ignored at this time. When CS is the “L” level, device is in select (active) status. CS has to be the “L” level before inputting op-code. The Chip Select pin is pulled up internally to the VDD pin. 3 WP Write Protect pin This is a pin to control writing to a status register. When WP is the “L” level, writing to a status register is not operated. 7 HOLD Hold pin This pin is used to interrupt serial input/output without making chips deselect. When HOLD is the “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become don’t care. While the hold operation, CS has to be retained the “L” level. 6 SCK Serial Clock pin This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge, SO is output synchronously to a falling edge. 5 SI Serial Data Input pin This is an input pin of serial data. This inputs op-code, address, and writing data. 2 SO Serial Data Output pin This is an output pin of serial data. Reading data of FRAM memory cell array and status register data are output. This is High-Z during standby. 8 VDD Supply Voltage pin 4 GND Ground pin DS501-00012-0v01-E MB85RS64 ■ BLOCK DIAGRAM Control Circuit CS SCK HOLD Row Decoder Serial-Parallel Converter Address Counter SI FRAM Cell Array 8,192 ✕ 8 FRAM Status Register Column Decoder/Sense Amp/ Write Amp WP Data Register SO Parallel-Serial Converter DS501-00012-0v01-E 3 MB85RS64 ■ SPI MODE MB85RS64 corresponds to the SPI mode 0 (CPOL  0, CPHA  0) , and SPI mode 3 (CPOL  1, CPHA  1) . CS SCK SI 7 6 5 MSB 4 3 2 1 0 LSB SPI Mode 0 CS SCK SI 7 6 5 4 MSB 3 2 1 0 LSB SPI Mode 3 4 DS501-00012-0v01-E MB85RS64 ■ SERIAL PERIPHERAL INTERFACE (SPI) MB85RS64 works as a slave of SPI. More than 2 devices can be connected by using microcontroller equipped with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus connected to use. SCK MOSI MISO SO SPI Microcontroller SI SO SCK MB85RS64 CS SI SCK MB85RS64 CS HOLD HOLD SS1 SS2 HOLD1 HOLD2 MOSI : Master Out Slave In MISO : Master In Slave Out SS : Slave Select System Configuration with SPI Port SO SI SCK Microcontroller MB85RS64 CS HOLD System Configuration without SPI Port DS501-00012-0v01-E 5 MB85RS64 ■ STATUS REGISTER Bit No. Bit Name Function WPEN Status Register Write Protect This is a bit composed of nonvolatile memories (FRAM). WPEN protects writing to a status register (see “■ WRITING PROTECT”) relating with WP input. Writing with the WRSR command and reading with the RDSR command are possible. 6 to 4  Not Used Bits These are bits composed of nonvolatile memories, writing with the WRSR command is possible, and “000” is written before shipment. These bits are not used but they are read with the RDSR command. 3 BP1 2 BP0 7 1 WEL 0 0 Block Protect This is a bit composed of nonvolatile memory. This defines block size for writing protect with the WRITE command (see “■ BLOCK PROTECT”). Writing with the WRSR command and reading with the RDSR command are possible. Write Enable Latch This indicates FRAM Array and status register are writable. The WREN command is for setting, and the WRDI command is for resetting. With the RDSR command, reading is possible but writing is not possible with the WRSR command. WEL is reset after the following operations. The time when power is up. The time when the WRDI command is input. The time when the WRSR command is input. The time when the WRITE command is input. This is a bit fixed to “0”. ■ OP-CODE MB85RS64 accepts 6 kinds of command specified in op-code. Op-code is a code composed of 8 bits shown in the table below. Do not input invalid codes other than those codes. If CS is risen while inputting op-code, the command are not performed. Name Description Op-code 6 WREN Set Write Enable Latch 0000 0110B WRDI Reset Write Enable Latch 0000 0100B RDSR Read Status Register 0000 0101B WRSR Write Status Register 0000 0001B READ Read Memory Code 0000 0011B WRITE Write Memory Code 0000 0010B DS501-00012-0v01-E MB85RS64 ■ COMMAND  WREN The WREN command sets WEL (Write Enable Latch) . WEL has to be set with the WREN command before writing operation (WRSR command and WRITE command) . CS 0 1 2 3 4 5 6 7 SCK SI Invalid 0 0 0 0 0 1 1 Invalid 0 High-Z SO  WRDI The WRDI command resets WEL (Write Enable Latch) . Writing operation (WRITE command and WRSR command) are not performed when WEL is reset. CS 0 1 2 3 4 5 6 7 SCK SI Invalid SO DS501-00012-0v01-E 0 0 0 0 0 1 0 0 Invalid High-Z 7 MB85RS64  RDSR The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. Continuously reading status register is enabled by keep on sending SCK before rising CS with the RDSR command. CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 0 Invalid 1 Data Out High-Z SO Invalid LSB MSB  WRSR The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR command. A SI value correspondent to bit 1 is ignored. Bit 0 of the status register is fixed to “0” and cannot be written. The SI value corresponding to bit 0 is ignored. the WP signal level shall be fixed before performing the WRSR command, and do not change the WP signal level until the end of command sequence. CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK Data In Instruction SI SO 8 0 0 0 0 0 0 0 1 7 MSB High-Z 6 5 4 3 2 1 0 LSB DS501-00012-0v01-E MB85RS64  READ The READ command reads FRAM memory cell array data. Arbitrary 16 bits address and op-code of READ are input to SI. The 3-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ command is completed, but keeps on reading with automatic address increment which is enabled by continuously sending clock for 8 cycles each to SCK before CS is risen. When it reaches the most significant address, it rolls over to come back to the starting address, and reading cycle keeps on infinitely. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCK SI SO 16-bit Address OP-CODE 0 0 0 0 0 0 1 1 X X X 12 11 10 5 4 MSB High-Z 3 2 1 Invalid 0 LSB MSB 7 6 Data Out 5 4 3 2 1 LSB 0 Invalid  WRITE The WRITE command writes data to FRAM memory cell array. WRITE op-code, arbitrary 16 bits of address and 8 bits of writing data are input to SI. The most significant address bit is invalid. When 8 bits of writing data is input, data is written to FRAM memory cell array. Risen CS will terminate the WRITE command, but if you continue sending the writing data for 8 bits each before CS is risen, it is possible to continue writing with automatic address increment. When it reaches the most significant address, it rolls over, comes back to the starting address, and writing cycle can be continued infinitely. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCK SI SO 16-bit Address OP-CODE 0 0 0 0 0 0 1 0 X X X 12 11 10 5 4 MSB High-Z DS501-00012-0v01-E Data In 3 2 1 0 7 6 LSB MSB 5 4 3 2 1 0 LSB 9 MB85RS64 ■ BLOCK PROTECT Writing protect block is configured by the WRITE command with BP1, BP0 value of the status register. BP1 BP0 Protected Block 0 0 None 0 1 1800H to 1FFFH (upper 1/4) 1 0 1000H to 1FFFH (upper 1/2) 1 1 0000H to 1FFFH (all) ■ WRITING PROTECT Writing operation of the WRITE command and the WRSR command are protected with the value of WEL, WPEN, WP as shown in the table. Protected Blocks Unprotected Blocks Status Register WEL WPEN WP 0 X X Protected Protected Protected 1 0 X Protected Unprotected Unprotected 1 1 0 Protected Unprotected Protected 1 1 1 Protected Unprotected Unprotected ■ HOLD OPERATION Hold status is retained without aborting a command if HOLD is the “L” level while CS is the “L” level. The timing for starting and ending hold status depends on the SCK to be the “H” level or the “L” level when a HOLD pin input is transited to the hold condition as shown in the diagram below. Arbitrary command operation is interrupted in hold status, SCK and SI inputs become don’t care. And, SO becomes High-Z while reading command (RDSR, READ) . If CS is risen with hold status, a command is aborted and device is reset. CS SCK HOLD Hold Condition 10 Hold Condition DS501-00012-0v01-E MB85RS64 ■ ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Min Max Unit Power supply voltage* VDD  0.5  4.0 V Input voltage* VIN  0.5 VDD  0.5 V VOUT  0.5 VDD  0.5 V TA  40  85 C Tstg  40  125 C Output voltage* Operation ambient temperature Storage temperature *:These parameters are based on the condition that VSS is 0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Min Typ Max Unit Power supply voltage* VDD 2.7 3.3 3.6 V Input high voltage* VIH VDD  0.8  VDD  0.3 V Input low voltage* VIL  0.5  VDD  0.2 V Operation ambient temperature TA  40   85 C *:These parameters are based on the condition that VSS is 0 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. DS501-00012-0v01-E 11 MB85RS64 ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics (within recommended operating conditions) Parameter Symbol Condition Value Min Typ Max CS  0 V to VDD   200 Unit A Input leakage current |ILI| WP, HOLD, SCK, SI  0 V to VDD   10 Output leakage current |ILO| VOUT  0 V to VDD   10 Operating power supply current IDD SCK  20 MHz  1.5 (TBD) 2.0 (TBD) mA Standby current ISB SCK  SI  CS  VDD  10 (TBD) 15 (TBD) A Output high voltage VOH IOH  2 mA VDD  0.5  VDD V Output low voltage VOL IOL  2 mA VSS  0.4 V 12 A DS501-00012-0v01-E MB85RS64 2. AC Characteristics Parameter Symbol Value Min Max Unit SCK clock frequency fCK 0 20 MHz Clock high time tCH 25  ns Clock low time tCL 25  ns Chip select set up time tCSU 10  ns Chip select hold time tCSH 10  ns Output disable time tOD  20 ns Output data valid time tODV  18 ns Output hold time tOH 0  ns Deselect time tD 60  ns Data in rise time tR  50 ns Data fall time tF  50 ns Data set up time tSU 5  ns Data hold time tH 5  ns HOLD set up time tHS 10  ns HOLD hold time tHH 10  ns HOLD output floating time tHZ  20 ns HOLD output active time tLZ  20 ns AC Test Condition Power supply voltage : 2.7 V to 3.6 V Operation ambient temperature :  40 C to  85 C Input voltage magnitude : 0.3 V to 2.7 V Input rising time : 5 ns Input falling time : 5 ns Input judge level : VDD/2 Output judge level : VDD/2 DS501-00012-0v01-E 13 MB85RS64 AC Load Equivalent Circuit 3.3 V 1.2 k Output 30 pF 0.95 k 3. Pin Capacitance Parameter Symbol Conditions Output capacitance CO Input capacitance CI VDD  VIN  VOUT  0 V f  1 MHz, TA   25 C 14 Value Unit Min Max  10 pF  10 pF DS501-00012-0v01-E MB85RS64 ■ TIMING DIAGRAM  Serial Data Timing tD CS tCSH tCSU tCH tCL SCK tSU tH Valid in SI tODV SO tOH tOD High-Z High-Z : H or L  Hold Timing CS SCK tHS tHH tHS tHS tHH tHS tHH tHH HOLD High-Z SO tHZ DS501-00012-0v01-E tLZ High-Z tHZ tLZ 15 MB85RS64 ■ POWER ON/OFF SEQUENCE tpd tf tr tpu VDD VDD 2.7 V 2.7 V VIH (Min) VIH (Min) 1.0 V 1.0 V VIL (Max) VIL (Max) GND GND CS CS >VDD × 0.8 * CS : don't care CS >VDD × 0.8 * CS * : CS (Max) < VDD  0.3 V Note :  Because turning the power-on from an intermediate level may cause malfunctions, when the power is turned on, VDD is required to be started from 0 V.  If the device does not operate within the specified conditions of read cycle, write cycle, power on/ off sequence, memory data can not be guaranteed. Parameter Symbol Value Min Max Unit CS level hold time at power OFF tpd 400  ns CS level hold time at power ON tpu 0.1  ms Power supply falling time tf 100  s/V Power supply rising time tr 30  s/V ■ NOTES ON USE Data written before performing IR reflow is not guaranteed after IR reflow. 16 DS501-00012-0v01-E MB85RS64 ■ ORDERING INFORMATION Package Shipping form Minimum shipping quantity MB85RS64PNF-G-JNE1 8-pin plastic SOP (FPT-8P-M02) Tube 1 MB85RS64PNF-G-JNERE1 8-pin plastic SOP (FPT-8P-M02) Embossed Carrier tape 1500 Part number DS501-00012-0v01-E 17 MB85RS64 ■ PACKAGE DIMENSION 8-pin plastic SOP Lead pitch 1.27 mm Package width × package length 3.9 mm × 5.05 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.75 mm MAX Weight 0.06 g (FPT-8P-M02) 8-pin plastic SOP (FPT-8P-M02) +0.25 Note 1) *1 : These dimensions include resin protrusion. Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. +.010 +0.03 *1 5.05 –0.20 .199 –.008 0.22 –0.07 +.001 .009 –.003 8 5 *2 3.90±0.30 6.00±0.40 (.154±.012) (.236±.016) Details of "A" part 45° 1.55±0.20 (Mounting height) (.061±.008) 0.25(.010) 0.40(.016) 1 "A" 4 1.27(.050) 0.44±0.08 (.017±.003) 0.13(.005) 0~8° M 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.15±0.10 (.006±.004) (Stand off) 0.10(.004) C 2002-2010 FUJITSU SEMICONDUCTOR LIMITED F08004S-c-4-9 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 18 DS501-00012-0v01-E MB85RS64 MEMO DS501-00012-0v01-E 19 MB85RS64 FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://sg.fujitsu.com/semiconductor/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fss/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 902 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fsk/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fsp/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. 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