FUJITSU SEMICONDUCTOR
DATA SHEET
DS501-00052-2v0-E
Memory FRAM
64 K (8 K 8) Bit SPI
MB85RS64TU
DESCRIPTION
MB85RS64TU is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 8,192 words
8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile
memory cells.
MB85RS64TU adopts the Serial Peripheral Interface (SPI).
The MB85RS64TU is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85RS64TU can be used for 1013 read/write operations, which is a significant
improvement over the number of read and write operations supported by Flash memory and E2PROM.
MB85RS64TU does not take long time to write data like Flash memories or E2PROM, and MB85RS64TU
takes no wait time.
MB85RS64TU is suitable for application in extremely cold region, such as flow meter or sensor device and
so forth, with extended operating temperature range.
FEATURES
• Bit configuration : 8,192 words 8 bits
• Serial Peripheral Interface : SPI (Serial Peripheral Interface)
Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)
• Operating frequency : 10 MHz (Max)
• High endurance : 1013 times / byte
• Data retention
: 10 years ( 85 C)
• Operating power supply voltage : 1.8 V to 3.6 V
• Low power consumption : Operating power supply current 0.8 mA (Max@10 MHz)
Standby current 9 A (Typ)
• Operation ambient temperature range : 55 C to +85 C
• Package
: 8-pin plastic SOP (FPT-8P-M02)
8-pin plastic SON (LCC-8P-M04)
RoHS compliant
Copyright 2018FUJITSU SEMICONDUCTOR LIMITED
2018.07
MB85RS64TU
PIN ASSIGNMENT
(TOP VIEW)
(TOP VIEW)
CS
1
8
VDD
SO
2
7
HOLD
CS
1
8
VDD
SO
2
7
HOLD
WP
3
6
SCK
VSS
4
5
SI
DIE PAD
WP
VSS
3
6
4
5
SCK
SI
(LCC-8P-M04)
(FPT-8P-M02)
PIN FUNCTIONAL DESCRIPTIONS
Pin
Name
Functional description
CS
Chip Select pin
This is an input pin to make chip select. When CS is the “H” level, device is in deselect
(standby) status and SO becomes High-Z. Inputs from other pins are ignored at this time.
When CS is the “L” level, device is in select (active) status. CS has to be the “L” level
before inputting op-code.
WP
Write Protect pin
This is a pin to control writing to a status register. The writing of status register (see “
STATUS REGISTER”) is protected in related with WP and WPEN. See “WRITING
PROTECT” for detail.
7
HOLD
Hold pin
This pin is used to interrupt serial input/output without making chip deselect. When
HOLD is the “L” level, hold operation is activated, SO becomes High-Z, and SCK and SI
become don’t care. While the hold operation, CS shall be retained the “L” level.
6
SCK
Serial Clock pin
This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising
edge, SO is output synchronously to a falling edge.
5
SI
Serial Data Input pin
This is an input pin of serial data. This inputs op-code, address, and writing data.
2
SO
Serial Data Output pin
This is an output pin of serial data. Reading data of FRAM memory cell array and status
register are output. This is High-Z during standby.
8
VDD
Supply Voltage pin
4
VSS
Ground pin
DIE PAD
Pin No.
1
3
2
It is allowed for the DIE PAD on the bottom of the SON8 package to be floating (no connection to anything) or to be connected to VSS.
DS501-00052-2v0-E
MB85RS64TU
BLOCK DIAGRAM
Control Circuit
SCK
HOLD
Row Decoder
CS
Address Counter
Serial-Parallel Converter
SI
FRAM Cell Array
8,192 ✕ 8
FRAM
Status Register
Column Decoder/Sense Amp/
Write Amp
WP
Data Register
SO
Parallel-Serial Converter
DS501-00052-2v0-E
3
MB85RS64TU
SPI MODE
MB85RS64TU corresponds to the SPI mode 0 (CPOL 0, CPHA 0) , and SPI mode 3 (CPOL 1, CPHA 1) .
CS
SCK
SI
7
6
5
MSB
4
3
2
1
0
LSB
SPI Mode 0
CS
SCK
SI
7
6
5
4
MSB
3
2
1
0
LSB
SPI Mode 3
4
DS501-00052-2v0-E
MB85RS64TU
SERIAL PERIPHERAL INTERFACE (SPI)
MB85RS64TU works as a slave of SPI. More than 2 devices can be connected by using microcontroller
equipped with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus
connected to use.
SCK
MOSI
MISO
SO
SPI
Microcontroller
SI
SO
SCK
MB85RS64TU
CS
SI
SCK
MB85RS64TU
CS
HOLD
HOLD
SS1
SS2
HOLD1
HOLD2
MOSI : Master Out Slave In
MISO : Master In Slave Out
SS
: Slave Select
System Configuration with SPI Port
SO
SI
SCK
Microcontroller
MB85RS64TU
CS
HOLD
System Configuration without SPI Port
DS501-00052-2v0-E
5
MB85RS64TU
STATUS REGISTER
Bit No.
Bit Name
Function
WPEN
Status Register Write Protect
This is a bit composed of nonvolatile memories (FRAM). WPEN protects
writing to a status register (see “ WRITING PROTECT”) relating with WP
input. Writing with the WRSR command and reading with the RDSR command are possible.
6 to 4
Not Used Bits
These are bits composed of nonvolatile memories, writing with the WRSR
command is possible, and “000” is written before shipment. These bits are
not used but they are read with the RDSR command.
3
BP1
2
BP0
7
1
WEL
0
0
Block Protect
This is a bit composed of nonvolatile memory. This defines size of write
protect block for the WRITE command (see “ BLOCK PROTECT”).
Writing with the WRSR command and reading with the RDSR command
are possible.
Write Enable Latch
This indicates FRAM Array and status register are writable. The WREN
command is for setting, and the WRDI command is for resetting. With the
RDSR command, reading is possible but writing is not possible with the
WRSR command. WEL is reset after the following operations.
After power ON.
After WRDI command recognition.
This is a bit fixed to “0”.
OP-CODE
MB85RS64TU accepts 8 kinds of command specified in op-code. Op-code is a code composed of 8 bits
shown in the table below. Do not input invalid codes other than those codes. If CS is risen while inputting
op-code, the command are not performed.
Name
Description
Op-code
WREN
Set Write Enable Latch
0000 0110B
WRDI
Reset Write Enable Latch
0000 0100B
RDSR
Read Status Register
0000 0101B
WRSR
Write Status Register
0000 0001B
READ
Read Memory Code
0000 0011B
WRITE
Write Memory Code
0000 0010B
Read Device ID
1001 1111B
RDID
SLEEP
RFU
*
6
Sleep Mode
Reserved for future use
1011 1001B
*1
0000 1011B
1:When this command is input, SO output will be unvalued.
DS501-00052-2v0-E
MB85RS64TU
COMMAND
WREN
The WREN command sets WEL (Write Enable Latch) . WEL shall be set with the WREN command before
writing operation (WRSR command and WRITE command) .
CS
0
1
2
3
4
5
6
7
SCK
SI
Invalid
0
0
0
0
0
1
1
Invalid
0
High-Z
SO
WRDI
The WRDI command resets WEL (Write Enable Latch) . Writing operation (WRITE command and WRSR
command) are not performed when WEL is reset.
CS
0
1
2
3
4
5
6
7
SCK
SI
Invalid
SO
DS501-00052-2v0-E
0
0
0
0
0
1
0
0
Invalid
High-Z
7
MB85RS64TU
RDSR
The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input
to SCK. The SI value is invalid during this time. SO is output synchronously to a falling edge of SCK. In the
RDSR command, repeated reading of status register is enabled by sending SCK continuously before rising
of CS.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
Invalid
1
Data Out
High-Z
SO
Invalid
LSB
MSB
WRSR
The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR
op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR
command. A SI value correspondent to bit 1 is ignored. Bit 0 of the status register is fixed to “0” and cannot
be written. The SI value corresponding to bit 0 is ignored. The WP signal level shall be fixed before performing
the WRSR command, and do not change the WP signal level until the end of command sequence.
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Data In
Instruction
SI
SO
8
0
0
0
0
0
0
0
1
7
MSB
High-Z
6
5
4
3
2
1
0
LSB
DS501-00052-2v0-E
MB85RS64TU
READ
The READ command reads FRAM memory cell array data. Arbitrary 16 bits address and op-code of READ
are input to SI. The 3-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output
synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ
command is completed, but keeps on reading with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant
address, it rolls over to the starting address, and reading cycle keeps on infinitely.
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13
18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK
SI
SO
16-bit Address
OP-CODE
0 0 0 0 0 0 1 1 X X X 12 11 10
5 4
MSB
High-Z
3
2
1
Invalid
0
LSB MSB
7
6
Data Out
5
4
3
2
1
LSB
0
Invalid
WRITE
The WRITE command writes data to FRAM memory cell array. WRITE op-code, arbitrary 16 bits of address
and 8 bits of writing data are input to SI. The 3-bit upper address bit is invalid. When 8 bits of writing data is
input, data is written to FRAM memory cell array. Risen CS will terminate the WRITE command. However,
if you continue sending the writing data for 8 bits each before CS rising, it is possible to continue writing with
automatic address increment. When it reaches the most significant address, it rolls over to the starting
address, and writing cycle keeps on continued infinitely.
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13
18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK
SI
SO
16-bit Address
OP-CODE
0 0 0 0 0 0 1 0 X X X 12 11 10
5 4
MSB
High-Z
DS501-00052-2v0-E
Data In
3
2
1
0
7
6
LSB MSB
5
4
3
2
1
0
LSB
9
MB85RS64TU
RDID
The RDID command reads fixed Device ID. After performing RDID op-code to SI, 32-cycle clock is input
to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. The output
is in order of Manufacturer ID (8bit)/Continuation code (8bit)/Product ID (1st Byte)/Product ID (2nd Byte).
In the RDID command, SO holds the output state of the last bit in 32-bit Device ID until CS is risen.
CS
0
1
2
3
4
5
6
7
1
0
0
1
1
1
1
1
8
31 32 33 34 35 36 37 38 39
9 10 11
SCK
SI
Invalid
Data Out
SO
High-Z
Data Out
8
31 30 29 28
7
6
5
4
3
2
MSB
1
0
LSB
bit
7
6
5
4
3
2
1
0
Hex
Manufacturer ID
Continuation code
0
0
0
1
0
1
0
1
0
1
1
1
0
1
0
1
04H
7FH
Product ID (1st Byte)
0
0
1
0
0
0
1
1
Product ID (2nd Byte)
0
0
0
0
1
1
Proprietary use
Density
Hex
Proprietary use
0
Fujitsu
23H
Density:00011B 64Kbit
Hex
0
03H
SLEEP
The SLEEP command shifts the LSI to a low power mode called “SLEEP mode”. The transition to the SLEEP
mode is carried out at the rising edge of CS after operation code in the SLEEP command. However, when
at least one SCK clock is inputted before the rising edge of CS after operation code in the SLEEP command,
this SLEEP command is canceled.
After the SLEEP mode transition, SCK and SI inputs are ignored and SO changes to a Hi-Z state.
Enter Sleep Mode
CS
0
1
2
3
4
5
6
7
1
0
1
1
1
0
0
1 Invalid
SCK
SI Invalid
SO
Hi-Z
Sleep Mode Entry
DS501-00052-2v0-E
10
MB85RS64TU
Returning to an normal operation from the SLEEP mode is carried out after tREC (Max 400 s) time from the
falling edge of CS (see the figure below). It is possible to return CS to H level before tREC time. However, it is
prohibited to bring down CS to L level again during tREC period.
CS
CS
tREC
From this time
Command input enable
Exit Sleep Mode
Sleep Mode Exit
DS501-00052-2v0-E
11
MB85RS64TU
BLOCK PROTECT
Writing protect block for WRITE command is configured by the value of BP0 and BP1 in the status register.
BP1
BP0
Protected Block
0
0
None
0
1
1800H to 1FFFH (upper 1/4)
1
0
1000H to 1FFFH (upper 1/2)
1
1
0000H to 1FFFH (all)
WRITING PROTECT
Writing operation of the WRITE command and the WRSR command are protected with the value of WEL,
WPEN, WP as shown in the table.
Protected Blocks
Unprotected Blocks
Status Register
WEL
WPEN
WP
0
X
X
Protected
Protected
Protected
1
0
X
Protected
Unprotected
Unprotected
1
1
0
Protected
Unprotected
Protected
1
1
1
Protected
Unprotected
Unprotected
HOLD OPERATION
Hold status is retained without aborting a command if HOLD is the “L” level while CS is the “L” level. The
timing for starting and ending hold status depends on the SCK to be the “H” level or the “L” level when a
HOLD pin input is transited to the hold condition as shown in the diagram below. In case the HOLD pin
transited to “L” level when SCK is “L” level, return the HOLD pin to “H” level at SCK being “L” level. In the
same manner, in case the HOLD pin transited to “L” level when SCK is “H” level, return the HOLD pin to “H”
level at SCK being “H” level. Arbitrary command operation is interrupted in hold status, SCK and SI inputs
become don’t care. And, SO becomes High-Z while reading command (RDSR, READ). If CS is rising during
hold status, a command is aborted. In case the command is aborted before its recognition, WEL holds the
value before transition to hold status.
CS
SCK
HOLD
Hold Condition
12
Hold Condition
DS501-00052-2v0-E
MB85RS64TU
ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Min
Max
Unit
Power supply voltage*
VDD
0.5
4.0
V
Input voltage*
VIN
0.5
VDD 0.5
V
VOUT
0.5
VDD 0.5
V
TA
55
85
C
Tstg
65
125
C
Output voltage*
Operation ambient temperature
Storage temperature
*:These parameters are based on the condition that VSS is 0 V.
WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without
limitation, voltage, current or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Min
Typ
Max
Unit
Power supply voltage*1
VDD
1.8
3.3
3.6
V
Operation ambient temperature*2
TA
55
85
C
*1: These parameters are based on the condition that VSS is 0 V.
*2: Ambient temperature when only this device is working. Please consider it to be the almost same as the
package surface temperature.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of
device and could result in device failure.
No warranty is made with respect to any use, operating conditions or combinations not represented
on this data sheet. If you are considering application under any conditions other than listed herein,
please contact sales representatives beforehand.
DS501-00052-2v0-E
13
MB85RS64TU
ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(within recommended operating conditions)
Parameter
Symbol
Condition
Input leakage current*1
|ILI|
Output leakage current*2
|ILO|
Operating power supply current
IDD
Value
Unit
Min
Typ
Max
WP, HOLD, SCK, CS,
SI 0 V to VDD
1
A
SO 0 V to VDD
1
A
SCK 0.1MHz
15
A
SCK 1 MHz
60
100
A
SCK 10MHz
500
800
A
Standby current
ISB
SCK SI CS VDD
9
12
A
Sleep current
IZZ
CS VDD
all inputs VSS or VDD
4
6
A
Input high voltage
VIH
VDD 1.8 V to 3.6 V
VDD 0.7
VDD 0.5
V
Input low voltage
VIL
VDD 1.8 V to 3.6 V
0.5
VDD 0.3
V
Output high voltage
VOH
IOH 2 mA
VDD 0.5
VDD
V
Output low voltage
VOL
IOL 2 mA
VSS
0.4
V
*
*
14
1: Applicable to; CS, WP, HOLD, SCK, SI
2: Applicable to; SO
DS501-00052-2v0-E
MB85RS64TU
*1
2. AC Characteristics
Parameter
Symbol
Value
Min
Max
Unit
SCK clock frequency
fCK
0
10
MHz
Clock high time
tCH
20
ns
Clock low time
tCL
20
ns
Chip select set up time
tCSU
10
ns
Chip select hold time
tCSH
10
ns
Output disable time
tOD
12
ns
Output data valid time
tODV
18
ns
Output hold time
tOH
0
ns
Deselect time
tD
40
ns
Data rising time
tR
50
ns
Data falling time
tF
50
ns
Data set up time
tSU
5
ns
Data hold time
tH
5
ns
HOLD set up time
tHS
10
ns
HOLD hold time
tHH
10
ns
HOLD output floating time
tHZ
20
ns
HOLD output active time
tLZ
20
ns
SLEEP resume time
tREC
400
s
AC Test Condition
Power supply voltage : 1.8 V to 3.6 V
Operation ambient temperature : 55 C to 85 C
Input voltage magnitude : 0 VIL 0.2 VDD ,0.8 VDD VIH VDD,
Input rising time : 5 ns
Input falling time : 5 ns
Input judge level : VDD/2
Output judge level : VDD/2
DS501-00052-2v0-E
15
MB85RS64TU
AC Load Equivalent Circuit
3.3 V
1.2 k
Output
30 pF
0.95 k
3. Pin Capacitance
Parameter
Symbol
Conditions
Output capacitance
CO
Input capacitance
CI
VDD VIN VOUT 0 V
f 1 MHz, TA 25 C
16
Value
Unit
Min
Max
8
pF
6
pF
DS501-00052-2v0-E
MB85RS64TU
TIMING DIAGRAM
Serial Data Timing
tD
CS
tCSH
tCSU
tCH
tCL
tCH
SCK
tSU
tH
Valid in
SI
tODV
SO
tOH
tOD
High-Z
High-Z
: H or L
Hold Timing
CS
SCK
tHS
tHH
tHS
tHS
tHH
tHS
tHH
tHH
HOLD
High-Z
SO
tHZ
DS501-00052-2v0-E
tLZ
High-Z
tHZ
tLZ
17
MB85RS64TU
POWER ON/OFF SEQUENCE
tpd
tf
tr
tpu
VDD
VDD
VDD(Min)
VDD(Min)
VIH (Min)
VIH (Min)
1.0 V
1.0 V
VIL (Max)
VIL (Max)
VSS
VSS
CS >VDD × 0.7 *
CS
CS >VDD × 0.7 *
CS : don't care
CS
* : CS (Max) < VDD 0.5 V
Parameter
Symbol
Value
Min
Max
Unit
CS level hold time at power OFF
tpd
400
ns
CS level hold time at power ON
tpu
250
s
Power supply rising time
tr
0.05
ms/V
Power supply falling time
tf
0.1
ms/V
If the device does not operate within the specified conditions of read cycle, write cycle or power on/off
sequence, memory data can not be guaranteed.
FRAM CHARACTERISTICS
Item
Min
Read/Write Endurance*
1
Data Retention*
2
10
13
10
Max
Unit
Parameter
Times/byte Operation Ambient Temperature TA 85 C
Years
Operation Ambient Temperature TA 85 C
*1 : Total number of reading and writing defines the minimum value of endurance, as an FRAM memory operates
with destructive readout mechanism.
*2 : Minimum values define retention time of the first reading/writing data right after shipment.
NOTE ON USE
We recommend programming of the device after reflow. Data written before reflow cannot be guaranteed.
18
DS501-00052-2v0-E
MB85RS64TU
ESD AND LATCH-UP
Test
DUT
Value
ESD HBM (Human Body Model)
JESD22-A114 compliant
|2000 V|
ESD MM (Machine Model)
JESD22-A115 compliant
|200 V|
ESD CDM (Charged Device Model)
JESD22-C101 compliant
|1000 V|
MB85RS64TUPNF-G-JNE2
MB85RS64TUPNF-G-JNERE2
MB85RS64TUPN-G-AMEWE1
Latch-Up (I-test)
JESD78 compliant
Latch-Up (Vsupply overvoltage test)
JESD78 compliant
Latch-Up (Current Method)
Proprietary method
Latch-Up (C-V Method)
Proprietary method
|200 V|
• Current method of Latch-Up Resistance Test
Protection Resistor
A
Test terminal
IIN
VIN
VDD
+
DUT
-
VSS
VDD
(Max.Rating)
V
Reference
terminal
Note : The voltage VIN is increased gradually and the current IIN of 300 mA at maximum shall flow.
Confirm the latch up does not occur under IIN 300 mA.
In case the specific requirement is specified for I/O and IIN cannot be 300 mA, the voltage shall be
increased to the level that meets the specific requirement.
DS501-00052-2v0-E
19
MB85RS64TU
• C-V method of Latch-Up Resistance Test
Protection Resistor
A
1
Test
2 terminal
SW
+
VIN
V
-
C
200pF
VDD
DUT
VDD
(Max.Rating)
VSS
Reference
terminal
Note : Charge voltage alternately switching 1 and 2 approximately 2 sec interval. This switching process is
considered as one cycle.
Repeat this process 5 times. However, if the latch-up condition occurs before completing 5 times, this
test must be stopped immediately.
REFLOW CONDITIONS AND FLOOR LIFE
[ JEDEC MSL ] : Moisture Sensitivity Level 3 (ISP/JEDEC J-STD-020D)
CURRENT STATUS ON CONTAINED RESTRICTED SUBSTANCES
This product complies with the regulations of REACH Regulations, EU RoHS Directive and China RoHS.
20
DS501-00052-2v0-E
MB85RS64TU
ORDERING INFORMATION
Package
Shipping form
Minimum shipping
quantity
MB85RS64TUPNF-G-JNE2
8-pin plastic SOP
(FPT-8P-M02)
Tube
*
MB85RS64TUPNF-G-JNERE2
8-pin plastic SOP
(FPT-8P-M02)
Embossed Carrier tape
1500
MB85RS64TUPN-G-AMEWE1
8-pin plastic SON
(LCC-8P-M04)
Embossed Carrier tape
1500
Part number
*: Please contact our sales office about minimum shipping quantity.
DS501-00052-2v0-E
21
MB85RS64TU
PACKAGE DIMENSION
8-pin plastic SOP
Lead pitch
1.27 mm
Package width ×
package length
3.9 mm × 5.05 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.75 mm MAX
Weight
0.06 g
(FPT-8P-M02)
8-pin plastic SOP
(FPT-8P-M02)
+0.25
Note 1) *1 : These dimensions include resin protrusion.
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
+.010
+0.03
*1 5.05 –0.20 .199 –.008
0.22 –0.07
+.001
.009 –.003
8
5
*2 3.90±0.30 6.00±0.20
(.154±.012) (.236±.008)
Details of "A" part
45°
1.55±0.20
(Mounting height)
(.061±.008)
0.25(.010)
0.40(.016)
1
"A"
4
1.27(.050)
0.44±0.08
(.017±.003)
0.13(.005)
0~8°
M
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.15±0.10
(.006±.004)
(Stand off)
0.10(.004)
C
22
2002-2012 FUJITSU SEMICONDUCTOR LIMITED F08004S-c-5-10
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
DS501-00052-2v0-E
MB85RS64TU
(continued)
8-pin plastic SON
Lead pitch
0.5 mm
Package width ×
package length
2.0 mm × 3.0 mm
Sealing method
Plastic mold
Mounting height
0.75 mm MAX
Weight
0.015g
(LCC-8P-M04)
8-pin plastic SON
(LCC-8P-M04)
1.6±0.10
(.063±.004)
2.00±0.07
(.079±.003)
0.40±0.07
(.016±.003)
3.00±0.07
(.118±.003)
1.40±0.10
(.055±.004)
INDEX AREA
1PIN CORNER
(C0.30(C.012))
0.50(.020)
TYP
0.05(.002) MAX
C
0.70±0.05
(.028±.002)
0.15(.006)
2011 FUJITSU SEMICONDUCTOR LIMITED HMbC8-04Sc-1-1
DS501-00052-2v0-E
0.25±0.05
(.010±.002)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
23
MB85RS64TU
MARKING
[MB85RS64TUPNF-G-JNE2]
[MB85RS64TUPNF-G-JNERE2]
RS64TU
E2YYWW
3XX
[FPT-8P-M02]
[MB85RS64TUPNF-G-AMEWE1]
Y Y WW
S64TU
0XX
[LCC-8P-M04]
24
DS501-00052-2v0-E
MB85RS64TU
PACKING INFORMATION
1. Tube
1.1 Tube Dimensions
• Tube/stopper shape
Tube
Transparent polyethylene terephthalate
(treated to antistatic)
Stopper
(treated to antistatic)
Tube length: 520 mm
Tube cross-sections and Maximum quantity
Maximum quantity
Package form
Package code
FPT-8P-M02
SOP, 8, plastic (2)
pcs/
tube
pcs/inner
box
pcs/outer
box
95
7600
30400
1.8
2.6
7.4
6.4
4.4
©2006-2010 FUJITSU SEMICONDUCTOR LIMITED
C 2006 FUJITSU LIMITED F08008-SET1-PET:FJ99L-0022-E0008-1-K-1
F08008-SET1-PET:FJ99L-0022-E0008-1-K-3
t 0.5
Transparent polyethylene terephthalate
(Dimensions
in mm)
DS501-00052-2v0-E
25
MB85RS64TU
1.2 Tube Dry pack packing specifications
IC
Tube
Stopper
For SOP
Index mark
Label I *1*3
Aluminum Iaminated bag
Heat seal
Dry pack
Desiccant
Humidity indicator
Aluminum Iaminated bag
(tubes inside)
Inner box
Cushioning material
Inner box
Label I
*1*3
Cushioning material
Outer box*2
Outer box
Use adhesive tapes.
Label II-A *3
Label II-B *3
*1: For a product of witch part number is suffixed with “E1” or “E2”, a “ G
barrier bag and the inner boxes.
Pb
” marks is display to the moisture
*2: The space in the outer box will be filled with empty inner boxes, or cushions, etc.
*3: Please refer to an attached sheet about the indication label.
Note: The packing specifications may not be applied when the product is delivered via a distributor.
26
DS501-00052-2v0-E
MB85RS64TU
1.3 Product label indicators
Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping)
[C-3 Label (50mm 100mm) Supplemental Label (20mm 100mm)]
XXXXXXXXXXXXXX
(Customer part number or FJ part number)
C-3 Label
(3N)1 XXXXXXXXXXXXXX XXX
(LEAD FREE mark)
(Part number and quantity)
QC PASS
(3N)2 XXXXXXXXXX XXXXXX
(FJ control number)
XXX pcs
XXXXXXXXXXXXXX
(Quantity)
(Customer part number or FJ part number)
(Customer part number or FJ part number
bar code)
XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx
XXXXXXXXXXXXXX (Customer part number or FJ part number)
(FJ control number bar code)
XX/XX
XXXX-XXX XXX
(Package count)
XXXX-XXX XXX
XXXXXXXXXX (FJ control number ) (Lot Number and quantity)
XXXXXXXXXXXXXX (Comment)
Perforated line
Supplemental Label
Label II-A: Label on Outer box [D Label] (100mm 100mm)
D Label
XXXXXXXXXXXXX (Customer Name)
(CUST.)
XXXXXXXXX (Delivery Address)
(DELIVERY POINT)
XXXXXXXXXXXXXX
(TRANS.NO.) (FJ control number)
XXXXXXXXXXXXXX
(PART NO.)
(Customer part number or
FJ part number)
XXX (FJ control number)
XXX (FJ control number)
XXX (FJ control number)
XXXXXXXXXXXXXX
(Part number)
(PART NAME) XXXXXXXXXXXXXX (Part number)
XXX/XXX
(Q’TY/TOTAL Q’TY)
(CUSTOMER'S
REMARKS)
XXXXXXXXXXXXXXXXXXXX
(3N)3 XXXXXXXXXXXXXX XXX
XX
(UNIT)
(PACKAGE COUNT)
XXX/XXX
(3N)4 XXXXXXXXXXXXXX XXX
(FJ control number + Product quantity)
(FJ control number + Product quantity
bar code)
(Part number + Product quantity)
(3N)5 XXXXXXXXXX
(FJ control number)
(Part number + Product quantity bar code)
(FJ control number bar code)
Label II-B: Outer boxes product indicate
XXXXXXXXXXXXXX
(Lot Number)
XXXX-XXX
XXXX-XXX
(Part number)
(Count)
X
X
(Quantity)
XXX
XXX
XXX
Note: Depending on shipment state, “Label II-A” and “Label II-B” on the external boxes might not be printed.
DS501-00052-2v0-E
27
MB85RS64TU
1.4 Dimensions for Containers
(1) Dimensions for inner box
H
W
L
L
W
H
540
125
75
(Dimensions in mm)
(2) Dimensions for outer box
H
W
L
L
W
H
565
270
180
(Dimensions in mm)
28
DS501-00052-2v0-E
MB85RS64TU
2. Emboss Tape
2.1 Tape Dimensions
PKG code
Reel No
FPT-8P-M02
3
Maximum storage capacity
pcs/reel
pcs/inner box
pcs/outer box
1500
1500
10500
ø1.5 +0.1
–0
8±0.1
1.75±0.1
2±0.05
4±0.1
B
0.3±0.05
A
B
A
5.5±0.1
12 +0.3
–0.1
5.5±0.05
ø1.5 +0.1
–0
SEC.B-B
2.1±0.1
6.4±0.1
0.4
3.9±0.2
SEC.A-A
C
2012 FUJITSU SEMICONDUCTOR LIMITED SOL8-EMBOSSTAPE9 : NFME-EMB-X0084-1-P-1
(Dimensions in mm)
Material : Conductive polystyrene
Heat proof temperature : No heat resistance.
Package should not be baked
by using tape and reel.
DS501-00052-2v0-E
29
MB85RS64TU
2.2 IC orientation
Index mark
• ER type
(User Direction of Feed)
(User Direction of Feed)
(Reel side)
2.3 Reel dimensions
Reel cutout dimensions
E
∗
D
C
B
A
W1
W2
r
W3
∗:
Reel No
Hub unit width dimensions
1
2
3
4
5
6
7
8
Tape width
8
12
16
24
Symbol
A
254 ± 2 254 ± 2 330 ± 2 254 ± 2 330 ± 2 254 ± 2 330 ± 2
B
32
C
13 ± 0.2
D
21 ± 0.8
10
11
44
12
13
56
12
Dimensions in mm
14
15
16
24
330 ± 2
100 +2
-0
100 +2
-0
E
150 +2
-0
100 +2
-0
150 +2
-0
100 +2
-0
100 ± 2
13 +0.5
-0.2
20.5 +1
-0.2
2 ± 0.5
W1
8.4 +2
-0
W2
less than
14.4
less than 18.4
less than 22.4
less than 30.4
less than 38.4
less than 50.4
less than
62.4
less than
18.4
less than
22.4
less than
30.4
W3
7.9 ~ 10.9
11.9 ~ 15.4
15.9 ~ 19.4
23.9 ~ 27.4
31.9 ~ 35.4
43.9 ~ 47.4
55.9 ~
59.4
12.4 ~
14.4
16.4 ~
18.4
24.4 ~
26.4
r
30
9
12.4 +2
-0
16.4 +2
-0
24.4 +2
-0
32.4 +2
-0
44.4 +2
-0
+0.1
56.4 +2
12.4 +1
16.4 +1
-0
-0
-0 24.4 -0
1.0
DS501-00052-2v0-E
MB85RS64TU
2.4 Taping (330mm Reel) Dry Pack Packing Specifications
Outside diameter: φ 330mm reel
Label I *1, *4
Embossed
tapes
Label I *1, *4
Desiccant
Humidity indicator
Aluminum laminated bag
Dry pack
Label I *1, *4
Heat seal
Inner box
Inner box
Label I *1, *4
Taping
Outer box *2, *3
Outer box
Use adhesive tapes.
Label II-A *4
Label II-B *4
*1: For a product of witch part number is suffixed with “E1” or “E2”, a “ G
barrier bag and the inner boxes.
Pb
” marks is display to the moisture
*2: The size of the outer box may be changed depending on the quantity of inner boxes.
*3: The space in the outer box will be filled with empty inner boxes, or cushions, etc.
*4: Please refer to an attached sheet about the indication label.
Note: The packing specifications may not be applied when the product is delivered via a distributor.
DS501-00052-2v0-E
31
MB85RS64TU
2.5 Product label indicators
Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping)
[C-3 Label (50mm 100mm) Supplemental Label (20mm 100mm)]
XXXXXXXXXXXXXX
(Customer part number or FJ part number)
C-3 Label
(3N)1 XXXXXXXXXXXXXX XXX
(LEAD FREE mark)
(Part number and quantity)
QC PASS
(3N)2 XXXXXXXXXX XXXXXX
(FJ control number)
XXX pcs
XXXXXXXXXXXXXX
(Quantity)
(Customer part number or FJ part number)
(Customer part number or FJ part number
bar code)
XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx
XXXXXXXXXXXXXX (Customer part number or FJ part number)
(FJ control number bar code)
XX/XX
XXXX-XXX XXX
(Package count)
XXXX-XXX XXX
XXXXXXXXXX (FJ control number ) (Lot Number and quantity)
XXXXXXXXXXXXXX (Comment)
Perforated line
Supplemental Label
Label II-A: Label on Outer box [D Label] (100mm 100mm)
D Label
XXXXXXXXXXXXX (Customer Name)
(CUST.)
XXXXXXXXX (Delivery Address)
(DELIVERY POINT)
XXXXXXXXXXXXXX
(TRANS.NO.) (FJ control number)
XXXXXXXXXXXXXX
(PART NO.)
(Customer part number or
FJ part number)
XXX (FJ control number)
XXX (FJ control number)
XXX (FJ control number)
XXXXXXXXXXXXXX
(Part number)
(PART NAME) XXXXXXXXXXXXXX (Part number)
XXX/XXX
(Q’TY/TOTAL Q’TY)
(CUSTOMER'S
REMARKS)
XXXXXXXXXXXXXXXXXXXX
(3N)3 XXXXXXXXXXXXXX XXX
XX
(UNIT)
(PACKAGE COUNT)
XXX/XXX
(3N)4 XXXXXXXXXXXXXX XXX
(FJ control number + Product quantity)
(FJ control number + Product quantity
bar code)
(Part number + Product quantity)
(3N)5 XXXXXXXXXX
(FJ control number)
(Part number + Product quantity bar code)
(FJ control number bar code)
Label II-B: Outer boxes product indicate
XXXXXXXXXXXXXX
(Lot Number)
XXXX-XXX
XXXX-XXX
(Part number)
(Count)
X
X
(Quantity)
XXX
XXX
XXX
Note: Depending on shipment state, “Label II-A” and “Label II-B” on the external boxes might not be printed.
32
DS501-00052-2v0-E
MB85RS64TU
2.6 Dimensions for Containers
(1) Dimensions for inner box
H
W
L
Tape width
L
W
H
12, 16
24, 32
44
40
365
50
345
65
56
75
(Dimensions in mm)
(2) Dimensions for outer box
H
W
L
L
W
H
415
400
315
(Dimensions in mm)
DS501-00052-2v0-E
33
MB85RS64TU
MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page
Section
Change Results
2
PIN ASSIGNMENT
24,26,31 PACKING INFORMATION
34
DIE PAD added.
Typo.
DS501-00052-2v0-E
MB85RS64TU
FUJITSU SEMICONDUCTOR LIMITED
Shin-Yokohama Chuo Building, 2-100-45 Shin-Yokohama,
Kohoku-ku, Yokohama, Kanagawa 222-0033, Japan
http://jp.fujitsu.com/fsl/en/
All Rights Reserved.
FUJITSU SEMICONDUCTOR LIMITED, its subsidiaries and affiliates (collectively, "FUJITSU SEMICONDUCTOR") reserves
the right to make changes to the information contained in this document without notice. Please contact your FUJITSU
SEMICONDUCTOR sales representatives before order of FUJITSU SEMICONDUCTOR device.
Information contained in this document, such as descriptions of function and application circuit examples is presented solely for
reference to examples of operations and uses of FUJITSU SEMICONDUCTOR device. FUJITSU SEMICONDUCTOR disclaims
any and all warranties of any kind, whether express or implied, related to such information, including, without limitation, quality,
accuracy, performance, proper operation of the device or non-infringement. If you develop equipment or product incorporating the
FUJITSU SEMICONDUCTOR device based on such information, you must assume any responsibility or liability arising out of or
in connection with such information or any use thereof. FUJITSU SEMICONDUCTOR assumes no responsibility or liability for any
damages whatsoever arising out of or in connection with such information or any use thereof.
Nothing contained in this document shall be construed as granting or conferring any right under any patents, copyrights, or any other
intellectual property rights of FUJITSU SEMICONDUCTOR or any third party by license or otherwise, express or implied.
FUJITSU SEMICONDUCTOR assumes no responsibility or liability for any infringement of any intellectual property rights or other
rights of third parties resulting from or in connection with the information contained herein or use thereof.
The products described in this document are designed, developed and manufactured as contemplated for general use including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and
manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high levels of safety is secured,
could lead directly to death, personal injury, severe physical damage or other loss (including, without limitation, use in nuclear
facility, aircraft flight control system, air traffic control system, mass transport control system, medical life support system and
military application), or (2) for use requiring extremely high level of reliability (including, without limitation, submersible repeater
and artificial satellite). FUJITSU SEMICONDUCTOR shall not be liable for you and/or any third party for any claims or damages
arising out of or in connection with above-mentioned uses of the products.
Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs and
safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures into your
facility, equipments and products such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal
operating conditions.
The products and technical information described in this document are subject to the Foreign Exchange and Foreign Trade Control
Law of Japan, and may be subject to export or import laws or regulations in U.S. or other countries. You are responsible for ensuring
compliance with such laws and regulations relating to export or re-export of the products and technical information described herein.
All company names, brand names and trademarks herein are property of their respective owners.
Edited: System Memory Company
Mouser Electronics
Authorized Distributor
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MB85RS64TUPNF-G-JNE2 MB85RS64TUPNF-G-JNERE2 MB85RS64TUPN-G-AMEWE1
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