MB86296S
PCI Graphics Controller
Specification
Revision 1.1
25 September, 2007
Copyright © FUJITSU LIMITED 2003-2004
ALL RIGHTS RESERVED
• The specifications in this manual are subject to change without notice.
Department before purchasing the product described in this manual.
Contact our Sales
• Information and circuit diagrams in this manual are only examples of device applications, they are
not intended to be used in actual equipment. Also, Fujitsu accepts no responsibility for infringement of
patents or other rights owned by third parties caused by use of the information and circuit diagrams.
• The contents of this manual must not be reprinted or duplicated without permission of Fujitsu.
• Fujitsu’s semiconductor devices are intended for standard uses (such as office equipment
(computers and OA equipment), industrial/communications/measuring equipment, and personal/home
equipment). Customers using semiconductor devices for special applications (including aerospace,
nuclear, military and medical applications) in which a failure or malfunction might endanger life or limb
and which require extremely high reliability must contact our Sales Department first. If damage is
caused by such use of our semiconductor devices without first consulting our Sales Department,
Fujitsu will not assume any responsibility for the loss.
• Semiconductor devices fail with a known probability. Customers must use safety design (such as
redundant design, fireproof design, over-current prevention design, and malfunction prevention
design) so that failures will not cause accidents, injury or death).
• If the products described in this manual fall within the goods or technologies regulated by the
Foreign Exchange and Foreign Trade Law, permission must be obtained before exporting the goods
or technologies.
！ CAUTION
Burns There is a danger of burns because the IC surface is heated
depending on the IC operating conditions. In this case, take
safety measures.
All Rights Reserved
The contents of this document are subject to change without notice. Customers are advised to consult with
FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and are not intended to be incorporated in devices
for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other
rights of third parties arising from the use of this information or circuit diagrams. The products described in this
document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed,
developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight
control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of
failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions. If any products described in this document represent goods or
technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of
Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
ii
Update history
Date
Version
Page count
28.2.2005
1.0
346
First edition
25.9.2007
1.1
356
Correct MMR Register (RAW > SAW) and some lingual improvements
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CONTENTS
1. GENERAL
1
1.1 Preface ........................................................................................................................................... 1
1.2 Features ......................................................................................................................................... 2
1.3 Block Diagram ................................................................................................................................ 3
1.4 Functional Overview ....................................................................................................................... 4
1.4.1 Host CPU interface .................................................................................................................. 4
1.4.2 External memory interface ....................................................................................................... 5
1.4.3 Display controller...................................................................................................................... 6
1.4.4 Video capture function ............................................................................................................. 8
1.4.5 Geometry processing ............................................................................................................... 9
1.4.6 2D Drawing............................................................................................................................. 10
1.4.7 3D Drawing............................................................................................................................. 12
1.4.8 Special effects ........................................................................................................................ 13
1.4.9 Others..................................................................................................................................... 15
2. PINS
16
2.1 Signals.......................................................................................................................................... 16
2.1.1 Signal lines ............................................................................................................................. 16
2.2 Pin Assignment............................................................................................................................. 17
2.2.1 Pin assignment diagram......................................................................................................... 17
2.2.2 Pin assignment table .............................................................................................................. 18
2.3 Pin Function.................................................................................................................................. 26
2.3.1 Host CPU interface ................................................................................................................ 26
2.3.2 Video output interface ............................................................................................................ 28
2.3.3 Video capture interface .......................................................................................................... 30
2.3.4 I2C interface............................................................................................................................ 31
2.3.5 Graphics memory interface .................................................................................................... 32
2.3.6 Clock input.............................................................................................................................. 33
2.3.7 Test pins ................................................................................................................................. 34
2.3.8 Reset sequence ..................................................................................................................... 34
2.3.9 How to switch internal operating frequency ........................................................................... 34
3. PROCEDURE OF THE HARDWARE INITIALIZATION
35
3.1. Hardware reset ............................................................................................................................. 35
3.2. Re-reset........................................................................................................................................ 35
3.3. Software reset ........................................................................................................................... 35
4.
HOST INTERFACE
36
4.1 Standard PCI Slave Accesses .................................................................................................... 36
4.1.1 PCI Slave Write ...................................................................................................................... 36
4.1.2 PCI Slave Read...................................................................................................................... 36
4.2 Burst Controller Accesses (including PCI Master)...................................................................... 36
4.2.1 Transfer Modes ..................................................................................................................... 37
4.2.2 Burst Controller Control/Status.............................................................................................. 38
4.3 FIFO Transfers............................................................................................................................ 39
4.4 GPIO/Serial Interface.................................................................................................................. 39
4.4.1 GPIO ....................................................................................................................................... 39
4.4.2 Serial Interface ........................................................................................................................ 39
4.5 Interrupt....................................................................................................................................... 40
4.5.1 Address Error Interrupt............................................................................................................ 40
4.6 Memory Map ............................................................................................................................... 41
5.
I2C Interface Controller
43
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5.1 Features ........................................................................................................................................ 43
5.2 Block diagram................................................................................................................................ 44
5.2.1 Block Diagram ......................................................................................................................... 44
5.2.2 Block Function Overview......................................................................................................... 45
5.3 Example application ...................................................................................................................... 46
5.3.1 Connection Diagram ............................................................................................................... 46
5.4 Function overview.......................................................................................................................... 47
5.4.1 START condition...................................................................................................................... 47
5.4.2 STOP condition ....................................................................................................................... 47
5.4.3 Addressing............................................................................................................................... 48
5.4.4 Synchronization of SCL........................................................................................................... 48
5.4.5 Arbitration ................................................................................................................................ 49
5.4.6 Acknowledge ........................................................................................................................... 49
5.4.7 Bus error.................................................................................................................................. 49
5.4.8 Initialize ................................................................................................................................... 50
5.4.9 1-byte transfer from master to slave ....................................................................................... 51
5.4.10 1-byte transfer from slave to master ..................................................................................... 52
5.4.11 Recovery from bus error........................................................................................................ 53
5.5 Note ............................................................................................................................................... 54
6. Graphics Memory
55
6.1. Configuration ................................................................................................................................ 55
6.1.1. Data type ................................................................................................................................ 55
6.1.2. Memory Mapping ................................................................................................................... 56
6.1.3. Data Format ........................................................................................................................... 56
6.2. Frame Management ..................................................................................................................... 58
6.2.1. Single Buffer........................................................................................................................... 58
6.2.2. Double Buffer ......................................................................................................................... 58
6.3. Memory Access ............................................................................................................................ 58
6.3.1. Memory Access by host CPU................................................................................................. 58
6.3.2. Priority of memory accessing ................................................................................................. 58
6.4. Connection with memory.............................................................................................................. 59
6.4.1. Connection with memory........................................................................................................ 59
7. DISPLAY CONTROLLER
60
7.1 Overview....................................................................................................................................... 60
7.2 Display Function ........................................................................................................................... 61
7.2.1 Layer configuration................................................................................................................. 61
7.2.2 Overlay ................................................................................................................................... 62
7.2.3 Display parameters ................................................................................................................ 64
7.2.4 Display position control .......................................................................................................... 65
7.3 Display Color ................................................................................................................................ 67
7.4 Cursor ........................................................................................................................................... 68
7.4.1 Cursor display function........................................................................................................... 68
7.4.2 Cursor control......................................................................................................................... 68
7.5 Display Scan Control .................................................................................................................... 69
7.5.1 Applicable display................................................................................................................... 69
7.5.2 Interlace display ..................................................................................................................... 70
7.6 Video Interface, NTSC/PAL Output .............................................................................................. 71
7.7 Programmable YCbCr/RGB conversion for L1-layer display ........................................................ 72
7.8 DCLKO shift ................................................................................................................................ 74
7.9 Syncronous register update of display........................................................................................ 74
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7.10 Dual Display ................................................................................................................................ 75
7.10.1 Overview .............................................................................................................................. 75
7.10.2 Destination Control............................................................................................................... 75
7.10.3 Output Signal Control........................................................................................................... 76
7.10.4 Output Circuit Example ........................................................................................................ 77
7.10.5 Display Clock and Timing.................................................................................................... 79
7.10.6 Limitation .............................................................................................................................. 79
8. Video Capture
80
8.1 Video Capture function .................................................................................................................. 80
8.1.1 Input data Formats .................................................................................................................. 80
8.1.2 Capturing of Video Signal ....................................................................................................... 80
8.1.3 Non-interlace Transformation.................................................................................................. 80
8.2 Video Buffer ................................................................................................................................... 81
8.2.1 Data Form ............................................................................................................................... 81
8.2.2 Synchronous Control............................................................................................................... 81
8.2.3 Area Allocation......................................................................................................................... 81
8.2.4 Window Display....................................................................................................................... 82
8.2.5 Interlace Display...................................................................................................................... 82
8.2.6 RGB555 Mode......................................................................................................................... 82
8.3 Scaling ........................................................................................................................................... 83
8.3.1 Down-scaling Function............................................................................................................ 83
8.3.2 Up-scaling Function ................................................................................................................ 83
8.3.2 Flow of image processing ....................................................................................................... 85
8.4 External video signal input conditions ........................................................................................... 88
8.4.1 RTB656 YUV422 input format................................................................................................. 88
8.4.2 RGB input format..................................................................................................................... 90
1) RGB Input Signals
90
2) Captured Range
90
3) Input Operation
92
4) Conversion Operation
94
8.5 Input Video Signal Parameter Setup ............................................................................................. 95
9. GEOMETRY ENGINE
96
9.1 Geometry Pipeline ........................................................................................................................ 96
9.1.1 Processing flow ...................................................................................................................... 96
9.1.2 Model-view-projection (MVP) transformation (OC→CC coordinate transformation) ............. 97
9.1.3 3D-2D transformation (CC→NDC coordinate transformation)............................................... 97
9.1.4 View port transformation (NDC→DC coordinate transformation) .......................................... 98
9.1.5 View volume clipping.............................................................................................................. 98
9.1.6 Back face culling .................................................................................................................. 100
9.2 Data Format................................................................................................................................ 101
9.2.1 Data format........................................................................................................................... 101
9.3 Setup Engine .............................................................................................................................. 102
9.3.1 Setup processing ................................................................................................................. 102
9.4 Log Output of Device Coordinates ............................................................................................. 102
9.4.1 Log output mode .................................................................................................................. 102
9.4.2 Log output destination address ............................................................................................ 102
9.4.3 Log output format .................................................................................................................. 102
10. DRAWING PROCESSING
103
10.1 Coordinate System ................................................................................................................... 103
10.1.1 Drawing coordinates .......................................................................................................... 103
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10.1.2 Texture coordinates ............................................................................................................ 104
10.1.3 Frame buffer....................................................................................................................... 104
10.2 Figure Drawing ......................................................................................................................... 105
10.2.1 Drawing primitives.............................................................................................................. 105
10.2.2 Polygon drawing function ................................................................................................... 105
10.2.3 Drawing parameters ........................................................................................................... 106
10.2.4 Anti-aliasing function .......................................................................................................... 107
10.3 Bit Map Processing................................................................................................................... 108
10.3.1 BLT ..................................................................................................................................... 108
10.3.2 Pattern data format ............................................................................................................ 108
10.4 Texture Mapping ....................................................................................................................... 109
10.4.1 Texture size ........................................................................................................................ 109
10.4.2 Texture color....................................................................................................................... 109
10.4.3 Texture Wrapping ............................................................................................................... 110
10.4.4 Filtering................................................................................................................................111
10.4.5 Perspective correction.........................................................................................................111
10.4.6 Texture blending ................................................................................................................. 112
10.4.7 Bi-linear high-speed mode ................................................................................................. 112
10.5 Rendering ................................................................................................................................. 114
10.5.1 Tiling ................................................................................................................................... 114
10.5.2 Alpha blending.................................................................................................................... 114
10.5.3 Logic operation................................................................................................................... 115
10.5.4 Hidden plane management ................................................................................................ 115
10.6 Drawing Attributes .................................................................................................................... 116
10.6.1 Line drawing attributes ....................................................................................................... 116
10.6.2 Triangle drawing attributes ................................................................................................. 116
10.6.3 Texture attributes................................................................................................................ 117
10.6.4 BLT attributes ..................................................................................................................... 118
10.6.5 Character pattern drawing attributes.................................................................................. 118
10.7 Bold Line................................................................................................................................... 119
10.7.1 Starting and ending points.................................................................................................. 119
10.7.2 Broken line pattern ............................................................................................................. 120
10.7.3 Edging ................................................................................................................................ 121
10.7.4 Interpolation of bold line joint ............................................................................................. 122
10.8 Shadowing................................................................................................................................. 123
10.8.1 Shadowing........................................................................................................................... 123
11 DISPLAY LIST
124
11.1 Overview .................................................................................................................................... 124
11.1.1 Header format...................................................................................................................... 125
11.1.2 Parameter format................................................................................................................. 125
11.2 Geometry Commands................................................................................................................ 126
11.2.1 Geometry command list ...................................................................................................... 126
11.2.2 Explanation of geometry commands ................................................................................... 130
11.3 Rendering Command................................................................................................................. 139
11.3.1 Command list....................................................................................................................... 139
11.3.2 Details of rendering commands........................................................................................... 143
12. PCI Configuration Registers
154
12.1 PCI Configuration register list.................................................................................................... 154
12.2 PCI Configuration Registers Descriptions ................................................................................. 155
13 Local Memory Registers
158
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13.1 Local memory register list......................................................................................................... 158
13.1.1 Host interface register list................................................................................................... 158
13.1.2 I2C interface register list ..................................................................................................... 160
13.1.3 Graphics memory interface register list ............................................................................. 160
13.1.4 Display controller register list ............................................................................................. 161
13.1.5 Video capture register list................................................................................................... 167
13.1.6 Drawing engine register list................................................................................................ 169
13.1.7 Geometry engine register list ............................................................................................. 175
13.2 Explanation of Local Memory Registers................................................................................... 176
13.2.1 Host interface registers ...................................................................................................... 177
13.2.2 I2C Interface Registers ....................................................................................................... 192
13.2.3 Graphics memory interface registers ................................................................................. 198
13.2.4 Display control register....................................................................................................... 201
13.2.5 Video capture registers ...................................................................................................... 255
13.2.6 Drawing control registers ................................................................................................... 271
13.2.7 Drawing mode registers ..................................................................................................... 274
13.2.8 Triangle drawing registers .................................................................................................. 291
13.2.9 Line drawing registers ........................................................................................................ 294
13.2.10 Pixel drawing registers ..................................................................................................... 295
13.2.11 Rectangle drawing registers............................................................................................. 295
13.2.12 Blt registers ...................................................................................................................... 296
13.2.13 High-speed 2D line drawing registers .............................................................................. 297
13.2.14 High-speed 2D triangle drawing registers........................................................................ 298
13.2.15 Geometry control register................................................................................................. 299
13.2.16 Geometry mode registers................................................................................................. 301
13.2.17 Display list FIFO registers ................................................................................................ 308
14. TIMING DIAGRAM
309
14.1 Host Interface ........................................................................................................................... 309
14.1.1 PCI Interface ...................................................................................................................... 309
14.1.2 EEPROM Timing ................................................................................................................ 310
14.1.3 Serial Interface Timing ....................................................................................................... 311
14.2 I2C Interface.............................................................................................................................. 312
14.3 Graphics Memory Interface ...................................................................................................... 313
14.3.1 Timing of read access to same row address...................................................................... 313
14.3.2 Timing of read access to different row addresses.............................................................. 314
14.3.3 Timing of write access to same row address ..................................................................... 315
14.3.4 Timing of write access to different row addresses ............................................................. 316
14.3.5 Timing of read/write access to same row address ............................................................. 317
14.3.6 Delay between ACTV commands ...................................................................................... 318
14.3.7 Delay between Refresh command and next ACTV command........................................... 318
14.4 Display Timing .......................................................................................................................... 319
14.4.1 Non-interlace mode............................................................................................................ 319
14.4.2 Interlace video mode.......................................................................................................... 320
14.4.3 Composite synchronous signal .......................................................................................... 321
15. ELECTRICAL CHARACTERISTICS
322
15.1 Introduction............................................................................................................................... 322
15.2 Maximum Rating....................................................................................................................... 322
15.3 Recommended Operating Conditions ...................................................................................... 323
15.3.1 Recommended operating conditions ................................................................................. 323
15.3.2 Note at power-on................................................................................................................ 324
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15.4 DC Characteristics.................................................................................................................... 325
15.4.1 DC Characteristics of PCI Buffer......................................................................................... 325
15.4.2 DC Characteristics of other than PCI buffer........................................................................ 327
15.5 AC Characteristics .................................................................................................................... 329
15.5.1 Host interface ..................................................................................................................... 329
15.5.2 I2C Interface ........................................................................................................................ 330
15.5.3 Video interface ................................................................................................................... 331
15.5.4 Video capture interface ....................................................................................................... 333
15.5.5 Graphics memory interface ................................................................................................ 334
15.6 AC Characteristics Measuring Conditions ................................................................................ 340
15.7 Timing Diagram ........................................................................................................................ 341
15.7.1 Host interface ..................................................................................................................... 341
15.7.2 Video interface ................................................................................................................... 342
15.7.3 Video capture interface ....................................................................................................... 344
15.7.4 Graphics memory interface ................................................................................................ 345
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1. GENERAL
1.1 Preface
The MB86296S is a graphics controller with a PCI host interface.
Note:
This device has a I2C interface. Purchase of Fujitsu I2C components conveys a license under the
Philips I2C Patent Right to use these components in an I2C system, provided that the system conforms
to the I2C Standard Specification as defined by Philips.
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1.2 Features
• Geometry Engine
The Geometry Engine supports the geometry processing that is basically compatible**1 with
ORCHID (MB86292). Display lists generated for ORCHID can be processed. Extensive geometric
operation processing such as coordinate conversions or clipping which normally load the CPU
dramatically can be reduced using the Geometry Engine. **1 (Floating point setup command is
changed or deleted. G_BeginCont command is deleted. GMDR0 CF&DF table mapping is
changed ... etc)
• 2D and 3D Drawing
MB86296's drawing functionality is compatible to the CREMSON (MB86290A). It can draw data
using the display lists created for CREMSON (however internal texture RAM is deleted).
The MB86296 also supports 3D rendering, such as texture mapping with perspective correction and
Gouraud shading, alpha blending and anti-aliasing for drawing smooth lines.
• Digital video capture
The digital video capture function can store digital video data such as TV images in graphics
memory; it can display drawn images and video images on the same screen.
• Display controller
The MB86296 has a display controller that is compatible with ORCHID.
In addition to the traditional XGA (1024 × 768 pixels) display, 4-layer overlay, left/right split display,
wrap-around scrolling, double buffers, and translucent display, 6-layer overlay functionality, 4-siding
for palette are expanded.
• Host CPU interface
The MB86296 has a 32 bit, 33MHz PCI interface fully compliant to PCI version 2.1.
• External memory interface
SDRAM and FCRAM can be connected.
• Optional function
Final device can be selected from the combination of geometry high-/low-speed version and video
capture function provided/ not provided.
• Others
CMOS technology 0.18µm
BGA256 Package
Supply voltage:1.8 V (internal operation) /3.3 V (I/O)
Current consumption (TYPICAL)
1.8 V : 500mA
3.3 V : 100mA
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1.3 Block Diagram
The CORAL-PA general block diagram is shown below:
Pixel Bus
PCI Bus
AD0-31
Host
Interface
MD0-31/63
SDRAM
or
FCRAM
MA0-14
Capture Controller
YUV/RGB
Display Controller
DRGB
External
Geometry
2D/3D
Memory
Engine
Rendering
Controller
Engine
Fig.1.1 CORAL-PA Block Diagram
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1.4 Functional Overview
1.4.1 Host CPU interface
Supported CPU
The MB86296 can be connected to any CPU with a 33MHz 32-bit PCI v2.1 host interface.
Configuration
EEPROM configuration supported
Serial interface for external device control through PCI interface
PCI Slave
Supports burst reads/writes of up to 8 double words (32 bytes).
Supports multi-burst transfers with automatic pre-fetch.
PCI Master
Supports transfers of up to 224-1 double words in bursts of between 1 and 8 double words.
Supports all combinations of transfer (PCI->PCI, PCI->Internal, Internal->PCI)
Host notification on burst complete and/or transfer complete
Optional external burst initiation control
Internal DMA
Supports transfers of up to 224-1 double words in bursts of between 1 and 8 double words.
Interrupt
Vertical (frame) synchronous detection
Field synchronous detection
External synchronous error detection
Register update
Drawing command error
Drawing command execution end
Burst/Transfer complete
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1.4.2 External memory interface
SDRAM or FCRAM can be connected.
64 bits or 32 bits can be selected for data bus.
Max. 133 MHz is available for operating frequency.
Connectable memory configuration is as shown below.
External Memory Configuration
Type
Data bus width
Use count
Total capacity
FCRAM 16 Mbits (x16 Bits)
32 Bits
2
4 Mbytes
SDRAM 64 Mbits (x32 Bits)
32 Bits
1
8 Mbytes
SDRAM 64 Mbits (x32 Bits)
64 Bits
2
16 Mbytes
SDRAM 64 Mbits (x16 Bits)
32 Bits
2
16 Mbytes
SDRAM 128 Mbits (x32 Bits)
32 Bits
1
16 Mbytes
SDRAM 128 Mbits (x32 Bits)
64 Bits
2
32 Mbytes
SDRAM 128 Mbits (x16 Bits)
32 Bits
2
32 Mbytes
SDRAM 256 Mbits (x16 Bits)
32 Bits
2
64 Mbytes
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1.4.3 Display controller
Video data output
Analog RGB video output is provided as well as 8-bit digital video output is provided. When
selecting each 8 bits output, usable external memory bus width is 32 bits only.
Screen resolution
LCD panels with wide range of resolutions are supported by using a programmable timing
generator as follows:
Screen Resolutions
Resolutions
1024 × 768
1024 × 600
800 × 600
854 × 480
640 × 480
480 × 234
400 × 234
320 × 234
Hardware cursor
MB86296S supports two hardware cursor functions. Each of these hardware cursors is specified
as a 64 × 64-pixel area. Each pixel of these hardware cursors is 8 bits and uses the same look-up
table as indirect color mode.
Double buffer method
The double buffer method in which drawing window and display window is switched in units of 1
frame enables the smooth animation.
Flipping (switching of display window area) is performed in synchronization with the vertical
blanking period using program.
Scroll method
Independent setting of drawing and display windows and their starting position enables the smooth
scrolling.
Display colors
• Supports indirect color mode which uses the look-up table (color palette) in 8 bits/pixels.
• Entry for look-up table (color palette) corresponds to color code for 8 bits, in other words, 256. Color
data is each 6 bits of RGB. Consequently, 256 colors can be displayed out of 260,000 colors.
• Supports direct color mode which specifies RGB with 16 bits/pixels.
• Supports direct color mode which specifies RGB with 24 bits/pixels.
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Overlay
Compatibility mode
Up to four extra layers (C, W, M and B) can be displayed overlaid.
The overlay position for the hardware cursors is above/below the top layer (C).
The transparent mode or the blend mode can be selected for overlay.
The M- and B-layers can be split into separate windows.
Window display can be performed for the W-layer.
Two palettes are provided: C-layer and M-/B-layer.
The W-layer is used as the video input layer.
L0, L2, L4 (0,0)
L3, L5 (HDB+1, 0)
L1 (WX, WY)
Window mode
• Up to six screens (L0 to 5) can be displayed overlaid.
• The overlay sequence of the L0- to L5-layers can be changed arbitrarily.
• The overlay position for the hardware cursors is above/below the L0-layer.
• The transparent mode or the blend mode can be selected for overlay.
• The L5-layer can be used as the blend coefficient plane (8 bits/pixel).
• Window display can be performed for all layers.
• Four palettes corresponded to L0 to 3 are provided.
• The L1-layer is used as the video input layer.
• Background color display is supported in window display for all layers.
L0 (L0WX, L0WY)
L4 (L4WX, L4WY)
L2 (L2WX, L2WY)
L1 (L1WX, L1WY)
L5 (L5WX, L5WY)
L3 (L3WX, L3WY)
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1.4.4 Video capture function
Video input
• The input format is either ITU RBT-656 or RGB666.
• Video data is stored in graphics memory once and then displayed on the screen in synchronization
with the display scan.
Scaling
• A scale-up factor 1 to 2 can be used. PAL or NTSC images can be displayed on a wide screen.
• A scale-down factor 1 to 1/32 can be used.
• Picture-in-picture can be used to display drawn images and video images on the same screen.
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1.4.5 Geometry processing
The MB86296 has a geometry engine for performing the numerical operations required for graphics
processing. The geometry engine uses the floating-point format for highly precise operations. It
selects the required geometry processing according to the set drawing mode and primitive type and
executes processing to the final drawing.
Primitives
Point, line, line strip, independent triangle, triangle strip, triangle fan, and arbitrary polygon are
supported.
MVP Transformation
MVP Transformation
Setting a 4 × 4 transformation matrix enables transformation of a 3D model view projection. Twodimensional affine transformation is also possible.
Clipping
Clipping stops drawing of figures outside the window (field of view). Polygons (including concave
shapes) can also be clipped.
Culling
Backfacing triangles are not drawn.
3D-2D Transformation
This function transforms 3D coordinates (normalization) into 2D coordinates in orthogonal or
perspective projections.
View port transformation
This function transforms normalized 2D coordinates into drawing (device) coordinates.
Primitive setup
This function automatically performs a variety of slope computations, etc., based on transforming
vertex data into coordinates and prepares for rendering (setup).
Log output of device coordinates
The view port conversion results are output to the local memory.
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1.4.6 2D Drawing
2D Primitives
MB86296S can perform 2D drawing for graphics memory (drawing plane) in direct color mode or
indirect color mode.
Wide bold lines and broken lines can be drawn. Smooth diagonal lines can also be drawn using
anti-aliasing.
A triangle can be tiled in a single color or 2D pattern (tiling) or mapped with a texture pattern by
specifying coordinates of the 2D pattern at each vertex (texture mapping). With texture mapping,
drawing/non-drawing can be set in pixel units. Moreover, transparent processing can be performed
using alpha blending. When drawing in single color or tiling without Gouraud shading or texture
mapping, high-speed 2DLine and high-speed 2DTriangle functions can be used. Only vertex
coordinates are set for these primitives. High-speed 2DTriangle is also used to draw polygons.
2D Primitives
Primitive type
Point
Line
Bold line strip
(provisional name)
Triangle
High-speed 2DLine
Arbitrary polygon
Description
Plots point
Draws line
Draws continuous bold line
This primitive is used when interpolating the bold line joint.
Draws triangle
Draws lines
Compared to line, this reduces the host CPU processing load.
Draws arbitrary closed polygon containing concave shapes
consisting of vertices
Arbitrary polygon drawing
Using this function, arbitrary closed polygons containing concave shapes consisting of vertices can
be drawn (there is no restriction on the count of vertices, however, polygons with crossing sides are
not supported.) In this case, a polygon drawing flag buffer is used on the graphics memory, as a
work area for drawing. When drawing polygons, draw the triangles for the polygon drawing flag
buffer using high-speed 2DTriangle. Decide on any vertex as a starting point to draw the triangle
along the edge. You can draw the final polygon form in a single color or with tiling or with texture
mapping in a drawing frame.
MB86296S
Specification Manual Rev1.0
10
FUJITSU LIMITED
BLT/Rectangle drawing
This function draws a rectangle using logic operations. It is used to draw pattern and copy the
image pattern within the drawing frame. It is also used for clearing drawing frame and Z buffer.
BLT Attributes
Attribute
Raster operation
Transparent processing
Alpha blending
Description
Selects two source logical operation mode
Performs BLT without drawing pixel consistent with the
transparent color.
The alpha map and source in the memory is subjected to alpha
blending and then copied to the destination.
Pattern (Text) drawing
This function draws a binary pattern (text) in a specified color.
Pattern (Text) Drawing Attributes
Attribute
Enlarge
Shrink
Description
Vertically × 2
Horizontally × 2
Vertically and Horizontally × 2
Vertically × 1/2
Horizontally 1/2
Vertically and Horizontally 1/2
Drawing clipping
This function sets a rectangle frame in drawing frame to prohibit the drawing of the outside the
frame.
MB86296S
Specification Manual Rev1.1
11
FUJITSU LIMITED
1.4.7 3D Drawing
3D Primitives
This function draws 3D objects in drawing memory in the direct color mode.
3D Primitives
Primitive
Point
Line
Triangle
Arbitrary polygon
Description
Plots 3D point
Draws 3D line
Draws 3D triangle
Draws arbitrary closed polygon containing concave shapes
consisting of vertexes
3D Drawing attributes
Texture mapping with bi-linear filtering/automatic perspective correction and Gouraud shading
provides high-quality realistic 3D drawing. A built-in texture mapping unit performs fast pixel
calculations. This unit also delivers color blending between the shading color and texture color.
Hidden plane management
MB86296S supports the Z buffer for hidden plane management.
MB86296S
Specification Manual Rev1.0
12
FUJITSU LIMITED
1.4.8 Special effects
Anti-aliasing
Anti-aliasing manipulates line borders of polygons in sub-pixel units and blend the pre-drawing
pixel color with color to make the jaggies be seen smooth. It is used as a functional option for 2D
drawing (in direct color mode only).
Bold line and broken line drawing
This function draws lines of a specific width and a broken line.
Line Drawing Attributes
Attribute
Line width
Broken line
Description
Selectable from 1 to 32 pixels
Set by 32 bit or 24 bit of broken line pattern
• Supports the verticality of starting and ending points.
• Supports the verticality of broken line pattern.
• Interpolation of bold line joint supports the following modes:
(1) Broken line pattern reference address fix mode
→ The same broken line pattern is kept referencing for the period of some pixels starting from the
joint and the starting point for the next line.
(2) No interpolation
• Supports the equalization of the width of bold lines.
• Supports the bold line edging.
• Not support the Anti-aliasing of dashed line patterns.
• For a part overlaid due to connection of bold lines, natural overlay can be represented by providing
depth information. (Z value).
Shading
Supports the shading primitive.
Drawing is performed to the body primitive coordinates (X, Y) with an offset as a shade. At this
drawing, the Z buffer is used in order to differentiate between the body and shade.
MB86296S
Specification Manual Rev1.1
13
FUJITSU LIMITED
Alpha blending
Alpha blending blends two image colors to provide a transparent effect. CORAL supports two
types of blending; blending two different colors at drawing, and blending overlay planes at display.
Transparent color is not used for these blending options.
There are two ways of specifying alpha blending for drawing:
(1) Set a transparent coefficient to the register; the transparent coefficient is applied for
transparency processing of one plane.
(2) Set a transparent coefficient for each vertex of the plane; as with Gouraud shading, the
transparent coefficient is linear-interpolated to perform transparent processing in pixel units.
In addition to the above, the following settings can be performed at texture mapping. When the
most significant bit of each texture cell is 1, drawing or transparency can be set. When the most
significant bit of each texture cell is 0, non-drawing can be set.
Alpha Blending
Type
Description
Drawing
Transparent ratio set in particular register
While one primitive (polygon, pattern, etc.), being drawn,
registered transparent ratio applied
A transparent coefficient set for each vertex. A linearinterpolated transparent coefficient applied.
This is possible only in direct color mode.
Overlay display
Blends top layer pixel color with lower layer pixel color
Transparent coefficient set in particular register
Registered transparent coefficient applied during one frame
scan
Gouraud Shading
Gouraud shading can be used in the direct color mode to provide 3D object real shading and color
gradation.
Gray Scale Gouraud Shading
Gray scale gouraud shading can be used in the in-direct color mode to draw a blend coefficient
layer.
MB86296S
Specification Manual Rev1.0
14
FUJITSU LIMITED
Texture mapping
MB86296 supports texture mapping to map a image pattern onto the surface of plane. For 2D
pattern texture mapping, MB86296 has a built-in pattern memory for a field of up to 64 × 64 pixels
(at 16-bit color), which performs high-speed texture mapping. The texture pattern can also be laid
out in the graphics memory. In this case, max. 4096 × 4096 pixels can be used.
Drawing of 8-/16-bit direct color is supported for the texture pattern. For drawing 8-bit direct color,
only point sampling can be specified for texture interpolation; only decal can be specified for the
blend mode.
Texture Mapping
Function
Filtering
Coordinates correction
Blend
Alpha blend
Wrap
Description
Point sample
Bi-linear filter
Linear
Perspective
Decal
Modulate
Stencil
Normal
Stencil
Stencil alpha
Repeat
Cramp
Border
1.4.9 Others
Top-left rule non-applicable mode
In addition to the top-left rule applicable mode in which the triangle borders are compatible with
CREMSON, the top-left rule non-applicable mode can be used.
Caution: Use perspective correct mode when use texture at the top-left rule non-applicable mode.
Top-left rule non-applicable primitives cannot use Geometry clip function.
Non-top-left-part’s pixel quality is less than body. (using approximate calculation)
MB86296S
Specification Manual Rev1.1
15
FUJITSU LIMITED
2. PINS
2.1 Signals
2.1.1 Signal lines
GPIO0-4
EEPROM0-4
A D0-31
DCLKO
CBE0-3
DCKLI
PAR
HSYNC
FRAME
VSYNC
TRDY
CSYNC
IRDY
DISPE
STOP
GV
DEVSEL
Host CPU
interface
Video output
interface
R2-7
IDSEL
CORAL PA
Graphics Controller
PERR
G2-7
B2-7
XRGBEN
SERR
REQ
BGA256
GNT
MD0-63
MA0-14
PCLK
MRAS
XRST
MCAS
XINT
MWE
BC
Graphics memory
interface
MDQM0-7
TC
MCLKO
BEN
MCLKI
SB
CCLK
SDA
Clock
CLK
SCL
S
VI0-7
CKM
RI0-5
CLKSEL0-1
GI0-5
Video capture
interface
BI0-5
XRE
RGBCLK
COLSEL
TESTH
Fig. 2.1 CORAL PA Signal Lines
MB86296S
Specification Manual Rev1.0
16
Test
FUJITSU LIMITED
2.2 Pin Assignment
2.2.1 Pin assignment diagram
INDEX
T OP VIEW
BGA256
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
NC
COMR
VRO
COMG
AVS
XTST
DACT
VL
MD60
MD59
VL
MD57
MD54
MD53
MD50
MD46
MD44
MD41
MD38
VS
B
VSYN
GI3
GI0
AVS
AOR
AOG
AOB
SMCK
CCLK
MD61
MD56
VH
VL
MD49
MD45
MD42
MD40
MD35
MD34
DQM7
C
GV
GI4
GI2
GI1
VREF
AVD
AVD
AVD
MST
MD62
MD55
MD52
MD48
VH
VL
MD39
MD36
MD33
VH
DQM4
D
BC
DE
DCKI
VS
XRE
COMB
AVS
VS
XSM
MD63
MD58
MD51
VS
MD43
MD47
MD37
VS
MD32
E
REQ
DCKO
HSYN
VH
VS
DQM6 MCAS
F
ECK
EDO
CSYN
XINT
MA11
MW E
MA13
VH
G
RST
VS
SB
VL
VL
MA14
MA9
MA6
H
EE
ECS
VH
VS
VS
MA10
MA8
MA4
J
PCLK
EDI
VL
TC
VL
MA7
MA5
MA0
K
VS
GNT
BEN
VL
MA3
MA2
MA1
VL
L
VH
AD29
AD30
AD31
M
AD27
VH
AD28
VL
N
AD25
AD26
VS
P
IDSL
CBE3
R
AD22
T
T hermal Balls
In order to reduce heat,
please connect to GND
DQM5 MRAS
MA12
DQM2 MCKO DQM0 DQM3
VS
VL
VS
DQM1
VS
VS
MD28
MD31
VH
AD24
VL
MD23
VL
MD29
MCKI
AD23
VH
VH
MD27
MD21
MD25
MD30
AD19
AD20
AD21
VS
MD16
MD18
MD22
MD26
U
AD17
AD18
VH
VS
VS
VS
VL
VS
VL
VS
VH
PVD
VS
VL
VH
MD10
VS
VH
MD19
MD24
V
CBE2
AD16
DSEL
SERR
VH
AD14
AD11
AD08
AD07
AD04
VL
S
CSL1
MD2
MD5
MD8
MD12
MD13
MD15
MD20
W
FRM
IRDY
STOP
PAR
CBE1
AD13
AD10
VH
AD06
VH
AD02
PVS
VL
CSL0
MD1
MD4
MD7
MD11
MD14
MD17
Y
VS
TRDY
PERR
VH
AD15
AD12
AD09
CBE0
AD05
AD03
AD01
AD00
CKM
CLK
VS
MD0
MD3
MD6
MD9
VS
PCI Interface Pins
Memory I/f Pins
DAC Pins
Clock Pins
Other Host I/f Pins
Muxed Memory I/f Pins
Disp Pins
Capture Pins
Test Pins
MB86296S
Specification Manual Rev1.1
17
FUJITSU LIMITED
2.2.2 Pin assignment table
JEDEC Number Pin Name
B
2
GI3
C
2
GI4
D
E
B
3
4
1
DCKI
VH
VSYN
E
3
HSYN
D
C
F
E
D
G
G
2
1
3
2
4
4
3
DE
GV
CSYN
DCKO
VS
VL
SB
D
1
BC
F
2
EDO
E
F
1
4
REQ
XINT
H
G
F
3
2
1
VH
VS
ECK
H
2
ECS
J
4
TC
J
G
3
1
VL
XRST
MB86296S
Specification Manual Rev1.0
I/O
Input
Function
RGB Input Green[3]. May also be configured as
GPIO input.
Input
RGB Input Green[4]. May also be configured as
GPIO input.
Input
Video output interface dot clock input.
VDDH - 3.3V power supply.
I/O
Video output interface vertical sync output. Vertical
sync input in external sync mode.
I/O
Video output interface horizontal sync output.
Horizontal sync input in external sync mode.
Output Video output interface display enable period.
Output Video output interface graphics/video switch.
Output Video output interface composite sync output.
Output Video output interface dot clock signal for display.
VSS - ground.
VDDL 1.8V power supply.
I/O
Host interface Slave Busy signal. May also be
configured as GPIO input/output. In addition this
signal is used as RGB input Green[5] and serial
interface strobe depending on configuration.
I/O
Host interface Burst Complete signal. May also be
configured as GPIO input/output. In addition this
signal is used as RGB input Red[0].
I/O
PCI configuration EEPROM data output. May also
be configured as GPIO input/output. In addition this
signal is used as RGB input Red[1] and serial
interface data out depending on configuration.
Output PCI request.
Output External interrupt. By default (and PCI standard) it is
(open drain) active low. However it may be configured as active
high if desired.
VDDH 3.3V power supply.
VSS - ground.
I/O
PCI configuration EEPROM clock output. May also
be configured as GPIO input/output. In addition this
signal is used as RGB input Red[2] and serial
interface clock out depending on configuration.
I/O
PCI configuration EEPROM select output. May also
be configured as GPIO input/output. In addition this
signal is used as RGB input Red[3] depending on
configuration.
I/O
Host interface transfer complete. May also be
configured as GPIO input/output. Note that the state
of this pin is latched at external reset to help provide
initial I/O configuration. If it is in an active high state
then the EEPROM enable register bit is set.
VDDL 1.8V power supply.
Input
Device reset.
18
FUJITSU LIMITED
H
J
4
2
VS
EDI
I/O
H
1
EE
I/O
K
3
BEN
I/O
K
J
K
K
L
M
L
L
L
N
M
N
P
M
M
N
R
P
N
R
T
R
P
U
P
Y
T
R
V
U
T
W
T
V
2
1
4
1
1
1
2
3
4
1
2
4
1
3
4
2
1
2
3
4
1
2
3
1
4
1
2
3
1
2
3
1
4
2
GNT
PCLK
VL
VS
VH
AD27
AD29
AD30
AD31
AD25
VH
VS
IDSL
AD28
VL
AD26
AD22
CBE3
VS
VH
AD19
AD23
AD24
AD17
VL
VS
AD20
VH
CBE2
AD18
AD21
FRM
VS
AD16
Output
Input
I/O
I/O
I/O
I/O
I/O
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
MB86296S
Specification Manual Rev1.1
VSS - ground.
PCI configuration EEPROM data input. May also be
configured as GPIO input/output. In addition this
signal is used as RGB input Red[4] and serial
interface data in depending on configuration.
PCI configuration EEPROM enable. May also be
configured as GPIO input/output. In addition this
signal is used as RGB input Red[5] depending on
configuration.
Host interface burst enable used as an external
trigger of the host interface burst controller. May
also be configured as GPIO input/output. Note that
the state of this pin is latched at external reset to
help provide initial I/O configuration. If it is in an
active high state then the RGB input enable register
bit is set.
PCI grant.
PCI clock (33MHz).
VDDL 1.8V power supply.
VSS - ground.
VDDH 3.3V power supply.
PCI address/data bit 27.
PCI address/data bit 29.
PCI address/data bit 30.
PCI address/data bit 31.
PCI address/data bit 25.
VDDH 3.3V power supply.
VSS - ground.
PCI Initialisation Device Select (IDSEL).
PCI address/data bit 28.
VDDL 1.8V power supply.
PCI address/data bit 26.
PCI address/data bit 22.
PCI command/byte enable 3.
VSS - ground.
VDDH 3.3V power supply.
PCI address/data bit 19.
PCI address/data bit 23.
PCI address/data bit 24.
PCI address/data bit 17.
VDDL 1.8V power supply.
VSS - ground.
PCI address/data bit 20.
VDDH 3.3V power supply.
PCI command/byte enable 2.
PCI address/data bit 18.
PCI address/data bit 21.
PCI Frame.
VSS - ground.
PCI address/data bit 16.
19
FUJITSU LIMITED
U
V
W
W
V
3
3
2
3
4
VH
DSEL
IRDY
STOP
SERR
U
Y
V
W
Y
V
W
U
U
V
Y
W
Y
U
V
W
Y
W
U
V
Y
U
W
Y
V
W
Y
U
Y
Y
Y
W
V
U
Y
5
2
5
4
3
6
5
4
7
7
4
6
5
6
8
7
6
8
9
9
7
8
9
8
10
10
9
10
10
11
12
11
11
11
13
VS
TRDY
VH
PAR
PERR
AD14
CBE1
VS
VL
AD11
VH
AD13
AD15
VS
AD08
AD10
AD12
VH
VL
AD07
AD09
VS
AD06
CBE0
AD04
VH
AD05
VS
AD03
AD01
AD00
AD02
VL
VH
CKM
I/O
I/O
I/O
Output
VDDH 3.3V power supply.
PCI Device Select (DEVSEL).
PCI Initiator Ready.
PCI Stop.
PCI System Error.
(open drain)
W
12
PVS
U
13
VS
Y
14
CLK
V
12
S
U
12
PVD
W
13
VL
MB86296S
Specification Manual Rev1.0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input
Input
Input
-
VSS - ground.
PCI Target Ready.
VDDH 3.3V power supply.
PCI Parity.
PCI Parity Error.
PCI address/data bit 14.
PCI command/byte enable 1.
VSS - ground.
VDDL 1.8V power supply.
PCI address/data bit 11.
VDDH 3.3V power supply.
PCI address/data bit 13.
PCI address/data bit 15.
VSS - ground.
PCI address/data bit 8.
PCI address/data bit 10.
PCI address/data bit 12.
VDDH 3.3V power supply.
VDDL 1.8V power supply.
PCI address/data bit 7.
PCI address/data bit 9.
VSS - ground.
PCI address/data bit 6.
PCI command/byte enable 0.
PCI address/data bit 4.
VDDH 3.3V power supply.
PCI address/data bit 5.
VSS - ground.
PCI address/data bit 3.
PCI address/data bit 1.
PCI address/data bit 0.
PCI address/data bit 2.
VDDL 1.8V power supply.
VDDH 3.3V power supply.
Clock Mode. If low then the output from the internal
PLL is used as the internal clock. If high then the
PCI clock is used.
PLL Ground.
VSS - ground.
Clock input.
PLL reset.
PLL 1.8V power supply.
VDDL 1.8V power supply.
20
FUJITSU LIMITED
Y
W
V
U
Y
W
V
Y
U
Y
W
V
Y
W
V
Y
U
W
V
V
W
V
U
T
W
T
U
V
R
T
U
P
P
U
R
T
R
N
P
R
N
M
M
P
N
M
N
L
15
14
13
15
16
15
14
17
14
20
16
15
18
17
16
19
16
18
17
18
19
19
18
17
20
18
19
20
18
19
17
17
18
20
19
20
17
18
19
20
19
17
18
20
17
19
20
18
VS
CSL0
CSL1
VH
MD0
MD1
MD2
MD3
VL
VS
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
VH
MD16
MD17
MD18
MD19
MD20
MD21
MD22
VS
MD23
VL
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
VS
VL
MCKI
VS
VS
VH
MCKO
MB86296S
Specification Manual Rev1.1
Input
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input
Output
VSS - ground.
Clock rate selection 0.
Clock rate selection 1.
VDDH 3.3V power supply.
Graphics memory data bit 0.
Graphics memory data bit 1.
Graphics memory data bit 2.
Graphics memory data bit 3.
VDDL 1.8V power supply.
VSS – ground.
Graphics memory data bit 4.
Graphics memory data bit 5.
Graphics memory data bit 6.
Graphics memory data bit 7.
Graphics memory data bit 8.
Graphics memory data bit 9.
Graphics memory data bit 10.
Graphics memory data bit 11.
Graphics memory data bit 12.
Graphics memory data bit 13.
Graphics memory data bit 14.
Graphics memory data bit 15.
VDDH 3.3V power supply.
Graphics memory data bit 16.
Graphics memory data bit 17.
Graphics memory data bit 18.
Graphics memory data bit 19.
Graphics memory data bit 20.
Graphics memory data bit 21.
Graphics memory data bit 22.
VSS - ground.
Graphics memory data bit 23.
VDDL 1.8V power supply.
Graphics memory data bit 24.
Graphics memory data bit 25.
Graphics memory data bit 26.
Graphics memory data bit 27.
Graphics memory data bit 28.
Graphics memory data bit 29.
Graphics memory data bit 30.
Graphics memory data bit 31.
VSS - ground.
VDDL 1.8V power supply.
Graphics memory clock input.
VSS - ground.
VSS - ground.
VDDH 3.3V power supply.
Graphics memory clock output.
21
FUJITSU LIMITED
L
M
L
L
K
J
K
K
K
H
J
H
G
J
J
H
F
G
H
F
E
F
G
D
G
A
E
F
C
D
E
19
20
17
20
20
20
19
18
17
20
19
17
20
18
17
19
20
19
18
17
20
19
18
20
17
20
19
18
20
19
18
DQM0
DQM1
DQM2
DQM3
VL
MA0
MA1
MA2
MA3
MA4
MA5
VS
MA6
MA7
VL
MA8
VH
MA9
MA10
MA11
MA12
MA13
MA14
MRAS
VL
VS
MCAS
MWE
DQM4
DQM5
DQM6
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
B
20
DQM7
Output
E
C
D
17
19
18
VS
VH
MD32
I/O
C
18
MD33
I/O
B
19
MD34
I/O
B
18
MD35
I/O
C
17
MD36
I/O
D
16
MD37
I/O
A
19
MD38
I/O
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Specification Manual Rev1.0
Graphics memory data mask 0.
Graphics memory data mask 1.
Graphics memory data mask 2.
Graphics memory data mask 3.
VDDL 1.8V power supply.
Graphics memory address bit 0.
Graphics memory address bit 1.
Graphics memory address bit 2.
Graphics memory address bit 3.
Graphics memory address bit 4.
Graphics memory address bit 5.
VSS - ground.
Graphics memory address bit 6.
Graphics memory address bit 7.
VDDL 1.8V power supply.
Graphics memory address bit 8.
VDDH 3.3V power supply.
Graphics memory address bit 9.
Graphics memory address bit 10.
Graphics memory address bit 11.
Graphics memory address bit 12.
Graphics memory address bit 13.
Graphics memory address bit 14.
Graphics memory row address strobe.
VDDL 1.8V power supply.
VSS - ground.
Graphics memory column address strobe.
Graphics memory write enable.
Graphics memory data mask 4.
Graphics memory data mask 5.
Graphics memory data mask 6. May also be
configured as Blue[0] for the RGB output.
Graphics memory data mask 7. May also be
configured as Blue[1] for the RGB output.
VSS - ground.
VDDH 3.3V power supply.
Graphics memory data bit 32. May also be
configured as Blue[2] for the RGB output.
Graphics memory data bit 32. May also be
configured as Blue[3] for the RGB output.
Graphics memory data bit 32. May also be
configured as Blue[4] for the RGB output.
Graphics memory data bit 32. May also be
configured as Blue[5] for the RGB output.
Graphics memory data bit 32. May also be
configured as Blue[6] for the RGB output.
Graphics memory data bit 32. May also be
configured as Blue[7] for the RGB output.
Graphics memory data bit 32. May also be
configured as Green[0] for the RGB output.
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C
16
MD39
I/O
B
17
MD40
I/O
A
18
MD41
I/O
C
B
15
16
VL
MD42
I/O
D
D
17
14
VS
MD43
I/O
C
A
14
17
VH
MD44
I/O
B
15
MD45
I/O
A
16
MD46
I/O
D
15
MD47
I/O
C
13
MD48
I/O
B
14
MD49
I/O
A
15
MD50
I/O
B
D
13
12
VL
MD51
I/O
C
12
MD52
I/O
A
14
MD53
I/O
D
B
A
13
12
13
VS
VH
MD54
I/O
C
11
MD55
I/O
B
11
MD56
I/O
A
12
MD57
I/O
D
11
MD58
I/O
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Specification Manual Rev1.1
Graphics memory data bit 32. May also be
configured as Green[1] for the RGB output.
Graphics memory data bit 32. May also be
configured as Green[2] for the RGB output.
Graphics memory data bit 32. May also be
configured as Green[3] for the RGB output.
VDDL 1.8V power supply.
Graphics memory data bit 32. May also be
configured as Green[4] for the RGB output.
VSS - ground.
Graphics memory data bit 32. May also be
configured as Green[5] for the RGB output.
VDDH 3.3V power supply.
Graphics memory data bit 32. May also be
configured as Green[6] for the RGB output.
Graphics memory data bit 32. May also be
configured as Green[7] for the RGB output.
Graphics memory data bit 32. May also be
configured as Red[0] for the RGB output.R0
Graphics memory data bit 32. May also be
configured as Red[1] for the RGB output.R1
Graphics memory data bit 32. May also be
configured as Red[2] for the RGB output.R2
Graphics memory data bit 32. May also be
configured as Red[3] for the RGB output.R3
Graphics memory data bit 32. May also be
configured as Red[4] for the RGB output.R4
VDDL 1.8V power supply.
Graphics memory data bit 51. May also be
configured as Red[5] for the RGB output.R5
Graphics memory data bit 52. May also be
configured as Red[6] for the RGB output.R6
Graphics memory data bit 53. May also be
configured as Red[7] for the RGB output. R7
VSS - ground.
VDDH 3.3V power supply.
Graphics memory data bit 54. May also be
configured as I2C serial data (SDA).
Graphics memory data bit 55. May also be
configured as I2C serial clock (SCL).
Graphics memory data bit 56. May also be
configured as ITU-RBT-656 video capture data input
bit 0 (VI0). When the RGB input is enabled this pin
acts as Blue[0].
Graphics memory data bit 57. May also be
configured as ITU-RBT-656 video capture data input
bit 1 (VI1). When the RGB input is enabled this pin
acts as Blue[1].
Graphics memory data bit 58. May also be
configured as ITU-RBT-656 video capture data input
bit 2 (VI2). When the RGB input is enabled this pin
acts as Blue[2].
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A
A
11
10
VL
MD59
I/O
A
9
MD60
I/O
B
10
MD61
I/O
C
10
MD62
I/O
D
10
MD63
I/O
A
B
D
A
C
D
B
A
B
C
D
A
B
C
A
D
A
B
C
A
B
C
A
D
B
8
9
8
7
9
9
8
6
7
8
6
5
6
7
4
7
1
5
6
3
4
5
2
5
3
VL
CCLK
VS
DACT
MST
XSM
SMCK
XTST
AOB
AVD2
COMB
AVS2
AOG
AVD1
COMG
AVS1
NC
AOR
AVD0
VRO
AVS0
VREF
COMR
XRE
GI0
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Input
Output
Input
GI0
C
4
GI1
GI1
C
3
GI2
GI2
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Specification Manual Rev1.0
VDDL 1.8V power supply.
Graphics memory data bit 59. May also be
configured as ITU-RBT-656 video capture data input
bit 3 (VI3). When the RGB input is enabled this pin
acts as Blue[3].
Graphics memory data bit 60. May also be
configured as ITU-RBT-656 video capture data input
bit 4 (VI4). When the RGB input is enabled this pin
acts as Blue[4].
Graphics memory data bit 61. May also be
configured as ITU-RBT-656 video capture data input
bit 5 (VI5). When the RGB input is enabled this pin
acts as Blue[5].
Graphics memory data bit 62. May also be
configured as ITU-RBT-656 video capture data input
bit 6 (VI6). When the RGB input is enabled this pin
acts as HSYNC.
Graphics memory data bit 63. May also be
configured as ITU-RBT-656 video capture data input
bit 7 (VI7). When the RGB input is enabled this pin
acts as VSYNC.
VDDL 1.8V power supply.
ITU-RBT-656 video capture clock input.
VSS - ground.
Test signal.
Test signal.
Test Signal.
Test Signal.
Test Signal.
Analog Signal (B) output
Analog Power Supply(3.3V)
Analog B Signal Compensation pin
Analog Ground
Analog Singnal (G) output
Analog Power Supply(3.3V)
Analog G Signal Compensation pin
Analog Ground
Not connected.
Analog Singnal (R) output
Analog Power Supply(3.3V)
Analog Reference current output
Analog Ground
Analog Reference Voltage input
Analog R Signal Compensation pin
RGB output/video input/I2C enable.
RGB Input Green[0]. May also be configured as
GPIO input.
RGB Input Green[1]. May also be configured as
GPIO input.
RGB Input Green[2]. May also be configured as
GPIO input.
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Notes
VSS/PLLVSS
: Ground
VDDH
: 3.3-V power supply
VDDL/PLLVDD
: 1.8-V power supply
PLLVDD
: PLL power supply (1.8 V)
OPEN
: Do not connect anything.
TESTH
: Input a 3.3 V-power supply.
AVS
: Analog Ground
AVD
: Analog power supply (3.3 V)
- It is recommended that PLLVDD should be isolated on the PCB.
- It is recommended that AVD should be isolated on the PCB.
- Insert a bypass capacitor with good high frequency characteristics between the power supply and
ground.
Place the capacitor as near as possible to the pin.
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2.3 Pin Function
2.3.1 Host CPU interface
Table 2-1 Host CPU Interface Pins
Pin name
I/O
Description
AD0-31
In/Out
PCI Address/Data
CBE0-3
In/Out
PCI Bus Command/Byte Enable
PAR
In/Out
PCI Parity
FRM
In/Out
PCI Cycle Frame
TRDY
In/Out
PCI Target Ready
IRDY
In/Out
PCI Initiator Ready
STOP
In/Out
PCI Stop
DSEL
In/Out
PCI Device Select
IDSEL
Input
PCI Initialisation Device Select
PERR
In/Out
PCI Parity Error
SERR
Output
(Open Drain)
System Error
REQ
Output
PCI Bus Master Request
GNT
Input
PCI Bus Grant
PCLK
Input
PCI Clock – 33MHz
XRST
Input
System Reset (including PCI)
XINT
Output
(Open Drain)
Interrupt
BC
Output
Burst Complete. Indicates a burst is complete when using
the DMA/Burst Controller.
This pin may also be configured as a GPIO Input/Output and
acts as RI0 (Red Input 0) when the RGB Input is enabled.
TC
Output
Transfer Complete. Indicates that a whole transfer is
complete when using the DMA/Burst Controller.
This may also be configured as a GPIO Input/Output.
In addition this pin may be used to automatically enable the
EEPROM at the reset phase. To do this a pull up should be
applied.
BEN
Input
Enables the Burst Controller to start/continue execution.
This pin may also be configured as a GPIO Input/Output.
In addition this pin may be used to automatically enable the
RGB Input pins as RGB inputs. To do this a pull up should
be applied.
SB
Output
Slave Busy. Indicates that the PCI Slave is busy completing
a write transfer.
This pin may also be configured as a GPIO Input/Output, the
Serial Interface Strobe Output and acts as GI5 (Green Input
5) when the RGB Input is enabled.
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EE
Input
EEPROM Enable. Enables the PCI EEPROM Configuration.
This pin may also be configured as a GPIO Input/Output and
acts as RI5 (Red Input 5) when the RGB Input is enabled.
ECS
Output
EEPROM Chip Select . This pin may also be configured as a
GPIO Input/Output and acts as RI3 (Red Input 3) when the
RGB Input is enabled.
ECK
Output
EEPROM Clock. This pin may also be configured as a GPIO
Input/Output, the Serial Interface clock Output and acts as
RI2 (Red Input 2) when the RGB Input is enabled.
EDO
Output
EEPROM Data Out. This pin may also be configured as a
GPIO Input/Output, the Serial Interface Data Output and
acts as RI1 (Red Input 1) when the RGB Input is enabled.
EDI
Input
EEPROM Data In. This pin may also be configured as a
GPIO Input/Output, the Serial Interface Data Input and acts
as RI4 (Red Input 4) when the RGB Input is enabled.
GI0-4
Input
GPIO Inputs. These pins also act as GI0-4 (Green Inputs 04) when the RGB Input is enabled.
The EE, ECK, ECS, EDO, EDI, BC, TC, SB and BEN signals can all be configured as GPIO
inputs/outputs and default to GPIO inputs at reset unless otherwise specified by the reset control pins
(TC, BEN) which can be used to enable the EEPROM or the RGB input. The GI0-4 signals can be
GPIO inputs only, which is their default state unless the RGB input is enabled in which case they are
used as Green[0-4].
The Host Interface also has a serial interface function built in. This uses the EDI/EDO signals as data
in/out, the ECK pin as a serial clock output and the SB pin as a strobe output. The serial interface may
only be used when neither the EEPROM nor the RGB input is in use.
Once the device has been reset all configuration of the host interface related pins is done using the IO
Mode register (IOM).
Note that to enable the RGB input the XRE signal must be active low and also the appropriate register
in the capture engine must be configured.
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2.3.2 Video output interface
Table 2-2 Video Output Interface Pins
Pin name
DCKO
DCKI
HSYN
Output
Input
I/O
I/O
VSYN
I/O
CSYN
DE
GV
R7-0
Output
Output
Output
Output
G7-0
Output
B7-0
Output
XRE
Input
AOR
AOG
AOB
COMR
COMG
COMB
VREF
VRO
Analog Output
Analog Output
Analog Output
Analog
Analog
Analog
Analog
Analog
Description
Dot clock signal for display
Dot clock signal input
Horizontal sync signal output
Horizontal sync input
Vertical sync signal output
Vertical sync input
Composite sync signal output
Display enable period signal
Graphics/video switch
Digital picture (R) output. . These pins are multiplexed
MD53-46. These pins are available when XRE=0.
Digital picture (G) output. . These pins are multiplexed
MD45-38. These pins are available when XRE=0.
Digital picture (B) output. These pins are multiplexed MD3732 and DQM7-6. These pins are available when XRE=0.
Signal to switch between digital RGB output, capture signals
/memory bus (MD 63-32, DQM7-6)
Analog Signal (R) output
Analog Signal (G) output
Analog Signal (B) output
Analog (R) Compensation output
Analog (G) Compensation output
Analog (B) Compensation output
Analog Voltage Reference input
Analog Reference Current output
It is possible to output digital RGB when XRE = 0 (Memory bus = 32bit).
Additional setting of external circuits can generate composite video signal.
Synchronous to external video signal display can be performed.
Either mode which is synchronous to DCLKI signal or one which is synchronous to dot clock, as for
normal display can be selected.
Since HSYNC and VSYNC signals are set to input state after reset, these signals must be pulled up
LSI externally.
The GV signal switches graphics and video at chroma key operation. When video is selected, the
“Low” level is output.
AOR, AOG and AOB must be terminated at 75 ohm.
1.1 V is input to VREF. A bypass capacitor ( with good high-frequency characteristics ) must be
inserted between VREF and AVS.
COMR, COMG and COMB are tied to analog VDD via 0.1 uF ceramic capacitors.
VRO must be pulled down to analog ground by a 2.7 k ohm resister.
When not using DAC, it is possible to connect all of analog pins(AVD, AOUTR,G,B, ACOMPR,G,B,
VREF, VRO) to GND.
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The 16bit/pixel color mode and 8bit/pixel color mode are converted to digital R:G:B=8:8:8 as the below.
A) 16bit/pixel color mode
R:G:B=5:5:5 data
Digital
in graphics memory
R:G:B=8:8:8
0
0
1-31
Add 111 to lower 3bits
Formula=X*8+7
B) 8bit/pixel color mode
R:G:B=6:6:6 data
Digital
in color palette
R:G:B=8:8:8
0
0
1-63
Add 11 to lower 2bits
Formula=X*4+3
The Y,Cb,Cr mode is converted to R:G:B=8:8:8 directly.
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2.3.3 Video capture interface
1. ITU-656 Input Signals
Table 2-3 Video Capture Interface Pins
Pin name
I/O
CCLK
Input
VI7-0
Input
Description
Digital video input clock signal input
ITU656 Digital video data input. These pins are multiplexed MD63MD56.
Inputs ITU-RBT-656 format digital video signal
Digital video data input can be used only when the XRE pin is “0”. MD63-MD56 are assigned as
the digital video data input pins.
When video capture is not used and the XRE pin is 0, input the “High” level to MD63-MD56.
2. RGB Input Signals
The signals used for video capture are not assigned on dedicated pins but share the same pins
with other functions. There is a set of signals corresponding to the RGB capture modes.
Direct Input Mode
Pin name
I/O
Description
RGBCLK
Input
Clock for RGB input. This pin is multiplexed CCLK.
RI5-0
Input
Red component value. These pins are multiplexed EE, EDI, ECS,
ECK, EDO and BC.
GI5-0
Input
Green component value. These pins are multiplexed SB and GPI4GPI0.
BI5-0
Input
Blue component value. These pins are multiplexed MD61-MD56.
VSYNCI
Input
Vertical sync for RGB capture. This pin is multiplexed MD63.
HSYNCI
Input
Horizontal sync for RGB capture. This pin is multiplexed MD62.
Note :
- the RGB bit of VCM(video capture mode) register enables RGB input mode of video
capture.
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2.3.4 I2C interface
Pin name
I/O
SDA
I/O
SCL
I/O
Description
2
I C or Video capture test signal. This pin is
multiplexed MD54.
2
I C or Video capture test signal. This pin is
multiplexed MD55.
I2C interface signals can be used only when the XRE pin is “0”. MD55-MD54 are assigned as the
I2C interface pins.
When I2C interface is not used and the XRE pin is 0, input the “High” level to MD63-MD56.
Note)
Input voltage level is 3.3V. Please be careful, it does not support to 5V input.
(The device whose output voltage is 5V is not connectable.)
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2.3.5 Graphics memory interface
Graphics memory interface pins
Pin name
I/O
Description
MD31 - MD0
I/O
Graphics memory bus data
MD53 - MD32
I/O
Graphics memory bus data or digital R7-0, G7-0,
B7-2 output (when XRE = 0)
MD55 - MD54
I/O
Graphics memory bus data or SCL, SDA (when
XRE=0)
MD63 - MD56
I/O
Graphics memory bus data or video input (when
XRE=0)
MA0 to 14
Output
Graphics memory bus data
MRAS
Output
Row address strobe
MCAS
Output
Column address strobe
MWE
Output
Write enable
DQM5 - DQM0
Output
Data mask
DQM7 - DQM6
Output
Data mask or digital B1-0 output (when XRE = 0)
MCLK0
Output
Graphics memory clock output
MCLK1
Input
Graphics memory clock input
Connect the interface to the external memory used as memory for image data. The interface can
be connected to 64-/128-/256-Mbit SD RAM (16- or 32-bit length data bus) without using any
external circuit.
64 bits or 32 bits can be selected for the memory bus data. .
Connect MCLKI to MCLK0.
When XRE is fixed at “1”, MD63 - MD32 and DQM7 - DQM6 can be used as graphics memory
interface.
When XRE is fixed at “0”, these signals can be used as digital RGB output and digital video data
input.
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2.3.6 Clock input
Table 2-4 Clock Input Pins
Pin name
I/O
Description
CLK
Input
Clock input signal
S
Input
PLL reset signal
CKM
Input
Clock mode signal
CSL [1:0]
Input
Clock rate select signal
Inputs source clock for internal operation clock and display dot clock. Normally, 4 Fsc (= 14.31818
MHz: NTSC) is input. An internal PLL generates the internal operation clock of 166 MHz/133 MHz
and the display base clock of 400 MHz. Even if don’t use an internal PLL (use BCLKI as internal clock
and use DCLKI as dot clock), don’t stop the PLL (Not fixed the S pin to low level).
CKM
Clock mode
L
Output from internal PLL selected
H
PCI bus clock selected
• When CKM = L, selects input clock frequency when built-in PLL used according to setting of CSL
pins
CSL1
CSL0
Input clock
frequency
Multiplication
rate
Display
reference clock
L
L
Inputs 13.5-MHz
clock frequency
× 29
391.5 MHz
L
H
Inputs 14.32-MHz
clock frequency
× 28
400.96 MHz
H
L
Inputs 17.73-MHz
clock frequency
× 22
390.06 MHz
H
H
Inputs 33.33-MHz
clock frequency
× 12
399.96
Please connect the crystal oscillator directly with the terminal CLK.
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2.3.7 Test pins
Table 2-5 Test Pins
Pin name
TESTH
I/O
Input
Description
Input 3.3-V power.
2.3.8 Reset sequence
See Section 15.3.2.
2.3.9 How to switch internal operating frequency
• Switch the operating frequency immediately after a reset (before rewriting MMR mode register of
external memory interface).
• Any operating frequency can be selected from the five combinations shown in Table 2-6.
Table 2-6 Frequency Setting Combinations
Clock for geometry engine
Clock for other than geometry engine
166 MHz
133 MHz
166 MHz
100 MHz
133 MHz
133 MHz
133 MHz
100 MHz
100 MHz
100 MHz
• The following relationship is disabled: Clock for geometry engine < Clock for other than geometry
engine
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3. PROCEDURE OF THE HARDWARE INITIALIZATION
3.1. Hardware reset
1.Do the hardware reset. (see section 15.3.2)
2.After the hardware reset, set the CCF(Change of Frequency) register (section 13.2.1).
In being unstable cycle after the hardware reset, keep 32 bus cycles open.
3.Set the graphics memory interface register, MMR (Memory I/F Mode Register).
After setting the CCF register, take 200 us to set the MMR register.
In being unstable memory access cycle, keep 32 bus cycles open.
4.Other registers, except for the CCF register and the MMR register, should be set after
setting the CCF register.
In case of not using memory access, the MMR register could be set in any order after
the CCF register is set.
3.2. Re-reset
1. Reset XRST signal.
2. See section 3.1 for registers setting after the procedure of re-reset.
3.3. Software reset
1. Set the value of the SRST register (see section 13.2.1) for re-reset.
2. It is not necessary to reset the CCF register and the MMR register again.
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4. HOST INTERFACE
The Coral PA has a 33MHz, 32-bit PCI host interface compliant to PCI version 2.1. It includes both
PCI master and PCI slave functions and an internal DMA/burst controller for multi-burst transfers of
large quantities of data between all combinations of PCI data space and Coral PA internal data space.
PCI EEPROM configuration is also supported.
Additional functions provided by the host interface are optional host interface status/control signals
which may aid in the reduction of PCI retries, the provision of general purpose IO (GPIO) signals for
control of external devices via the PCI interface including support for a simple serial interface.
4.1 Standard PCI Slave Accesses
An external PCI master will access the Coral PA as a PCI slave.
4.1.1 PCI Slave Write
For a PCI slave write, data will be “posted” into a temporary buffer from where it is written to the target
internal client. This temporary buffer is 16 dwords deep. PCI slave writes of any size are supported but
typically a retry will occur after each 16 dword burst. Note that when writing to the display list FIFO a
burst should be no more than 16 dwords (64 bytes) due to FIFO address space limitations.
When the write from the temporary buffer to the internal client is being performed the Slave Busy (SB)
signal becomes active. While this is happening PCI accesses will be rejected. If the SB signal is used
then PCI retries may be reduced.
Coral PA does not perform any fast back to back transactions.
4.1.2 PCI Slave Read
For a PCI slave read the read requested will be passed to an internal client from where data will be
fetched into the temporary buffer (8 dwords deep). Typically a retry will occur to actually fetch the data.
In order to fetch the correct number of words from the read address the burst size must be specified.
This is done by writing to the Slave Burst Read Size (SRBS) register. Bursts of between 1 and 8
dwords are supported. If the PCI master retries and reads less than the specified burst size then the
remaining dwords will be discarded. This means that the Slave Burst Read Size can be permanently
configured as 8 dwords. However there will be an increased latency on the pre-fetch stage if this is
done.
Note: Data is not guaranteed when the burst transfer more than the burst length set as the SRBS
register is performed.
4.2 Burst Controller Accesses (including PCI Master)
The Coral PA host interface includes a burst controller which can be used for transferring large
quantities of contiguous data between all combinations (source/destination) of PCI data space and
Coral PA internal data space. Control/status monitoring is done through internal registers with the
optional aid of external signals – Burst Complete (BC), Transfer Complete (TC) and Burst Enable
(BEN).
A transfer can be any number of dwords from 1 to 16777215 (224-1) dwords, split up into a number of
individual bursts of size from 1 to 8 dwords. However, as for burst length, it is set to 2-8 only at the
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time of “Slave Mode Coral PA to PCI” mentioned later. If the transfer size is not an integer multiple of
the burst size then the final burst of the transfer will be less than the configured burst size. A transfer is
from a source address to a destination address with the source/destination being in either PCI or Coral
PA data space as appropriate to the transfer mode. After each burst of a transfer the source and/or
the destination address may be incremented (or not) by the burst size enabling transfers both to/from
memory and also FIFO-like sources/destinations. Note that when writing to the display list FIFO, the
destination address should be configured to not increment between bursts.
4.2.1
Transfer Modes
There are 6 transfer modes configurable through the Burst Setup Register (BSR). These are:
Mode
Function
000b
Slave Mode PCI to Coral PA. In this mode a PCI master writes bursts of data directly into a
temporary buffer from where it is transferred to the destination address by the Burst
Controller. While this can also be accomplished using simple PCI Slave writes there are
benefits in using this mode when transferring large quantities of data. For a normal PCI
write the Coral PA PCI slave interface is blocked until the write to the destination address
has completed. Depending on the destination there may be some delay in doing this. Using
the burst controller the data is transferred out of the PCI interface into the temporary buffer
from where it is transferred to the destination. In this case the PCI slave interface is quickly
cleared and so other operations can take place or the next burst can be written in.
001b
Slave Mode Coral PA to PCI. In this mode the burst controller reads data from a Coral PA
internal address into its temporary buffer and then waits for the data to be read using a PCI
slave read from this buffer’s address. While this can also be accomplished using simple
PCI Slave reads there are benefits in using this mode when transferring large quantities of
data. A normal PCI read will typically be accomplished by a PCI read request followed by a
retry to fetch the data. Using this mode the burst controller can be used to automatically
fetch the next data to be read. Depending on internal latencies this should reduce the
number of retries.
010b
Coral PA to Coral PA. In this mode data is read from a source address internal to Coral PA
into a temporary buffer, from where it is written to a destination, also internal to Coral PA.
An example of where this mode may be used is to transfer display list data from graphics
memory to the display list FIFO.
011b
Reserved.
100b
PCI to Coral PA (PCI Master read). In this mode the source address is in PCI data space
and the destination address internal to Coral PA. For each burst of the transfer “burst size”
dwords of data are read as a PCI Master read into a temporary buffer, from where they are
written to the internal destination address. An example of where this mode will be used is
display list transfer to the FIFO/graphics memory.
101b
Coral PA to PCI (PCI Master write). In this mode the source address is internal to Coral PA
and the destination address is in PCI data space. For each burst of the transfer “burst size”
dwords of data are fetched from an internal address into a temporary buffer, from where
they are written to the destination address using a PCI master write. An example of where
this mode may be used is to transfer graphics memory data to external PCI memory.
110b
PCI to PCI (PCI Master read/write). This mode is effectively a PCI to PCI DMA. Data is
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read from a source address in PCI data space into a temporary buffer from where it is
written to the destination address, also in PCI data space.
111b
Reserved.
The figure below illustrates a PCI to Coral (Master Read) transfer. The Host CPU will program up the
BCU registers (using normal PCI Slave writes) and trigger the transfer. The Coral then reads data from
the source memory as a PCI Master and writes to the destination inside the Coral.
Coral PA
Memory
(PCI Slave)
3) Onward transfer
2) Master Read
from source
RAM
PCI Bus
BCU
to destination
Internal Bus
1) Slave Write to
Host CPU
(PCI Master)
setup transfer
All other BCU transfers use the BCU RAM in a similar way but with source/destination dependent on
transfer type.
When Coral PA is master (bcu mode: 100b, 101b, 110b), Coral PA cannot issue an odd address to
PCI area. If the beginning address is set to the odd address in 64-bit boundary, Coral PA issues the
previous even address. Note: The odd address in 64-bit boundary means 0x004, 0x00C, 0x014….
In master read, Coral PA begins to read the previous even address and read the setting of burst size
(BSIZE of BCR register) plus 1.
In master write, Coral PA begins to write the previous even address with disable write byte enable and
write the setting of burst size (BSIZE of BCR register) plus 1.
4.2.2
Burst Controller Control/Status
All setup/control and status for the burst controller can be done through registers. These provide ways
of specifying the parameters for a burst (source/destination address, address increment (or not) and
burst/transfer size. In addition, a transfer can be started/paused/aborted and also its progress
monitored using the enable and status registers.
The key status indicators are Burst Complete and Transfer Complete, which become active at the end
of each burst/transfer respectively. These may either be active high or toggle state at the end of each
burst/transfer. When active high they will have to be cleared after each burst/transfer. This may be
done using a clear on read mode (default) or by manually writing to the appropriate register.
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The burst/transfer complete indications are also available though the main interrupt status register
(IST) and can trigger the main external interrupt (XINT). If being used for this they must be configured
as active high (ie. not toggle mode). In addition burst/transfer complete can be made available as
external signals (BC/TC) for connection directly to an external device (eg. through some form of GPIO
or interrupt).
Normally a transfer will be configured and enabled using internal registers. However it is possible to
configure the transfer but not actually start it. An external signal (BEN) can then be used to trigger the
transfer and pause it between bursts. This may be useful, for example, when doing PCI Master reads
from a client which takes time to pre-fetch more data for the next burst.
4.3 FIFO Transfers
Unlike Coral LQ/Coral LB there are no specific transfer mechanisms to write data into the display list
FIFO. A write to the FIFO interface occurs automatically when it is specified as a destination address
either for a PCI Slave Write or in a Burst Controller transfer. If this is not desired, and the main internal
bus should be used, then the Override FIFO Use register may be set. Under normal circumstances
there should be no need to use this feature.
As previously stated when the FIFO address is specified as the destination in the Burst Controller the
destination should not be incremented after each burst. This will not happen automatically and must
be specifically configured. In addition when writing to the FIFO using a PCI Slave Write the FIFO
address space is limited to 16 dwords (64 bytes). This means that a PCI Slave Write burst to the FIFO
must not be more than 16 dwords, otherwise data will be written to invalid locations for retries after 2
bursts of 8 dwords.
4.4 GPIO/Serial Interface
The Host Interface supports optional register mapped General Purpose IO (GPIO) and Serial Interface
functions.
4.4.1 GPIO
Depending on configuration there are up to 14 GPIO signals. 5 of these (GI0, GI1, GI2, GI3, GI4) are
inputs only. The remainder (BEN,SB,TC,BC,EE,ECS,ECK,EDI, EDO) may be either input or output. All
reset to GPIO inputs unless otherwise configured using the reset configuration mechanism to enable
the EEPROM/RGB input.
Operation of the GPIO is simply through the reading of the GPIO Data (GD) register for GPIO Inputs
and writing to this register (with write mask) for the GPIO Outputs. GPIO Inputs may be configured
selectively to trigger an external interrupt (via the interrupt status register (IST)) when they change
state (0->1 or 1->0 transition).
4.4.2 Serial Interface
A simple serial interface is available depending on configuration. This uses the EDI/EDO pins as serial
data input/output, the ECK as the serial clock output and SB as the serial interface strobe. The serial
data out signal may be tri-stated when not in use.
Up to 8 bits of data is shifted out/in based on the serial clock. This may be 1/16, 1/32, 1/64 or 1/128 of the
main internal clock. The clock polarity may be specified to be high/low and it may be gated when the
serial interface is inactive.
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The strobe signal has configurable polarity and may be active only for the first cycle of a transfer or the
complete transfer. It may also be disabled completely. Configured strobe settings may be overridden
on a transfer by transfer basis if required.
An interrupt may be generated when a transfer is complete.
4.5 Interrupt
The Coral PA MB86296 issues interrupt requests to the host CPU. The following interrupt triggers
may enabled/disabled using the Interrupt Mask Register (IMASK).
• Vertical synchronization detect
• Field synchronization detect
• External synchronization error detect
• Register update
• Drawing command error
• Drawing command execution end
• Internal Bus/FIFO Timeout
• Serial Interface transfer complete
• GPIO input change
• Burst Complete
• Transfer Complete
• Host Interface Fatal (PCI error)
• Address Error (invalid address accessed)
In addition the I2C interface can trigger an interrupt, but this is non-maskable through the IMASK
register.
By default the external interrupt is active low (PCI standard) and is open drain. If required it may be
configured to be active high using the Interrupt Polarity (IP) register.
Once an interrupt is detected by the host it can read the interrupt status register (IST) to determine the
source of the interrupt. The exception to this is the I2C interrupt. Once read the interrupt status register
must be cleared by writing 0 to the appropriate bit/bits (selective clearing is possible). Note that the
Burst Complete/Transfer Complete interrupts must be cleared by writing to the Burst Status (BST)
register.
4.5.1 Address Error Interrupt
Certain addresses are invalid depending on operation. For example the Burst Controller cannot
access the Host Interface internal registers. If an attempt is made to do this then the access will be
terminated and an Address Error Interrupt triggered.
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4.6 Memory Map
The local memory base address of Coral-PA is determined by Memory Base Address Register 0 (PCI
Byte Address=0x10) in PCI Configuration Registers.
The following shows the local memory map of Coral PA to the host CPU memory space.
Note: Burst read which follows a Host interface registers from a Graphics memory domain and follows
a Graphics memory domain from a Geometry Engine registers is prohibition.
Ex.)Bust size=8 don’t read 1fbffe4-1fbfffc and 1ffffe4-1fffffc
64 MB Space
32 MB to 256 KB
256 KB
32 MB
Graphics
memory
area
0000000 to 1FBFFFF
Register area
1FC0000 to 1FFFFFF
Graphics
memory
area
2000000 to 3FFFFFF
Fig. 3.1 Memory Map
Table 3-4 Address Space
Size
Resource
Base address
(Name)
32 MB to 256 KB
Graphics Memory
00000000
64 KB
Host interface registers
2
(I C interface registers)
01FC0000
(01FCC000)
(HostBase)
(I2CBase)
32 KB
Display registers
01FD0000
(DisplayBase)
32 KB
Video capture registers
01FD8000
(CaptureBase)
64 KB
Internal texture memory
01FE0000
(TextureBase)
32 KB
Drawing registers
01FF0000
(DrawBase)
32 KB
Geometry engine registers
01FF8000
(GeometryBase)
32 MB
Graphics memory
02000000
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If required the register area can be moved by writing 1 to bit 0 at HostBase + 005Ch (RSW: Register
location Switch). In the initial state, the register space is at the center (1FC0000) of the 64 MB space.
Coral PA may be accessed after about 20 bus clocks after writing 1 to RSW.
Note: Burst read which follows a Host interface registers from a Graphics memory domain is
prohibition.
Ex.)Bust size=8 don’t read 3fbffe4-3fbfffc
64 MB space
32 MB
Graphics memory
area
0000000 to 1FFFFFF
32 MB to 256 KB
Graphics memory
area
2000000 to 3FBFFFF
256 KB
Register area
3FC0000 to 3FFFFFF
Fig. 3.2 Alternate Memory Map
Table 3-5 Alternate Address Mapping
Size
Resource
Base address
(Name)
64 MB to 256 KB
Graphics memory
00000000
64 KB
Host interface registers
2
(I C interface registers)
03FC0000
(03FCC000)
(HostBase)
(I2CBase)
32 KB
Display registers
03FD0000
(DisplayBase)
32 KB
Video capture registers
03FD8000
(CaptureBase)
64 KB
Internal texture memory
03FE0000
(TextureBase)
32 KB
Drawing registers
03FF0000
(DrawBase)
32 KB
Geometry engine registers
03FF8000
(GeometryBase)
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5. I2C Interface Controller
5.1 Features
- Master transmission and receipt
- Slave transmission and receipt
- Arbitration
- Clock synchronization
- Detection of slave address
- Detection of general call address
- Detection of transfer direction
- Repeated generation and detection of START condition
- Detection of bus error
- Correspondence to standard-mode (100kbit/s ) / high-speed-mode (400kbit/s)
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5.2 Block diagram
5.2.1 Block Diagram
SDA
SCL
START condition/ST OP condition
detecting circuit
noise filter
ADR
Comparater
Host Bus
DAR
Host IF
BSR
BCR
CCR
Arbitration Lost
detecting circuit
START condition/ST OP condition
generating circuit
Shift Clock
generating circuit
I2C UNIT
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5.2.2 Block Function Overview
START condition / STOP condition detecting circuit
This circuit performs detection of START condition and STOP condition from the state of SDA
and SCL.
START condition / STOP condition generating circuit
This circuit performs generation of START condition and STOP condition by changing the state of
SDA and SCL.
Arbitration Lost detecting circuit
This circuit compares the data output to SDA line with the data input into SDA line at the time of
data transmission, and it checks whether these data is in agreement. When not in agreement, it
generates arbitration lost.
Shift Clock generating circuit
This circuit performs generating timing count of the clock for serial data transfer, and output
control of SCL clock by setup of a clock control register.
Comparater
Comparater compares whether the received address and the self-address appointed to be the
address register is in agreement, and whether the received address is a global address.
ADR
ADR is the 7-bit register which appoints a slave address.
DAR
DAR is the 8-bit register used by serial data transfer.
BSR
BSR is the 8-bit register for the state of I2C bus etc. This register has following functions:
- detection of repeated START condition
- detection of arbitration lost
- storage of acknowledge bit
- data transfer direction
- detection of addressing
- detection of general call address
- detection of the 1st byte
BCR
BCR is the 8-bit register which performs control and interruption of I2C bus. This register has
following functions:
- request / permission of interruption
- generation of START condition
- selection of master / slave
- permission to generate acknowledge
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CCR
CCR is the 7-bit register used by serial data transfer. This register has following functions:
- permission of operation
- setup of a serial clock frequency
- selection of standard-mode / high-speed-mode
Noise filter
This noise filter consists of a 3 step shift register. When all three value that carried out the
continuation sampling of the SCL/SDA input signals is “1”, the filter output is “1”. Conversely
when all three value is “0”, the filter output is “0”. To other samplings it holds the state before 1
clock.
5.3 Example application
5.3.1 Connection Diagram
3.3V
CORAL
Slave Device
SDA
SDA
SCL
SCL
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5.4 Function overview
Two bi-directional buses, serial data line (SDA) and serial clock line (SCL), carry information at I2Cbus. Scarlet I2C interface has SDA input (SDAI) and SDA output (SDAO) for SDA and is connected to
SDA line via open-drain I/O cell. And this interface also has SCL input (SCLI) and SCL output (SCLO)
for SCL line and is connected to SCL line via open-drain I/O cell. The wired theory is used when the
interface is connected to SDA line and SCL line.
5.4.1 START condition
If “1” is written to MSS bit while the bus is free, this module will become a master mode and will
generate START condition simultaneously. In a master mode, even if a bus is in a use state (BB=1),
START condition can be generated again by writing “1” to SCC bit.
There are two conditions to generate START condition.
- “1” writing to MSS bit in the state where the bus is not used (MSS=0 & BB=0 & INT=0 & AL=0)
- “1” writing to SCC bit in the interruption state in a master mode (MSS=1 & BB=1 & INT=1 & AL=0)
If “1” writing is performed to MSS bit in an idol state, AL bit will be set to “1”. “1” writing to MSS bit
other than the above is disregarded.
SDA
SCL
START condition
5.4.2 STOP condition
If “0” is written to MSS bit in a master mode (MSS=1), this module will generate STOP condition and
will become a slave mode.
There is a condition to generate STOP condition.
- “0” writing to MSS bit in the interruption state in a master mode (MSS=1 & BB=1 & INT=1 & AL=0)
“0” writing to MSS bit other than the above is disregarded.
SDA
SCL
STOP condition
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5.4.3 Addressing
In a master mode, it is set to BB=”1” and TRX=”0” after generation of START condition, and the
contents of DAR register are output from MSB. When this module receives acknowledge after
transmission of address data, the bit-0 of transmitting data (bit-0 of DRA register after transmission) is
reversed and it is stored in TRX bit.
- Transfer format of slave address
A transfer format of slave address is shown below:
MSB
A6
A5
A4
A3
slave address
A2
A1
A0
LSB
R/W
ACK
- Map of slave address
A map of slave address is shown below:
1110
1111
1111
R/W
0
1
X
X
X
X
Description
General call address
START byte
CBUS address
Reserved
Reserved
Reserved
-----
slave address
0000 000
0000 000
0000 001
0000 010
0000 011
0 0 0 0 1XX
0 0 0 1 XXX
X
Available slave address
XXX
0 XX
1 XX
X
X
10-bit slave addressing*1
Reserved
*1 This module does not support 10-bit slave address.
5.4.4 Synchronization of SCL
When two or more I2C devices turn into a master device almost simultaneously and drive SCL line,
each devices senses the state of SCL line and adjusts the drive timing of SCL line automatically in
accordance with the timing of the latest device.
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5.4.5 Arbitration
When other masters have transmitted data simultaneously at the time of master transmission,
arbitration takes places. When its own transmitting data is “1” and the data on SDA line is “0”, the
master considers that the arbitration was lost and sets “1” to AL. And if the master is going to generate
START condition while the bus is in use by other master, it will consider that arbitration was lost and
will set “1” to AL.
When the START condition which other masters generated is detected by the time the master actually
generated START condition, even when it checked the bus is in nonuse state and wrote in MSS=”1”, it
considers that the arbitration was lost and sets “1” to AL.
When AL bit is set to “1”, a master will set MSS=”0” and TRX= “0” and it will be a slave receiving mode.
When the arbitration is lost (it has no royalty of a bus), a master stops a drive of SDA. However, a
drive of SCL is not stopped until 1 byte transfer is completed and interruption is cleared.
5.4.6 Acknowledge
Acknowledge is transmitted from a reception side to a transmission side. At the time of data reception,
acknowledge is stored in LRB bit by ACK bit.
When the acknowledge from a master reception side is not received at the time of slave transmission,
it sets TRX=”0” and becomes slave receiving mode. Thereby, a master can generate STOP condition
when a slave opens SCL.
5.4.7 Bus error
When the following conditions are satisfied, it is judged as a bus error, and this interface will be in a
stop state.
- Detection of the basic regulation violation on I2C-bus under data transfer (including ACK bit)
- Detection of STOP condition in a master mode
- Detection of the basic regulation violation on I2C-bus at the time of bus idol
SDA
SCL
D7
START
1
D6
D5
2
3
SDA changed under data transmission (SCL=H). It becomes bus error.
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5.4.8 Initialize
Start
ADR: write
CCR: write
CS[4:0]: write
EN: 1write
BCR: write
BER: 0write
BEIE: 1write
INT: 0write
INTE: 1write
setup of slave address
setup of clock frequency
setup of macro enable
setup of interruption
End
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5.4.9 1-byte transfer from master to slave
master
DAR: write
M SS: 1write
slave
Start
START condition
BB set,TRX reset
BB set,TRX set
Transfer of address data
AAS set
Acknowledge
LRB reset
INT set, TRX set
DAR: write
INT: 0write
Interruption
INT set,TRX reset
ACK: 1write
INT: 0write
data transfer
acknowledge
LRB reset
INT set
M SS: 0write
INT reset
BB reset, TRX reset
interruption
STOP condition
End
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INT set
DAR: read
INT: 0write
BB reset,TRX reset
AAS reset
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5.4.10 1-byte transfer from slave to master
master
DAR:write
M SS:1write
slave
Start
START condition
BB set, TRX reset
BB set, TRX set
Transfer of address data
AAS set
Acknowledge
LRB reset
INT set, TRX set
ACK: 0write
INT: 0write
INT set, TRX reset
DAR: write
INT: 0write
Iterruption
Data transfer
Negative acknowledge
LRB set, RTX set
IN T set
INT set
DAR: read
M SS: 0write
INT reset
BB reset, TRX reset
Interruption
INT: 0write
STOP condition
End
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BB reset, TRX reset
AAS reset
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5.4.11 Recovery from bus error
Start
BCR: write
BER: 0write
BEIE: 1write
Cancellation of error flag
CCR: write
CS[4:0]: write
EN: 1write
Setup of clock frequency
Setup of macro enable
BCR: write
BER: 0write
BEIE: 1write
INT: 0write
INTE: 1write
Setup of interruption
End
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5.5 Note
A ) About a 10-bit slave address
This module does not support the 10-bit slave address. Therefore, please do not specify the slave
address of from 78H to 7bH to this module. If it is specified by mistake, a normal transfer cannot be
performed although acknowledge bit is returned at the time of 1 byte reception.
B ) About competition of SCC, MSS, and INT bit
Competition of the following byte transfer, generation of START condition, and generation of STOP
condition happens by the simultaneous writing of SCC, MSS, and INT bit. At this time the priority is
as follows.
1) The following byte transfer and generation of STOP condition
If “0” is written to INT bit and “0” is written to MSS bit, priority will be given to “0” writing to MSS
bit and STOP condition will be generated.
2) The following byte transfer and generation of START condition
If “0” is written to INT bit and “1” is written to SCC bit, priority will be given to “1” writing to SCC
bit and START condition will be generated.
3) Generation of START condition and generation of STOP condition
The simultaneous writing of “1” in SCC bit and “0” to MSS bit is prohibition.
C ) About setup of S serial transfer clock
When the delay of the positive edge of SCL terminal is large or when the clock is extended by the
slave device, it may become smaller than setting value (calculation value) because of generation of
overhead.
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6. Graphics Memory
6.1. Configuration
The Coral uses local external memory (Graphics memory) for drawing and display
management. The configuration of this Graphics memory is described as follows:
6.1.1. Data type
The Coral handles the following types of data. Display list can be stored in the host (main)
memory as well. Texture/tile pattern and text pattern can be defined by a display list as well.
Drawing Frame
This is a rectangular image data field for 2D/3D drawing. The Coral is able to have plural
drawing frames and display a part of these area if it is set to be bigger than display size. The
maximum size is 4096x4096 pixel in 32 pixel units. And both indirect color ( 8 bits / pixel) and
direct color ( 16 bits / pixel) mode are applicable.
Display Frame
This is a rectangle picture area for display. The Coral is able to set display layer up to 6 layers.
Z Buffer
Z buffer is required for eliminating hidden surfaces. In 16 bits modes, 2 bytes and in 8 bits
mode, 1 byte are required per 1 pixel. This area has to be cleared before drawing.
Polygon Drawing Flag Buffer
This area is used for polygon drawing. It is required 1 bit memory area per 1 pixel and 1 x-axis
line area both backward and forward of it. Initially, this area has to be cleared.
Frame buffer, Z buffer,
Displaylist and etc
By XRES size
Base Address of Polygon
Drawing Buffer(PFBR)
By drawing frame sizy
Polygon drawing flag area
=> (Y resolution + 2) * X resolution
By XRES size
Frame buffer, Z buffer,
Displaylist and etc
Specially, when you use Polygon with Shadow, required area is depending on geometory view
volume clip parameter. (Normally depending on drawing clipping parameter) Above “Y
resolution” is “Possible_view_clipped_Max_Ydc-Possible_view_clipped_Min_Ydc+1+6”. (+6
mergin must be needed)
Displaylist Buffer
The displaylist is a list of drawing commands and parameters.
Texture Pattern
This pattern is used for texture mapping. The maximum size is up to 4096 x 4096 pixels.
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Cursor Pattern
This is used for hardware cursor. The data format is indirect color ( 8 bits / pixel) mode. And the
Coral is able to display two cursor of 64 x 64 pixel size.
6.1.2. Memory Mapping
A graphics memory is mapped linearly to host CPU address field. Each of these above data is
able to be allocated anywhere in the Graphics memory according to the respective register
setting. ( However there are some restrictions of an addressing boundary depending on a data
type.)
6.1.3. Data Format
Direct Color ( 16 bits / pixel )
This data format is described RGB as each 5 bit. Bit15 is used for alpha bit of layer blending.
15
14
13
12
A
11
10
9
8
R
7
6
5
4
3
G
2
1
0
B
Indirect Color ( 8 bits / pixel )
This data format is a color index code for looking up table (palette).
7
6
5
4
3
2
1
0
Color Code
Z Value
It is possible to use Z value as 8 bits or 16 bits. These data format are unsigned integer.
1 ) 16 bits mode
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Unsigned Integer
2 ) 8 bits mode
7
6
5
4
3
2
1
0
Unsigned Integer
Polygon Drawing Flag
This data format is 1 bit per 1 pixel.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P31
P30
P29
P28
P27
P26
P25
P24
P23
P22
P21
P20
P19
P18
P17
P16
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Texture / Tile Pattern
It is possible to use a pattern as direct color mode ( 16 bits / pixel) or indirect color mode ( 8 bits
/ pixel).
1 ) Direct color mode ( 16 bits / pixel)
This data format is described RGB as each 5 bit. Bit15 is used for alpha bit of stencil or stencil
blending. ( Only texture mapping)
15
14
13
12
A
11
10
9
8
R
7
6
5
4
3
G
2
1
0
B
2) Indirect color mode ( 8 bits / pixel)
This data format is a color index code for looking up table (palette).
7
6
5
4
3
2
1
0
Color Code
Cursor Pattern
This data format is a color index code for looking up table (palette).
7
6
5
4
3
2
1
0
Color Code
Video Capture data
This data format is Y:Cb:Cr=4:2:2 and 32 bits per 2 pixel.
15
14
13
12
11
10
9
8
7
6
5
4
Y0
31
30
29
28
3
2
1
0
19
18
17
16
Cb
27
26
25
24
23
22
21
20
Y1
Cr
Direct Color ( 32 bits / pixel )
This data format is described RGB as each 8 bit. Bit31 is used for alpha bit of layer blending.
But the Coral does not support this color mode drawing. Therefore please draw this layer by
CPU writing.
15
14
13
12
11
10
9
8
7
6
5
4
G
31
30
29
A
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2
1
0
19
18
17
16
B
27
26
25
24
Reserved
23
22
21
20
R
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6.2. Frame Management
6.2.1. Single Buffer
The entire or partial area of the drawing frame is assigned as a display frame. The display field
is scrolled by relocating the position of the display frame. When the display frame crosses the
border of the drawing frame, the other side of the drawing frame is displayed, assuming that the
drawing frame is rolled over (top and left edges assumed logically connected to bottom and
right edges, respectively). To avoid the affect of drawing on display, the drawing data can be
transferred to the Graphics Memory in the blanking time period.
6.2.2. Double Buffer
Two drawing frames are set. While one frame is displayed, drawing is done at the other frame.
Flicker-less animation can be performed by flipping these two frames back and forth. Flipping is
done in the blanking time period. There are two flipping modes: automatically at every scan
frame period, and by user control. The double buffer is assigned independently for the L2, L3,
L4, L5 layers.
6.3. Memory Access
6.3.1. Memory Access by host CPU
Graphics memory is mapped linearly to host CPU address field. The host CPU can access the
Graphics memory like a SRAM.
6.3.2. Priority of memory accessing
The priority of Graphics memory accessing is the follows:
1.
2.
3.
4.
5.
Refresh
Video Capture
Display processing
Host CPU accessing
Drawing accessing
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6.4. Connection with memory
6.4.1. Connection with memory
The memory controller of Coral supports simple connection with SD/FCRAM by setting
MMR(Memory Mode Register).
If there is N(=11 to 13) address pins in SD/FCRAM, please connect the SD/FCRAM
address(A[n]) pin to the Coral’s memory address(MA[n]) pin and SD/FCRAM bank pin to the
Coral’s next address(MA[N]) pin. Then please set MMR by a number and type of memory.
The follows are the connection table between Coral pin and SD/FCRAM pin.
64M bit SDRAM(x16 bit)
Coral pins
SDRAM pins
MA[11:0]
A[11:0]
MA12
BA0
MA13
BA1
64M bit SDRAM(x32 bit)
Coral pins
SDRAM pins
MA[10:0]
A[10:0]
MA11
BA0
MA12
BA1
128M bit SDRAM(x16 bit)
Coral pins
SDRAM pins
MA[11:0]
A[11:0]
MA12
BA0
MA13
BA1
128M bit SDRAM(x32 bit)
Coral pins
SDRAM pins
MA[11:0]
A[11:0]
MA12
BA0
MA13
BA1
256M bit SDRAM(x16 bit)
Coral pins
SDRAM pins
MA[12:0]
A[12:0]
MA13
BA0
MA14
BA1
16M bit FCRAM(x16 bit)
Coral pins
FCRAM pins
MA[10:0]
A[10:0]
MA11
BA
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7. DISPLAY CONTROLLER
7.1 Overview
Display control
Window display can be performed for six layers. Window scrolling, etc., can also be performed.
Backward compatibility
Backward compatibility with previous products is supported in the four-layer display mode or in the
left/right split display mode.
Video timing generator
The video display timing is generated according to the display resolution (from 320 × 240 to 1024 ×
768).
Color look-up
There are two sets of color look-up tables by palette RAM for the indirect color mode (8 bits/pixel).
Cursor
Two sets of hardware cursor patterns (8 bits/pixel, 64 × 64 pixels each) can be used.
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7.2 Display Function
7.2.1 Layer configuration
Six-layer window display is performed. Layer overlay sequence can be set in any order. A four-layer
display mode and left/right split display mode are also provided, supporting backward compatibility
with previous products.
L0 (L0WX,L0WY)
L4 (L4WX,L4WY)
L2 (L2WX,L2WY)
L0,L2,L4 (0,0)
L1 (WX,WY)
L3,L5 (HDB+1,0)
L1 (L1WX,L1WY)
L5 (L5WX,L5WY)
background color
L3 (L3WX,L3WY)
(a) Six layerd window display
(b) Four layered display for downward compatibility
Configuration of Display Layers
The correspondence between the display layers for this product and for previous products is shown
below.
Layer
correspondence
Coordinates of starting point
Window mode
Compatibility
mode
Width/height
Window mode
Compatibility mode
L0
C
(L0WX, L0WY)
(0, 0)
(L0WW, L0WH + 1)
(HDP + 1, VDP + 1)
L1
W
(L1WX, L1WY)
(WX, WY)
(L1WW, L1WH + 1)
(WW, WH + 1)
L2
ML
(L2WX, L2WY)
(0, 0)
(L2WW, L2WH + 1)
(HDB + 1, VDP + 1)
L3
MR
(L3WX, L3WY)
(HDB, 0)
(L3WW, L3WH + 1)
(HDP − HDB, VDP + 1)
L4
BL
(L4WX, L4WY)
(0, 0)
(L4WW, L4WH + 1)
(HDB + 1, VDP + 1)
L5
BR
(L5WX, L5WY)
(HDB, 0)
(L5WW, L5WH + 1)
(HDP − HDB, VDP + 1)
C, W, ML, MR, BL, and BR above mean layers for previous products. The window mode or the
compatibility mode can be selected for each layer. It is possible to use new functions through minor
program changes by allowing the coexistence of display modes instead of separating them completely.
However, if high resolutions are displayed, the count of layers that can be displayed simultaneously
and pixel data may be restricted according to the graphics memory ability to supply data.
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7.2.2 Overlay
(1) Overview
Image data for the six layers (L0 to L5) is processed as shown below.
L0(C) data
Cursor0 data
Pallet-0
Cursor1 data
L4(BL) data
Pallet-1
YUV/RGB
L5(BR) data
L2 data
L3 data
Pallet-2
Blender
L3(MR) data
Layer Selector
L2(ML) data
Overlay
L1(W) data
Pallet-3
L4 data
L5 data
The fundamental flow is: Palette → Layer selection → Blending. The palettes convert 8-bit color
codes to the RGB format. The layer selector exchanges the layer overlay sequence arbitrarily.
The blender performs blending using the blend coefficient defined for each layer or overlays in
accordance with the transparent-color definition.
The L0 layer corresponds to the C layer for previous products and shares the palettes with the
cursor. As a result, the L0 layer and cursor are overlaid before blend operation.
The L1 layer corresponds to the W layer for previous products. To implement backward
compatibility with previous products, the L1 layer and lower layers are overlaid before blend
operation.
The L2 to L5 layers have two paths; in one path, these layers are input to the blender separately
and in the other, these layers and the L1 layer are overlaid and then are input to the blender.
When performing processing using the extended mode, select the former; when performing the
same processing as previous products, select the latter. It is possible to specify which one to
select for each layer.
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(2) Overlay mode
Image layer overlay is performed in two modes: simple priority mode, and blend mode.
In the simple priority mode, processing is performed according to the transparent color defined for
each layer. When the color is a transparent color, the value of the lower layer is used as the image
value for the next stage; when the color is not a transparent color, the value of the layer is used as
the image value for the next stage.
Dview = Dnew (when Dnew does not match transparent color)
= Dlower (when Dnew matches transparent color)
When the L1 layer is in the YCbCr mode, transparent color checking is not performed for the L1
layer; processing is always performed assuming that transparent color is not used.
In the blend mode, the blend ratio “r” defined for each layer is specified using 8-bit tolerance, and
the following operation is performed:
Dview = Dnew*r + Dlower*(1 – r)
Blending is enabled for each layer by mode setting and a specific bit of the pixel is set to “1”. For 8
bits/pixel, the MSB of RAM data enables blending; for 16 bits/pixel, the MSB of data of the relevant
layer enables blending; for 24 bits/pixel, the MSB of the word enables blending.
(3) Blend coefficient layer
In the normal blend mode, the blend coefficient is fixed for each layer. However, in the blend
coefficient layer mode, the L5 layer can be used as the blend coefficient layer. In this mode, the
blend coefficient can be specified for each pixel, providing gradation, for example. When using this
mode, set the L5 layer to 8 bits/pixel, widow display mode and extend overlay mode.
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7.2.3 Display parameters
The display area is defined according to the following parameters.
independently at the respective register.
Each parameter is set
HTP
HSP
HDP
HSW
HDB
VDP
LnWX
LnWW
LnWH
VTR
VSP
LnWY
VSW
Fig. 5.1 Display Parameters
Note: The actual parameter settings are little different from the above. The details, please refer
“14.3.1 Interlaced mode”.
HTP
Horizontal Total Pixels
HSP
Horizontal Synchronize pulse Position
HSW
Horizontal Synchronize pulse Width
HDP
Horizontal Display Period
HDB
Horizontal Display Boundary
VTR
Vertical Total Raster
VSP
Vertical Synchronize pulse Position
VSW
Vertical Synchronize pulse Width
VDP
Vertical Display Period
LnWX
Layer n Window position X
LnWY
Layer n Window position Y
LnWW
Layer n Window Width
LnWH
Layer n Window Height
When not splitting the window, set HDP to HDB and display only the left side of the window. The
settings must meet the following relationship:
0 < HDB ≤ HDP < HSP < HSP + HSW + 1 < HTP
0 < VDP < VSP < VSP + VSW + 1 < VTR
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7.2.4 Display position control
The graphic image data to be displayed is located in the logical 2D coordinates space (logical graphics
space) in the Graphics Memory. There are six logical graphics spaces as follows:
• L0 layer
• L1 layer
• L2 layer
• L3 layer
• L4 layer
• L5 layer
The relation between the logical graphics space and display position is defined as follows:
Origin Address (OA)
Display Address (DA)
Display Position X,Y (DX,DY)
Stride (W)
Height (H)
Logical Frame
Display Frame
VDP
HDP
Fig. 5.2 Display Position Parameters
OA
Origin Address
W
Stride
Origin address of logical graphics space. Memory address of top left
edge pixel in logical frame origin
Width of logical graphics space. Defined in 64-byte unit
H
Height
Height of logical graphics space. Total raster (pixel) count of field
DA
Display Address
DX
DY
Display Position
Display origin address. Top left position address of display frame
origin
Display origin coordinates.
Coordinates in logical frame space of display frame origin
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MB86296S scans the logical graphics space as if the entire space is rolled over in both the horizontal
and vertical directions. Using this function, if the display frame crosses the border of the logical
graphics space, the part outside the border is covered with the other side of the logical graphics space,
which is assumed to be connected cyclically as shown below:
Logical Frame Origin
64 w
Previous display
origin
Additionally
drawn area
New display origin
L
Fig. 5.3 Wrap Around of Display Frame
The expression of the X and Y coordinates in the frame and their corresponding linear addresses (in
bytes) is shown below.
A(x,y) = x × bpp/8 + 64wy (bpp = 8 or 16)
The origin of the displayed coordinates has to be within the frame.
parameters are subject to the following constraints:
To be more specific, the
0 ≤ DX < w × 64 × 8/bpp (bpp = 8 or 16)
0 ≤ DY < H
DX, DY, and DA have to indicate the same point within the frame. In short, the following relationship
must be satisfied.
DA = OA + DX × bpp/8 + 64w × DY (bpp = 8 or 16)
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7.3 Display Color
Color data is displayed in the following modes:
Indirect color (8 bits/pixel)
In this mode, the index of the palette RAM is displayed. Data is converted to image data consisting
of 6 bits for R, G, and B via the palette RAM and is then displayed.
Direct color (16 bits/pixel)
Each level of R, G, and B is represented using 5 bits.
Direct color (24 bits/pixel)
Each level of R, G, and B is represented using 8 bits.
YCbCr color (16 bits/pixel)
In this mode, image data is displayed with YCbCr = 4:2:2. Data is converted to image data
consisting of 8 bits for R, G, and B using the operation circuit and is then displayed.
The display colors for each layer are shown below.
Layer
Compatibility mode
Extended mode
L0
Direct color (16, 24), Indirect color (P0)
Direct color (16, 24), Indirect color (P0)
L1
Direct color (16, 24), Indirect color (P1), YCbCr
Direct color (16, 24), Indirect color (P1), YCbCr
L2
Direct color (16, 24), Indirect color (P1)
Direct color (16, 24), Indirect color (P2)
L3
Direct color (16, 24), Indirect color (P1)
Direct color (16, 24), Indirect color (P3)
L4
Direct color (16, 24), Indirect color (P1)
Direct color (16, 24)
L5
Direct color (16, 24), Indirect color (P1)
Direct color (16, 24)
“Pn” stands for the corresponding palette RAM. Four palettes are used as follows:
Palette 0 (P0)
This palette corresponds to the C-layer palette for previous products. This palette is used for the
L0 layer. This palette can also be used for the cursor.
Palette 1 (P1)
This palette corresponds to the M/B layer palette for previous products. In the compatibility mode,
this palette is common to layers L1 to 5. In the extended mode, this palette is dedicated to the L1
layer.
Palette 2 (P2)
This palette is dedicated to the L2 layer. This palette can be used only for the extended mode.
Palette 3 (P3)
This palette is dedicated to the L3 layer. This palette can be used only for the extended mode.
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7.4 Cursor
7.4.1 Cursor display function
CORAL can display two hardware cursors. Each cursor is specified as 64 × 64 pixels, and the cursor
pattern is set in the Graphics Memory. The indirect color mode (8 bits/pixel) is used and the L0 layer
palette is used. However, transparent color control (handling of transparent color code and code 0) is
independent of L0 layer. Blending with lower layer is not performed.
7.4.2 Cursor control
The display priority for hardware cursors is programmable. The cursor can be displayed either on
upper or lower the L0 layer using this feature. A separate setting can be made for each hardware
cursor. If part of a hardware cursor crosses the display frame border, the part outside the border is
not shown.
Usually, cursor 0 is preferred to cursor 1. However, with cursor 1 displayed upper the L0 layer and
cursor 0 displayed lower the L0 layer, the cursor 1 display is preferred to the cursor 0.
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7.5 Display Scan Control
7.5.1 Applicable display
The following table shows typical display resolutions and their synchronous signal frequencies. The
pixel clock frequency is determined by setting the division rate of the display reference clock. The
display reference clock is either the internal PLL (400.9 MHz at input frequency of 14.318 MHz), or the
clock supplied to the DCLKI input pin. The following table gives the clock division rate used when the
internal PLL is the display reference clock:
Table 4-1 Resolution and Display Frequency
Resolution
Division rate
of reference
clock
Pixel
frequency
Horizontal
total pixel
count
Horizontal
frequency
Vertical
total raster
count
Vertical
frequency
320 × 240
1/60
6.7 MHz
424
15.76 kHz
263
59.9 Hz
400 × 240
1/48
8.4 MHz
530
15.76 kHz
263
59.9 Hz
480 × 240
1/40
10.0 MHz
636
15.76 kHz
263
59.9 Hz
640 × 480
1/16
25.1 MHz
800
31.5 kHz
525
59.7 Hz
854 × 480
1/12
33.4 MHz
1062
31.3 kHz
525
59.9 Hz
800 × 600
1/10
40.1 MHz
1056
38.0 kHz
633
60.0 Hz
1024 × 768
1/6
66.8 MHz
1389
48.1 kHz
806
59.9 Hz
Pixel frequency = 14.318 MHz × 28 × reference clock division rate (when internal PLL selected)
= DCLKI input frequency × reference clock division rate (when DCLKI selected)
Horizontal frequency = Pixel frequency/Horizontal total pixel count
Vertical frequency = Horizontal frequency/Vertical total raster count
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7.5.2 Interlace display
CORAL can perform both a non-interlace display and an interlace display.
When the DCM register synchronization mode is set to interlace video (11), images in memory are
output in odd and even rasters alternately to each field, and one frame (odd + even fields) forms one
screen.
When the DCM register synchronization mode is set to interlace (10), images in memory are output in
raster order. The same image data is output to odd fields and even fields. Consequently, the count of
rasters on the screen is half of that of interlace video. However, unlike the non-interlace mode, there
is a distinction between odd and even fields depending on the phase relationship between the
horizontal and vertical synchronous signals.
Odd
Eve
Non-Interlace
Interlace Video
Interlace
Fig. 5.4 Display Difference between Synchronization Modes
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7.6 Video Interface, NTSC/PAL Output
To achieve NTSC/PAL signals, a NTSC/PAL encoder must be connected externally as shown below:
CORAL
NTSC Encoder
AOUTR
R-IN
AOUTG
G-IN
AOUTB
B-IN
CSYNC
CSYNC-IN
1/4
CLK
VIDEO-OUT
Fsc-IN
14.318 MHz
Fig. 5.6 Example of NTSC/PAL Encoder Connection
Note) The neither CSYNC and VSYNC pins are impossible to output the 2.5H width signal.
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7.7 Programmable YCbCr/RGB conversion for L1-layer display
L1-layer can display video data in YCbCr format but RGB conversion coefficients are hard-wired and
fixed about previous products. Coral-PA can program RGB conversion coefficients by registers.
YCbCr data is converted by following expression.
R = a11*Y + a12*(Cb−128) + a13*(Cr−128) + b1
G = a21*Y + a22*(Cb−128) + a23*(Cr−128) + b2
B = a31*Y + a32*(Cb−128) + a33*(Cr−128) + b3
aij ---- 11bit signed real ( lower 8bit is fraction, two's complement )
bi ----- 9bit signed integer ( two's complement )
It is represended by matrix operation.
R
G
B
=A
Y
Cb-128
Cr-128
+b
where
A=
a11
a21
a31
a12
a22
a32
a13
a23
a33
,b=
b1
b2
b3
These parameters are set on registers shown bellow.
L1YCR0 (a12,a11), L1YCR1(b1,a13)
L1YCG0 (a22,a21), L1YCG1(b2,a23)
L1YCB0 (a32,a31), L1YCB1(b3,a33)
Same conversion with previous products is applied by initial values of these registers after reset.
The register values just after reset is as follow.
a11 = 0x12b (299/256) , a12 = 0x0, a13 = 0x198 (408/256)
a21 = 0x12b (299/256), a22 = 0x79c (-100/256), a23 = 0x72f (-209/256)
a31 = 0x12b (299/256), a32 = 0x204 (516/256), a33 = 0x0
b1= b2= b3= 0x1f0 (-16)
It is possible to control brightness, contrast, hue , color saturation by change these parameters.
Addition of a constant value into b means inclease of brightness.
Multiplication of a constant scalar value greater than one into A means increase of contrast.
Two dimentional rotation of Cb-128 and Cr-128 means change of hue.
Color saturation is intensity of color, relative to Y-component.
New coefficients including these changes can be got by following expression.
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A = c1 A0
b = bo +
1 0
0
0 cos(t) sin(t)
0 -sin(t) cos(t)
1 0 0
0 c2 0
0 0 c2
= A0
c1
0
0 cos(t)c1c2
0 -sin(t)c1c2
0
sin(t)c1c2
cos(t)c1c2
c3
c3
c3
A0 , b0 : initial value
c1: contrast parameter, 1 is standard. 1.2 is stronger, for example.
c2: color saturation parameter, 1 is standard. 0 means mono chrome image.
c3: brightness parameter, 0 is standard.
t : hue rotation parameter, 0-deg is standard
Note: new aij and bi should be clipped in valid range of value for corresponding registers.
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7.8 DCLKO shift
1) Delay
DCLKO delay function is available if internal PLL is used for DCLK. DCKD field in DCM3 register
defines delay value by internal PLL clock cycle.
DCKD
delay
000000
No additional delay
000010
+2 PLL clock
000100
+3 PLL clock
000110
+4 PLL clock
:
111110
:
+33 PLL clock
2) Inversion
DCLKO inversion is also available with/without delay function. This function is effective with no
relation to DCLK clock source.
CKinv-bit of DCM3 enables this function.
7.9 Syncronous register update of display
To update position related parameters without disturbing display, it is need to update synchronously
with VSYNC interrupt and finish at a time.
This synchronous register update mode eases this limitation. In this mode, written parameters are hold
in intermediate registers and update at once synchronously with VSYNC.
RUM-bit of DCM2 register enables this mode.
RUF-bit of DCM2 register controls start of update and shows whether update is done or not.
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7.10 Dual Display
7.10.1 Overview
This function enables to display two screens on two display devices. It is possible to control which
layer is included in a screen. It is assumed here that display device "0" has screen "0" and display
device "1" has screen "1".
screen"0"
display
device"0"
screen"1"
display
device"1"
MB86296
7.10.2 Destination Control
A layer or cursor can be included in both screens or one screen. If a layer is NOT included into a
screen, this layer is treated as "transparent" . If all bits of a screen are set "0", then background
color is displayed on the screen.
This destination control can be thought virtually as crosspoint switch shown next
background layer 0
color
layer 1
layer 5
cur 0
cur 1
screen 0
SC0en0
SC0en1
SC0en5
SC0en6
SC0en7
screen 1
SC1en0
SC1en1
SC1en5
SC1en6
SC1en7
MDen (multi display enable) bit of MDC(multi display control) register enables this function.
SC0en (screen"0" enable) field of MDC register defines which layers and cursors are included in
screen “0”.
SC1en (screeen"1" enable) field of MDC register defines which layers and cursors are included in
screen “1”.
bit-0 ---- L0 is included
bit-1 ---- L1 is included
:
bit-5 ---- L5 is included
bit-6 ---- Cursor0 is included
bit-7 ---- Cursor1 is included
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7.10.3 Output Signal Control
There are two mode to output two screens. In parallel mode, one screen is output at digital RGB
while another screen is output at analog RGB. In multiplex mode, two screens are multiplexed and
output at digital RGB.
(1) parallel output mode
DCLKO (SE)
DCLKO (BE)
DE
Digital RGB
sc0
Analog RGB
sc0
sc1
sc0
sc1
sc1
Note: Analog RGB is shown as corresponding data value
(2) multiplex output mode
DCLKO (SE)
DCLKO (BE)
DE
Digital RGB
sc0
Analog RGB
sc1
sc0
sc1
sc1
sc0
sc1
sc1
sc1
Note: Analog RGB is shown as corresponding data value
In BE (bi-edge) DCLKO mode, two ouput phases can be identified both edge of DCLKO.
In SE (single-edge) DCLKO mode, two output phases cab be identified an edge of HSYNC or DE.
DCLKO (SE)
HSYNC
ref edge
sc0 is first
Digital RGB
sc0
sc1
DE
even clocks
POM(parallel output mode) bit in DCM3 register defines which output mode is used, parallel or
multiplex. POM=0 means multiplex, POM=1 means parallel, respectively.
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CKed( clock edge) bit in DCM3 register defines which DCLKO clock mode is used, BE(bi-edge) or
SE(single-edge). DCKed=0
7.10.4 Output Circuit Example
There are three types of output circuit for dual display, primalry.
Parallel, Digital Multiplex(SE), Digital Multiplex(BE)
Here these three examples are described.
(1) Parallel output
Two screens are given as analog signals in this example.
MB86296 (pallarel output)
(BE mode)
DAC (positive edge input)
DCLKO
R0
G0
B0
DR[7:0]
DG[7:0]
DB[7:0]
display
device"0"
HSYNC0
VSYNC0
HSYNC
VSYNC
R1
G1
B1
HSYNC1
VSYNC1
AOR
AOG
AOB
(POM=1,DCKed=1)
display
device"1"
(2) Multiplexed digital output with SE mode DCLKO
In this case, CPLD can be used to demultiplex two digital streams of each screen. In following
example, one economical CPLD demultiplexes RGB 6bit/component video data stream.
MB86296 (mux output)
DCLKO
XC9572XL-TQ100
(SE mode)
DCKi
DCK0
HSYNC
HSi
HS0
VSYNC
VSi
VS0
DE
Di[18]
DR[7:2]
DG[7:2]
Di[17:0]
D0[18]
D0[17:0]
R0,G0,B0
DCK1
DCLK1
HSYNC1
VSYNC1
DE1
DB[7:2]
HS1
(POM=0,DCKed=0)
VS1
D1[18]
D1[17:0]
MB86296S
Specification Manual Rev1.1
DCLK0
HSYNC0
VSYNC0
DE0
77
R1,G1,B1
display
device "0"
display
device "1"
FUJITSU LIMITED
module XC9572XL ( DCKi, HSi,VSi,Di, DCK0,HS0,VS0,D0, DCK1,HS1,VS1,D1 );
input DCKi,HSi,VSi;
input[18:0] Di;
output DCK0,HS0,VS0, DCK1,HS1,VS1;
output[18:0] D0,D1;
reg HS0,HS1, VS0,VS1, DCK0,DCK1;
reg[18:0] D0,D1;
always @(posedge DCKi) begin
HS0
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