MB86R01

MB86R01 DATA SHEET July, 2009 the 1.4 edition FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL MB86R01 DATA SHEET Trademarks ARM is a registered trademark of ARM Limited in UK, USA and Taiwan. ARM is a trademark of ARM Limited in Japan and Korea. ARM926EJ-S and ETM9 are trademarks of ARM Limited. • The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. • The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. • Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. • The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. • Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. • Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. • The company names and brand names herein are the trademarks or registered trademarks of their respective owners. All rights reserved, Copyright FUJITSU MICROELECTRONICS LIMITED 2007 - 2009 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL i MB86R01 DATA SHEET Revision History Date 2007/07/12 2007/08/20 Ver. 1.0 1.1 Newly issued 8.3.1. Recommended Power On/Off Sequence • Revised the last line of description (PLL reference clock part) 8.4.3. ADC • Revised value of table 8-16 • Revised and deleted descriptive content of note • Revised footnote (*2) of table 8-17 8.4.4. I2C Bus Fast Mode I/O • Revised table 8-18 and footnote • Deleted footnote (*3) 8.5.9. I2C Bus Timing • Revised footnote (*2) of table 8-37 8.5.12. MLB Signal Timing • Revised MLB to MediaLB • Revised footnote of table 8-42, 8-45 4. Function list • Revised contents of the list 6. Pin assignment • Revised figures in 1-8/1-9 pages • Added "top view" statement 7.1. Pin Multiplex • Revised description of note • Added mode setting description to pin multiplex group #1 ~ #5 • Revised table of pin multiplex group #2 and #4 7.2.4. USB 2.0 Host/Function related pin • Revised description of USB_EXT12K pin 7.2.5. External interrupt controller related pin • Revised title 7.2.12. A/D converter related pin • Revised pin name: AD_AVD0 → AD_AVD, AD_AVS1 → AD_AVS 7.2.24. Unused pin • Added this section 7.2.25. Unused pin with pin multiplex function in the duplex case • Added this section 8.4.2. DDR2SDRAM IF I/O (SSTL_18) • Revised table 8-12 8.5.1. Memory Controller Signal Timing • Revised table 8-21 • Revised figure 8-8 and 8-9 • Added figure 8-10, 8-11, and 8-12 8.5.6.2. Input Signal • Revised figure 8-23 6. Pin assignment • Revised figure and table 7.2.2. IDE66 related pin • Revised type • Revised status pin after reset 7.2.3. SD memory controller related pin • Unified SD_DAT[0] and SD_DAT[3:1] 7.2.7. CAN related pin • Revised type Contents 2007/11/09 1.2 2008/02/07 1.3 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL ii MB86R01 DATA SHEET Date 2008/02/07 Ver. 1.3 Contents 7.2.8. I2S related pin • Revised type • Revised status pin after reset 7.2.10. SPI related pin • Revised type 7.2.11. PWM related pin • Revised type • Added comment 7.2.13. DDR2 related pin • Revised resistance value of *2 7.2.15. Video captured related pin • Revised type • Added comment 7.2.18. ICE related pin • Revised status pin after reset of XSRST 7.2.20. ETM related pin • Revised pin name in description column of TRACECLK 7.2.22. MediaLB related pin • Revised pin name • Revised type 7.2.24. Unused pin • Revised process • Deleted BIGEND • Revised pin name of B17, B16, C17, C16, and D16 7.2.25. Unused pin with pin multiplex function in the duplex case • Revised process 8.1. Maximum Ratings • Revised table 8-1 7.2.14. DISPLAY related pin • Added note 8.1. Maximum Ratings • Revised table 8-1 8.3.2. Power On Reset • Revised figure 8-3 • Revised description 8.5.5.1. Clock • Revised table 8-28 8.5.7. I2S Signal Timing • Revised table 8-34 and 8-35 8.5.10. SPI Signal Timing • Revised table 8-38 2009/07/07 1.4 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL iii MB86R01 DATA SHEET Contents 1. Outline ................................................................................................................. 1 2. Feature................................................................................................................. 1 3. Block diagram..................................................................................................... 2 4. Function list ........................................................................................................ 4 5. Package dimension ............................................................................................ 6 6. Pin assignment ................................................................................................... 7 7. Pin function....................................................................................................... 10 7.1. Pin Multiplex......................................................................................................................................... 10 7.2. Pin Function .......................................................................................................................................... 16 7.2.1. External bus interface related pin.................................................................................................. 17 7.2.2. IDE66 related pin .......................................................................................................................... 17 7.2.3. SD Memory controller related pin................................................................................................. 18 7.2.4. USB 2.0 Host/Function related pin ............................................................................................... 18 7.2.5. External interrupt controller related pin ........................................................................................ 18 7.2.6. UART related pin .......................................................................................................................... 19 7.2.7. CAN related pin ............................................................................................................................ 19 7.2.8. I2S related pin ............................................................................................................................... 19 7.2.9. I2C related pin ............................................................................................................................... 20 7.2.10. SPI related pin ............................................................................................................................... 20 7.2.11. PWM related pin ........................................................................................................................... 20 7.2.12. A/D converter related pin.............................................................................................................. 20 7.2.13. DDR2 related pin .......................................................................................................................... 21 7.2.14. DISPLAY related pin .................................................................................................................... 22 7.2.15. Video capture related pin............................................................................................................... 23 7.2.16. System related pin ......................................................................................................................... 23 7.2.17. JTAG related pin ........................................................................................................................... 23 7.2.18. ICE related pin .............................................................................................................................. 24 7.2.19. Multiplex setting related pin ......................................................................................................... 24 7.2.20. ETM related pin ............................................................................................................................ 24 7.2.21. Power supply related pin ............................................................................................................... 24 7.2.22. MediaLB related pin...................................................................................................................... 25 7.2.23. GPIO related pin ........................................................................................................................... 25 7.2.24. Unused pin .................................................................................................................................... 26 7.2.25. Unused pin with pin multiplex function in the duplex case .......................................................... 34 8. Electrical Characteristics................................................................................. 35 8.1. Maximum Ratings................................................................................................................................. 35 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL iv MB86R01 DATA SHEET 8.2. Recommended Operating Conditions ................................................................................................... 37 8.3. Precautions at Power On ....................................................................................................................... 38 8.3.1. Recommended Power On/Off Sequence ....................................................................................... 38 8.3.2. Power On Reset............................................................................................................................. 39 8.4. DC Characteristics ................................................................................................................................ 40 8.4.1. 3.3V Standard CMOS I/O ............................................................................................................. 40 8.4.1.1. 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 1).................................... 41 8.4.1.2. 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 2).................................... 42 8.4.1.3. 3.3V Standard CMOS I/O V-I Characteristics (Driving Capability 3) .................................. 43 8.4.2. DDR2SDRAM IF I/O (SSTL_18) ................................................................................................ 44 8.4.3. ADC .............................................................................................................................................. 46 8.4.4. I2C Bus Fast Mode I/O .................................................................................................................. 47 8.4.4.1. I2C IO V-1 Characteristic Figure ........................................................................................... 48 8.4.5. USB2.0.......................................................................................................................................... 49 8.5. AC CHARACTERISTIC ...................................................................................................................... 50 8.5.1. Memory Controller Signal Timing ................................................................................................ 50 8.5.2. DDR2SDRAM IF.......................................................................................................................... 54 8.5.2.1. DDR2SDRAM IF Timing Diagram ...................................................................................... 55 8.5.3. GPIO Signal Timing...................................................................................................................... 58 8.5.4. PWM Signal Timing ..................................................................................................................... 59 8.5.4.1. Output Signal ........................................................................................................................ 59 8.5.5. GDC Display Signal Timing ......................................................................................................... 60 8.5.5.1. Clock ..................................................................................................................................... 60 8.5.5.2. Input Signal ........................................................................................................................... 60 8.5.5.3. Output Signal ........................................................................................................................ 61 8.5.6. GDC Video Capture Signal Timing............................................................................................... 63 8.5.6.1. Clock ..................................................................................................................................... 63 8.5.6.2. Input Signal ........................................................................................................................... 63 8.5.7. I2S Signal Timing ......................................................................................................................... 65 8.5.8. UART Signal Timing .................................................................................................................... 67 8.5.9. I2C Bus Timing.............................................................................................................................. 68 8.5.10. SPI Signal Timing ......................................................................................................................... 69 8.5.11. CAN Signal Timing....................................................................................................................... 70 8.5.12. MediaLB Signal Timing................................................................................................................ 71 8.5.12.1. MediaLB AC Spec Type A .................................................................................................... 71 8.5.12.1.1. Clock ............................................................................................................................. 71 8.5.12.1.2. Input Signal ................................................................................................................... 71 8.5.12.1.3. Output Signal................................................................................................................. 71 8.5.12.2. MediaLB AC Spec Type B .................................................................................................... 72 8.5.12.2.1. Clock ............................................................................................................................. 72 8.5.12.2.2. Input Signal ................................................................................................................... 72 8.5.12.2.3. Output signal ................................................................................................................. 72 8.5.13. USB2.0 Signal Timing .................................................................................................................. 74 8.5.14. IDE66 Signal Timing .................................................................................................................... 76 8.5.14.1. IDE PIO Timing .................................................................................................................... 76 8.5.14.2. IDE Ultra DMA Timing ........................................................................................................ 78 8.5.15. SD Signal Timing.......................................................................................................................... 80 8.5.15.1. Clock ..................................................................................................................................... 80 8.5.15.2. Input/Output Signal ............................................................................................................... 80 8.5.16. ETM9 Trace Port Signal Timing ................................................................................................... 81 8.5.17. EXIRC Signal Timing ................................................................................................................... 82 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL v MB86R01 DATA SHEET 1. Outline MB86R01 is LSI product for the graphics applications with ARM Limited's CPU ARM926EJ-S and Fujitsu's GDC MB86296 as its core. This product contains peripheral I/O resources, such as in-vehicle LAN, HDD, and USB; therefore only a single chip of MB86R01 controls main graphics application system which usually requires 2 chips (CPU and GDC.) 2. Feature • • • • • CMOS 90nm technology Package: PBGA484 Power-supply voltage: (IO: 3.3 ± 0.3V, core: 1.2 ± 0.1V, DDR2: 1.8 ± 0.1V) Operation frequency: 333MHz (CPU), 83MHz (AHB), 41.5MHz (APB) CPU core • ARM926EJ-S • 16KB instruction cache/16KB data cache • 16KB ITCM/16KB DTCM • ETM9CS Single and JTAG ICE interface • Java acceleration (Jazelle technology) Bus architecture • Multi-layer AHB bus architecture Interrupt Built-in SRAM Clock/Reset control function Remap/Boot control function 16 bit external bus interface with decoding engine 32 bit DDR2 memory interface (target: 166MHz: 333Mbps) Graphics display controller • 2D/3D rendering engine of Fujitsu MB86296 • RGB66 video output × 1ch (extensible to RGB888 with using option I/O) • ITU RBT-656 video capture × 1ch (extensible to RGB666 with using option I/O) USB 2.0 host (HS/FS protocols) × 1ch IDE66 (ATA/ATAPI-5) × 1ch SD memory interface (SDIO/CPRM: unsupported) × 1ch 10 bit A/D converter (1MS/s) × 2ch I2C (I/O voltage: 3.3V) × 2ch UART × 3ch (extensible up to 6ch with using option I/O) 32/16 bit timer × 2ch DMAC × 8ch • • • • • • • • • • • • • • • • Option I/O (with pin multiplex) • • • • • RGB666 video output is extensible to 2ch Video capture is extensible to 2ch MediaLB (MOST50) × 1ch is addable CAN (I/O voltage: 3.3V) × 2ch is addable USB 2.0 function (HS/FS protocols) is switchable (USB 2.0 function and USB 2.0 host are accessed exclusively) • GPIO is addable up to 24 • SPI × 1ch is addable • PWM × 2ch is addable FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 1 MB86R01 DATA SHEET • I2S is addable up to 3ch • The number of UART channel is extensible up to 6ch • The data width in the external bus interface is extensible to 32 bit 3. Block diagram Figure 3-1 shows block diagram of MB86R01. JTAG_SEL Chip_JTAG DDR2 Controller JTAG IF ETM9CSSingle AHB2AXI HBUS2AXI MBUS2AXI MBUS2AXI I-Cache 16KB I-TCM 16KB DRAW & GEO D-Cache 16KB D-TCM 16KB HOST IF DISP DISP I External BUS I/F D CAP CAP CCPB SRAM 32KB S1-08 SRAM 32KB M1-2 S1-01 DMAC 8ch S1-02 M1-0 M1-1 BOOT ROM 32KB S1-04 I2S_0 I2S_1 I2S_2 S1-05 S1-13 S1-14 S1-10 S1-03 S1-11 S1-00 M1-5 USB2.0 DMAC M1-8 M1-4 M1-6 S1-07 S1-06 S1-15 S1-12 S1-09 M1-7 Function S2-00 USB2.0 Function Wrapper S2-03 PHY USB2.0 Host Wrapper S2-02 SDMC IDE66 DMAC IDE66 S2-04 MediaLB S2-01 M2-0 Slave No. Master No. IRC ×2 IRC EXTIRC 4ch CRG UART UART ×2 ×4 GPIO 24ch RBC 32bit Timer 2ch I2C I2C ×2 ×2 CAN CAN ×2 ×2 UART PWM ×2 ×2 ADC ADC ×2 ×4 PWM 2ch SPI ×1 CCNT UART UART ×2 ×4 Figure 3-1 Block diagram of MB86R01 CPU core This is CPU core block of ARM926EJ-S which is connected to each I/O through AHB bus in LSI. Instruction (I)/Data (D) function as a separate bus master for Harvard architecture. GDC_TOP This is MB86296 compatible GDC which has 2 functions: AHB slave function writes required display list for drawing to GDC with having CPU or DMA controller as master, and AXI master function reads display list arranged in DDR2 memory with having GDC as master. AXI bus This bus bridges main memory and internal resource. Following four bus masters are connected. • AHB1: Each bus master of AHB bus such as CPU and DMA controller • HBUS: HOST IF on GDC • DRAW & GEO: Draw (2D/3D drawing) and GEO (geometry engine) on GDC • MBUS: DISP (display controller) and CAP (Video capture) on GDC FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 2 MB86R01 DATA SHEET AHB1 bus Following resources are connected. • CPU core: Bus masters of instruction (I)/data (D) • GDC: GDC register part • AHB2AXI: AXI port for main memory access • CCPB: Encrypted ROM decoding block • External BUS I/F: External bus interface (connected through CCPB) • SRAM: General purpose internal SRAM 32KB × 2 • DMAC: General purpose DMA × 8ch It operates as bus master at data transfer • Boot ROM: Built-in boot ROM • I2S_0/1/2: Serial audio controller × 3ch • USB 2.0 Function DMAC: USB function DMAC It operates as bus master at data transfer • USB2.0 Host: It operates as USB2.0 EHCI, USB1.1 OHCI bus masters • IDE66/IDE66DMAC: Register part of IDE host controller and built-in DMAC The DMAC part operates as bus master at data transfer • MLB: MediaLB controller • AHB2 • APBBRG0/1/2: AHB-APB bridge circuit × 3ch AHB2 bus • CCPB: Encrypted ROM decoding block • USB 2.0 Function: USB 2.0 function controller's register part • USB 2.0 Host: USB 2.0 host controller's register part • SDMC: SD memory controller • DDR2 controller: DDR2 controller's register part APB_TOP_0 This block bridges between APBBRG0 bus and AHB1 bus, and following low-speed peripheral resources are connected. • Interrupt controller (IRC) × 2ch • External interrupt controller (EXTIRC) • Clock reset generator (CRG) • UART (ch0 and ch1) × 2ch • Remap boot controller (RBC) • 32 bit general-purpose timer (32 bit timer) × 2ch APB_TOP_1 This block bridges between APBBRG1 bus and AHB1 bus, and following low-speed peripheral resources are connected. • I2C controller × 2ch • CAN controller × 2ch • UART (ch2 and ch3) × 2ch • A/D converter (ADC) × 2ch APB_TOP_2 This block bridges between APBBRG2 bus and AHB1 bus, and following low-speed peripheral resources are connected. • PWM controller (PWM) • SPI controller (SPI) • CCNT • UART (ch4 and ch5) × 2ch FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 3 MB86R01 DATA SHEET 4. Function list Function list of MB86R01 is shown below. Function CPU core Outline • • • • • • • • ARM926EJ-S processor core Core operation frequency: 333MHz 16KB instruction cache 16KB data cache Tightly-Coupled memory for 16KB instruction (ITCM) Tightly-Coupled memory for 16KB data (DTCM) ETM9CS Single and JTAG ICE debugging interface Java acceleration (Jazelle technology) TM Bus architecture • Multilayer AHB bus architecture (software interrupt) • Speeding up data transfer between main memory and each bus master with 64 bit AXI bus Interrupt • High-speed interrupt × 1ch h (soft interrupt) • Normal interrupt × 64ch (external interrupt × 4ch + built-in internal interrupt × 60ch) • Up to 16 interrupt levels are settable by channel • PLL multiplication: selectable from ×15 ~ 49 • Operation frequency: 333MHz (CPU), 83MHz (AHB), 41.5MHz (APB) • Low power consumption mode (clock to ARM and module is stoppable) • Hardware reset, software reset, and watchdog reset • ROM area is able to be mapping to built-in SRAM area Clock Reset Remap External bus interface • Three chip select signals • Provided 32M byte address space in each chip select • Supported 16/32 bit width SRAM/Flash ROM connection • Programmable weight controller • Encrypted ROM compound engine DDR2 controller • • • • Supported DDR2SDRAM (DDR2-400) Connectable capacity: 256 ~ 512M bit × 2 or 256 ~ 512M bit × 1 I/O width: Selectable from ×16/×32 bit Max. transfer rate: 166MHz/333Mbps Built-in SRAM DMAC Timer GPIO (*2) PWM (*2) A/D converter • Mounted general purpose SRAM of 32KB × 2 (32 bit bus) • AHB connection × 8ch • Transfer mode: Block, burst, and demand • 32/16 bit programmable × 2 channels • Max. 24 is usable • Interrupt function • Built-in 2 channels • Duty ratio and phase are configurable • 10 bit successive approximation type A/D converter × 2ch • Sampling rate: 648KS/s (max. sampling plate) • Nonlinearity error: ± 2.0LSB (max.) FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 4 MB86R01 DATA SHEET Function GDC (*1) Outline • Display controller RGB666 or RGB888 output Max. resolution is 1024 × 768 Max. 6 layered display Max. 2 screen output • Digital video capture function BT.601, BT.656, and RGB666 Max. 2 inputs • Geometry engine (MB86296 compatible display list is usable) • 2D/3D drawing function (MB86296 compatible display list is usable) I2S (*2) • • • • • • • • Audio output × 3ch (L/R)/Audio input × 3ch (L/R) Supported three-wire serial (I2S, MSB-Justified) and serial PCM data transfer interface Master/Slave operations are selectable Resolution capability: Max. 32 bit/sample Max. 6 channels (dedicated channel: 3ch, option: 3ch) 1 channel: capable of input/output CTS/RTS signals 8 bit pre-scaler for baud rate clock generation Enabled DMA transfer UART (*2) I2C SPI (*2) CAN (*2) • 3.3V pin × 2ch • Supported standard mode (max. 100kbps)/high-speed mode (max. 400kbps) • Full duplex/Synchronous transmission • Transfer data length: 1 bit unit (max. 32 bit) (programmable setting) • Mounted BOSCH C_CAN module × 2ch • Conformed to CAN protocol version 2.0 part A and B • I/O voltage: 3.3V • 16 channels • MediaLB clock speed: 256Fs/512Fs/1024Fs • Built-in 9K bit channel buffer • USB 2.0 compliant Host/Function controller × 1ch (pin multiplex) • HS/FS protocol support (supported VBus and isochronous transfer) MediaLB (*2) USB (*2) IDE (*2) • • • • Supported ATA/ATAPI-5 Equipped 1 channel Supported primary IDE channel Equipped transmission FIFO buffer (512 byte × 2) and reception FIFO buffer (512 byte × 2) for the ultra DMA transfer • Unsupported single word DMA and multiword DMA SDMC • • • • Conformed to SD memory card physical layer specification 1.0 Equipped 1 channel Supported SD memory card and multimedia card Unsupported SPI mode, SDIO mode, and CPRM CCNT • Mode selection of multiplex pin group 2 and 4 • Software reset control • AXI interconnection control (priority and WAIT setting) • Conformed to IEIEEE1149.1 (IEEE Standard Test Access Port and Boundary-Scan • Supported JTAG ICE connection Architecture) JTAG *1: Number of layer of simultaneous display and number of output display as well as capture input for displaying in high resolution may be restricted due to data supply capacity of graphics memory (DDR2 controller). *2: A part of external pin functions of this LSI is multiplexed. Max. number of usable channel is limited by pin multiplex function setting. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 5 MB86R01 DATA SHEET 5. Package dimension Package dimension of MB86R01 is shown below. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 6 MB86R01 DATA SHEET 6. Pin assignment Pin assignment of MB86R01 is shown below. (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 2 101 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 75 3 102 193 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 169 74 4 103 194 277 352 351 350 349 348 347 346 345 344 343 342 341 340 339 338 337 336 335 334 255 168 73 5 104 195 278 353 420 419 418 417 416 415 414 413 412 411 410 409 408 407 406 405 404 333 254 167 72 6 105 196 279 354 7 106 197 280 355 8 107 198 281 356 9 108 199 282 357 10 109 200 283 358 11 110 201 284 359 12 111 202 285 360 13 112 203 286 361 14 113 204 287 362 15 114 205 288 363 16 115 206 289 364 17 116 207 290 365 18 117 208 291 366 19 118 209 292 367 20 119 210 293 368 21 120 211 294 369 421 448 447 446 445 444 443 442 422 449 468 467 466 465 464 441 423 450 469 480 479 478 463 440 424 451 470 481 484 477 462 439 425 452 471 482 483 476 461 438 426 453 472 473 474 475 460 437 427 454 455 456 457 458 459 436 428 429 430 431 432 433 434 435 403 332 253 166 71 402 331 252 165 70 401 330 251 164 69 400 329 250 163 68 399 328 249 162 67 398 327 248 161 66 397 326 247 160 65 396 325 246 159 64 395 324 245 158 63 394 323 244 157 62 393 322 243 156 61 392 321 242 155 60 391 320 241 154 59 390 319 240 153 58 389 318 239 152 57 388 317 238 151 56 22 121 212 295 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 316 237 150 55 23 122 213 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 236 149 54 24 123 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 148 53 25 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 52 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 7 MB86R01 DATA SHEET (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A VSS VSS DCLKO0 VSS DCLKIN0 DOUTG0 DOUTG0 DOUTB0 [6] [2] [4] XSRST TRACE DATA[3] TRACE CTL TRACE CLK RTCK XRST TRACE DATA[0] PLLVSS PLLVDD TDO VSS CLK MEM XCS[4] MEM XCS[2] MEM XCS[0] VDDI MEM XRD MEM XWR[1] MEM XWR[0] MEM EA[24] VDDI VSS MEM EA[23] MEM EA[22] MEM EA[21] VSS MEM EA[20] MEM EA[19] MEM EA[18] MEM EA[17] VSS MEM EA[16] MEM EA[15] MEM EA[14] MEM EA[13] VDDE MEM EA[12] MEM EA[11] MEM EA[10] MEM EA[9] VDDE MEM EA[8] MEM EA[7] MEM EA[6] MEM EA[5] VDDI MEM EA[4] MEM EA[3] MEM EA[2] MEM ED[10] MEM ED[6] MEM ED[2] MEM EA[1] MEM ED[15] MEM ED[13] MEM ED[9] MEM ED[5] MEM ED[1] VSS MEM ED[14] MEM ED[12] MEM ED[8] MEM ED[4] MEM ED[0] VSS B VSS DOUTB1 [2] DE0 HSYNC0 VDDE DOUTR0 DOUTG0 DOUTG0 DOUTB0 [4] [7] [3] [5] XTRST TMS VINITHI CRIPM3 VDDE VSS MEM ED[11] MEM ED[7] MEM ED[3] VSS MDQS P[3] MDQS N[3] VSS MDQS P[2] MDQS N[2] VSS C GV0 VSYNC0 DOUTR0 DOUTR0 DOUTR0 DOUTG0 DOUTB0 DOUTB0 [7] [5] [2] [4] [6] [2] TRACE JTAGSEL DATA[1] TRACE PLLTDTRST DATA[2] VDDI VSS TCK CRIPM2 CRIPM0 MEM RDY VDDE D DOUTB1 DOUTB1 DOUTB1 DOUTB1 DOUTR0 DOUTR0 DOUTG0 DOUTB0 DOUTB0 [6] [5] [4] [3] [6] [3] [5] [7] [3] DOUTG1 DOUTG1 DOUTG1 DOUTB1 [4] [3] [2] [7] DOUTR1 DOUTG1 DOUTG1 DOUTG1 [2] [7] [6] [5] DCLKIN DOUTR1 DOUTR1 DOUTR1 1 [5] [4] [3] VSS VDDE DOUTR1 DOUTR1 [7] [6] VSYNC1 HSYNC1 VIN0 [7] VIN0 [3] VIN VSYNC0 VIN HSYNC0 USB AVSF1 USB AVDF1 USB AVSF2 USB AVDF2 VIN1 [7] VIN1 [4] VIN1 [1] VDDE VSS VSS VDDE VDDE TDI CRIPM1 E VDDI VSS VDDE F VDDE VDDI G VDDI VSS MDQ[30] MDM[3] MDQ[31] H VDDI VSS MDQ[25] MDQ[28] MDQ[24] J DCLKO1 VIN0 [5] VIN0 [1] CCLK0 GV1 VIN0 [6] VIN0 [2] VDDE VSS DDRVDE MDQ[27] MDQ[26] MDQ[29] K DE1 VIN0 [4] VIN0 [0] VDDI USB_ AVSB USB AVSF2 USB AVSF2 VSS VSS VDDI VDDE VDDE VDDI VDDI VDDE VDDE VDDI DDRVDE MDM[2] MDQ[23] VREF1 L VDDE VDDI VSS VSS VSS VSS VSS VSS VDDI DQ22 MDQ[20] MDQ[17] MDQ[16] M VDDE VDDE VSS VSS VSS VSS VSS VSS DDRVDE VSS MDQ[19] MDQ[18] MDQ[21] N VSS USB AVSP USB HSDP USB HSDM USB AVSF2 USB CRYCK48 VIN1 [6] VSS VINFID0 USB AVDP USB FSDP USB FSDM USB AVSF2 USB MODE VIN1 [5] VIN1 [2] VDDE I2S SDO2 PWM_O1 VDDI USB AVDB USB EXT12K USB AVSF2 VDDI VDDE VSS VSS VSS VSS VSS VSS DDRVDE VDDI ODT VSS DDRVDE MCKP P VDDI VSS VSS VSS VSS VSS VSS VDDI VDDI OCD VSS DDRVDE MCKN R VDDI VSS VSS VSS VSS VSS VSS VDDI VSS MDQ[14] MDM[1] MDQ[15] VSS MDQS P[1] MDQS N[1] VSS MDQS P[0] MDQS N[0] VSS T VDDE VSS VSS VSS VSS VSS VSS DDRVDE DDRVDE MDQ[12] MDQ[9] MDQ[8] U VDDE VDDI VDDI VDDE VDDE VDDI VDDI DDRVDE DDRVDE MDQ[11] MDQ[10] MDQ[13] V VSS VIN1 [3] VIN1 [0] VDDI MDQ[6] MDM[0] MDQ[7] VREF0 W VDDE VSS MDQ[4] MDQ[1] MDQ[0 Y VDDE VSS MDQ[3] MDQ[5] MDQ[2] AA CCLK1 VIN VIN VSYNC1 HSYNC1 I2S SDI2 I2S WS2 VSS AD VRL0 AD VR0 AD VIN0 AD VRH0 AD AVD AD VRL1 AD VR1 AD VIN1 AD VRH1 AD AVS DDRVDE MCAS MRAS MCKE AB VINFID1 I2S SCK2 I2S ECLK2 VSS VSS IDE DD[15] VDDE IDE DD[11] IDE DD[10] IDE DD[9] IDE DD[8] VDDE IDE DD[7] IDE DD[6] IDE DD[5] IDE DD[4] VDDI IDE DD[3] IDE DD[2] IDE DD[1] IDE DD[0] VDDI IDE DA[2] IDE DA[1] IDE DA[0] IDE CSEL VSS IDE XDIOW IDE XDIOR VSS VDDE VSS VSS UART SIN2 UART SOUT2 UART XCTS0 UART SIN0 VSS SD CLK SD CMD UART SOUT1 UART SIN1 VDDE SD DAT[3] VDDE VDDI INT_A [2] I2C SDA0 I2C SCL0 I2C SCL1 VDDI DDRVDE MCS MWE MBA[0] MBA[1] AC IDE IDE DIORDY DINTRQ MPX TEST MODE_1 MODE[0] [0] MPX PLL MODE_1 BYPASS [1] BIGEND VDDE VPD DDRTYPEODTCONT MA[0] INT_A [1] INT_A [3] I2C SDA1 TEST MODE[2] MCKE START INT_A [0] MA[2] MA[10] MA[1] AD IDE IDE IDE PWM_O0 XCBLID DDMARQ DD[14] VSS IDE IDE IDE XDDMAC DD[13] XDASP K IDE IDE XIOCS16 DRESET IDE DD[12] VDDE UART XRTS0 UART SOUT0 SD USB DAT[2] PRTPWR SD DAT[1] SD DAT[0] SD XMCD SD WP MA[9] MA[6] MA[5] MA[3] AE MPX IDE MODE_5 XDCS[0] [0] MA[13] MA[4] MA[11] MA[7] AF VSS VSS MPX TEST IDE MODE_5 MODE[1] XDCS[1] [1] MA[8] MA[12] VSS VSS FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 8 MB86R01 DATA SHEET Pin assignment table Pin NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 JEDEC A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 N1 P1 R1 T1 U1 V1 W1 Y1 AA1 AB1 AC1 AD1 AE1 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AE26 AD26 AC26 AB26 AA26 Y26 W26 V26 U26 T26 R26 P26 N26 M26 L26 K26 J26 H26 G26 F26 E26 D26 C26 B26 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 PIN NAME Pin NO VSS 101 VSS 102 DOUTB1[2] 103 DOUTB1[6] 104 DOUTG1[4] 105 DOUTR1[2] 106 DCLKIN1 107 VSS 108 DCLKO1 109 VIN0[5] 110 VIN0[1] 111 CCLK0 112 VSS 113 USB_AVSP 114 USB_HSDP 115 USB_HSDM 116 USB_AVSF2 117 USB_CRYCK48 118 VIN1[6] 119 VSS 120 CCLK1 121 VINFID1 122 I2S_SCK2 123 I2S_ECLK2 124 VSS 125 VSS 126 VSS 127 IDE_XIOCS16 128 IDE_XDRESET 129 IDE_DD[12] 130 IDE_DD[8] 131 IDE_DD[4] 132 IDE_DD[0] 133 IDE_CSEL 134 IDE_XDCS[1] 135 MPX_MODE_5[1] 136 TESTMODE[1] 137 AD_AVD 138 AD_AVS 139 UART_SOUT0 140 UART_SIN0 141 UART_SIN1 142 SD_DAT[0] 143 SD_WP 144 I2C_SCL1 145 I2C_SDA1 146 INT_A[0] 147 MA[8] 148 MA[12] 149 VSS 150 VSS 151 MA[7] 152 MA[3] 153 MA[1] 154 MBA[1] 155 VSS 156 MDQSN[0] 157 MDQSP[0] 158 VSS 159 MDQSN[1] 160 MDQSP[1] 161 VSS 162 MCKN 163 MCKP 164 VSS 165 MDQSN[2] 166 MDQSP[2] 167 VSS 168 MDQSN[3] 169 MDQSP[3] 170 VSS 171 MEM_ED[3] 172 MEM_ED[7] 173 MEM_ED[11] 174 VSS 175 VSS 176 VSS 177 MEM_EA[1] 178 MEM_EA[4] 179 MEM_EA[8] 180 MEM_EA[12] 181 MEM_EA[16] 182 MEM_EA[20] 183 VSS 184 MEM_XRD 185 CLK 186 VSS 187 TDO 188 PLLVDD 189 PLLVSS 190 XRST 191 TRACEDATA[3] 192 XSRST 193 DOUTB0[4] 194 DOUTG0[2] 195 DOUTG0[6] 196 DCLKIN0 197 VSS 198 DCLKO0 199 VSS 200 JEDEC B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N2 P2 R2 T2 U2 V2 W2 Y2 AA2 AB2 AC2 AD2 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AD25 AC25 AB25 AA25 Y25 W25 V25 U25 T25 R25 P25 N25 M25 L25 K25 J25 H25 G25 F25 E25 D25 C25 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 C3 D3 E3 F3 G3 H3 J3 K3 PIN NAME Pin NO DE0 201 GV0 202 DOUTB1[5] 203 DOUTG1[3] 204 DOUTG1[7] 205 DOUTR1[5] 206 VDDE 207 GV1 208 VIN0[6] 209 VIN0[2] 210 VDDE 211 VINFID0 212 USB_AVDP 213 USB_FSDP 214 USB_FSDM 215 USB_AVSF2 216 USB_MODE 217 VIN1[5] 218 VIN1[2] 219 VDDE 220 I2S_SDO2 221 PWM_O1 222 PWM_O0 223 VSS 224 IDE_XDASP 225 IDE_XDDMACK 226 IDE_DD[13] 227 IDE_DD[9] 228 IDE_DD[5] 229 IDE_DD[1] 230 IDE_DA[0] 231 IDE_XDCS[0] 232 MPX_MODE_5[0] 233 BIGEND 234 AD_VRH0 235 AD_VRH1 236 UART_XRTS0 237 UART_XCTS0 238 UART_SOUT1 239 SD_DAT[1] 240 SD_XMCD 241 I2C_SCL0 242 INT_A[3] 243 MCKE_START 244 MA[13] 245 MA[4] 246 MA[11] 247 MA[5] 248 MA[10] 249 MBA[0] 250 MCKE 251 MDQ[2] 252 MDQ[0] 253 VREF0 254 MDQ[13] 255 MDQ[8] 256 MDQ[15] 257 DDRVDE 258 DDRVDE 259 MDQ[21] 260 MDQ[16] 261 VREF1 262 MDQ[29] 263 MDQ[24] 264 MDQ[31] 265 MEM_ED[0] 266 MEM_ED[4] 267 MEM_ED[8] 268 MEM_ED[12] 269 MEM_ED[14] 270 MEM_ED[15] 271 MEM_EA[3] 272 MEM_EA[7] 273 MEM_EA[11] 274 MEM_EA[15] 275 MEM_EA[19] 276 MEM_EA[23] 277 MEM_XWR[1] 278 MEM_XCS[4] 279 VDDE 280 CRIPM3 281 VINITHI 282 TMS 283 TRACEDATA[0] 284 TRACECTL 285 XTRST 286 DOUTB0[5] 287 DOUTG0[3] 288 DOUTG0[7] 289 DOUTR0[4] 290 VDDE 291 HSYNC0 292 VSYNC0 293 DOUTB1[4] 294 DOUTG1[2] 295 DOUTG1[6] 296 DOUTR1[4] 297 DOUTR1[7] 298 VSYNC1 299 VIN0[7] 300 JEDEC L3 M3 N3 P3 R3 T3 U3 V3 W3 Y3 AA3 AB3 AC3 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 P24 N24 M24 L24 K24 J24 H24 G24 F24 E24 D24 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 D4 E4 F4 G4 H4 J4 K4 L4 M4 N4 P4 R4 T4 U4 V4 W4 Y4 AA4 AB4 AC4 AC5 AC6 AC7 AC8 PIN NAME Pin NO VIN0[3] 301 VINVSYNC0 302 VINHSYNC0 303 USB_AVSF1 304 USB_AVDF1 305 USB_AVSF2 306 USB_AVDF2 307 VIN1[7] 308 VIN1[4] 309 VIN1[1] 310 VINVSYNC1 311 I2S_SDI2 312 IDE_DIORDY 313 IDE_XCBLID 314 IDE_DDMARQ 315 IDE_DD[14] 316 IDE_DD[10] 317 IDE_DD[6] 318 IDE_DD[2] 319 IDE_DA[1] 320 IDE_XDIOR 321 MPX_MODE_1[1] 322 PLLBYPASS 323 AD_VIN0 324 AD_VIN1 325 VDDE 326 UART_SOUT2 327 SD_CMD 328 SD_DAT[2] 329 USB_PRTPWR 330 I2C_SDA0 331 INT_A[1] 332 TESTMODE[2] 333 MA[9] 334 MA[6] 335 MA[2] 336 MWE 337 MRAS 338 MDQ[5] 339 MDQ[1] 340 MDQ[7] 341 MDQ[10] 342 MDQ[9] 343 MDM[1] 344 VSS 345 VSS 346 MDQ[18] 347 MDQ[17] 348 MDQ[23] 349 MDQ[26] 350 MDQ[28] 351 MDM[3] 352 MEM_ED[1] 353 MEM_ED[5] 354 MEM_ED[9] 355 MEM_ED[13] 356 MEM_EA[2] 357 MEM_EA[6] 358 MEM_EA[10] 359 MEM_EA[14] 360 MEM_EA[18] 361 MEM_EA[22] 362 MEM_XWR[0] 363 MEM_XCS[2] 364 CRIPM0 365 CRIPM2 366 TCK 367 JTAGSEL 368 TRACEDATA[1] 369 TRACECLK 370 DOUTB0[2] 371 DOUTB0[6] 372 DOUTG0[4] 373 DOUTR0[2] 374 DOUTR0[5] 375 DOUTR0[7] 376 DOUTB1[3] 377 DOUTB1[7] 378 DOUTG1[5] 379 DOUTR1[3] 380 DOUTR1[6] 381 HSYNC1 382 DE1 383 VIN0[4] 384 VIN0[0] 385 VDDI 386 USB_AVSB 387 USB_AVSF2 388 USB_AVSF2 389 VSS 390 VSS 391 VIN1[3] 392 VIN1[0] 393 VINHSYNC1 394 I2S_WS2 395 IDE_DINTRQ 396 IDE_DD[15] 397 IDE_DD[11] 398 IDE_DD[7] 399 IDE_DD[3] 400 JEDEC PIN NAME Pin NO AC9 IDE_DA[2] 401 AC10 IDE_XDIOW 402 AC11 MPX_MODE_1[0] 403 AC12 TESTMODE[0] 404 AC13 AD_VR0 405 AC14 AD_VR1 406 AC15 VDDE 407 AC16 UART_SIN2 408 AC17 SD_CLK 409 AC18 SD_DAT[3] 410 AC19 VPD 411 AC20 INT_A[2] 412 AC21 DDRTYPE 413 AC22 ODTCONT 414 AC23 MA[0] 415 AB23 MCS 416 AA23 MCAS 417 Y23 MDQ[3] 418 W23 MDQ[4] 419 V23 MDM[0] 420 U23 MDQ[11] 421 T23 MDQ[12] 422 R23 MDQ[14] 423 P23 OCD 424 N23 ODT 425 M23 MDQ[19] 426 L23 MDQ[20] 427 K23 MDM[2] 428 J23 MDQ[27] 429 H23 MDQ[25] 430 G23 MDQ[30] 431 F23 MEM_ED[2] 432 E23 MEM_ED[6] 433 D23 MEM_ED[10] 434 D22 MEM_EA[5] 435 D21 MEM_EA[9] 436 D20 MEM_EA[13] 437 D19 MEM_EA[17] 438 D18 MEM_EA[21] 439 D17 MEM_EA[24] 440 D16 MEM_XCS[0] 441 D15 MEM_RDY 442 D14 CRIPM1 443 D13 TDI 444 D12 PLLTDTRST 445 D11 TRACEDATA[2] 446 D10 RTCK 447 D9 DOUTB0[3] 448 D8 DOUTB0[7] 449 D7 DOUTG0[5] 450 D6 DOUTR0[3] 451 D5 DOUTR0[6] 452 E5 VDDE 453 F5 VDDE 454 G5 VDDI 455 H5 VDDI 456 J5 VSS 457 K5 VSS 458 L5 VDDE 459 M5 VDDE 460 N5 VDDI 461 P5 USB_AVDB 462 R5 USB_EXT12K 463 T5 USB_AVSF2 464 U5 VDDI 465 V5 VDDI 466 W5 VDDE 467 Y5 VDDE 468 AA5 VSS 469 AB5 VSS 470 AB6 VDDE 471 AB7 VDDE 472 AB8 VDDI 473 AB9 VDDI 474 AB10 VSS 475 AB11 VSS 476 AB12 VDDE 477 AB13 AD_VRL0 478 AB14 AD_VRL1 479 AB15 VSS 480 AB16 VSS 481 AB17 VSS 482 AB18 VDDE 483 AB19 VDDE 484 AB20 VDDI AB21 VDDI AB22 DDRVDE AA22 DDRVDE Y22 VSS W22 VSS V22 MDQ[6] U22 DDRVDE T22 DDRVDE R22 VSS P22 VDDI N22 VDDI M22 VSS L22 MDQ[22] K22 DDRVDE J22 DDRVDE JEDEC H22 G22 F22 E22 E21 E20 E19 E18 E17 E16 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 K10 L10 M10 N10 P10 R10 T10 U10 U11 U12 U13 U14 U15 U16 U17 T17 R17 P17 N17 M17 L17 K17 K16 K15 K14 K13 K12 K11 L11 M11 N11 P11 R11 T11 T12 T13 T14 T15 T16 R16 P16 N16 M16 L16 L15 L14 L13 L12 M12 N12 P12 R12 R13 R14 R15 P15 N15 M15 M14 M13 N13 P13 P14 N14 PIN NAME VSS VSS VDDI VDDI VDDE VDDE VSS VSS VDDI VDDI VDDE VDDE VSS VSS VDDI VDDI VDDE VDDE VSS VSS VDDI VDDI VDDE VDDE VDDI VDDI VDDE VDDE VDDI VDDI VDDE VDDE VDDI VDDI DDRVDE DDRVDE VDDI VDDI DDRVDE DDRVDE VDDI VDDI VDDE VDDE VDDI VDDI VDDE VDDE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 9 MB86R01 DATA SHEET 7. 7.1. Pin function External pin function of MB86R01 is described below. Pin Multiplex This LSI adopts pin multiplex function, and a part of external pin function is multiplexed. The external pin function is categorized into following five groups. Each group is able to set the external pin function individually; therefore, the function can be flexibly set depending on the peripheral I/O resource to be used. 1. Pin multiplex group #1 (setting pin: MPX_MODE_1[1:0]) • Mode 0: Pin related to DISPLAY1 • Mode 1: Pin related to external bus interface • Mode 2: Pin related to I2S0, GPIO, and DISPLAY0 data width extension 2. Pin multiplex group #2 (setting register: CMUX_MD.MPX_MODE_2[2:0]) • Mode 0: Pin related to CAP1, CAP0 synchronizing signal, PWM, and I2S2 • Mode 1: Pin related to CAP1 (NRGB666) • Mode 2: Pin related to GPIO, CAN, I2S1, MediaLB, and I2S2 • Mode 3: Pin related to GPIO, CAN, I2S1, MediaLB, and SPI • Mode 4: Pin related to GPIO, CAN, I2S1, MediaLB, and I2S2 (input) 3. Pin multiplex group #3 (setting pin: USB_MODE) • Mode 0: Pin related to USB 2.0 host • Mode 1: Pin related to USB 2.0 function 4. Pin multiplex group #4 (setting register: CMUX_MD.MPX_MODE_4[1:0]) • Mode 0: Pin related to IDE • Mode 1: Pin related to I2S1, CAN, GPIO, and PWM 5. Pin multiplex group #5 (setting pin: MPX_MODE_5[1:0]) • Mode 0: Pin related to ETM • Mode 1: Pin related to UART3, UART4, and UART5 • Mode 2: Pin related to UART3, UART4, and PWM Note: Mode should be changed when each pin is not in operation. PWM, I2S1, and CAN pins may be duplicated and allocated to external pin depending on group combination; in this case, use either of them. For unused pin, follow the procedure in 1.6.27, unused pin with pin multiplex function in the duplex case. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 10 MB86R01 DATA SHEET Pin multiplex group #1 (setting pin: MPX_MODE_1 [1:0]) Mode 0 Pin related to DISPLAY1 DOUTR1[7] DOUTR1[6] DOUTR1[5] DOUTR1[4] DOUTR1[3] DOUTR1[2] DOUTG1[7] DOUTG1[6] DOUTG1[5] DOUTG1[4] DOUTG1[3] DOUTG1[2] DOUTB1[7] DOUTB1[6] DOUTB1[5] DOUTB1[4] DOUTB1[3] DOUTB1[2] DE1 HSYNC1 VSYNC1 GV1 Mode 1 Pin related to external bus interface MEM_ED[31] MEM_ED[30] MEM_ED[29] MEM_ED[28] MEM_ED[27] MEM_ED[26] MEM_ED[25] MEM_ED[24] MEM_ED[23] MEM_ED[22] MEM_ED[21] MEM_ED[20] MEM_ED[19] MEM_ED[18] MEM_ED[17] MEM_ED[16] MEM_XWR[3] MEM_XWR[2] XDACK[7] DREQ[6] XDACK[6] DREQ[7] Mode 2 Pin related to Pin related to GPIO DISPLAY0 GPIO_PD[12] GPIO_PD[11] GPIO_PD[10] GPIO_PD[9] GPIO_PD[8] GPIO_PD[7] GPIO_PD[6] DOUTR0[1] DOUTR0[0] DOUTG0[1] DOUTG0[0] DOUTB0[1] DOUTB0[0] - Pin No. JEDEC Pin related to I2S0 I2S_ECLK0 I2S_SCK0 I2S_WS0 I2S_SDI0 I2S_SDO0 - 198 281 106 197 280 6 105 196 279 5 104 195 278 4 103 194 277 3 283 282 199 108 H3 H4 G2 G3 G4 F1 F2 F3 F4 E1 E2 E3 E4 D1 D2 D3 D4 C1 K4 J4 J3 J2 Pin related to external bus interface XDACK[7] DREQ[6] XDACK[6] DREQ[7] Pin multiplex group #1 mode setting This mode is set with external pin, MPX_MODE_1[1:0]. MPX_MODE_1[1] pin "L" "L" "H" "H" MPX_MODE_1[0] pin "L" "H" "L" "H" Pin multiplex group #1 mode Mode 0 Mode 1 Mode 2 Mode 0 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 11 MB86R01 DATA SHEET Pin multiplex group #2 (setting register: PIN MPX Select.MPX_MODE_2 [2:0]) Mode0 Pin No. JEDEC Pin related to Mode1 Mode2 Mode3 Mode4 CAP0/1 208 19 118 209 292 119 210 293 211 294 22 202 203 112 123 122 121 V3 W1 W2 W3 W4 Y2 Y3 Y4 AA3 AA4 AB1 M3 N3 N2 AD2 AC2 AB2 VIN1[7] VIN1[6] VIN1[5] VIN1[4] VIN1[3] VIN1[2] VIN1[1] VIN1[0] VINVSYNC1 VINHSYNC1 VINFID1 VINVSYNC0 VINHSYNC0 VINFID0 - Pin related to Pin related Pin related Pin related to CAP1 to PWM to I2S2 GPIO (NRGB666) RI1[7] GPIO_PD[5] RI1[6] GPIO_PD[4] RI1[5] RI1[4] RI1[3] RI1[2] GI1[7] GI1[6] VINVSYNC1 VINHSYNC1 VINFID1 GI1[5] GI1[4] GI1[3] PWM_O0 GI1[2] GPIO_PD[3] PWM_O1 BI1[7] GPIO_PD[2] I2S_SDO2 BI1[6] I2S_ECLK2 BI1[5] - Pin related to CAN CAN_TX0 CAN_RX0 CAN_TX1 CAN_RX1 - 24 AD1 - - 23 AC1 295 AB4 212 AB3 I2S_SCK2 I2S_WS2 I2S_SDI2 BI1[4] BI1[3] BI1[2] Pin Pin related Pin related Pin related Pin related Pin related Pin related Pin related Pin related Pin related Pin related to related to to I2S1/2 to MediaLB to GPIO to CAN to I2S1 to MediaLB to GPIO to CAN to I2S1/2 MediaLB SPI - GPIO_PD[5] - GPIO_PD[5] - GPIO_PD[4] - GPIO_PD[4] CAN_TX0 CAN_TX0 CAN_RX0 CAN_RX0 CAN_TX1 CAN_TX1 CAN_RX1 CAN_RX1 I2S_SCK1 I2S_SCK1 - I2S_SCK1 I2S_WS1 I2S_WS1 I2S_WS1 I2S_ECLK1 - I2S_ECLK1 - I2S_ECLK1 I2S_SDI1 I2S_SDI1 I2S_SDI1 I2S_SDO1 I2S_SDO1 - I2S_SDO1 - MLB_DATA - MLB_DATA MLB_DATA MLB_SIG MLB_SIG MLB_SIG MLB_CLK MLB_CLK MLB_CLK - GPIO_PD[3] - GPIO_PD[3] - GPIO_PD[2] - GPIO_PD[2] I2S_SDO2 SPI_DO GPIO_PD[1] Reserved I2S_ECLK2 GPIO_PD[0] (Input/Output) I2S_SCK2 SPI_SCK - I2S_SCK2 I2S_WS2 SPI_SS I2S_WS2 I2S_SDI2 SPI_DI I2S_SDI2 - Pin multiplex group #2 mode setting This mode is set with MPX_MODE_2 bit (bit 2-0) in the multiplex mode setting register (CMUX_MD.) MPX_MODE_2 (bit 2-0) of the CMUX_MD register 000 001 010 011 100 101 – 0110 111 Pin multiplex group #2 mode Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Reserved (Initial value) FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 12 MB86R01 DATA SHEET Pin multiplex group #3 (setting pin: USB_MODE) Pin No. JEDEC Mode 0 Pin related to USB 2.0 host USB_FSDP USB_FSDM USB_HSDP USB_HSDM USB_CRYCK48 USB_PRTPWR Mode 1 Pin related to USB 2.0 function USB_FSDP USB_FSDM USB_HSDP USB_HSDM USB_CRYCK48 USB_PRTPWR 114 115 15 16 18 230 R2 T2 R1 T1 V1 AD19 Pin multiplex group #3 mode setting This mode is set with external pin, USB_MODE. USB_MODE pin "L" "H" Pin multiplex group #3 mode Mode 0 Mode 1 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 13 MB86R01 DATA SHEET Pin multiplex group #4 (setting register: PIN_MPX_Select.MPX_MODE_4 [1:0]) Mode 0 Pin No. JEDEC 29 28 125 215 296 214 297 216 127 30 298 217 128 31 299 218 129 32 300 219 130 33 213 301 220 131 35 132 221 302 34 126 AF4 AF3 AE3 AD4 AC4 AD3 AC5 AD5 AE5 AF5 AC6 AD6 AE6 AF6 AC7 AD7 AE7 AF7 AC8 AD8 AE8 AF8 AC3 AC9 AD9 AE9 AF10 AE10 AD10 AC10 AF9 AE4 Pin related to Pin related to IDE I2S1 IDE_XDRESET IDE_XIOCS16 I2S_SDI1 IDE_XDASP I2S_WS1 IDE_DDMARQ I2S_ECLK1 IDE_DINTRQ I2S_SDO1 IDE_XCBLID I2S_SCK1 IDE_DD[15] IDE_DD[14] IDE_DD[13] IDE_DD[12] IDE_DD[11] IDE_DD[10] IDE_DD[9] IDE_DD[8] IDE_DD[7] IDE_DD[6] IDE_DD[5] IDE_DD[4] IDE_DD[3] IDE_DD[2] IDE_DD[1] IDE_DD[0] IDE_DIORDY IDE_DA[2] IDE_DA[1] IDE_DA[0] IDE_XDCS[1] IDE_XDCS[0] IDE_XDIOR IDE_XDIOW IDE_CSEL IDE_XDDMACK Pin related to CAN CAN_TX0 CAN_RX0 CAN_TX1 CAN_RX1 Mode 1 Pin related to GPIO GPIO_PD[23] GPIO_PD[22] GPIO_PD[21] GPIO_PD[20] GPIO_PD[19] GPIO_PD[18] GPIO_PD[17] GPIO_PD[16] GPIO_PD[15] GPIO_PD[14] GPIO_PD[13] - Pin related to PWM PWM_O1 PWM_O0 - Unused pin (input/output) Reserved (output) Reserved (input/output) Reserved (input) Reserved (output) Reserved (output) Reserved (output) Reserved (output) Reserved (output) Reserved (output) Reserved (output) Pin multiplex group #4 mode setting This mode is set with MPX_MODE_4 bit (bit 5-4) in the multiplex mode setting register (CMUX_MD.) MPX_MODE_4 (Bit 5-4) of the CMUX_MD register 00 01 10 11 Pin multiplex group #4 mode Mode 0 Mode 1 Reserved (Initial value) FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 14 MB86R01 DATA SHEET Pin multiplex group #5 (setting pin: MPX_MODE_5 [1:0]) Pin No. JEDEC Mode 0 Pin related to ETM TRACECLK TRACECTL TRACEDATA[3] TRACEDATA[2] TRACEDATA[1] TRACEDATA[0] Mode 1 Pin related to UART3/4/5 UART_SIN3 UART_SOUT3 UART_SIN4 UART_SOUT4 UART_SIN5 UART_SOUT5 Mode 2 Pin related to UART3/4 Pin related to PWM UART_SIN3 UART_SOUT3 UART_SIN4 UART_SOUT4 PWM_O1 PWM_O0 - 270 185 92 346 269 184 C10 B10 A10 D11 C11 B11 Pin multiplex group #5 mode setting This mode is set with external pin, MPX_MODE_5[1:0]. MPX_MODE_5[1] pin "L" "L" "H" "H" MPX_MODE_5[0] pin "L" "H" "L" "H" Pin multiplex group #5 mode Mode 0 Mode 1 Mode 2 Mode 0 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 15 MB86R01 DATA SHEET 7.2. Format Pin Function Pin function list is shown in the following format. Analog /Digital Status of pin after reset Pin name I/O Polarity Type Description Meaning of item and sign Pin name Name of external pin. I/O Input/Output signal's distinction based on this LSI. • I: Pin that can be used as input • O: Pin that can be used as output • IO: Pin that can be used as input and output (interactive pin) Polarity Active polarity of external pin's input/output signals • P: "H" active pin (positive logic) • N: "L" active pin (negative logic) • PN: "H" and "L" active pins Analog/Digital Signal type of external pin • A: Analog signal • D: Digital signal Type Input/Output circuit type of external pin. • CLK: • POD: Pseudo Open Drain • PU: Pull Up • PD: Pull Down • ST: Schmitt Type • Tri: Tri-state Pin status after reset Pin status after external pin reset • H: "H" level • L: "L" level • HiZ: High impedance • X: "H" level or "L" level • A: Clock output Description Outline of external pin function FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 16 MB86R01 DATA SHEET 7.2.1. Pin name External bus interface related pin I/O O O O O O Polarity N N N N N Analog /Digital D D D D D Type Status of pin after reset H H H H H Description Chip select 4 Chip select 2 Chip select 0 Read strobe Write strobe MEM_XWR[3] -> MEM_ED[31:24], MEM_XWR[2] -> MEM_ED[23:16] (optional pin) Write strobe MEM_XWR[1] -> MEM_ED[15:8], MEM_XWR[0] -> MEM_ED[7:0] Ready input for slow device Address bus Bi-directional data bus (optional pin) Bi-directional data Bus External DMA request External DMA acknowledge MEM_XCS[4] MEM_XCS[2] MEM_XCS[0] MEM_XRD MEM_XWR[3:2] MEM_XWR[1:0] O N D - H MEM_RDY MEM_EA[24:1] MEM_ED[31:16] MEM_ED[15:0] DREQ[7:6] XDACK[7:6] I O IO IO I O P P D D D D D D - L HiZ HiZ L 7.2.2. Pin name IDE_XDRESET IDE_DD[15:0] IDE66 related pin I/O O IO O O O O I I O O I I I I Polarity N N P N N P P N P N N P N Analog /Digital D D D D D D D D D D D D D D Type PD PD PD PD Status of pin after reset H L H L H H H L IDE reset IDE device data IDE chip select IDE device address IDE device I/O read IDE device I/O write IDE I/O channel ready IDE device DMA request IDE device DMA acknowledge IDE cable select IDE 16 bit I/O IDE device active IDE Interrupt IDE cable ID Description IDE_XDCS[1:0] IDE_DA[2:0] IDE_XDIOR IDE_XDIOW IDE_DIORDY IDE_DDMARQ IDE_XDDMACK IDE_CSEL IDE_XIOCS16 IDE_XDASP IDE_DINTRQ IDE_XCBLID FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 17 MB86R01 DATA SHEET 7.2.3. Pin name SD_CLK SD_CMD SD_DAT[3:0] SD_WP SD_XMCD SD Memory controller related pin I/O O IO IO I I Polarity N P N Analog /Digital D D D D D Type Status of pin after reset L HiZ HiZ Media clock Media command Media data Media write protection Media card detection Description 7.2.4. Pin name USB_FSDP USB_FSDM USB_HSDP USB_HSDM USB 2.0 Host/Function related pin I/O IO IO IO IO I O O Polarity Analog /Digital A A A A D D A Type CLK Status of pin after reset L D+ for FS D- for FS D+ for HS D- for HS Clock used for USB communication USB port power control External resistance pin This should be connected to USB_AVDB through 12kΩ resistance. PLL ground Reference voltage ground PLL power supply Reference voltage power supply Driver/Receiver ground 1 Driver/Receiver power supply 1 Driver/Receiver ground 2 Driver/Receiver power supply 2 Description USB_CRYCK48 USB_PRTPWR USB_EXT12K USB_AVSP USB_AVSB USB_AVDP USB_AVDB USB_AVSF1 USB_AVDF1 USB_AVSF2 USB_AVDF2 I I I I I I I I - A A A A A A A A - - 7.2.5. Pin name INT_A[3:0] External interrupt controller related pin I/O I Polarity PN Analog /Digital D Type Status of pin after reset Description Asynchronous external interrupt requests FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 18 MB86R01 DATA SHEET 7.2.6. Pin name UART_SIN0 UART_SOUT0 UART_XCTS0 UART_XRTS0 UART_SIN1 UART_SOUT1 UART_SIN2 UART_SOUT2 UART_SIN3 UART_SOUT3 UART_SIN4 UART_SOUT4 UART_SIN5 UART_SOUT5 UART related pin I/O I O I O I O I O I O I O I O Polarity P P N N P P P P P P P P P P Analog /Digital D D D D D D D D D D D D D D Type Status of pin after reset H H H H H H H Input data signal Output data signal Clear to send Request to send Input data signal Output data signal Input data signal Output data signal Input data signal (optional) Output data signal (optional) Input data signal (optional) Output data signal (optional) Input data signal (optional) Output data signal (optional) Explanation 7.2.7. Pin name CAN_TX0 CAN_RX0 CAN_TX1 CAN_RX1 CAN related pin I/O O I O I Polarity Analog /Digital D D D D Type PD PD PD PD Status of pin after reset H H Explanation Transmission (optional) Reception (optional) Transmission (optional) Reception (optional) 7.2.8. Pin name I2S_ECLK0 I2S_SCK0 I2S_WS0 I2S_SDI0 I2S_SDO0 I2S_ECLK1 I2S_SCK1 I2S_WS1 I2S_SDI1 I2S_SDO1 I2S_ECLK2 I2S_SCK2 I2S_WS2 I2S_SDI2 I2S_SDO2 I2S related pin I/O I IO IO I O I IO IO I O I IO IO I O Polarity PN P P PN P P PN P P Analog /Digital D D D D D D D D D D D D D D D Type PD PD PD PD PD PD PD Status of pin after reset HiZ HiZ Hiz L L L L L L Clock (optional) Sync (optional) Input data signal (optional) Output data signal (optional) External clock (optional) Clock (optional) Sync(optional) Input data signal (optional) Output data signal (optional) External clock (optional) Clock (optional) Sync (optional) Input data signal (optional) Output data signal (optional) Explanation External clock (optional) FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 19 MB86R01 DATA SHEET 7.2.9. Pin name I2C_SCL0 I2C_SDA0 I2C_SCL1 I2C_SDA1 I2C related pin I/O IO IO IO IO Polarity Analog /Digital D D D D Type POD POD POD POD Status of pin after reset HiZ HiZ HiZ HiZ I2C clock I2C data I2C clock I2C data Explanation 7.2.10. Pin name SPI_DO SPI_DI SPI_SCK SPI_SS SPI related pin I/O O I O O Polarity P P PN Analog /Digital D D D D Type PD PD PD Status of pin after reset L L L Explanation Serial data output (optional) Serial data input (optional) Serial clock (optional) Slave select (optional) 7.2.11. Pin name PWM_O0 PWM_O1 PWM related pin I/O O O Polarity Analog /Digital D D Type PD (*1) PD (*1) Status of pin after reset L L Explanation PWM out 0 (optional) PWM out 1 (optional) *1: Only PWM pin of the pin multiplex group #2 is with pull-down resistance. 7.2.12. Pin name AD_VIN0 AD_VRH0 AD_VRL0 AD_AVD AD_VR0 AD_VIN1 AD_VRH1 AD_VRL1 AD_AVS AD_VR1 A/D converter related pin I/O I I I I O I I I I O Polarity Analog /Digital A A A A A A A A A A Type Status of pin after reset A/D analog input Reference voltage "H" input Reference voltage "L" input Analog power supply Reference output A/D analog input Reference voltage "H" input Reference voltage "L" input Analog ground Reference output Explanation FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 20 MB86R01 DATA SHEET 7.2.13. Pin name MA[13:0] MBA[1:0] MDQ[31:0] MDM[3:0] MDQSP[3:0] MDQSN[3:0] MCKP MCKN MCKE MCS MRAS MCAS MWE DDRVDE VREF1 VREF0 OCD ODT ODTCONT MCKE_START DDR2 related pin I/O O O IO O IO IO O O O O O O O I I I O O O I Polarity P P P P P N P N P N N N N P P Analog /Digital D D D D D D D D D D D D D A A A A A D D Type CLK CLK Status of pin after reset H H H HiZ HiZ HiZ L H L L H H H L Address Bank address Data (*5) Data mask (*6) Data strobe (*5) Data strobe (*5) Clock output Clock output Clock enable Chip select Row address strobe Column address strobe Write enable SSTL_18 1.8V power supply Reference voltage input (DDRVDE/2) Reference voltage input (DDRVDE/2) Off chip driver reference voltage input (*1) On-die termination reference voltage input (*2) On-die termination control (*3) Set a state of MCKE in reset 0: Low (*4) 1: High (reserved) Pull-up pin to VDDE via high resistance Explanation DDRTYPE I P D - - *1: Pull up the pin to DDRVDE (1.8V power supply), via 200Ω resistance *2: PCB impedance Z = 100Ω or 50Ω: Pull up pin to DDRVDE (1.8V power supply), via a 180Ω resistance. PCB impedance Z = 150Ω or 75Ω: Pull up pin to DDRVDE (1.8V power supply), via a 240Ω resistance. *3: It connects it with the ODT pin of DDR2SDRAM *4: Pull down pin to VSS, via high resistance *5: This is process of unused pin at 16 bit mode. Pull down the pin to VSS via high resistance. Unused pins at 16 bit mode are as follows: "MDQ[31:16], MDQSP[3:2], MDQSN[3:2]" *6: This is process of MDM[3:2] at 16 bit mode. Be sure to open this pin. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 21 MB86R01 DATA SHEET 7.2.14. Pin name HSYNC0 VSYNC0 GV0 DCLKIN0 DCLKO0 DE0 DOUTR0[7:2] DOUTR0[1:0] DOUTG0[7:2] DOUTG0[1:0] DOUTB0[7:2] DOUTB0[1:0] HSYNC1 VSYNC1 GV1 DCLKIN1 DCLKO1 DE1 DOUTR1[7:2] DOUTG1[7:2] DOUTB1[7:2] DISPLAY related pin I/O IO IO O I O O O O O O O O IO IO O I O O O O O Polarity Analog /Digital D D D D D D D D D D D D D D D D D D D D D Type CLK CLK CLK CLK Status of pin after reset HiZ HiZ L X X X X X X X X HiZ HiZ L X X X X X Explanation Video output interface horizontal sync output Horizontal sync input in external sync mode Video output interface vertical sync output Vertical sync input in external sync mode Video output interface graphics/video switch Video output interface dot clock input Video output interface dot clock output DE/CSYNC Digital RGB output0 DataR[7:2] Digital RGB output0 DataR[1:0] (optional) Digital RGB output0 DataG[7:2] Digital RGB output0 DataG[1:0] (optional) Digital RGB output0 DataB[7:2] Digital RGB output0 DataB[1:0] (optional) Video output interface horizontal sync output Horizontal sync input in external sync mode Video output interface vertical sync output Vertical sync input in external sync mode Video output interface graphics/video switch Video output interface dot clock input Video output interface dot clock output DE/CSYNC Digital RGB output1 DataR[7:2] Digital RGB output1 DataG[7:2] Digital RGB output1 DataB[7:2] Note: When R:G:B = 5:5:5, lower 1 bit is set with the data contents of the upper 5 bits. [Upper 5 bits] DOUTR0[7:3]=00000 DOUTR0[7:3]=00001-11111 DOUTR1[7:3]=00000 DOUTR1[7:3]=00001-11111 [Lower 1 bit] -> DOUTR0[2]=0 (Low) -> DOUTR0[2]=1 (High) -> DOUTR1[2]=0 (Low) -> DOUTR1[2]=1 (High) DOUTG0[7:2], DOUTG1[7:2], DOUTB0[7:2], and DOUTB1[7:2] have also the same spec. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 22 MB86R01 DATA SHEET 7.2.15. Pin name VIN0[7:0] VINVSYNC0 VINHSYNC0 VINFID0 CCLK0 VIN1[7:0] VINVSYNC1 VINHSYNC1 VINFID1 CCLK1 RI1[7:2] GI1[7:2] BI1[7:2] Video capture related pin I/O I I I I I I I I I I I I I Polarity Analog /Digital D D D D D D D D D D D D D Type PD PD CLK PD PD CLK PD PD (*1) PD (*2) Status of pin after reset Description Video capture Data[7:0] Video capture vertical sync input Video capture horizontal sync input Video input field identification signal 0 in odd field Video capture input clock Video capture Data[7:0] Video capture vertical sync input Video capture horizontal sync input Video input field identification signal 0 in odd field Video capture input clock NRGB666 capture DataR[7:2] (optional) NRGB666 capture DataG[7:2] (optional) NRGB666 capture DataB[7:2] (optional) *1: GI1[3] is not applicable. *2: BI1[2] is not applicable. 7.2.16. Pin name CLK XRST CRIPM[3:0] VINITHI PLLBYPASS BIGEND System related pin I/O I I I I I I Polarity N Analog /Digital D D D D D D Type CLK ST Status of pin after reset Input clock System reset PLLMODE setting Boot high address PLL bypass mode setting LSI endian setting Low: Little endian High: Big endian PLL ground Test pin Pull up the pin to VDDE, via high resistance PLL power supply Description PLLVSS PLLTDTRST PLLVDD I I I - A D A - - 7.2.17. Pin name TCK XTRST TMS TDI TDO JTAG related pin I/O I I I I O Polarity N N Analog /Digital D D D D D Type ST, PU ST, PU PU PU Tri Status of pin after reset HiZ Test clock Test reset Test mode Test data input Test data output Description FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 23 MB86R01 DATA SHEET 7.2.18. Pin name RTCK XSRST ICE related pin I/O O IO Polarity N Analog /Digital D D Type ST, PU Status of pin after reset H H Return test clock System reset Description 7.2.19. Pin name JTAGSEL Multiplex setting related pin I/O I Polarity Analog /Digital D Type Status of pin after reset Description JTAG selection 1: DFT, 0: Normal Pull it down to VSS, via high resistance External pin multiplex mode 5 External pin multiplex mode 1 USB selection 0: Host, 1: Function Test mode selection pin Pull it down to VSS, via high resistance Test mode selection pin Pull it down to VSS, via high resistance MPX_MODE_5[1:0] MPX_MODE_1[1:0] USB_MODE TESTMODE[2:0] VPD I I I I I - D D D D D - - 7.2.20. ETM related pin I/O O Polarity Analog /Digital D Type Status of pin after reset L Description Exported clock for TRACEDATA[3:0] and TRACECTL They are valid on bath edges of TRACECLK for max. integrity. Trace control signal used by the trace tool such as RealView supplied by ARM Limited. Trace data used by the trace tool such as RealView supplied by ARM Limited. Pin name TRACECLK TRACECTL O - D - H TRACEDATA[3:0] O - D - LHHH 7.2.21. Power supply related pin I/O I I I Polarity Analog /Digital D D D Type Status of pin after reset Description Ground External pin power supply Internal power supply Pin name VSS VDDE VDDI FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 24 MB86R01 DATA SHEET 7.2.22. MediaLB related pin I/O IO IO I Polarity P P Analog /Digital D D D Type PD PD CLK Status of pin after reset HiZ HiZ Description Data (optional) (*1) Control (optional) (*1) Clock (optional) (*1) Pin name MLB_DATA MLB_SIG MLB_CLK *1: MediaLB pin of this LSI uses 3.3[V] I/O; therefore, when connecting bus's voltage is not 3.3[V], level conversion at external side is needed. 7.2.23. Pin name GPIO_PD[23:0] GPIO related pin I/O IO Polarity Analog /Digital D Type PD (*1) Status of pin after reset HiZ Description General purpose I/O port (optional) *1: GPIO_PD[12:6] is not applicable. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 25 MB86R01 DATA SHEET 7.2.24. Unused pin Proceed following processes for unused pin. Pin No. 3 4 5 6 7 9 10 11 12 14 15 16 17 18 19 21 22 23 24 28 29 30 31 32 33 34 35 36 38 39 40 41 42 43 44 JEDEC C1 D1 E1 F1 G1 J1 K1 L1 M1 P1 R1 T1 U1 V1 W1 Pin name DOUTB1[2], MEM_XWR[2], DOUTB0[0] DOUTB1[6], MEM_ED[18], DOUTR0[0] DOUTG1[4], MEM_ED[22], GPIO_PD[8] DOUTR1[2], MEM_ED[26], GPIO_PD[12] DCLKIN1 DCLKO1 VIN0[5] VIN0[1] CCLK0 USB_AVSP USB_HSDP USB_HSDM USB_AVSF2 USB_CRYCK48 VIN1[6], RI1[6], GPIO_PD[4] Connect to VSS. Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. Connect to VSS. Pull down to VSS through 10kΩ resistance. Keep the pin open. Pull up to VDDE or pull down to VSS through high resistance. Process Pull up to VDDE or pull down to VSS through high resistance. AA1 CCLK1 AB1 AC1 VINFID1, I2S_SDO1 I2S_SCK2, BI1[4], SPI_SCK AD1 I2S_ECLK2, BI1[5], Reserved (input/output), GPIO_PD[0] AF3 IDE_XIOCS16, I2S_SDI1 Pull up to VDDE or pull down to VSS through high resistance. AF4 IDE_XDRESET, Reserved (output) Keep the pin open. AF5 AF6 AF7 AF8 AF9 IDE_DD[12], CAN_RX1 IDE_DD[8], GPIO_PD[20] IDE_DD[4], GPIO_PD[16] IDE_DD[0], Reserved (input/output) IDE_CSEL, Reserved (output) Pull up to VDDE or pull down to VSS through high resistance. Connect to VSS. Keep the pin open. Pull up to VDDE or pull down to VSS through high resistance. AF10 IDE_XDCS[1], Reserved (output) AF11 MPX_MODE_5[1] AF13 AD_AVD AF14 AD_AVS AF15 UART_SOUT0 AF16 UART_SIN0 AF17 UART_SIN1 AF18 SD_DAT[0] AF19 SD_WP FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 26 MB86R01 DATA SHEET Pin No. 45 46 47 48 49 52 53 54 55 57 58 60 61 63 64 66 67 69 70 72 73 74 78 79 80 81 82 83 85 88 92 94 95 96 97 99 101 102 103 104 105 JEDEC AF20 I2C_SCL1 AF21 I2C_SDA1 AF22 INT_A[0] AF23 MA[8] AF24 MA[12] AE26 MA[7] AD26 MA[3] AC26 MA[1] AB26 MBA[1] Y26 U26 T26 P26 N26 L26 K26 H26 G26 E26 D26 C26 A24 A23 A22 A21 A20 A19 A17 A14 A10 A8 A7 A6 A5 A3 B2 C2 D2 E2 F2 MDQSN[0] MDQSN[1] MDQSP[1] MCKN MCKP MDQSN[2] MDQSP[2] MDQSN[3] MDQSP[3] MEM_ED[3] MEM_ED[7] MEM_ED[11] MEM_EA[1] MEM_EA[4] MEM_EA[8] MEM_EA[12] MEM_EA[16] MEM_EA[20] MEM_XRD TDO Pin name Process Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. Pull down to VSS through high resistance. W26 MDQSP[0] Keep the pin open. Pull down to VSS through high resistance. Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. TRACEDATA[3], UART_SIN4 DOUTB0[4] DOUTG0[2] DOUTG0[6] DCLKIN0 DCLKO0 DE0 GV0 DOUTB1[5], MEM_ED[17], DOUTG0[1] DOUTG1[3], MEM_ED[21], GPIO_PD[7] DOUTG1[7], MEM_ED[25], GPIO_PD[11] Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. Pull up to VDDE or pull down to VSS through high resistance. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 27 MB86R01 DATA SHEET Pin No. 106 108 109 110 112 113 114 115 116 117 118 119 121 122 123 125 126 127 128 129 130 131 132 133 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 JEDEC G2 J2 K2 L2 N2 P2 R2 T2 U2 V2 W2 Y2 AB2 AC2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 Pin name DOUTR1[5], MEM_ED[29], I2S_WS0 GV1, DREQ[7] VIN0[6] VIN0[2] VINFID0, GI1[3], MLB_CLK USB_AVDP USB_FSDP USB_FSDM USB_AVSF2 USB_MODE VIN1[5], RI1[5], CAN_TX0 VIN1[2], RI1[2], CAN_RX1 I2S_SDO2, BI1[6], SPI_DO, GPIO_PD[1] PWM_O1, BI1[7], GPIO_PD[2] IDE_XDASP, I2S_WS1 IDE_XDDMACK, Reserved (output) IDE_DD[13], CAN_TX1 IDE_DD[9], GPIO_PD[21] IDE_DD[5], GPIO_PD[17] IDE_DD[1], GPIO_PD[13] IDE_DA[0], PWM_O0 Connect to VSS. Connect to VDDI. Process Pull up to VDDE or pull down to VSS through high resistance. Pull down to VSS through 10kΩ resistance. Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. AD2 PWM_O0, GI1[2], GPIO_PD[3] AE10 IDE_XDCS[0], Reserved (output) AE11 MPX_MODE_5[0] AE13 AD_VRH0 AE14 AD_VRH1 AE15 UART_XRTS0 AE16 UART_XCTS0 AE17 UART_SOUT1 AE18 SD_DAT[1] AE19 SD_XMCD AE20 I2C_SCL0 AE21 INT_A[3] AE22 MCKE_START AE23 MA[13] AE24 MA[4] AE25 MA[11] AD25 MA[5] AC25 MA[10] AB25 MBA[0] Pull down to VSS through high resistance. Keep the pin open. Keep the pin open. Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. Pull up to VDDE or pull down to VSS through high resistance. Pull up to VDDE or pull down to VSS through high resistance. Connect to VSS. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 28 MB86R01 DATA SHEET Pin No. 151 152 153 154 155 156 157 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 183 184 185 187 188 189 190 192 193 194 195 196 197 198 199 JEDEC AA25 MCKE Y25 V25 U25 T25 R25 L25 K25 J25 H25 G25 F25 E25 D25 C25 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B12 B11 B10 B8 B7 B6 B5 B3 C3 D3 E3 F3 G3 H3 J3 MDQ[2] VREF0 MDQ[13] MDQ[8] MDQ[15] MDQ[16] VREF1 MDQ[29] MDQ[24] MDQ[31] MEM_ED[0] MEM_ED[4] MEM_ED[8] MEM_ED[12] MEM_ED[14] MEM_ED[15] MEM_EA[3] MEM_EA[7] MEM_EA[11] MEM_EA[15] MEM_EA[19] MEM_EA[23] MEM_XWR[1] MEM_XCS[4] TMS W25 MDQ[0] Pin name Keep the pin open. Process Pull down to VSS through high resistance. Connect to DDRVDE/2[V]Reference voltage. Pull down to VSS through high resistance. M25 MDQ[21] Connect to DDRVDE/2[V]Reference voltage. Pull down to VSS through high resistance. Pull up to VDDE or pull down to VSS through high resistance. TRACEDATA[0], UART_SOUT5, PWM_O0 TRACECTL, UART_SOUT3 DOUTB0[5] DOUTG0[3] DOUTG0[7] DOUTR0[4] HSYNC0 VSYNC0 DOUTB1[4], MEM_ED[16], DOUTG0[0] DOUTG1[2], MEM_ED[20], GPIO_PD[6] DOUTG1[6], MEM_ED[24], GPIO_PD[10] DOUTR1[4], MEM_ED[28], I2S_SDI0 DOUTR1[7], MEM_ED[31], I2S_ECLK0 VSYNC1, XDACK[6] Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 29 MB86R01 DATA SHEET Pin No. 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 224 225 227 228 229 230 231 232 234 235 236 237 238 239 240 241 242 243 JEDEC K3 L3 M3 N3 P3 R3 T3 U3 V3 W3 Y3 AB3 AC3 VIN0[7] VIN0[3] Pin name Process Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. Connect to VSS. Connect to VDDE. Connect to VSS. Connect to VDDI. Keep the pin open. VINVSYNC0, GI1[5], MLB_DATA VINHSYNC0, GI1[4], MLB_SIG USB_AVSF1 USB_AVDF1 USB_AVSF2 USB_AVDF2 VIN1[7], RI1[7], GPIO_PD[5] VIN1[4], RI1[4], CAN_RX0 VIN1[1], GI1[7], I2S_SCK1 I2S_SDI2, BI1[2], SPI_DI IDE_DIORDY, Reserved (input) AA3 VINVSYNC1, I2S_ECLK1 Pull up to VDDE or pull down to VSS through high resistance. AD3 IDE_XCBLID, I2S_SCK1 AD4 IDE_DDMARQ, I2S_ECLK1 AD5 IDE_DD[14], CAN_RX0 AD6 IDE_DD[10], GPIO_PD[22] AD7 IDE_DD[6], GPIO_PD[18] AD8 IDE_DD[2], GPIO_PD[14] AD9 IDE_DA[1], PWM_O1 AD10 IDE_XDIOR, Reserved (output) AD11 MPX_MODE_1[1] AD13 AD_VIN0 AD14 AD_VIN1 AD16 UART_SOUT2 AD17 SD_CMD AD18 SD_DAT[2] AD19 USB_PRTPWR AD20 I2C_SDA0 AD21 INT_A[1] AD23 MA[9] AD24 MA[6] AC24 MA[2] AB24 MWE AA24 MRAS Y24 V24 U24 T24 MDQ[5] MDQ[7] MDQ[10] MDQ[9] Keep the pin open. Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. Pull up to VDDE or pull down to VSS through high resistance. Connect to VSS. Keep the pin open. Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. Pull down to VSS through high resistance. W24 MDQ[1] FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 30 MB86R01 DATA SHEET Pin No. 244 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 267 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 287 288 289 292 JEDEC R24 L24 K24 J24 H24 G24 F24 E24 D24 C24 C23 C22 C21 C20 C19 C18 C17 C16 C13 C11 C10 C9 C8 C7 C6 C5 C4 D4 E4 F4 G4 H4 J4 K4 L4 M4 P4 R4 T4 W4 MDM[1] MDQ[17] MDQ[23] MDQ[26] MDQ[28] MDM[3] MEM_ED[1] MEM_ED[5] MEM_ED[9] MEM_ED[13] MEM_EA[2] MEM_EA[6] MEM_EA[10] MEM_EA[14] MEM_EA[18] MEM_EA[22] MEM_XWR[0] MEM_XCS[2] TCK Pin name Process Pull down to VSS through high resistance. M24 MDQ[18] Pull up to VDDE or pull down to VSS through high resistance. TRACEDATA[1], UART_SIN5, PWM_O1 TRACECLK, UART_SIN3 DOUTB0[2] DOUTB0[6] DOUTG0[4] DOUTR0[2] DOUTR0[5] DOUTR0[7] DOUTB1[3], MEM_XWR[3], DOUTB0[1] DOUTB1[7], MEM_ED[19], DOUTR0[1] DOUTG1[5], MEM_ED[23], GPIO_PD[9] DOUTR1[3], MEM_ED[27], I2S_SDO0 DOUTR1[6], MEM_ED[30], I2S_SCK0 HSYNC1, DREQ[6] DE1, XDACK[7] VIN0[4] VIN0[0] USB_AVSB USB_AVSF2 USB_AVSF2 VIN1[3], RI1[3], CAN_TX1 Keep the pin open. Keep the pin open. Pull up to VDDE or pull down to VSS through high resistance. Connect to VSS. Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 31 MB86R01 DATA SHEET Pin No. 293 294 295 296 297 298 299 300 301 302 303 305 306 308 309 310 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 JEDEC Y4 Pin name VIN1[0], GI1[6], I2S_WS1 Keep the pin open. Process AA4 VINHSYNC1, I2S_SDI1 AB4 AC5 AC6 AC7 AC8 AC9 I2S_WS2, BI1[3], SPI_SS IDE_DD[15], CAN_TX0 IDE_DD[11], GPIO_PD[23] IDE_DD[7], GPIO_PD[19] IDE_DD[3], GPIO_PD[15] IDE_DA[2], Reserved (output) Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. AC4 IDE_DINTRQ, I2S_SDO1 AC10 IDE_XDIOW, Reserved (output) AC11 MPX_MODE_1[0] AC13 AD_VR0 AC14 AD_VR1 AC16 UART_SIN2 AC17 SD_CLK AC18 SD_DAT[3] AC20 INT_A[2] AC21 DDRTYPE AC22 ODTCONT AC23 MA[0] AB23 MCS AA23 MCAS Y23 V23 U23 T23 R23 P23 N23 M23 L23 K23 J23 H23 G23 F23 E23 D23 D22 MDQ[3] MDM[0] MDQ[11] MDQ[12] MDQ[14] OCD ODT MDQ[19] MDQ[20] MDM[2] MDQ[27] MDQ[25] MDQ[30] MEM_ED[2] MEM_ED[6] MEM_ED[10] MEM_EA[5] Pull up to VDDE or pull down to VSS through high resistance. Pull down to VSS through high resistance. Keep the pin open. Pull down to VSS through high resistance. W23 MDQ[4] Pull up to VDDE or pull down to VSS through high resistance. Keep the pin open. Pull up to VDDE or pull down to VSS through high resistance. Pull up to VDDE through high resistance. Keep the pin open. Pull up to VDDE or pull down to VSS through high resistance. Connect to VSS. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 32 MB86R01 DATA SHEET Pin No. 336 337 338 339 340 341 342 344 346 347 348 349 350 351 352 362 363 364 378 379 391 398 JEDEC D21 D20 D19 D18 D17 D16 D15 D13 D11 D10 D9 D8 D7 D6 D5 P5 R5 T5 MEM_EA[9] MEM_EA[13] MEM_EA[17] MEM_EA[21] MEM_EA[24] MEM_XCS[0] MEM_RDY TDI Pin name Process Pull up to VDDE or pull down to VSS through high reistance. TRACEDATA[2], UART_SOUT4 RTCK DOUTB0[3] DOUTB0[7] DOUTG0[5] DOUTR0[3] DOUTR0[6] USB_AVDB USB_EXT12K USB_AVSF2 Connect to VDDE. Pull down to VSS through 10kΩ resistance. Connect to VSS. Keep the pin open. AB13 AD_VRL0 AB14 AD_VRL1 V22 L22 MDQ[6] MDQ[22] Pull down to VSS through high resistance. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 33 MB86R01 DATA SHEET 7.2.25. Unused pin with pin multiplex function in the duplex case PWM, I2S1, and CAN pins may be duplicated and allocated to external pin depending on pin multiplex function's group combination. In this case, follow the procedure below. Pin No. 122 123 220 131 269 184 118 292 209 119 297 127 216 30 210 293 211 294 22 28 125 215 214 296 JEDEC AC2 Pin multiplex group: pin name Pin multiplex group #2:PWM_O1 Keep the pin open. Process AD2 Pin multiplex group #2:PWM_O0 AD9 Pin multiplex group #4:PWM_O1 AE9 C11 B11 W2 W4 W3 Y2 AC5 AE5 AF5 Y3 Y4 Pin multiplex group #4:PWM_O0 Pin multiplex group #5:PWM_O1 Pin multiplex group #5:PWM_O0 Pin multiplex group #2:CAN_TX0 Pin multiplex group #2:CAN_TX1 Pin multiplex group #2:CAN_RX0 Pin multiplex group #2:CAN_RX1 Pin multiplex group #4:CAN_TX0 Pin multiplex group #4:CAN_TX1 Pin multiplex group #4:CAN_RX1 Pin multiplex group #2:I2S_SCK1 Pin multiplex group #2:I2S_WS1 Pull down to VSS through high resistance. Keep the pin open. Pull down to VSS through high resistance. Keep the pin open. Pull down to VSS through high resistance. Keep the pin open. Keep the pin open. Pull down to VSS through high resistance. AD5 Pin multiplex group #4:CAN_RX0 AA3 Pin multiplex group #2:I2S_ECLK1 AA4 Pin multiplex group #2:I2S_SDI1 AB1 AF3 AE3 Pin multiplex group #2:I2S_SDO1 Pin multiplex group #4:I2S_SDI1 Pin multiplex group #4:I2S_WS1 AD4 Pin multiplex group #4:I2S_ECLK1 AD3 Pin multiplex group #4:I2S_SCK1 AC4 Pin multiplex group #4:I2S_SDO1 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 34 MB86R01 DATA SHEET 8. 8.1. Electrical Characteristics Maximum Ratings Table 8-1, Table 8-2, and Table 8-3 show the maximum ratings. Table 8-1 Maximum Ratings Symbol VDDI, PLLVDD VDDE DDRVDE VI -0.5 to 1.8 (*1) -0.5 to 4.0 (*2) -0.5 to 2.5 (*3) -0.5 to VDDI + 0.5 (< 1.8V) -0.5 to VDDE + 0.5 (< 4.0V) -0.5 to DDRVDE + 0.5 (< 2.5V) -0.5 to VDDI + 0.5 (< 1.8V) -0.5 to VDDE + 0.5 (< 4.0V) -0.5 to DDRVDE + 0.5 (< 2.5V) -55 to 125 -40 to 125 1.5 1.2V: 690.1 (*4) 1.8V: 508 (*4) 3.3V: 125.3 (*4) Rating Unit V Parameter Supply voltage Input voltage V Output voltage VO V °C °C W Storage temperature Junction temperature Power consumption Supply current TST TJ PD ID mA *1: Power supply for internal part or PLL *2: Power supply for I/O part *3: Power supply for SSTL_18 I/O part *4: Current specification necessary for each voltage power supply Note: • Applying stress exceeding the maximum ratings (voltage, current, temperature, etc.) may cause damage to semiconductor devices. Never exceed the ratings above. • Since thermal destruction of elements might occur, do not connect IC output or I/O pin directly, or connect them to VDD or VSS directly, except the pin designed output timing to prevent such incident. • Provide ESD protection, such as grounding when handling the product; otherwise externally-charged electric charge flows into the IC and discharges, which may cause circuit destruction. • Applying voltage higher than VDD or lower than VSS to I/O pins of CMOS IC, or applying voltage higher than the ratings between VDD and VSS may cause latch up. The latch up increases supply current, resulting in thermal destruction of elements. When handling the product, never exceed the maximum ratings. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 35 MB86R01 DATA SHEET Table 8-2 ADC Maximum Ratings Symbol AD_AVD0 AD_VRH0 AD_VRH1 AD_VRL0 AD_VRL1 AD_VIN0 AD_VIN1 AD_VR0 AD_VR1 TJ -0.5 to 4.0 -0.5 to VDDE + 0.5 (< 4.0V) V Rating Unit V Parameter Supply voltage Input voltage Output voltage Junction temperature -0.5 to VDDE + 0.5 (< 4.0V) -40 to 125 V °C The maximum ratings of USB PHY are shown in Table 8-3. Table 8-3 USB2.0 Maximum Ratings Symbol USB_AVDF1 USB_AVDB USB_AVDF2 USB_AVDP Junction temperature Supply current TJ USB_AVDF1 USB_AVDB USB_AVDF2 USB_AVDP VSS--0.5 to 4.0 VSS--0.5 to 1.8 -40 to 125 Total 37.5 19.2 13.0 Rating Unit V V °C mA mA mA Parameter Supply voltage The maximum ratings are the limits that must not be exceeded. As long as USB PHY is used within the range predetermined in the maximum ratings, it never suffers permanent damage. However, this does not assure normal logic operation. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 36 MB86R01 DATA SHEET 8.2. Recommended Operating Conditions Table 8-4 3.3V Standard CMOS I/O Recommended Operating Conditions Parameter Power supply voltage Input voltage (High level) Input voltage (Low level) 3.3V CMOS 3.3V CMOS Symbol VDDE VDDI, PLLVDD VIH VIL TA TJ Rating Min. 3.0 1.1 2.0 -0.3 -40 -40 Typ. 3.3 1.2 – – – – Max. 3.6 1.3 VDDE + 0.3 0.8 85 125 Unit V V V °C °C Operating ambient temperature Junction temperature Table 8-5 SSTL_18 Recommended Operating Conditions Parameter Power supply voltage Junction temperature Symbol VDE (DDRVDE) VDDI TJ Min. 1.7 1.10 -40 Typ. 1.8 1.20 – Max. 1.9 1.30 125 Unit V V °C The recommended operating conditions for the standard SSTL_18 (excerpted from JESD8-15a). Table 8-6 USB2.0 Recommended Operating Conditions Parameter Symbol Value Min. 3.0 1.1 1.1 -40 Typ. 3.3 1.2 1.2 – Max. 3.6 1.3 1.3 125 Unit V V V °C USB_AVDF1 Supply voltage USB_AVDB USB_AVDF2 USB_AVDP TJ Junction temperature Clock to be input to USB_CRYCLK48 should meet followings: • 48MHz±100ppm clock • 100ps or less jitter Note: The recommended operating conditions are primarily intended to assure the normal operation of semiconductor device. The values of electrical characteristics are guaranteed under the requirements above, so use the product accordingly. Using the product without observing the conditions may affect the product's reliability. Performance of this product is not guaranteed using under the unspecified conditions and unspecified combination of logic. Be sure to contact Fujitsu when using the product under such conditions. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 37 MB86R01 DATA SHEET 8.3. 8.3.1. Precautions at Power On Recommended Power On/Off Sequence Follow the power on/off sequence as shown below: : VDDI (internal and PLLVDD) → DDRVDE (external) → VDDE (external) → Signal : Signal → VDDE (external) → DDRVDE (external) → VDDI (internal and PLLVDD) VDDI VDDE DDRVDE Figure 8-1 Recommended Power On/Off Sequence (1) There is no limitation on the sequence of power on/off of VDDI, VDDE, and DDRVDE if the following condition is met. (Figure 8-2) • Do not apply VDDE and DDRVDE (external) continuously more than 1 second when VDDI (internal) is off. VDDI VDDE DDRVDE 1 sec. or less 1 sec. or less Figure 8-2 Recommended Power On/Off Sequence (2) Perform power on/off for VREF according to the DDR2-SDRAM regulation. Perform power on/off so that power for PLLVDD (PLL) does not exceed VDDI. Turn on all power. Turning on only a part of them is prohibited. CMOS IC becomes unstable immediately after power-on so that proceed reset immediately. Set the reset pins (XTRST and XRST) to Low when power-on. Input clock to CLK pin immediately after power-on. It requires at least 100 clocks (input clock to CLK pin) for the reset signal "L" applied to the XRST pin to be transmitted to all internal circuits. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 38 MB86R01 DATA SHEET 8.3.2. VDDI (internal) Power On Reset VDDE (external) DDRVDE (DRAM) Input clock immediately after power-on CLK N ote: Clock is just an image, not the actual one. XRST Input "L" when power-on 2 μs or more P LL Lockup Time XSRST output "L" when power-on For inputting the external signal to XSRST, input XSRST after changing XRST from "L" to "H". XTRST input is required only when MB86R01 is in DFT mode(JTAGSEL=”H”). Input "L" when power-on XTRST Figure 8-3 Power On Sequence Input XRST pin to Low when power-on. Keep XRST pin High after setting to Low level for 2μs or more. Access the other registers or memory controller after PLL Lockup Time. When MB86R01 is in DFT mode, XTRST should be input as well as XRST. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 39 MB86R01 DATA SHEET 8.4. 8.4.1. DC Characteristics 3.3V Standard CMOS I/O Table 8-7 shows 3.3V standard CMOS I/O DC characteristics. Table 8-7 Standard CMOS I/O DC Characteristics Measurement condition: VDDE = 3.3 ±0.3V, VSS = 0V, TJ = -40 to 125°C Parameter H level input voltage L level input voltage H level output voltage L level output voltage H level output V-I characteristic L level output V-I characteristic Input leakage current Symbol VIH VIL VOH VOL – IOH = -100μA IOL = 100μA Driving capability 1 IOH = 4mA Driving capability 2 IOH = 6mA Driving capability 3 IOH = 8mA Driving capability 1 IOL = 4mA – Driving capability 2 IOL = 6mA Driving capability 3 IOL = 8mA IL – – ±4 μA See Figure 8-4, Figure 8-5, and Figure 8-6 characteristics – – Condition Rating Min. 2.0 -0.3 VDDE - 0.2 0 Typ. – – – – Max. VDDE + 0.3 0.8 VDDE 0.2 Unit V V V V Driving capabilities 1 to 3 in the table above indicate the following external pins: Driving capability 1: TDO, MEM_EA[24:1], MEM_ED[15:0], MEM_RDY, MEM_XCS0, MEM_XCS2, MEM_XCS4, MEM_XRD, MEM_XWR0, MEM_XWR1 Driving capability 2: VINHSYNC0, VINVSYNC0, I2S_ECLK2, I2S_SCK2, I2S_SDO2,I2S_WS2, IDE_DD[15:0], IDE_DINTRQ, IDE_XCBLID, IDE_XDASP, PWM_O0, PWM_O1, VIN10-7, VINFID1, DOUTB1[7:2], DOUTG1[7:2], DOUTR1[7:2], GV1, HSYNC0, HSYNC1, SD_CMD, SD_DAT[3:0], TRACECLK, TRACEDATA[3:0], VIN0[7:0], VSYNC0, VSYNC1, XSRST, DE0, DE1, DOUTB0[7:2], DOUTG0[7:2], DOUTR0[7:2], GV0, IDE_CSEL, IDE_DA[2:0], IDE_XDCS[1:0], IDE_XDDMACK, IDE_XDIOR, IDE_XDIOW, IDE_XDRESET, RTCK, SD_CLK, TRACECTL, UART_SOUT[2:0], UART_XRTS0, USB_PRTPWR Driving capability 3: DCLKO[1:0] FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 40 MB86R01 DATA SHEET 8.4.1.1. 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 1) VDDE = 3.0 V VDDE = 3.3 V VDDE = 3.6 V Conditions MIN: Process = Slow TJ = 125°C TYP: Process = Typical TJ = 25°C MAX: Process = Fast TJ = -40°C Figure 8-4 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 1) FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 41 MB86R01 DATA SHEET 8.4.1.2. 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 2) VDDE = 3.0 V VDDE = 3.3 V VDDE = 3.6 V Conditions MIN: Process = Slow TJ = 125°C TYP: Process = Typical TJ = 25°C MAX: Process = Fast TJ = -40°C Figure 8-5 3.3V Standard CMOS I/O V-I Characteristic (Driving Capability 2) FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 42 MB86R01 DATA SHEET 8.4.1.3. 3.3V Standard CMOS I/O V-I Characteristics (Driving Capability 3) VDDE = 3.0 V VDDE = 3.3 V VDDE = 3.6 V Conditions MIN: Process = Slow TJ = 125°C TYP: Process = Typical TJ = 25°C MAX: Process = Fast TJ = -40°C Figure 8-6 3.3 V Standard CMOS I/O V-I Characteristic (Driving Capability 3) FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 43 MB86R01 DATA SHEET 8.4.2. DDR2SDRAM IF I/O (SSTL_18) SSTL_18 DC characteristics (excerpted from JESD8-15a). Table 8-8 Symbol VIH (DC) VIL (DC) SSTL18 Input DC Logic Levels (Single Ended) Parameter DC input logic High DC input logic Low Min. VREF + 125 -300 Max. VDDQ + 300 VREF - 125 Unit mV mV Table 8-9 Symbol VIH (AC) VIL (AC) SSTL18 Input AC Logic Levels (Single Ended) Parameter AC input logic High AC input logic Low Min. VREF + 250 – Max. – VREF - 250 Unit mV mV Table 8-10 Symbol VREF SSTL18 Input AC Test Conditions (Single Ended) Condition Input reference voltage Value 0.5 × VDDQ 1.0 1.0 Unit V V V/ns VSWING (max.) Input single maximum peak to peak swing SLEW Input single minimum slew rate Table 8-11 Symbol VIN (DC) VID (DC) SSTL18 Input DC Logic Levels (Differential Ended) Parameter DC input signal voltage DC differential input voltage Min. -300 250 Max. VDDQ + 300 VDDQ + 600 Unit mV mV Table 8-12 Symbol VID (AC) VIX (AC) SSTL18 Input AC Logic Levels (Differential Ended) Parameter AC differential input voltage AC differential cross point voltage Min. 500 0.5 × VDDQ - 175 Max. VDDQ + 600 0.5 × VDDQ + 175 Unit mV mV Table 8-13 Symbol Vr VSWING SLEW SSTL18 Input AC Test Conditions (Differential Ended) Parameter Input timing measurement reference level Input signal peak to peak swing voltage Input signal slew rate Min. Max. VIX (cross point) 1.0 – Unit V V V/ns – 1.0 Table 8-14 SSTL18 Output DC Current Drive Symbol IOH (DC) IOL (DC) Parameter Output minimum source DC current Output minimum sink DC current Min. -11.4 (*3) 11.4 (*3) Max. – – Unit mA mA Notes (*1) (*2) *1: VDDQ = 1.7V, VOUT = 1420mV *2: VDDQ = 1.7V, VOUT = 280mV *3: The value is different from JESD8-15a. (JESD8-15a: ±13.4mA) FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 44 MB86R01 DATA SHEET Table 8-15 Symbol VOX SSTL18 Differential AC parameters Parameter AC differential cross point voltage Min. 0.5 × VDDQ - 125 Max. 0.5 × VDDQ + 125 Unit mV Note: External pin for DDR2SDRAM IO buffer is as follows. MDQSP[3:0], MDQSN[3:0], MDM[3:0], MDQ[31:0], MCKP, MCKN, MA[13:0], MBA[1:0], MCAS, MCKE, MCS, MRAS, MWE, ODTCONT, OCD, ODT, VREF0, VREF1 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 45 MB86R01 DATA SHEET 8.4.3. ADC Parameter Symbol AD_AVD0 AD_VRH0 AD_VRH1 AD_VRL0 AD_VRL1 AD_VR0 (*2) AD_VR1 (*2) AD_VIN0 AD_VIN1 AD_VIN0 AD_VIN1 Value Min. 2.70 AD_AVD0*0.75 VSS (*1) 0.05 AD_VRL0 AD_VRL1 0 Typ. 3.00 – – – – – Max. 3.60 AD_AVD0 AD_AVD0*0.25 – AD_VRH0 AD_VRH1 500 Unit V V V μF V kHz Table 8-16 Recommended Operating Conditions Power supply voltage Reference voltage (H) Reference voltage (L) Decoupling capacitor Analog input voltage Analog input frequency Note: *1: VSS = AD_AVS1 (analogue GND) *2: In the case that VR is decoupled with AVS by decoupling capacitor, A/D outputs incorrect result at immediately after power-on or at the resumption from power down mode. Because charge current for decoupling capacitors is supplied through the reference resistance, it takes about 2ms to get correct result (it is the case decoupling capacitor is 0.1µF.). Table 8-17 ADC Characteristics (VDD = 1.2V, AVD = 3.0V, FS = 100KS/s, FC = 1.4MHz, FVIN = 1 kHz, TA = 25°C (*1)) Symbol Value Min. – -1 – -3 7.3 Typ. -20 Typ. -20 -2.0 -1.5 Typ. 0.8 – AD_AVD0/2 – 9 AD_VRL0+1LSB AD_VRL1+1LSB AD_VRH0-1LSB AD_VRH1-1LSB – – Max. 1.2 50 – 3 10.7 Typ. +20 Typ. +20 +2.0 +1.5 Unit mA µA V % kΩ Parameter AD_AVD0 Supply current (included reference current) Reference voltage (M) Reference resistance AD_VR0 AD_VR1 AD_VRH0 AD_VRH1 AD_VRL0 AD_VRL1 Zero transition voltage (*2) Full scale transition Voltage (*2) Integral non linearity (*3) Differential non linearity (*3) mV mV LSB LSB *1: VR is connected to AVS with decoupling capacitor (0.1µF). Unique voltage is supplied to VRH and VRL by voltage source. *2: VZT and VFST are dependent on chip layout and wiring resistance. *3: 1LSB = (VFST-VZT)/1022, INLn = ((1LSBxn + VZT) - Vn)/1LSB, DNLn = (Vn + 1 -Vn)/1LSB - 1 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 46 MB86R01 DATA SHEET 8.4.4. Table 8-18 I2C Bus Fast Mode I/O I2C I/O DC Characteristics Symbol VIL VIH Vhys VOL1 Standard Mode Min. -0.5 0.7 VDDE n/a 0 Max. 0.3 VDDE (*2) n/a 0.4 250 Fast Mode (*1) Min. -0.5 0.7 VDDE 0.05 VDDE 0 20 + 0.1Cb (*3) -10 – Max. 0.3 VDDE (*2) – 0.4 250 Unit V V V V Parameter & Condition "L" level input voltage "H" level input voltage Schmitt trigger hysteresis VDDE > 2[v] "L" level output voltage Sink current 3[mA] VDDE > 2[v] Output slew rate (Tfall) Bus capacitance 10[pF] ~ 400[pF] VIH (min.) to VIL (max.) tof – -10 – ns μA pF Data line leakage Ii Input voltage 0.1 ~ 0.9 VDDE (max.) I/O pin capacitance Ci 10 10 10 10 *1: The I2C Bus Fast Mode I/O buffer is downward compatible with standard mode. *2: 90nm Technology: Complies with the maximum ratings 4[V]. *3: Cb: Capacitance for 1 bus line (Unit: pF). *4: The I2C Bus Fast Mode I/O buffer itself has no function to prevent spike of 50ns pulse width (max.). Therefore, provide any input filter to prevent spike for both internal and external semiconductor device. Note: External pin for I2C IO buffer is as follows. I2C_SCL0, I2C_SDA0, I2C_SCL1, I2C_SDA1 FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 47 MB86R01 DATA SHEET 8.4.4.1. I2C IO V-1 Characteristic Figure Current (A) Voltage (V) Figure 8-7 I2C V-I Characteristic Figure FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 48 MB86R01 DATA SHEET 8.4.5. USB2.0 Parameter Symbol Value Min. 100 525 150 (the absolute value) VHSCM -50 Typ. – – – – – – – – – – Max. 200 625 Unit Table 8-19 Recommended Operating Conditions (High-speed) Input levels for high-speed: high-speed squelch detection threshold (differential signal amplitude) High-speed disconnect detection threshold (differential signal amplitude) High-speed differential input signaling levels (this spec is based on "Template 6") High-speed data signaling common mode voltage range (guideline for receiver) Output levels for high-speed: High-speed idle level High-speed data signaling high High-speed data signaling low Chirp J level (differential voltage) Chirp K level (differential voltage) Terminations in high-speed: Termination voltage in high-speed VHSTERM -10 10 mV VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK -10.0 360 -10.0 700 -900 10.0 440 10.0 1100 -500 mV mV mV mV mV VHSSQ VHSDSC mV mV mV – 500 mV Table 8-20 Recommended Operating Conditions (Full-speed/Low-speed) Parameter Input levels for full-speed/low-speed: High (driving) High (floating) Low Differential input sensitivity Differential common mode range Output levels for full-speed/low-speed: Low High (driven) SE1 Output signal crossover voltage Input capacitance for full-speed/low-speed: Downstream facing port (being shared with CIND upstream facing port at device mode, so the less (CINUB) value is selected as the maximum spec) Transceiver edge rate control capacitance Terminations in full-speed/low-speed: Bus pull-up resistor on upstream port (idle bus) RPUI (this is used only in the device mode (HOSTMODE = "0" setting).) Bus pull-up resistor on upstream port (upstream RPUA port receiving) (this is used only in the device mode (HOSTMODE = "0" setting).) Input impedance exclusive of pull-up/pull-down ZINP Termination voltage on upstream port pull-up VTERM 0.9 – 1.575 kΩ CEDGE – – – – 100 75 pF pF VOL VOH VOSE1 VCRS 0.0 2.8 0.8 1.3 – – – – 0.3 3.6 – 2.0 V V V V VIH VIHZ VIL VDI VCM 2.0 2.7 – 0.2 0.8 – – – – – – 3.6 0.8 – 2.5 V V V V V Symbol Value Min. Typ. Max. Unit 1.425 300 3.0 – – – 3.090 – 3.6 kΩ kΩ V FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 49 MB86R01 DATA SHEET 8.5. 8.5.1. AC CHARACTERISTIC Memory Controller Signal Timing Symbol Description Chip Select delay time Address delay time Data output delay time Data output HiZ time SRAM/NOR Flash data setup time SRAM/NOR Flash data hold time NOR Flash page Read data setup time NOR Flash page Read data hold time XRD delay time XWR delay time Value Min – – – – 12 0 13 0 – – Typ – – – – – – – – – – Max 10 11 11 12 – – – – 10 10 Unit ns ns ns ns ns ns ns ns ns ns In this chapter, the AC timing of external ports is described. Table 8-21 Memory Controller AC Timing Signal Name MEM_XCS0 MEM_XCS2 MEM_XCS4 MEM_EA[24:1] tcso tao tdo tdoz tdsr MEM_ED[31:0] tdhr tdsp tdhp MEM_XRD trdo MEM_XWR[3:0] twro Standard clock of output delay is internal clock. Standard clock of MEM_RDY is internal clock. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 50 MB86R01 DATA SHEET Figure 8-8 SRAM/NOR Flash Read Figure 8-9 SRAM/NOR Flash Write FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 51 MB86R01 DATA SHEET Figure 8-10 Low speed device Read Internal CLK MEM_XCS0 MEM_XCS2 MEM_XCS4 tcso tcso tao MEM_EA[24:1] tao Min 2Cycle(Internal CLK) + twro MEM_RDY Min 0[ns] twro MEM_XWR[1:0] twro tdo MEM_ED[31:0] tdo X tdo Figure 8-11 Low speed device Write FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 52 MB86R01 DATA SHEET Figure 8-12 NOR Flash Page Read FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 53 MB86R01 DATA SHEET 8.5.2. DDR2SDRAM IF This is able to connect with DDR2 SDRAM which is in conformance with DDR2-400 in the JEDEC (JESD79-2C.) Timing regulation is described below, and output load condition is according to the PCB design guideline. Table 8-22 Write Spec (1 and 2): CK-CMD/ADD and CK-DQS Item Symbol Spec formula Criteria value (*1) Min. 2172 2455 -1083 Typ. – – – Max. – – 772 Unit ps ps Ps CMD/ADD setup valid-data from CK↑ tVD_setup_CMD (tCK/2) - 828 CMD/ADD hold valid-data from CK↑ tVD_hold_CMD Skew between DQS↑ vs. CK↑ tSkew_DQS_CK *1: Spec for tck = 6ns (333Mbps) is indicated (tCK/2) - 545 Not tCK dependent Table 8-23 Write Spec (3): DQ-DQS Item DQ/DM setup valid-data from DQS DQ/DM hold valid-data from DQS Symbol tVD_setup_DQ tVD_hold_DQ Spec formula （tCK/4) - 884 （tCK/4) - 776 Criteria value (*1) Min. 616 724 Typ. – – Max. – – Unit ps ps *1: Spec for tck = 6ns (333Mbps) is indicated Table 8-24 Read Spec (1): DQ-DQS Item tSETUP DQ from DQS tHOLD DQ from DQS Symbol tSETUP_DQ tHOLD_DQ Spec formula - (0.1875*tCK – 208 ) 0.1875*tCK + 503 Criteria value (*1) Min. -917 1628 Typ. – – Max. – – Unit ps Ps *1: Spec for tck = 6ns (333Mbps) is indicated Table 8-25 Read Spec (2): DQ-R.T.T (RoundTrip Time) Item DQS RoundTripTime @CL = 3 (CK_out DRAM DQS_in) Symbol tRTT_DQS Spec formula 1112 -595 Criteria value (*1) Min. -355 Typ. – Max. +1426 Unit ps *1: Spec for tck = 6ns (333Mpbs) is indicated *2: Spec shows total delay value including tDQSCK delay of DRAM FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 54 MB86R01 DATA SHEET 8.5.2.1. DDR2SDRAM IF Timing Diagram MB86R01 DDR2 SDRAM (DDR2-400) CK DDR2C CMD/AD DQ DQS * External load condition: PCB design guideline Timing regulation point Figure 8-13 Timing Regulation Point FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 55 MB86R01 DATA SHEET tCK = 6ns@166MHz CK_out /CK_out tVD_setup_CMD tVD_hold_CMD CMD/ADD_out tSkew_DQS_CK tSkew_DQS_CK Valid Data DQS_out Figure 8-14 Write Spec (1 and 2): CK-CMD/ADD and CK-DQS tCK = 6ns@166MHz DQS_out tVD_setup_DQ tVD_hold_DQ DQ_out DM_out Valid Data0 Valid Data1 Valid Data2 Valid Data3 Figure 8-15 Write Spec (3): DQ-DQS FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 56 MB86R01 DATA SHEET tCK = 6ns@166MHz DQS_in tHOLD_DQ tSETUP_DQ tHOLD_DQ tSETUP_DQ DQ_in Figure 8-16 Read Spec (1): DQ-DQS tCK = 6ns@166MHz C K_ Ou CL = 3 or 3 DQS_in@delay Min tRTT_DQS@Min tRTT_DQS@Max DQS_in@delay Max Figure 8-17 Read Spec (2): DQS-R.T.T (RoundTrip Time) FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 57 MB86R01 DATA SHEET 8.5.3. GPIO Signal Timing Signal Symbol Description Data output delay time Input data-width Value Min. – A Typ. – – Max. 13 – Unit ns Ns Table 8-26 AC Timing GPIO_PD[23:0] tdo tdw Internal clock is the standard of output delay. A indicates APB bus clock cycle, and it is different from the output delay standard clock. Internal CLK tdo Output GPIO_PD[23:0] Input Figure 8-18 GPIO Timings tdw FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 58 MB86R01 DATA SHEET 8.5.4. 8.5.4.1. PWM Signal Timing Output Signal Value Min. 2.0 2.0 Typ. – – Max. 14.0 14.0 Table 8-27 AC Timing of Ide Data Input Signal Signal PWM_O0 PWM_O1 Symbol T0 T1 Description Output delay of PWM_O0 based on APBBusClock Output delay of PWM_O1 based on APBBusClock Unit ns ns APB-BusClock T0 PWM_O0 T1 PWM_O1 Figure 8-19 PWM Output Timing FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 59 MB86R01 DATA SHEET 8.5.5. 8.5.5.1. Table 8-28 Signal GDC Display Signal Timing Clock AC timing of Video Interface Clock Signal Symbol Fdclki0 Description DCLKI frequency DCLKI H width DCLKI L width DCLKI frequency DCLKI H width DCLKI L width DCLK frequency (*1) DCLK frequency (*1) DCLKO frequency DCLKO frequency Value Min. – 5 5 – 5 5 – – – – Typ. – – – – – – – – – – Max. 80 – – 80 – – 80 80 80 80 Unit MHz ns ns MHz ns ns MHz MHz MHz MHz DCLKI0 Thdclki0 Tldclki0 Fdclki1 DCLKI1 Thdclki1 Tldclki1 DCLK (internal) Tldclk0 DCLK (internal) Tldclk1 DCLKO0 DCLKO1 Fdclko Fdclko *1: Internal display clock of PLL synchronization mode is generated by division of internal PLL in the display clock prescaler. *2: DCLKI or internal display clock of PLL is output. 8.5.5.2. Input Signal 1) Applied the signal only in PLL synchronization mode (CKS = 0) (Reference clock = Clock output from internal PLL) Table 8-29 AC Timing of Video Interface Input Signal (1) Signal HSYNC0 (i) HSYNC1 (i) VSYNC0 (i) VSYNC1 (i) Symbol Description Value Min. 3.0 3.0 1 1 Typ. – – – – Max. – – – – Unit Clock Clock HSYNC HSYNC Twhsync0 HSYNC input pulse width Twvsync1 VSYNC input pulse width Twvsync Twvsync VSYNC input pulse width VSYNC input pulse width 2) Applied the signal only in DCLKI synchronization mode (CKS = 1) (Reference clock = DCLKI) Table 8-30 AC Timing of Video Interface Input Signal (2) Signal Symbol Description Value Min. 3.0 6.0 1.0 3.0 6.0 1.0 1 1 Typ. – – – – – – – – Max. – – – – – – – – Unit Clock ns ns Clock ns ns HSYNC HSYNC Twhsync0 HSYNC input pulse width HSYNC0 (i) Tshsync0 HSYNC Input setup time Thhsync0 HSYNC Input hold time Twhsync1 HSYNC input pulse width HSYNC1 (i) VSYNC0 (i) VSYNC1 (i) Tshsync1 HSYNC Input setup time Thhsync1 HSYNC Input hold time Twvsync0 VSYNC input pulse width Twvsync1 VSYNC input pulse width FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 60 MB86R01 DATA SHEET 8.5.5.3. Output Signal Value Min. 0 Typ. – Max. 5.5 Table 8-31 AC Timing of Video Interface Input Signal Signal DOUTR0[5:0], DOUTG0[5:0], DOUTB0[5:0] DOUTR1[5:0], DOUTG1[5:0], DOUTB1[5:0] HSYNC0 (o) HSYNC1 (o) VSYNC0 (o) VSYNC1 (o) CSYNC0 CSYNC1 GV0 GV1 Symbol Tdrgb0 Description RGB output delay time Unit ns Tdrgb1 RGB output delay time 0 0 0 0 0 0 0 0 0 – – – – – – – – – 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 ns ns ns ns ns ns ns ns Ns Tdhsync0 HSYNC output delay time Tdhsync1 HSYNC output delay time Tdvsync0 VSYNC output delay time Tdvsync1 VSYNC output delay time Tdcsync0 CSYNC output delay time Tdcsync1 CSYNC output delay time Tdgv0 Tdgv1 GV output delay time GV output delay time Note: If hold time is deficient, inverting DCLKO clock is recommended. DCLK In 1/Fdclkin Twhsyncn Thdclkin Tldclkin HSYNCn (i) Tshsyncn Thhsyncn Twvsyncn VSYNCn (i) Tsvsyncn Thvsyncn Figure 8-20 Display Input Signal Timing FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 61 MB86R01 DATA SHEET DCLKOn DCLKOn (inverted) DOUTRn[5:0] DOUTGn[5:0] DOUTBn[5:0] HSYNCn (o) Tdhsyncn 1/Fdclkon Tddrgbn VSYNCn (o) Tdvsyncn CSYNCn Tdcsyncn GVn Tdgvn Figure 8-21 Display Output Signal Timing There is no definition of AC characteristics about analog signal. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 62 MB86R01 DATA SHEET 8.5.6. 8.5.6.1. GDC Video Capture Signal Timing Clock Value Min. – 3 3 Typ. – – – Max. 80 – – Table 8-32 AC Timing of Video Capture Interface Clock Signal Signal CCLK0, CCLK1 Symbol Description Capture clock frequency Capture clock H width Capture clock L width Unit MHz ns ns fCCLK tHCCLK tLCCLK Note: It depends on the resolution of the video source. 8.5.6.2. Input Signal Value Min. 6 1 6 1 6 1 6 1 6 1 6 1 6 1 Typ. – – – – – – – – – – – – – – Max. – – – – – – – – – – – – – – Table 8-33 AC Timing of Video Capture Interface Input Signal Signal VIN0[7:0], VIN1[7:0] RI1[7:2] GI1[7:2] BI1[7:2] VINHSYNC0, VINHSYNC1 VINVSYNC0, VINVSYNC1 VINFID0, VINFID1 Symbol Description Input setup time Input hold Time Input setup time Input hold Time Input setup time Input hold Time Input setup time Input hold Time Input setup time Input hold Time Input setup time Input hold Time Input setup time Input hold Time Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns tSVI tHVI tSRI tHRI tSGI tHGI tSBI tHBI tSHSI tHHSI tSVSI tHVSI tSFI tHFI 1/fCCLK tHCCLK tLCCLK CCLK0, CCLK1 Figure 8-22 Video Capture Clock Input Signal Timing FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 63 MB86R01 DATA SHEET CCLK0/1 VIN0 /1 R I,GI,BI VINHSYNC0/1 VINVSYNC0/1 VINFID0/1 t SVI t SRI t SGI t SBI t SHSI t SVSI t SFI tHVI tHRI tHGI tHBI tHHSI tHVSI tHFI Figure 8-23 Video Capture Input Signal Timing FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 64 MB86R01 DATA SHEET 8.5.7. Table 8-34 Signal I2S Signal Timing Timing Requirements Symbol Description Operating frequency, I2S_SCKx (slave Mode) Pulse duration, I2S_SCKx High (slave Mode) Pulse duration, I2S_SCKx Low (slave Mode) Setup time, external I2S_WSx High before I2S_SCKx Low (slave mode) Hold time, external I2S_WSx High after I2S_SCKx Low (slave Mode) Setup time, I2S_SDIx valid before I2S_SCKx Low (master mode) Setup time, I2S_SDIx valid before I2S_SCKx Low (slave Mode) Hold time, I2S_SDIx valid after I2S_SCKx Low (master mode) Hold time, I2S_SDIx valid after I2S_SCKx Low (slave mode) Value Min. – 0.45*T 0.45*T 8 Typ. – – – – Max. 0.5*B 0.55*T 0.55*T – Unit MHz ns ns ns tscyc I2S_SCKx tshw tslw tsfi I2S_WSx thfi tsdi I2S_SDIx 4 8 8 4 4 – – – – – – – – – – ns ns ns ns ns thdi B indicates AHB bus clock frequency. T indicates I2S_SCKx cycle. Table 8-35 Signal Switching Characteristics Symbol Description Operating frequency, I2S_SCKx (master mode) Pulse duration, I2S_SCKx high (master mode) Pulse duration, I2S_SCKx low (master mode) Delay time, I2S_SCKx High to I2S_WSx transition (master mode) Delay time, I2S_SCKx High to I2S_SDOx valid except the first bit of transmit frame. (master mode) Delay time, I2S_SCKx high to I2S_SDOx valid except the first bit of transmit frame. (slave mode) Delay time, I2S_SCKx high to the first bit of a transmit frame when FSPH bit of I2Sx_CNTREG register is 1. (master mode) Value Min. – 0.45*T 0.45*T -12 -12 3 -14 Typ. – – – – – – – Max. 0.5*B 0.55*T 0.55*T 12 17 32 17 Unit MHz ns ns ns ns ns ns tmcyc I2S_SCKx tmhw tmlw I2S_WSx tdfs tddo I2S_SDOx tdfb1 B indicates AHB bus clock frequency. T indicates I2S_SCKx cycle. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 65 MB86R01 DATA SHEET tmcyc tmhw I2S_SCKx tmlw tdfs tdfs I2S_WSx (FSPH=0, FSLN=0) tdfs I2S_WSx (FSPH=1, FSLN=0) tdfs tdfs tdfs I2S_WSx (FSPH=0, FSLN=1) tdfs tdfb1 tddo tdfs I2S_WSx (FSPH=1, FSLN=1) I2S_SDOx tsdi I2S_SDIx thd i tsdi thd i FSPH is bit 2 of I2Sx_CNTREG register. FSLN is bit 1 of I2Sx_CNTREG register. Figure 8-24 Master Mode Timing tscyc tshw I2S_SCKx tslw tsfi thfi I2S_WSx (FSPH=0, FSLN=0) tsfi thfi I2S_WSx (FSPH=1,FSLN=0) tsfi I2S_WSx (FSPH=0, FSLN=1) tsfi I2S_WSx (FSPH=1, FSLN=1) tdfb1 thd i tddo thd i I2S_SDOx tsdi I2S_SDIx tsdi Figure 8-25 Slave Mode Timing FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 66 MB86R01 DATA SHEET 8.5.8. UART Signal Timing Signal Symbol Description Value Min. Typ. Max. Unit Table 8-36 AC Timing UART_SOUT0 UART_SOUT1 UART_SOUT2 UART_SOUT3 UART_SOUT4 UART_SOUT5 UART_SIN0 UART_SIN1 UART_SIN2 UART_SIN3 UART_SIN4 UART_SIN5 UART_XRTS0 UART_XCTS0 tdo Data output delay time – – 12 ns tdw Input data width 16*A – – ns trtso tctsw XRTS output delay time Input XCTS data width – A – – 11 – ns ns Internal clock is the standard of output delay. A indicates APB bus clock cycle, and it is different from the output delay standard clock. Internal CLK UART_SOUT0 UART_SOUT1 UART_SOUT2 UART_SOUT3 UART_SOUT4 UART_SOUT5 UART_XRTS0 UART_SIN0 UART_SIN1 UART_SIN2 UART_SIN3 UART_SIN4 UART_SIN5 UART_XCTS0 Figure 8-26 tdo trtso tdw ～ ～ tctsw ～ ～ UART Timing FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 67 MB86R01 DATA SHEET 8.5.9. Signal I2C Bus Timing Symbol Value Description Normal mode High-speed mode Min. 250 (*1) 100 (*1) 0.0 (*1) 0.0 (*1) 4.7 (*1) 1.3 (*1) 1.0 (*1) 2.5 (*1) 4.0 (*1) 0.6 (*1) 4.7 (*1) 1.3 (*1) 2*m + 2 (*2) Int (1.5*m) + 2 (*2) m + 2 (*2) Int (0.5*m) + 2 (*2) m (*2) m (*2) 4.0 (*2) 0.6 (*2) 4.7 (*2) 1.3 (*2) Typ. – – – – – – – – – – – – – – – – – – – – – – Max. – – – – – – – – – – – – – – – – – – – – – – Unit ns ns ns ns µs µs µs µs µs µs µs µs PCLK (*3) PCLK (*3) PCLK (*3) PCLK (*3) PCLK (*3) PCLK (*3) µs µs µs µs Table 8-37 AC timing of I2C signal TS2SDAI SDAI setup time Normal mode I2C_SDA0 T SDAI hold time I2C_SDA1 H2SDAI High-speed mode TWBFI TCSCLI BUS free time SCLI cycle time Normal mode High-speed mode Normal mode High-speed mode Normal mode High-speed mode Normal mode High-speed mode Normal mode High-speed mode Normal mode High-speed mode Normal mode High-speed mode Normal mode High-speed mode Normal mode High-speed mode TWHSCLI SCLI H width TWLSCLI SCLI L width TCSCLO SCLO cycle time TWHSCLO SCLO H width TWLSCLO SCLO L width TS2SCLI SCLI setup time TH2SCLI SCLI hold time I2C_SCL0 I2C_SCL1 *1: I2C bus specification value *2: See I2C bus interface's clock control register (I2CxCCR) of the MB86R01 LSI product specifications for the "m" value *3: PCLK = APB bus clock cycle STOP START D7 D6 D5 D4 D3 D2 D1 D0 ACK RESTART I2C_SDA0(in) I2C_SDA1(in) TS2SCLI I2C_SCL0(in) I2C_SCL1(in) TWBFI TH2SCLI TS2SDAI TH2SDAI TS2SCLI TH2SCLI TCSCLI TWHSCLI TWLSCLI STOP START D7 D6 D5 D4 D3 D2 D1 D0 ACK RESTART I2C_SDA0(out) I2C_SDA1(out) TS2SCLO I2C_SCL0(out) I2C_SCL1(out) TH2SCLO TH2SDAO TS2SCLO TH2SCLO TCSCLO TWHSCLO TWLSCLO Figure 8-27 I2C Access Timing FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 68 MB86R01 DATA SHEET 8.5.10. SPI Signal Timing Signal Symbol Description Operating frequency Setup time, SPI_DI valid before SPI_SCK Hold time, SPI_DI valid after SPI_SCK Delay time, SPI_SCK Delay time, SPI_SCK Value Min. – 15 15 -2 -2 Typ. – – – – – Max. 0.5*A – – 5 5 Unit MHz ns ns ns ns Table 8-38 SPI AC Timing SPI_SCK SPI_DI SPI_DO SPI_SS tcyc tsdi thdi tdo tsso A indicates APB bus clock frequency. tcyc SPI_SCK SPI_SCK tdo SPI_DO tsdi SPI_DI thdi tsso SPI_SS Figure 8-28 SPI Timing Polarity of SPI_SCK is determined by the register setting. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 69 MB86R01 DATA SHEET 8.5.11. Table 8-39 CAN Signal Timing CAN AC Timing Symbol Description Data output delay time Input data width Value Min. – 1000 Typ. – – Max. 17 – Unit ns ns Signal CAN_TX0 CAN_TX1 CAN_RX0 CAN_RX1 tdo tdw Internal clock is the standard of output delay. Internal CLK tdo CAN_TX0 CAN_TX1 tdw CAN_RX0 CAN_RX1 Figure 8-29 ～ ～ CAN Timing FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 70 MB86R01 DATA SHEET 8.5.12. 8.5.12.1. MediaLB Signal Timing MediaLB AC Spec Type A Ground = 0V; Load capacitance = 60pF; MediaLB speed = 256Fs or 512Fs; Fs = 48kHz; all timing parameters specified from the valid voltage threshold as listed below; unless otherwise noted. 8.5.12.1.1. Clock Value Table 8-40 AC Timing of Clock Signal Signal Symbol Description MLBCLK operating frequency (*1) MLBCLK rising time MLBCLK falling time MLBCLK cycle time MLBCLK low time MLBCLK high time MLBCLK pulse width variation Unit Comment Min. Typ. Max. 11.264 – – 256xFs at 44.0kHz MHz 512xFs at 44.1kHz – 22.5792 – – – 24.6272 512xFs at 48.1kHz – – – – 30 14 30 14 – – – 81 40 37 17 38 17 – 3 3 – – – – – – 2 ns VIL to VIH ns VIH to VIL ns ns ns 256xFs 512xFs 256xFs 512xFs 256xFs 512xFs fmck tmckr tmckf MLBCLK tmckc tmckl tmckh tmpwv ns pp (*2) *1: The controller can shut off MLBCLK to place MediaLB in a low-power state. *2: Pulse width variation is measured at 1.25V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp). 8.5.12.1.2. Input Signal Value Min. 4 0 Typ. – – Max. – – Table 8-41 AC Timing of Input Signal Signal Symbol Description MLBSIG and MLBDAT input valid to MLBCLK falling MLBSIG and MLBDAT input hold from MLBCLK low Unit ns ns Comment MLBSIG, MLBDAT input tdsmcf tdhmcf 8.5.12.1.3. Output Signal Value Min. 0 4 Typ. – – Max. Table 8-42 AC Timing of Output Signal Signal Symbol Description MLBSIG and MLBDAT output high impedance from MLBCLK low Bus hold time Unit ns ns (*1) Comment MLBSIG, MLBDAT output tmcfdz tmdzh tmckl – *1: The board must be designed to ensure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 71 MB86R01 DATA SHEET 8.5.12.2. MediaLB AC Spec Type B Ground = 0V, Load capacitance = 40pF, MediaLB speed = 1024Fs, and Fs = 48kHz. All timing parameters are specified from the valid voltage threshold as listed below; unless otherwise noted. 8.5.12.2.1. Clock Value Min. 45.056 – – – – – 6.8 9.7 – Typ. Max. Table 8-43 AC Timing of Clock Signal Signal Symbol Description MLBCLK operating frequency (*1) MLBCLK rising time MLBCLK falling time MLBCLK cycle time MLBCLK low time MLBCLK high time MLBCLK pulse width variation Unit Comment fmck tmckr tmckf tmckc tmckl tmckh tmpwv – – 1024xFs at 44.0kHz 49.152 – MHz 1024xFs at 48.0kHz – 49.2544 1024xFs at 48.1kHz – – 20.3 7.8 10.4 – 1 1 – – – 0.5 ns VIL to VIH ns VIH to VIL ns ns ns ns pp (*2) MLBCLK *1: The controller can shut off MLBCLK to place MediaLB in a low-power state. *2: Pulse width variation is measured at 1.25V by triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ns peak-to-peak (pp). 8.5.12.2.2. Input Signal Value Min. 1 0 Typ. – – Max. – – Table 8-44 AC Timing of Input Signal Signal Name MLBSIG, MLBDAT input Symbol Description MLBSIG and MLBDAT input valid to MLBCLK falling MLBSIG and MLBDAT input hold from MLBCLK low Unit ns ns Comment tdsmcf tdhmcf 8.5.12.2.3. Output signal Value Min. 0 2 Typ. – – Max. Table 8-45 AC Timing of Output Signal Signal Name Symbol Description MLBSIG and MLBDAT output high impedance from MLBCLK low Bus hold time Unit ns ns (*1) Comment MLBSIG, MLBDAT Output tmcfdz tmdzh tmckl – *1: The board must be designed to ensure that the high-impedance bus does not leave the logic state of the final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed. FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 72 MB86R01 DATA SHEET Figure 8-30 MediaLB Timing Figure 8-31 MediaLB Pulse Width Variation Timing FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 73 MB86R01 DATA SHEET 8.5.13. Signal USB2.0 Signal Timing Symbol Driver characteristics: Description Value Min. 500 500 Typ. – – Max. – – Unit Table 8-46 High-speed AC Timing USB_HSDP USB_HSDM USB_FSDP USB_FSDM thsr thsf – zhsdrv Rise time (10% - 90%) Fall time (10% - 90%) Driver waveform requirements Driver output resistance (which also serves as highspeed termination) High-speed data rate Data source jitter Receiver jitter tolerance ps ps Complying with USB2.0 specification (section 7.1.2) 40.5 – 49.5 Ω Clock timing: thsdrat – – 479.760 – 480.240 Mb/s High-speed data timing: Complying with USB2.0 specification (section 7.1.2) Table 8-47 Full-speed AC Timing Signal Symbol Driver characteristics: Description Value Min. 4 4 90 Typ. – – – Max. 20 20 111.11 Unit tfr tff tfrfm tfdraths USB_HSDP USB_HSDM USB_FSDP USB_FSDM Rise time (10% - 90%) Fall time (10% - 90%) Difference rise and fall time matching ns ns % Clock timing: (in case of using UTMI i/f and setting FSSEL = "0") Full-speed data rate for hubs and devices which are 11.9940 capable of high-speed Source jitter total (including frequency tolerance): To next transition For paired transitions Source jitter for differential transition to SE0 transition Receiver jitter: To next transition For paired transitions Source SE0 interval of EOP Receiver SE0 interval of EOP Width of SE0 interval during differential transition – 12.0060 Mb/s Full-speed data timings: (in case of using UTMI i/f and setting FSSEL = "0") tdj1 tdj2 tfdeop tjr1 tjr2 tfeopt tfeopr tfst -3.5 -4 -2 -18.5 -9 160 82 – – – – – – – – 3.5 4 5 18.5 9 175 – 14 ns ns ns ns ns ns Table 8-48 Signal USB_HSDP USB_HSDM USB_FSDP USB_FSDM Low-speed AC Timing Symbol Driver characteristics: Description Value Min. 75 75 80 Typ. – – – Max. 300 300 125 Unit tlr tlf tlrfm Rise time (10% - 90%) Fall time (10% - 90%) Rise and fall time matching ns ns % FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 74 MB86R01 DATA SHEET Differential Data Lines 90% 10% 90% 10% Rise Time Figure 8-32 Fall Time Data Signal Rise and Fall Time FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 75 MB86R01 DATA SHEET 8.5.14. 8.5.14.1. IDE66 Signal Timing IDE PIO Timing Value mode0 600 70 290 – 60 30 50 5 30 20 0 35 1250 5 mode1 383 50 290 – 45 20 35 5 30 15 0 35 1250 5 mode2 330 30 290 – 30 15 20 5 30 10 0 35 1250 5 mode3 180 30 80 70 30 10 20 5 30 10 0 35 1250 5 mode4 120 25 70 25 20 10 20 5 30 10 0 35 1250 5 Table 8-49 AC timing of Register Access Symbol t0 t1 t2 t2i t3 t4 t5 t6 t6Z t9 tRD tA tB tC Description Cycle time (min.) Address valid to IDE_XDIOR/IDE_XDIOW setup (min.) IDE_XDIOR/IDE_XDIOW pulse width 8 bit (min.) IDE_XDIOR/IDE_XDIOW recovery time (min.) IDE_XDIOW data setup (min.) IDE_XDIOW data hold (min.) IDE_XDIOR data setup (min.) IDE_XDIOR data hold (min.) IDE_XDIOR data tristate (max.) IDE_XDIOR/IDE_XDIOW to address valid hold (min.) Read data valid to IDE_DIORDY active (if IDE_DIORDY initially low after tA) (min.) IDE_DIORDY setup time IDE_DIORDY pulse width (max.) IDE_DIORDY assertion to release (max.) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Table 8-50 AC timing of Data Access Symbol t0 t1 t2 t2i t3 t4 t5 t6 t6Z t9 tRD tA tB tC Description Cycle time (min.) Address valid to IDE_XDIOR/IDE_XDIOW setup (min.) IDE_XDIOR/IDE_XDIOW pulse width 8 bit (min.) IDE_XDIOR/IDE_XDIOW recovery time (min.) IDE_XDIOW data setup (min.) IDE_XDIOW data hold (min.) IDE_XDIOR data setup (min.) IDE_XDIOR data hold (min.) IDE_XDIOR data tristate (max.) IDE_XDIOR/IDE_XDIOW to address valid hold (min.) Read data valid to IDE_DIORDY active (if IDE_DIORDY initially low after tA) (min.) IDE_DIORDY setup time IDE_DIORDY pulse width (max.) IDE_DIORDY assertion to release (max.) Value mode0 600 70 165 – 60 30 50 5 30 20 0 35 1250 5 mode1 383 50 125 – 45 20 35 5 30 15 0 35 1250 5 mode2 240 30 100 – 30 15 20 5 30 10 0 35 1250 5 mode3 180 30 80 70 30 10 20 5 30 10 0 35 1250 5 mode4 120 25 70 25 20 10 20 5 30 10 0 35 1250 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 76 MB86R01 DATA SHEET t0 IDE_XDCS[1:0] IDE_DA[2:0] t1 Valid t2 t9 t2i IDE_XDIOR/ IDE_XDIOW IDE_DD[15:0] (Write Data) IDE_DD[15:0] (Read Data) tA DATA t3 t4 DATA t5 t6 t6Z IDE_DIORDY (no wait) IDE_DIORDY (wait) tC tB tRD tC Figure 8-33 PIO Access Timing FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 77 MB86R01 DATA SHEET 8.5.14.2. Table 8-51 Symbol IDE Ultra DMA Timing AC timing of Ultra DMA Value Description Typical sustained average 2 cycle time 2 cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to next falling edge of STROBE) Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge) Data valid setup time at sender (from data valid until STROBE edge) Data valid setup time at sender (from STROBE edge until data may become invalid) First STROBE time (for device to first negateDSTROBE from STOP during data in Burst) Limited interlock time Interlock time with minimum Unlimited interlock time Maximum time allowed for output drivers to release (from asserted or negated) Minimum delay time required for output Drivers to assert or negate (from released) Envelope time (from DMACK- to STOP and HDMARDY- during data in burst initiation and from IDE_XDDDMACK to STOP during data out burst initiation) Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of DMARDY) Minimum time to assert STOP or negate IDE_DMARQ Maximum time before releasing IDE_DIORDY Minimum time before driving STROBE Setup and hold times for DMACK(before assertion or negation) Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates burst) mode0 240 – mode1 160 – mode2 120 – mode3 90 – mode4 60 – Unit Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. T2cycleTYP ns T2cycle 230 – 154 – 115 – 86 – 57 – ns Tcycle Tdvs Tdvh 112 70 6.2 – – – 73 48 6.2 – – – 54 30 6.2 – – – 39 20 6.2 – – – 25 6.7 6.2 – – – ns ns ns Tfs Tli Tmli Tui Taz Tzah Tzad – 0 20 0 – 20 0 230 150 – – 10 – – – 0 20 0 – 20 0 200 150 – – 10 – – – 0 20 0 – 20 0 170 150 – – 10 – – – 0 20 0 – 20 0 130 100 – – 10 – – – 0 20 0 – 20 0 120 100 – – 10 – – ns ns ns ns ns ns ns Tenv 20 70 20 70 20 70 20 55 20 55 ns Trfs Trp Tiordyz tziordy Tack Tss – 160 – 0 20 50 75 – 20 – – – – 125 – 0 20 50 70 – 20 – – – – 100 – 0 20 50 60 – 20 – – – – 100 – 0 20 50 60 – 20 – – – – 100 – 0 20 50 60 – 20 – – – ns ns ns ns ns ns FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 78 MB86R01 DATA SHEET IDE_DMARQ Tui IDE_XDDMACK Tfs Tss Tli Tli Tmli IDE_XDIOW (STOP) IDE_XDIOR (HDMARDY) Tack Tenv Tzad Tack Tziordy Tiordyz IDE_DIORDY (DSTROBE) Taz Tcycle T2cycle DATA Tdvs Tdvh Tcycle Taz DATA Tdvs Tdvh DATA Tazh Tdvs Tdvh CRC IDE_DD[15:0] IDE_XDCS[1:0] Tack Tack IDE_DA[2:0] Figure 8-34 IDE Read Access Timing IDE_DMARQ Tui IDE_XDDMACK Tack Tenv Tli Tui Trp IDE_XDIOW (STOP) Tziordy Trfs Tli Tmli Tack Tiordyz IDE_DIORDY (DDMARDY) IDE_XDIOR (HSTROBE) Tcycle T2cycle Tcycle Tdvs Tdvh DATA CRC IDE_DD[15:0] DATA Tdvs Tdvh DATA Tdvs Tdvh IDE_XDCS[1:0] Tack Tack IDE_DA[2:0] Figure 8-35 IDE Write Access Timing FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 79 MB86R01 DATA SHEET 8.5.15. 8.5.15.1. SD Signal Timing Clock Value Min. – Typ. – Table 8-52 AC Timing of Clock Signal Signal Name SD_CLK Symbol t_CLK SD_CLK cycle Description Unit Max. 20.83 (*1) MHz *1: 20.83MHz for SD memory card and 20MHz for multimedia card (MMC) 8.5.15.2. Input/Output Signal Value Min. -6.0 13.0 19.0 Typ. – – – Max. 3.0 – – Table 8-53 AC Timing of Data Signal Signal Name Symbol tD_DAT SD_DAT[3:0] tS_DAT tH_DAT Description Output data delay (standard of SD_CLK falling edge) Input data setup (standard of SD_CLK rising edge) Input data hold (standard of SD_CLK rising edge) Unit ns ns ns SD_CLK t_SDCLK SD_DAT[3:0] tD_DAT tD_DAT Figure 8-36 Output Timing to Media SD_CLK SD_DAT[3:0] tS_DAT VALID DATA tH _DAT tS_DAT VALID DATA tH_DAT Figure 8-37 Input Timing from Media FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 80 MB86R01 DATA SHEET 8.5.16. ETM9 Trace Port Signal Timing Symbol Tctlsr Description TRACECTL setup time to rising edge of TRACECLK. TRACECTL hold time to rising edge of TRACECLK. TRACECTL setup time to falling edge of TRACECLK. TRACECTL hold time to falling edge of TRACECLK. TRACEDATA setup time to rising edge of TRACECLK. TRACEDATA hold time to rising edge of TRACECLK. TRACEDATA setup time to falling edge of TRACECLK. TRACEDATA hold time to falling edge of TRACECLK. Value Min. 2 1 2 1 2 1 2 1 Typ. – – – – – – – – Max. – – – – – – – – Unit ns ns ns ns ns ns ns ns Table 8-54 AC Timing of Trace Signal Signal Name TRACECTL Tctlhr Tctlsf Tctlhf Tdatasr Tdatahr Tdatasf Tdatahf TRACEDATA[3:0] TRACECLK TRACECTL Tctlsf Tctlhf Tctlsr Tctlhr TRACEDATA[3:0] Tdatasf Tdatahf Tdatasr Tdatahr [NOTE] MB86R01 supports only half-rate clocking mode. Figure 8-38 Trace Signal Timing FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 81 MB86R01 DATA SHEET 8.5.17. EXIRC Signal Timing Symbol Description Input data-width Value Min. A Typ. – Max. – Unit ns Table 8-55 AC Timing Signal Name INT_A[3:0] tdw The case that external interrupt input request is edge (rising edge and falling edge), input data width (tdw) is regulated as follows. When level ("H" or "L") is selected as the request, it should be held until interrupt process is completed. A indicates APB bus clock cycle. APB BUS CLK tdw INT_A[3:0] Figure 8-39 EXIRC Timing FUJITSU MICROELECTRONICS PROPRIETARY AND CONFIDENTIAL 82