MB88111

FUJITSU SEMICONDUCTOR DATA SHEET DS04-13106-2E Linear IC Converter CMOS A/D Converter (With 24-Channel Input at 10-bit Resolution) MB88111 s DESCRIPTION The MB88111 is an analog-to-digital converter that converts its analog input to a 10-bit digital value and outputs it as serial data. The MB88111 employs a successive approximation method for A/D conversion. It has 24 input channels to be A/ D converted selectively by setting in an internal register. Since the MB88111 can input and output 16-bit serial data in synchronization with the clock, it can be easily connected to the serial I/O port in a 16-bit microcontroller. s FEATURES • • • • • • • • • • • • • • 24-channel analog input RC-type successive approximation system with a sample-and-hole circuit 10-bit resolution Conversion speed within 50 µs (at a system clock rate of 1 MHz) Digitally converted data output from the MSB Digitally converted data output as 16-bit serial data Clock-synchronous serial transfer system Internal extended serial interface Capable of triggering A/D conversion through an external pin Capable of input through an 8-channel port Serial data output format selectable using an external pin 10-bit monotonicity No missing code Power supply voltage ranging from 3.5 to 5.5 V (Continued) s PACKAGES 44-pin, Plastic QFP 48 pin, Plastic SH-DIP (FPT-44P-M11) (DIP-48P-M01) MB88111 (Continued) • Operating temperature ranging from –40 to +50°C • CMOS process • Package options of 44-pin QFP and 48-pin SH-DIP s PIN ASSIGNMENT (Top view) AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 24 33 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AVRH AV CC V CC 34 35 36 37 38 39 40 41 42 32 31 30 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 AN19 AN20 AN21 AN22 AN23 AGND AVRL V SS TESTI N.C. MOD INDEX 43 44 1 2 3 4 5 6 7 8 9 10 13 12 11 IRQX SOT ENDC ATGX RSTX CCLK SIN ESIN CS2X AN18 CS1 AN8 AN9 SCK (FPT-44P-M11) (Continued) 2 MB88111 (Continued) (Top view) AN1 AN0 AVRH AV CC V CC N.C. RSTX SCK CCLK SIN ESIN SOT ENDC IRQX ATGX CS2X CS1 N.C. MOD N.C. TESTI V SS AVRL AGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 INDEX 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 AN2 AN3 AN4 AN5 AN6 AN7 N.C. AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 N.C. AN19 AN20 AN21 AN22 AN23 (DIP-48P-M01) 3 MB88111 s PIN DESCRIPTION Pin no. QFP 41 to 26 DIP Symbol I/O I Circuit type F Descriptions Analog input pins. The pin to be subject to conversion is selected by the command input through the SIN pin. Also, a series of pins from AN16 to AN23 can be used as a port input. Pin for selecting a serial data output mode: “L”: Mode A for output from the SOT pin in synchronization with the fall of the SCK signal. “H”: Mode B for output from the SOT pin in synchronization with the rise of the SCK signal. Input pins for selecting an extended serial interface mode. Setting the CS1 level to “H” and the CS2X level to “L” enables A/D converted data transfer. Setting the CS1 level to “L” or the CS2X level to “H” clears the register command without affecting A/D conversion. Serial data input to the external extended serial input pin ESIN is output to the SOT pin as it is. (See Section 7 “Extended Serial Interface” in “s OPERATION.”) Serial data input pin This pin is a hysteresis input with a filter. Serial data output pin System clock input pin This pin is a hysteresis input. Serial data transfer clock input pin This pin is a hysteresis input with a filter. External trigger input pin. This pin incorporates a pullup resistor. The ATC command initiates A/D conversion at the rise of the signal at this pin. The pin is a hysteresis input. A/D conversion interrupt signal input pin. The signal level becomes “L” upon completion of A/D conversion; it becomes “H” upon reception of data to be converted. A/D conversion completion signal output pin. The signal level becomes “H” upon completion of A/D conversion; it becomes “L” upon reception of data to be converted. Serial input extension input pin. When the CS1 level is “L” or the CS2X level is “H,” data input to the ESIN pin is output to the SOT pin as it is. Reset signal input pin. This pin incorporates a pull-up resistor. Setting the signal level to “L” initializes the internal circuit of the device. This pin is a hysteresis input with a filter. 2 to 1, AN0 to AN15 48 to 43, 41 to 34 25 to 18 33 to 31, AN16 to 29 to 25 AN23 12 19 MOD I G A 11 10 17 16 CS1 CS2X I A 4 6 3 2 9 10 12 9 8 15 SIN SOT CCLK SCK ATGX I O I I I B H B B C 8 14 IRQX O H 7 13 ENDC O H 5 11 ESIN I A 1 7 RSTX I D (Continued) 4 MB88111 (Continued) Pin no. QFP 14 DIP 21 Symbol TESTI I/O I Circuit type E Descriptions Test input pin. This pin incorporates a pull-down resistor. Maintain the pin at “L” level during normal use. Digital circuit power supply pin Digital circuit ground pin Analog circuit power supply pin Analog circuit ground pin Reference (high) voltage input pin Reference (low) voltage input pin Non-connection pin 44 15 43 17 42 16 13 5 22 4 24 3 23 6, 18, 20, 30, 42 VCC VSS AVCC AGND AVRH AVRL N.C. — — — — — — — — — — — — — — s I/O CIRCUIT TYPE Type A Circuit • CMOS input Remarks B • Hysteresis input • CMOS input C • Input with pull-up resistor • CMOS input (Continued) 5 MB88111 (Continued) Type D Circuit Remarks • Input with pull-up resistor • Hysteresis input • CMOS input E • Input with pull-down resistor • CMOS input F • Analog input G • Analog input • Hysteresis input • CMOS input H • CMOS output 6 MB88111 s BLOCK DIAGRAM AV CC AGND AVRH AVRL Multiplexer AN0 10-bit D/A converter AN15 AN16 Port input Sample-and-hold circuit Successive approximation register Comparator AN23 ENDC Control circuit IRQX ATGX Interface control circuit SCK ESIN SIN MOD CS2X CS1 Command register Data register Output select circuit SOT RSTX TESTI CCLK V CC V SS 7 MB88111 s FUNCTIONAL DESCRIPTION 1. SC (Serial Command) Register (Reset status: 0000H) The SC register contains an A/D converter command and an input channel identification. Accessing this register after releasing it from the reset status activates the A/D converter. Note that this register accepts setting even during A/D conversion. Note also that input of a command to the register must take an interval of at least 4 CCLKs after input of the previous command. MSB bf be bd bc bb ba Channel b9 b8 b7 b6 b5 b4 b3 b2 b1 LSB b0 Command Don't care (1) Command bits A string of command bits selects an A/D converter command such as STOP Setting a command during execution . of another command cancels the command currently being executed. bf 0 0 0 0 1 be 0 0 1 1 0 bd 0 1 0 1 0 Command name STOP STC — — NOP Function Stops A/D conversion (if it is being executed) and initializes the A/D converter. This command has the same effect as RSTX. Executes A/D conversion of the specified channel once. (See Section 3 “STC (Standard Conversion) Command.”) Unused (*) Unused (*) No-op command. Input of this command during A/D conversion does not affect operation. If followed by this command, the ATC command can transfer converted data while holding the NOP command. The basic operation of this command is the same as that of the STC command. The ATC command can leave the A/D conversion start timing to the external trigger pin ATGX. (See Section 4 “ATC (Auto Trigger Conversion) Command.”) Unused (*) Unused (*) 1 0 1 ATC 1 1 1 1 0 1 — — * : These command settings cause the STOP command to be executed. 8 MB88111 (2) Channel select bits A string of channel select bits selects the pin to be subject to A/D conversion. This bit string is enabled only for the STC or ATC command. bc 0 0 0 0 0 . . . 0 0 0 0 0 bb 0 0 0 0 0 . . . 1 1 1 1 1 ba 0 0 0 0 1 . . . 0 1 1 1 1 b9 0 0 1 1 0 . . . 1 0 0 1 1 b8 0 1 0 1 0 . . . 1 0 1 0 1 Pin to be selected AN0 AN1 AN2 AN3 AN4 . . . AN11 AN12 AN13 AN14 AN15 bc 1 . . . 1 1 1 1 1 1 1 1 1 bb 0 . . . 0 1 1 1 1 1 1 1 1 ba 0 . . . 1 0 0 0 0 1 1 1 1 b9 0 . . . 1 0 0 1 1 0 0 1 1 b8 0 . . . 1 0 1 0 1 0 1 0 1 Port input AN16 to AN23 (*2) Undefined (*1) Pin to be selected AN16 . . . AN23 *1: These settings of the bit string cause the STOP command to be executed. *2: This setting is enabled only for the STC command. (See Section 5 “Port Input Command.”) If this setting is made for the ATC command, the STOP command is executed. 2. Data Output Format Upon completion of A/D conversion, the ENDC pin level becomes “H” and the IRQX pin level becomes “L.” Execution of serial transfer at this time outputs data in the format illustrated below. The data output timing can be selected by the MOD pin between the falling edge (mode A) or rising edge (mode B) of the SCK signal. When the ENDC pin level is “L,” 0000H is output. MSB Bf Be Bd Bc Bb Ba B9 B8 B7 B6 B5 ENDC B4 B3 B2 B1 LSB B0 Converted data A/D converted pin ENDC (A/D conversion completion flag): This bit is set to “1” upon completion of A/D conversion. It is set to “0” upon completion of serial transfer. Note: SCK input upon low-to-high transition of the ENDC pin level should be avoided. Otherwise, data may not be output correctly. 9 MB88111 3. STC (Standard Conversion) Command Input of the STC command executes A/D conversion of the specified channel once. Impletion of A/D conversion, the ENDC signal rises while the IRQX signal falls. Clock input to the SCK pin after A/D conversion outputs data to the SOT pin. Upon completion of data output, the ENDC signal falls while the IRQX signal rises. If the next command is STOP or NOP, the A/D conversion is terminated. If the STC command is input during A/D conversion, the command currently being executed is cancelled and the STC command is executed. • Example of STC command execution (1) STC command input during A/D conversion cancels the current command and executes A/D conversion of the new specified channel. Output data at this time is 0000H. 16 Cycle SCK SIN AN0 AN1 AN2 STOP SOT 0000H Data 0 0000H Data 2 ENDC IRQX A/D AN0 conversion AN1 conversion AN2 conversion • Example of STC command execution (2) NOP command input during A/D conversion does not affect operation. Output data at this time is 0000H. If A/ D conversion is completed during NOP command input, the ENDC and IRQX pin levels become “H” and “L” respectively upon completion of the NOP command input. 16 Cycle SCK SIN AN3 NOP NOP AN4 NOP STOP SOT 0000H 0000H Data 3 0000H 0000H Data 4 ENDC IRQX AN3 conversion AN4 conversion A/D 10 MB88111 4. ATC (Auto Trigger Conversion) Command The ATC command is the same as the STC command in basic operation. This command can initiates A/D conversion using the external trigger pin ATGX. The external trigger signal is sampled by 1 µs clock and filtered by 1 clock. The external trigger signal input during A/D conversion is ignored. If the next command is the STOP command, A/D conversion is terminated. If it is the NOP command, the ATC command is executed continuously. The channel cannot be changed at this time. To change the channel, input the ATC command to that effect. • Example of ATC command execution (1) NOP command input during A/D conversion enables the same channel to be A/D converted. An attempt to set the ATGX signal low during A/D conversion is ignored. NOP command input during A/D conversion does not affect operation. Output data at this time is 0000H. 16 Cycle SCK SIN SOT ENDC IRQX ATGX A/D AN5 conversion AN5 conversion AN6 conversion AN5 0000H NOP Data 5 AN6 Data 5 NOP 0000H STOP Data 6 • Example of ATC command execution (2) Setting the ATGX signal low again after A/D conversion restarts A/D conversion. In data output mode B, however, do not use the ATC command in this way, or data will not be output correctly. If A/D conversion is completed during NOP command input, the ENDC and IRQX pin levels become “H” and “L” respectively upon completion of the NOP command input. 16 Cycle SCK SIN SOT ENDC IRQX ATGX A/D AN7 conversion AN7 conversion AN7 conversion AN7 0000H AN8 Data 7 NOP 0000H STOP Data 8 AN8 conversion 11 MB88111 5. Port Input Command The port input command executes I/O evaluation of 8-channel inputs from the AN16 to AN23 pins at a prescribed threshold in 10 clock cycles and outputs the results as port input data. The processing sequence is activated each time port input is selected by the STC command. Port input data is output in the following format: MSB Bf Be Bd Bc Bb Ba B9 B8 B7 “0” B6 B5 ENDC B4 B3 B2 “1” B1 LSB B0 Evaluation data Evaluation data: The evaluation values of AN23 to AN16 are output to bits Bf to B8. Evaluation value “H”: Vin ≥ 0.8 x Vcc “L”: Vin ≤ 0.2 x Vcc ENDC (A/D completion flag): This bit is set to “1” upon completion of A/D conversion. It is set to “0” upon completion of serial transfer. • Example of STC command execution (3) (Port input command) 16 Cycle 10 Cycle 16 Cycle SCK SIN SOT ENDC IRQX AN16 to AN23 A/D Evaluation CH9 STOP 0000H Data 9 12 MB88111 6. Serial Output Select Function The MB88111 can select the serial data output timing between the rising edge or falling edge of the clock signal according to the setting of the MOD pin. Mode A (MOD = “L”) SCK MSB SOT MSB Bf Be Bd Bc Bb Ba B9 B8 B7 B6 B5 B4 B3 B2 B1 LSB B0 LSB b0 SIN bf be bd bc bb ba b9 b8 b7 b6 b5 b4 b3 b2 b1 Serial data is output at the falling edge of the SCK signal. Note: A/D converted data is not guaranteed if the MOD pin is switched when the ENDC signal is active. Before changing the output mode, make the ENDC inactive or set the RSTX pin level to “L” after switching the MOD pin. Mode B (MOD = “H”) SCK MSB LSB B0 LSB b0 SOT SIN Bf MSB bf Be Bd Bc Bb Ba B9 B8 B7 B6 B5 B4 B3 B2 B1 be bd bc bb ba b9 b8 b7 b6 b5 b4 b3 b2 b1 Serial data is output at the rising edge of the SCK signal. Note: A/D converted data is not guaranteed if the MOD pin is switched when the ENDC signal is active. Before changing the output mode, make the ENDC inactive or set the RSTX pin level to “L” after switching the MOD pin. The first bit is output when the ENDC signal becomes “H.” 7. Extended Serial Interface The MB88111 can select whether to output A/D converted data or to output data input to the ESIN pin by controlling the CS1 and CS2X pins. CS1 H L L H CS2X L L H H Connection to the ESIN pin SOT pin A/D converted data Note: A/D converted data is not guaranteed if the CS1 or CS2X setting is changed during SCK input. 13 MB88111 s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = AGND = 0 V) Parameter Symbol VCC Power supply voltage Input voltage Output voltage Power consumption Storage temperature * : VCC ≥ AVCC ≥ AVRH AVCC AVRH VIN VOUT PD Tstg — — Based on VSS (Ta = +25°C) Conditions Ratings Min. –0.3 –0.3 –0.3 –0.3 –0.3 — –55 Max. +7.0 +7.0* +7.0* VCC + 0.3 VCC + 0.3 150 +150 Unit V V V V V mW °C 2. Recommended Operating Conditions Parameter Symbol VCC AVCC Power supply voltage VCC AGND AVRH AVRL Operation temperature * : VCC ≥ AVCC ≥ AVRH Ta Values Min. 3.5* 0 AVCC × 0.8 0 –40 Max. 5.5* 0 AVCC AVCC × 0.2 +105 Unit V V V V °C 14 MB88111 3. DC Characteristics (1) Digital section (VCC = +3.5 V to +5.5 V, VSS = AGND = 0 V, Ta = –40°C to +105°C) Value Symbol Conditions Unit Min. Typ. Max. VCC VCC ICC — Operation at CLK = 1 MHz (with no load) VIN = VSS VIN = VSS VCC = 5.0 V 3.5 — 5.0 0.5 5.5 1.5 V mA Parameter Power supply voltage Power supply current Pin name Low-level input leakage current MOD, CCLK CS1, CS2X SCK, ESIN SIN ATGX RSTX IIZL1 –2 — 2 µA IIZL2 –200 –100 –50 µA High-level input leakage current MOD, CCLK CS1, CS2X SCK, ESIN SIN, ATGX RSTX MOD, ESIN CS1, CS2X IIZL1 VIN = VCC –2 — 2 µA VIL VILS VIH VIHS — — — — VSS − 0.3 VSS − 0.3 0.7 VCC 0.8 VCC — — — — 0.3 VCC 0.2 VCC VCC + 0.3 VCC + 0.3 V V V V Low-level input voltage SCK, CCLK SIN, ATGX RSTX, * MOD, ESIN CS1, CS2X High-level input voltage SCK, CCLK SIN, ATGX RSTX, * SCK, CCLK SIN, ATGX RSTX, * SOT IRQX ENDC Hysteresis width Low-level output voltage High-level output voltage VHYS VOL VOH — IOL = 2.5 mA IOH = –400 µA 0.02 VCC — VCC − 0.4 — — — 0.3 VCC 0.4 — V V V * : AN16 to AN23 (port input mode) 15 MB88111 (2) Analog section (AVCC, VCC = +3.5 V to +5.5 V (VCC ≥ AVCC), VSS = AGND = 0 V, Ta = –40°C to +105°C) Value Pin name Symbol Conditions Unit Min. Typ. Max. — — — AN0 to AN23 — — — — — CCLK AVCC AVRH AVRH AVRL AN0 to AN23 — — IA IR — — — — — — — — — — — CCLK = 1 MHz — — — — — — — — — — — — — — — 800 — — 0.8 AVCC 0 AVRL –200 10 10 — — — — — — 1000 3.0 150 — — — — — — ±1 ±1 ±1/2 ±1/2 ±2 50 1200 6.0 300 AVCC 0.2 AVCC AVRH 200 bits bits LSB LSB LSB LSB LSB µs KHz mA µA V V V nA Parameter Resolution Monotonic increase Linearity error Differential linearity error Full-scale transition error Zero-transition error Total error Conversion time Input clock frequency Supply current Reference voltage supply current Analog reference voltage Analog input voltage Multiplexer OFF-leakage current • No missing code is guaranteed. Notes: • If the output impedance of the external input is too high, the analog voltage sampling time may be insufficient. • In the power-on sequence, turn the power supply for the digital system first before turning that for the analog system on. Analog input equivalent circuit Analog input Comparator R ON1 R ON2 C0 ⋅ RON1 = About 1.5 kΩ ⋅ RON2 =About 1.5 kΩ ⋅ C0 =About 15 pF Note: The above values are reference values. 16 MB88111 4. AC Characteristics (AVCC, VCC = +3.5 V to +5.5 V (VCC ≥ AVCC), VSS = AGND = 0 V, Ta = –40°C to +105°C) Values Parameter Symbol Conditions Unit Min. Max. CCLK clock cycle time Low-level CCLK clock pulse width High-level CCLK clock pulse width CCLK clock rise time CCLK clock fall time SCK clock cycle time Low-level SCK clock pulse width High-level SCK clock pulse width SCK clock rise time SCK clock fall time SIN setup time SIN hold time Command interval ENDC reset time RSTX pulse width RSTX ↑ → SCK ↓ time SCK ↑ → CS1 ↓ time SCK ↑ → CS2X ↑ time CS1 ↑ → SCK ↓ time CS2X ↓ → SCK ↓ time SOT output delay time (mode A) SOT output delay time (mode B) ENDC ↑ → SOT output (mode B) STC command A/D conversion time ATC command A/D conversion time ATGX setup time ATGX hold time Port input evaluation time Port input setup time Port input hold time Extended serial HL propagation delay Extended serial LH propagation delay Noise filter width fCLK tCKL tCKH tCr tCf fSCK tSKL tSKH tSr tSf tSIS tSIH tCOM tENR tRSH tRSS tCSS tCSH tSODA tSODB tSOHB tSTC tSATC tSATS tSATH tPOT tPTS tPTH tSHL tSLH tINF fCLK = 1/fCLK — — — tSCK = 1/fSCK — — — — — CCLK = 1 MHz See “Load conditions.” — — — — See “Load conditions.” See “Load conditions.” See “Load conditions.” CCLK = 1 MHz CCLK = 1 MHz CCLK = 1 MHz CCLK = 1 MHz CCLK = 1 MHz — — See “Load conditions.” See “Load conditions.” — 800 400 400 – 400 400 400 – 50 250 4 – 100 1 500 500 — — — — — 4 2 — 0 0 — — 15 1200 — — 10 1200 — — 10 — — — 1 — — — — 300 300 200 50 50 — — 10 — — 100 100 — KHz ns ns ns KHz ns ns ns ns ns µs µs ns µs ns ns ns ns ns µs µs µs µs µs ns ns ns ns ns 17 MB88111 AC Test Condition Measurement point C L = 50 pF s TIMING DIAGRAM 1. Input Clock Timing t CLK t CKH CCLK t Cf t CKL t Cr t SCK t SKH SCK t Sf t SKL t Sr Evaluation levels are 80% and 20% of the VCC. 18 MB88111 2. Serial Data Input Timing t RSH RSTX t RSS SCK t COM t CSS t CSH CS1 (CS2X) t SIS t SIH SIN b0 t ENR bf be ENDC Evaluation levels are 80% and 20% of the VCC. 3. Serial Data Output Timing Mode A SCK t SODA SOT Bf Be Evaluation levels are 80% and 20% of the VCC. Mode B SCK t SODB SOT t SOHB Bf Be ENDC Evaluation levels are 80% and 20% of the VCC. 19 MB88111 4. A/D Conversion and Port Input Evaluation STC command (normal mode) SCK SIN b0 t STC ENDC Evaluation levels are 80% and 20% of the VCC. ATC command SCK SIN b0 t ATS t ATH ATGX t ATC ENDC Evaluation levels are 80% and 20% of the VCC. 20 MB88111 STC command (port input mode) SCK SOT b0 t PTS AN16 to AN23 t POT t PTH ENDC Evaluation levels are 80% and 20% of the VCC. 5. Extended Serial Interface ESIN t SHL t SLH SOT Evaluation levels are 80% and 20% of the VCC. 6. Noise Filter t INF t INF Evaluation levels are 80% and 20% of the VCC. 21 MB88111 s DEFINITIONS OF A/D CONVERTER TERMS • Resolution Analog transition identifiable by the A/D converter • Linearity error Deviation of the straight line drawn between the zero transition point (00 0000 0000 ↔ 00 0000 0001) and the full-scale transition point (11 1111 1110 ↔ 11 1111 1111) of the device from actual conversion characteristics • Differential linearity error Deviation from the ideal input voltage required to shift output code by one LSB • Total error Difference between actual and logical values. This error is caused by a zero transition error, full-scale transition error, linearity error, quantum error, and by noise. Ideal I/O characteristics 3FF 3FE 3FD Digital output 1.5 LSB Digital output 3FF 3FE 3FD Actual conversion characteristics {1 LSB×(N–1) +0.5 LSB} Total error 004 003 002 001 VOT (Ideal value) VFST (Ideal value) 004 003 002 001 VNT' (Measured value) Actual conversion characteristics Ideal characteristics 1 LSB (Ideal value) 0.5 LSB AVRL Analog input 1 LSB (Ideal value) = AVRH–AVRL [v] 1024 [v] AVRH AVRL Analog input Total error of digital output N = AVRH VNT'– {1 LSB × (N–1) +0.5 LSB} 1 LSB V OT (Ideal value) = 0.5 LSB V FST (Ideal value) = AVRH - 1.5 LSB [v] (Continued) 22 MB88111 (Continued) Zero transition error 004 Actual conversion characteristics 003 Digital output Digital output 3FE 3FF Full-scale transition error Ideal characteristics Actual conversion characteristics 002 Actual conversion characteristics 001 3FD VFST' (Measured value) Actual conversion characteristics 3FC VOT'(Measured value) AVRL Analog input VOT'–0.5 LSB 1 LSB Analog input VFST' – (AVRH–1.5 LSB) 1 LSB AVRH Zero transition error = Full scale transition error = Linearity error 3FF 3FE 3FD Digital output VFST' (Measured value) Digital output N Actual conversion characteristics { 1 L S B × ( N – 1 ) + V OT' } Differential linearity error Ideal characteristics N+1 Actual conversion characteristics 004 003 002 VNT' (Measured value) Actual conversion characteristics Ideal characteristics N-1 V(N + 1)T' VNT' (Measured (Measured value) value) N-2 Actual conversion characteristics AVRH Analog input 001 VOT' (Measured value) AVRH Analog input AVRL AVRL VNT' – {1 LSB' × (N–1)+V OT' } Linearity error of digital output N = 1 LSB' 1 LSB' = VFST' – VOT' 1022 [V] Differential linearity error of digital output N = V(N+1)T' –VNT' 1 LSB' –1 23 MB88111 s ORDERING INFORMATION Part number Package 44-pin, Plastic QFP (FPT-44P-M11) 48-pin, Plastic SH-DIP (DIP-48P-M01) Remarks MB88111PFQ MB88111P-SH 24 MB88111 s PACKAGE DIMENSIONS 44-pin, Plastic QFP (FPT-44P-M11) 14.40±0.40 SQ (.567±.016) 10.00±0.20 SQ (.394±.008) 33 23 2.35(.093)MAX (Mounting height) 0.05(.002)MIN (STAND OFF) Details of "A" part 34 22 0.15(.006) INDEX 8.00 (.315) REF 11.60±0.30 (.457±.012) 0.20(.008) 0.18(.007)MAX 0.53(.021)MAX 44 "A" 12 Details of "B" part LEAD No. 1 11 0.80(.0315)TYP 0.30±0.10 (.012±.004) "B" 0.16(.006) M 0.15±0.05 (.006±.002) 0~10° 1.40±0.30 (.055±.012) 0.10(.004) C 1994 FUJITSU LIMITED F44018S-1C-1 Dimensions in mm (inches). 48-pin, Plastic SH-DIP (DIP-48P-M01) 43.69 –0.30 +.008 1.720 –.012 +0.20 INDEX-1 13.80±0.25 (.543±.010) INDEX-2 5.25(.207) MAX 3.00(.118) MIN +0.50 0.51(.020)MIN 0.25±0.05 (.010±.002) 1.00 –0 +.020 .039 –0 1.778±0.18 (.070±.007) 1.778(.070) MAX 0.45±0.10 (.018±.004) 15.24(.600) TYP 15°MAX 40.894(1.610)REF C 1994 FUJITSU LIMITED D48002S-3C-3 Dimensions in mm (inches). 25 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. 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You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. F9703 © FUJITSU LIMITED Printed in Japan 24