MB88151APNF-G-801-JNE1

FUJITSU SEMICONDUCTOR DATA SHEET DS04-29127-1E ASSP Spread Spectrum Clock Generator MB88151A ■ DESCRIPTION MB88151A is a clock generator for EMI (Electro Magnetic Interference) reduction. The peak of unnecessary radiation noise (EMI) can be attenuated by making the oscillation frequency slightly modulate periodically with the internal modulator. It corresponds to both of the center spread which modulates frequency in modulation off as Middle Centered and down spread which modulates so as not to exceed frequency in modulation off. ■ FEATURES MB88151A100/101 (multiply-by-1) Input frequency/ Output frequency Modulation clock cycle-cycle jitter MB88151A200/201 (multiply-by-2) MB88151A400/401 (multiply-by-4) MB88151A500/501 (multiply-by-1/2) 16.6 MHz to 33.4 MHz/ 8.3 MHz to 16.7 MHz MB88151A800/801 (multiply-by-8) 8.3 MHz to 16.7 MHz 66.4 MHz to 133.6 MHz 16.6 MHz to 33.4 MHz/ 16.6 MHz to 33.4 MHz/ 16.6 MHz to 33.4 MHz/ 16.6 MHz to 33.4 MHz 33.2 MHz to 66.8 MHz 66.4 MHz to 133.6 MHz Less than100 ps Less than 100 ps Less than 150 ps Less than 200 ps Less than 150 ps • • • • • • • Modulation rate : ± 0.5%, ± 1.5% (Center spread), − 1.0%, − 3.0% (Down spread) Equipped with oscillation circuit : Range of oscillation 8.3 MHz to 33.4 MHz Modulation clock output Duty : 40% to 60% Low current consumption by CMOS process : 5 mA (24 MHz : Typ-sample, no load) Power supply voltage : 3.3 V ± 0.3 V Operating temperature : − 40 °C to + 85 °C Package : SOP 8-pin Copyright©2007 FUJITSU LIMITED All rights reserved MB88151A ■ PRODUCT LINEUP MB88151A has five kinds of multiplication type. Product Input frequency range MB88151A-100/101 MB88151A-200/201 MB88151A-400/401 MB88151A-500/501 MB88151A-800/801 8.3 MHz to 16.7 MHz 16.6 MHz to 33.4 MHz Multiplier ratio Multiply-by-1 Multiply-by-2 Multiply-by-4 Multiply-by-1/2 Multiply-by-8 Output frequency range 16.6 MHz to 33.4 MHz 33.2 MHz to 66.8 MHz 66.4 MHz to 133.6 MHz 8.3 MHz to 16.7 MHz 66.4 MHz to 133.6 MHz ■ PIN ASSIGNMENT TOP VIEW XIN 1 VSS 2 MB88151A SEL0 3 SEL1 4 8 XOUT 7 VDD 6 ENS/XPD 5 CKOUT FPT-8P-M02 ■ PIN DESCRIPTION Pin name XIN VSS SEL0 SEL1 CKOUT ENS/XPD VDD XOUT I/O I ⎯ I I O I ⎯ O Pin no. 1 2 3 4 5 6 7 8 GND pin Modulation rate setting pin Modulation rate setting pin Modulated clock output pin Modulation enable setting pin (with pull-up resistance)/ Power down pin (with pull-up resistor)* Power supply voltage pin Resonator connection pin Description Resonator connection pin/clock input pin * : XPD = 800 kΩ pull-up resistor at “L” 2 MB88151A ■ I/O CIRCUIT TYPE Pin Circuit type Remarks CMOS hysteresis input SEL0, SEL1 50 kΩ 800 kΩ CMOS hysteresis input with 50 kΩ + 800 kΩ (Typ) pull-up resistors Note : If “L” is input to XPD when the XPD function is selected, 50 kΩ pull-up resistor is disconnected. ENS • CMOS output • IOL = 4 mA CKOUT Note : For XIN and XOUT pins, refer to “■OSCILLATION CIRCUIT”. 3 MB88151A ■ HANDLING DEVICES Preventing Latch-up A latch-up can occur if, on this device, (a) a voltage higher than VDD or a voltage lower than VSS is applied to an input or output pin or (b) a voltage higher than the rating is applied between VDD pin and VSS pin. The latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use this device, be very careful not to exceed the maximum rating. Handling unused pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or pull-down resistor. Unused output pin should be opened. The attention when the external clock is used Input the clock to XIN pin, and XOUT pin should be opened when you use the external clock. Please pay attention so that an overshoot and an undershoot do not occur to an input clock of XIN pin. Power supply pins Please design connecting the power supply pin of this device by as low impedance as possible from the current supply source. We recommend connecting electrolytic capacitor (about 10 µF) and the ceramic capacitor (about 0.01 µF) in parallel between VSS pin and VDD pin near the device, as a bypass capacitor. Oscillation circuit Noise near the XIN and XOUT pins may cause the device to malfunction. Design printed circuit boards so that electric wiring of XIN or XOUT pin and the resonator do not intersect other wiring. Design the printed circuit board that surrounds the XIN and XOUT pins with ground. 4 MB88151A ■ BLOCK DIAGRAM VDD SEL1 Modulation rate setting Modulation rate setting SEL0 Modulation enable setting/ ENS/XPD PLL block Modulation clock output CKOUT Power down setting Reference clock XOUT XIN Rf = 1 MΩ VSS 1 − M Phase compare Charge pump V/I conversion IDAC ICO Reference clock 1 − N Loop filter Modulation clock output 1 − L Modulation logic Modulation rate setting/ Modulation enable setting MB88151A PLL block A glitchless IDAC (current output D/A converter) provides precise modulation, thereby dramatically reducing EMI. 5 MB88151A ■ PIN SETTING When changing the pin setting, the stabilization wait time for the modulation clock is required. The stabilization wait time for the modulation clock take the maximum value of “■ ELECTRICAL CHARACTERISTICS • AC Characteristics Lock-up time”. ENS modulation enable setting (MB88151A-100/200/400/500/800) ENS Modulation L H No modulation Modulation Note : Spectrum does not spread when “L” is set to ENS. The clock with low jitter can be obtained. Because of ENS has Pull-up resistance, spectrum spread when “H” is set to it or open the terminal. XPD Power down setting (MB88151A-101/201/401/501/801) XPD L H Status Power down Status Operating status Note : CKOUT of output pins are fixed to “L” output during power down. SEL0, SEL1 Modulation rate setting SEL1 SEL0 L L H H L H L H Modulation rate ± 1.5% ± 0.5% − 1.0% − 3.0% Modulation type Center spread Center spread Down spread Down spread Note : The modulation rate can be changed at the level of the terminal. 6 MB88151A • Center spread Spectrum is spread (modulated) by centering on the frequency in modulation off. Radiation level Modulation width 3.0% −1.5% +1.5% Frequency Frequency in modulation off Center spread example of ± 1.5% modulation rate • Down spread Spectrum is spread (modulated) below the frequency in modulation off. Modulation width 3.0% Radiation level −3.0% Frequency Frequency in modulation off Down spread example of − 3.0% modulation rate 7 MB88151A ■ ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage* Input voltage* Output voltage* Storage temperature Operation junction temperature Output current Overshoot Undershoot Symbol VDD VI VO TST TJ IO VIOVER VIUNDER Rating Min − 0.5 VSS − 0.5 VSS − 0.5 − 55 − 40 − 14 ⎯ Max + 4.0 VDD + 0.5 VDD + 0.5 + 125 + 125 + 14 VDD + 1.0 (tOVER ≤ 50 ns) ⎯ Unit V V V °C °C mA V V VSS−1.0 (tUNDER ≤ 50 ns) * : The parameter is based on VSS = 0.0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Overshoot/Undershoot tUNDER ≤ 50 ns VIOVER ≤ VDD + 1.0 V VDD Input pin VSS tOVER ≤ 50 ns VIUNDER ≤ VSS − 1.0 V 8 MB88151A ■ RECOMMENDED OPERATING CONDITIONS (VSS = 0.0 V) Parameter Power supply voltage “H” level input voltage “L” level input voltage Input clock duty cycle Operating temperature Symbol VDD VIH VIL tDCI Ta Pin VDD XIN, SEL0, SEL1, ENS XIN ⎯ Conditions ⎯ ⎯ ⎯ 8.3 MHz to 33.4 MHz ⎯ Value Min 3.0 VDD × 0.8 VSS 40 − 40 Typ 3.3 ⎯ ⎯ 50 ⎯ Max 3.6 VDD + 0.3 VDD × 0.2 60 + 85 Unit V V V % °C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Input clock duty cycle (tDCI = tb/ta) ta tb XIN 1.5 V 9 MB88151A ■ ELECTRICAL CHARACTERISTICS • DC Characteristics (Ta = − 40 °C to + 85 °C, VDD = 3.3 V ± 0.3 V, VSS = 0.0 V) Parameter Symbol Pin Conditions No load capacitance at output 24 MHz MB88151A-100 At power down MB88151A-101 VOH Output voltage VOL Output impedance ZO CKOUT “H” level output, IOH = − 4 mA “L” level output, IOL = 4 mA Value Min ⎯ ⎯ VDD − 0.5 VSS ⎯ ⎯ ⎯ ⎯ ⎯ 25 500 Typ 5.0 Max 7.0 ⎯ VDD 0.4 ⎯ 16 Unit mA µA V V Ω pF Power supply current ICC VDD 10 ⎯ ⎯ 45 ⎯ ⎯ ⎯ ⎯ 50 800 CKOUT 8.3 MHz to 133.6 MHz XIN, SEL0, SEL1, ENS Ta = + 25 °C, VDD = VI = 0.0 V, f = 1 MHz 8.3 MHz to 66.8 MHz Input capacitance CIN 15 10 7 200 1200 kΩ pF Load capacitance CL RPUE RPUP CKOUT 66.8 MHz to 100 MHz 100 MHz to 133.6 MHz ENS XPD VIL = 0.0 V VIL = 0.0 V Input pull-up resistance 10 MB88151A • AC Characteristics (Ta = − 40 °C to + 85 °C, VDD = 3.3 V ± 0.3 V, VSS = 0.0 V) Parameter Oscillation frequency Symbol fx Pin XIN, XOUT Conditions Fundamental oscillation External clock input (multiply-by-1, 2, 4, divided by 2) External clock input (multiply-by-8) MB88151A-100/101 (Multiply by 1) MB88151A-200/201 (Multiply by 2) Output frequency fOUT CKOUT MB88151A-400/401 (Multiply by 4) MB88151A-500/501 (2-frequency division) MB88151A-800/801 (multiply-by-8) Output slew rate Output clock duty cycle SR tDCC CKOUT CKOUT 0.4 V to 2.4 V Load capacitance 15 pF 1.5 V Value Min 8.3 Typ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ fin/1900 (1900) fin/760 (760) 2 3 ⎯ Max 33.4 Unit MHz 16.6 33.4 MHz Input frequency fin XIN 8.3 16.6 33.2 66.4 8.3 66.4 0.4 40 fin/2200 (2200) fin/880 (880) ⎯ ⎯ ⎯ 16.7 33.4 66.8 133.6 16.7 133.6 4.0 60 fin/1600 (1600) fin/640 (640) 5 8 V/ns % kHz (clks) kHz (clks) ms MHz Modulation period (Number of input clocks per modulation) fMOD (nMOD) MB88151A-100/101, MB88151A-200/201, MB88151A-400/401, CKOUT MB88151A-500/501 MB88151A-800/801 Lock-up time tLK CKOUT 8.3 MHz to 80 MHz 80 MHz to 133.6 MHz MB88151A-100/101, MB88151A-200/201 No load capacitance, Ta = + 25 °C, VDD = 3.3 V 100 Cycle-cycle jitter tJC MB88151A-400/401, CKOUT MB88151A-800/801 No load capacitance, Ta = + 25 °C, VDD = 3.3 V MB88151A-500/501 No load capacitance, Ta = + 25 °C, VDD = 3.3 V ⎯ ⎯ 150 ps-rms ⎯ ⎯ 200 Note : The modulation clock stabilization wait time is required after the power is turned on, the IC recovers from power saving, or after FREQ (frequency range) or ENS (modulation ON/OFF) setting is changed. For the modulation clock stabilization wait time, assign the maximum value for lock-up time. 11 MB88151A f (Output frequency) Modulation waveform t fMOD (Min) fMOD (Max) Clock time nMOD (Max) Clock time nMOD (Min) t MB88151A contains the modulation period to realize the efficient EMI reduction. The modulation period fMOD depends on the input frequency and changes between fMOD (Min) and fMOD (Max) . Furthermore, the average value of fMOD equals the typical value of the electrical characteristics. 12 MB88151A ■ OUTPUT CLOCK DUTY CYCLE (tDCC = tb/ta) ta tb 1.5 V CKOUT ■ INPUT FREQUENCY (fin = 1/tin) tin 0.8 VDD XIN ■ OUTPUT SLEW RATE (SR) 2.4 V CKOUT tr tf 0.4 V Note : SR = (2.4 − 0.4) /tr, SR = (2.4 − 0.4) /tf ■ CYCLE-CYCLE JITTER (tJC = | tn − tn+1 |) CKOUT tn tn+1 Note : Cycle-cycle jitter is defined the difference between a certain cycle and immediately after (or, immediately before) . 13 MB88151A ■ MODULATION WAVEFORM • ±1.5% modulation rate, Example of center spread CKOUT Output frequency + 1.5 % Frequency at modulation OFF Time − 1.5 % fMOD • −1.0% modulation rate, Example of down spread CKOUT Output frequency Frequency at modulation OFF Time − 0.5 % − 1.0 % fMOD 14 MB88151A ■ LOCK-UP TIME 3.0 V VDD Internal clock stabilization wait time XIN Setting pin SEL0, SEL1, ENS CKOUT VIH tLK (lock-up time ) If the setting pin is fixed at the “H” or “L” level, the maximum time after the power is turned on until the set clock signal is output from CKOUT pin is (the stabilization wait time of input clock to XIN pin) + (the lock-up time “tLK”). For the input clock stabilization time, check the characteristics of the resonator or oscillator used. XIN ENS VIH VIL tLK (lock-up time ) tLK (lock-up time ) CKOUT For modulation enable control using the ENS pin during normal operation, the set clock signal is output from CKOUT pin at most the lock-up time (tLK) after the level at the ENS pin is determined. Note : When the pin setting is changed, the CKOUT pin output clock stabilization time is required. Until the output clock signal becomes stable, the output frequency, output clock duty cycle, modulation period, and cyclecycle jitter cannot be guaranteed. It is therefore advisable to perform processing such as cancelling a reset of the device at the succeeding stage after the lock-up time. 15 MB88151A XIN Internal clock stabilization wait time XPD tLK (lock-up time) CKOUT When the power down is controlled by XPD pin, the desired clock is obtained after the pin is set to H level until the maximum lock-up time tLK is elapsed. 16 MB88151A ■ OSCILLATION CIRCUIT The figure below shows the connection example about general resonator. The oscillation circuit has the built-in resistance (1 MΩ) . The value of capacity (C1 and C2) is required adjusting to the most suitable value of individual resonator. The most suitable value is different by individual resonator. Please refer to the resonator manufacturer which you use for the most suitable value. Input the clock to XIN pin, and do not connect anything with XOUT pin if you use the external clock (you do not use the resonator). • When using the resonator MB88151A LSI Internal Rf (1 MΩ) XIN Pin XOUT Pin MB88151A LSI External C1 C2 • When using an external clock MB88151A LSI Internal Rf (1 MΩ) XIN Pin XOUT Pin MB88151A LSI External External clock OPEN Note : Note that a jitter characteristic of an input clock may cause an affect a cycle-cycle jitter characteristic. 17 MB88151A ■ INTERCONNECTION CIRCUIT EXAMPLE C1 Xtal C2 1 2 SEL0 3 4 SEL1 MB88151A 8 7 6 5 R1 + ENS C4 C3 C1, C2 C3 C4 R1 : Oscillation stabilization capacitance (refer to “■OSCILLATION CIRCUIT”.) : Capacitor of 10 µF or higher : Capacitor about 0.01 µF (connect a capacitor of good high frequency property (ex. laminated ceramic capacitor) to close to this device.) : Impedance matching resistor for board pattern 18 MB88151A ■ SPECTRUM EXAMPLE CHARACTERISTICS The condition of the examples of the characteristic is shown as follows : Input frequency = 20 MHz (Output frequency = 20 MHz : Using MB88151A-100 (Multiply-by-1)), Power - supply voltage = 3.3 V, None load capacity, Modulation rate = ± 1.5% (center spread). Spectrum analyzer HP4396B is connected with CKOUT. The result of the measurement with RBW = 1 kHz (ATT use for − 6dB). CH B Spectrum 10 dB /REF 0 dBm No modulation −6.54 dBm Avg 4 ±1.5% modulation −24.45 dBm RBW# 1 kHZ VBW 1 kHZ CENTER 20 MHZ ATT 6 dB SWP 2.505 s SPAN 4 MHZ 19 MB88151A ■ ORDERING INFORMATION Part number MB88151APNF-G-100-JNE1 MB88151APNF-G-101-JNE1 MB88151APNF-G-200-JNE1 MB88151APNF-G-201-JNE1 MB88151APNF-G-400-JNE1 MB88151APNF-G-401-JNE1 MB88151APNF-G-500-JNE1 MB88151APNF-G-501-JNE1 MB88151APNF-G-800-JNE1 MB88151APNF-G-801-JNE1 MB88151APNF-G-100-JNEFE1 MB88151APNF-G-101-JNEFE1 MB88151APNF-G-200-JNEFE1 MB88151APNF-G-201-JNEFE1 MB88151APNF-G-400-JNEFE1 MB88151APNF-G-401-JNEFE1 MB88151APNF-G-500-JNEFE1 MB88151APNF-G-501-JNEFE1 MB88151APNF-G-800-JNEFE1 MB88151APNF-G-801-JNEFE1 MB88151APNF-G-100-JNERE1 MB88151APNF-G-101-JNERE1 MB88151APNF-G-200-JNERE1 MB88151APNF-G-201-JNERE1 MB88151APNF-G-400-JNERE1 MB88151APNF-G-401-JNERE1 MB88151APNF-G-500-JNERE1 MB88151APNF-G-501-JNERE1 MB88151APNF-G-800-JNERE1 MB88151APNF-G-801-JNERE1 8.3 MHz to 16.7 MHz 16.6 MHz to 33.4 MHz 8.3 MHz to 16.7 MHz 16.6 MHz to 33.4 MHz 8.3 MHz to 16.7 MHz 16.6 MHz to 33.4 MHz Input frequency Multiplier range ratio Multiplyby-1 Multiplyby-2 Multiplyby-4 Multiplyby-1/2 Multiplyby-8 Multiplyby-1 Multiplyby-2 Multiplyby-4 Multiplyby-1/2 Multiplyby-8 Multiplyby-1 Multiplyby-2 Multiplyby-4 Multiplyby-1/2 Multiplyby-8 Output frequency range 16.6 MHz to 33.4 MHz 33.2 MHz to 66.8 MHz 66.4 MHz to 133.6 MHz 8.3 MHz to 16.7 MHz 66.4 MHz to 133.6 MHz 16.6 MHz to 33.4 MHz 33.2 MHz to 66.8 MHz 66.4 MHz to 133.6 MHz 8.3 MHz to 16.7 MHz 66.4 MHz to 133.6 MHz 16.6 MHz to 33.4 MHz 33.2 MHz to 66.8 MHz 66.4 MHz to 133.6 MHz 8.3 MHz to 16.7 MHz 66.4 MHz to 133.6 MHz Package Remarks 8-pin plastic SOP (FPT-8P-M02) Emboss taping (EF type) Emboss taping (ER type) 20 MB88151A ■ PACKAGE DIMENSION 8-pin plastic SOP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 1.27 mm 3.9 × 5.05 mm Gullwing Plastic mold 1.75 mm MAX 0.06 g (FPT-8P-M02) 8-pin plastic SOP (FPT-8P-M02) Note 1) *1 : These dimensions include resin protrusion. Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. +.010 *1 5.05 –0.20 .199 –.008 8 +0.25 0.22 –0.07 .009 –.003 5 +0.03 +.001 *2 3.90±0.30 6.00±0.40 (.154±.012) (.236±.016) Details of "A" part 45˚ 1.55±0.20 (Mounting height) (.061±.008) 0.25(.010) 0.40(.016) 1 4 "A" 0~8˚ 1.27(.050) 0.44±0.08 (.017±.003) 0.13(.005) M 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.15±0.10 (.006±.004) (Stand off) 0.10(.004) C 2002 FUJITSU LIMITED F08004S-c-4-7 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 21 MB88151A FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. 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Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept. F0703