MB88153-100

FUJITSU SEMICONDUCTOR DATA SHEET DS04-29118-2E Spread Spectrum Clock Generator MB88153 ■ DESCRIPTION MB88153 is a clock generator for EMI (Electro Magnetic Interference) reduction. The peak of unnecessary (EMI) can be attenuated by making the oscillation frequency slightly modulate periodically with the internal modulator. It corresponds to both of the center spread which modulates input frequency as Middle Centered and down spread which modulates so as not to exceed input frequency. ■ FEATURE • • • • • • • • • • Power down pin : 600 µA (Max) consumption current at power down Input frequency : 16.6 MHz to 134 MHz Output frequency : 16.6 MHz to 134 MHz (One-fold input frequency) Modulation rate can select from ± 0.5%, ± 1.5% − 1.0% or − 3.0%. (For center spread / down spread.) Modulation clock output Duty : 40% to 60% Modulation clock Cycle-Cycle Jitter : Less than 100 ps Low current consumption by CMOS process : 4.0 mA (24 MHz : Typ-sample, no load) Power supply voltage : 3.3 V ± 0.3 V Operating temperature : − 40 °C to +85 °C Package : SOP 8-pin ■ PACKAGE 8-pin plastic SOP (FPT-8P-M02) MB88153 ■ PRODUCT LINEUP MB88153 has four kinds of modulation rate and modulation type (center/down spread). Product Modulation rate Modulation type MB88153-100 MB88153-101 MB88153-110 MB88153-111 −1.0% −3.0% ±0.5% ±1.5% Down Center ■ PIN ASSIGNMENT TOP VIEW CKIN 1 VDD 2 VSS 3 CKOUT 4 8 XPD MB88153 7 FREQ0 6 FREQ1 5 ENS FPT-8P-M02 ■ PIN DESCRIPTION Pin name CKIN VDD VSS CKOUT ENS FREQ1 FREQ0 XPD I/O I ⎯ ⎯ O I I I I Pin no. 1 2 3 4 5 6 7 8 Clock input pin Power supply voltage pin GND pin Modulated clock output pin “L” output at power down Modulation enable setting pin Frequency setting pin Frequency setting pin (with pull-up resistor) Power down pin (with pull-up resistor) Power down at “L” input Description 2 MB88153 ■ I/O CIRCUIT TYPE Pin Circuit type Remarks • CMOS hysteresis input CKIN, ENS, FREQ1 • CMOS hysteresis input with pull-up resistor 50 kΩ (typ) 50 kΩ FREQ0, XPD • CMOS output • “L” output at power down CKOUT 3 MB88153 ■ HANDLING DEVICES Preventing Latchup A latchup can occur if, on this device, (a) a voltage higher than VDD or a voltage lower than VSS is applied to an input or output pin or (b) a voltage higher than the rating is applied between VDD and VSS. The latchup, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use this device, be very careful not to exceed the maximum rating. Handling unused pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or pull-down resistor. Unused output pin should be opened. Power supply pins Please design connecting the power supply pin of this device by as low impedance as possible from the current supply source. We recommend connecting electrolytic capacitor (about 10 µF) and the ceramic capacitor (about 0.01 µF) in parallel between VSS and VDD near the device, as a bypass capacitor. Clock I/O circuit Noise near the CKIN pin may cause the device to malfunction. Design the printed circuit board so that the wiring for the clock input does not intersect any other wiring. Please pay attention so that an overshoot and an undershoot do not occur to an input clock of CKIN pin. Design the printed circuit board that surrounds the CKIN and CKOUT pins with ground. 4 MB88153 ■ BLOCK DIAGRAM VDD XPD Power down setting Frequency setting Frequency setting Modulation enable setting Reference clock PLL block Clock output CKOUT FREQ0 FREQ1 ENS CKIN VSS 1 − M Phase compare Charge pump V/I conversion Frequency setting IDAC ICO Reference clock 1 − N Modulation clock output Loop filter Modulation rate setting Modulation enable setting 1 − L Modulation logic MB88153 PLL block A glitchless IDAC (current output D/A converter) provides precise modulation, thereby dramatically reducing EMI. 5 MB88153 ■ PIN SETTING When changing the pin setting, the stabilization wait time for the modulation clock required. The stabilization wait time for the modulation clock takes the maximum value of Lock-Up time in “■ ELECTRICAL CHARACTERISTICS • AC characteristics”. ENS modulation enable setting ENS L H Modulation No modulation Modulation Note : Spectrum does not spread when “L” is set to ENS. The clock with low jitter can be obtained. FREQ0, FREQ1 frequency setting FREQ0 FREQ1 L L H H L H L H Input frequency range 16.6 MHz to 40 MHz 66 MHz to 134 MHz 33 MHz to 67 MHz 40 MHz to 80 MHz Note : It is set according to the frequency of the clock input to the device. Set FREQ0 pin to “H” for the pin opened because FREQ0 pin has pull-up resistor. XPD power down setting XPD L H Power down Power down Normal operation Note : When “L” is set to XPD pin, the power down operation is implemented and “L” is output to CKOUT pin. When “H” is input to XPD pin or XPD pin is opened, normal operation is implemented because the XPD pin has pull-up resistor. 6 MB88153 • Center spread Spectrum is spread (modulated) by centering on the input frequency. Radiation level 3.0% modulation width −1.5% +1.5% Frequency Input frequency Center spread example of ± 1.5% modulation rate • Down spread Spectrum is spread (modulated) below the input frequency. Radiation level 3.0% modulation width −3.0% Frequency Input frequency Down spread example of − 3.0% modulation rate 7 MB88153 ■ ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage* Input voltage* Output voltage* Storage temperature Operation junction temperature Output current Overshoot Undershoot Symbol VDD VI VO TST TJ IO VIOVER VIUNDER Rating Min − 0.5 VSS − 0.5 VSS − 0.5 − 55 − 40 − 14 ⎯ VSS − 1.0 (tUNDER ≤ 50 ns) Max + 4.0 VDD + 0.5 VDD + 0.5 + 125 + 125 + 14 VDD + 1.0 (tOVER ≤ 50 ns) ⎯ Unit V V V °C °C mA V V * : The parameter is based on VSS = 0.0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Overshoot/Undershoot tUNDER ≤ 50 ns VIOVER ≤ VDD + 1.0 V VDD Input pin VSS tOVER ≤ 50 ns VIUNDER ≤ VSS − 1.0 V 8 MB88153 ■ RECOMMENDED OPERATING CONDITIONS (VSS = 0.0 V) Parameter Power supply voltage “H” level input voltage Symbol VDD VIH Pin VDD CKIN, ENS, FREQ0, FREQ1, XPD CKIN, ENS, FREQ0, FREQ1, XPD CKIN ⎯ Conditions ⎯ ⎯ Value Min 3.0 VDD × 0.80 Typ 3.3 ⎯ Max 3.6 VDD + 0.3 Unit V V “L” level input voltage VIL ⎯ 16.6 MHz to 134 MHz ⎯ VSS ⎯ 50 ⎯ VDD × 0.20 60 + 85 V % °C Input clock duty cycle Operating temperature tDCI Ta 40 − 40 WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Input clock duty cycle (tDCI = tb/ta) ta tb CKIN 1.5 V 9 MB88153 ■ ELECTRICAL CHARACTERISTICS • DC Characteristics (Ta = − 40 °C to + 85 °C, VDD = 3.3 V ± 0.3 V, VSS = 0.0 V) Parameter Symbol VOH Output voltage VOL Output impedance ZO CKOUT Pin CKOUT Conditions “H” level output IOH = − 4 mA “L” level output IOL = 4 mA Value Min VDD − 0.5 VSS ⎯ Typ ⎯ ⎯ 45 Max VDD 0.4 ⎯ Unit V V Ω CKOUT 16.6 MHz to 134 MHz CKIN, ENS, Ta = + 25 °C, FREQ0, VDD = VI = 0.0 V, FREQ1, f = 1 MHz XPD 16.6 MHz to 67 MHz CKOUT 67 MHz to 100 MHz 100 MHz to 134 MHz FREQ0, XPD VDD VDD Input capacitance CIN ⎯ ⎯ 16 pF ⎯ ⎯ ⎯ 25 ⎯ ⎯ ⎯ ⎯ ⎯ 50 4.0 ⎯ 15 10 7 200 6.0 600 kΩ mA µA pF Load capacitance CL Input Pull-up resistance Power supply current Power down current RPU ICC Ipd VIL = 0.0 V No load capacitance at 24 MHz output Input clock stopping • AC Characteristics (Ta = − 40 °C to + 85 °C, VDD = 3.3 V ± 0.3 V, VSS = 0.0 V) Parameter Input frequency Output frequency Output slew rate Output clock duty cycle Modulation frequency Lock-up time Symbol fin fOUT SR tDCC fMOD tLK Pin CKIN CKOUT CKOUT Conditions ⎯ ⎯ Load capacitance 15 pF 0.4 V to 2.4 V ⎯ ⎯ Value Min 16.6 16.6 0.4 40 ⎯ ⎯ ⎯ Typ ⎯ ⎯ ⎯ ⎯ 12.5 2 ⎯ Max 134 134 4.0 60 ⎯ 5 Unit MHz MHz V/ns % kHz ms CKOUT 1.5 V CKOUT CKOUT Cycle-cycle jitter tJC No load capacitance, Ta = + 25 °C, CKOUT VDD = 3.3 V, Standard deviation σ 100 ps Note : The modulation clock stabilization wait time is required after the power is turned on, the IC recovers from power saving, or after FREQ (frequency range) or ENS (modulation ON/OFF) setting is changed. For the modulation clock stabilization wait time, assign the maximum value for lock-up time. 10 MB88153 ■ OUTPUT CLOCK DUTY CYCLE (tDCC = tb/ta) ta tb 1.5 V CKOUT ■ INPUT FREQUENCY (fin = 1/tin) tin 0.8 VDD CKIN ■ OUTPUT SLEW RATE (SR) 2.4 V CKOUT tr tf 0.4 V Note : SR = (2.4−0.4) /tr, SR = (2.4−0.4) /tf ■ CYCLE-CYCLE JITTER CKOUT tn tn+1 Note : Cycle-cycle jitter is defined the difference between a certain cycle and immediately after (or, immediately before) . 11 MB88153 ■ MODULATION WAVEFORM • ±1.5% modulation rate, Example of center spread CKOUT output frequency + 1.5 % Frequency at modulation OFF Time − 1.5 % fMOD = 12.5 kHz (Typ) • −1.0% modulation rate, Example of down spread CKOUT output frequency Frequency at modulation OFF Time − 0.5 % − 1.0 % fMOD = 12.5 kHz (Typ) 12 MB88153 ■ LOCK-UP TIME 3.0 V VDD External clock stabilization wait time CKIN XPD VIH Setting pin FREQ0, FREQ1, ENS CKOUT VIH tLK (lock-up time ) If the XPD pin is fixed at the “H” level, the maximum time after the power is turned on until the set clock signal is output from CKOUT pin is (the stabilization wait time of input clock to CKIN pin) + (the lock-up time “tLK”). For the input clock stabilization time, check the characteristics of the resonator or oscillator used. VDD 3.0 V External clock stabilization wait time CKIN XPD VIH Setting pin FREQ0, FREQ1, ENS CKOUT VIH tLK (lock-up time ) When XPD pin controls the power-down, stable clock is output from CKOUT pin after becoming XPD pin = “H” level (in the maximum after lock-Up time (tLK) ). 13 MB88153 (Continued) CKIN VIH XPD ENS VIH VIL tLK (lock-up time ) tLK (lock-up time ) CKOUT When ENS pin is controlled for enable modulation, it is necessary for the stably clock output from CKOUT pin to wait lock-up time (tLK) . Note : In the following cases, it is necessary for the stably clock output from CKOUT pin, to wait lock-up time (tLK) . - After releasing power-down - When you change other terminal settings Output frequency, output clock duty cycle, modulation frequency, and cycle-cycle jitter are not guaranteed until the output clock is stable. It is recommended to take procedure to release of reset after. lock-up time (tLK) on the device using the modulation clock or etc. 14 MB88153 ■ INTERCONNECTION CIRCUIT EXAMPLE CKIN VDD VSS 1 2 MB88153 3 8 7 6 5 XPD FREQ0 FREQ1 ENS R1 4 CKOUT C1 C2 C1 C2 R1 : Capacitor of 10 µF or higher : Capacitor of approximately 0.01 µF (connect a capacitor of good high frequency property (ex. laminated ceramic capacitor) to close to this device) : Impedance matching resistor for a circuit on a board 15 MB88153 ■ SPECTRUM EXAMPLE CHARACTERISTICS The condition of the examples of the characteristic is shown as follows: Input frequency = 20 MHz (Output frequency = 20 MHz), use for MB88153-111. Power-supply voltage = 3.3 V, None load capacity. Modulation rate = ± 1.5% (center spread). Spectrum analyzer HP4396B is connected with CKOUT. The result of the measurement with RBW = 1 kHz (ATT use for −6 dB) . CH B Spectrum 10 dB /REF 0 dBm No modulation −8.86 dBm Avg 4 ±1.5% modulation −26.54 dBm RBW# 1 kHZ VBW 1 kHZ CENTER 20 MHZ ATT 6 dB SWP 2.505 s SPAN 4 MHZ 16 MB88153 ■ ORDERING INFORMATION Part number MB88153PNF-G-100-JNE1 MB88153PNF-G-101-JNE1 MB88153PNF-G-110-JNE1 MB88153PNF-G-111-JNE1 MB88153PNF-G-100-JN-EFE1 MB88153PNF-G-101-JN-EFE1 MB88153PNF-G-110-JN-EFE1 MB88153PNF-G-111-JN-EFE1 MB88153PNF-G-100-JN-ERE1 MB88153PNF-G-101-JN-ERE1 MB88153PNF-G-110-JN-ERE1 MB88153PNF-G-111-JN-ERE1 modulation rate −1.0% −3.0% ±0.5% ±1.5% −1.0% −3.0% ±0.5% ±1.5% −1.0% −3.0% ±0.5% ±1.5% modulation type Down Down Center Center Down Down Center Center Down Down Center Center 8-pin plastic SOP Emboss taping (FPT-8P-M02) (ER type) 8-pin plastic SOP Emboss taping (FPT-8P-M02) (EF type) 8-pin plastic SOP (FPT-8P-M02) Package Remarks 17 MB88153 ■ PACKAGE DIMENSION 8-pin plastic SOP (FPT-8P-M02) Note 1) *1 : These dimensions include resin protrusion. Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. 0.22 –0.07 .009 –.003 8 5 +0.03 +.001 *1 5.05 –0.20 .199 –.008 +0.25 +.010 *2 3.90±0.30 6.00±0.40 (.154±.012) (.236±.016) Details of "A" part 45˚ 1.55±0.20 (Mounting height) (.061±.008) 0.25(.010) 0.40(.016) 1 4 "A" 0~8˚ 1.27(.050) 0.44±0.08 (.017±.003) 0.13(.005) M 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.15±0.10 (.006±.004) (Stand off) 0.10(.004) C 2002 FUJITSU LIMITED F08004S-c-4-7 Dimensions in mm (inches) Note : The values in parentheses are reference values. 18 MB88153 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. 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