MB89146V1P-SH

FUJITSU SEMICONDUCTOR DATA SHEET DS07-12522-3E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89140 Series MB89145/146 and MB89P147/PV140 s DESCRIPTION The MB89140 series is a line of single-chip microcontrollers that use the F2MC*-8L CPU core which can operate at low voltage but at high speed. The MB89140 series contains a variety of peripheral functions, such as timers, a serial interface, an A/D converter, and an external interrupt. The MB89140 series is applicable to a wide range of applications from welfare products to industrial equipment, including portable devices. *: F2MC stands for FUJITSU Flexible Microcontroller. s FEATURES • Minimum execution time: 0.5 µs/8-MHz oscillation • F2MC-8L family CPU core Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc. Instruction set optimized for controllers (Continued) s PACKAGES 64-pin Plastic SH-DIP 64-pin Plastic QFP 64-pin Ceramic MDIP 64-pin Ceramic MQFP (DIP-64P-M01) (FPT-64P-M06) (MDP-64C-P02) (MQP-64C-P01) MB89140 Series (Continued) • Low-voltage operation (when an A/D converter is not used) • Low current consumption (compatible with dual-clock system) • High-voltage ports on chip • Five types of timers 8-bit PWM timer (also usable as a reload timer) 12-bit MPG timer (also usable as a PPG output, PWM output, and reload timer) 8/16-bit timer (also usable as two 8-bit timers) 21-bit time-base timer • One serial interface Swichable transfer direction allows communication with various equipment. • 10-bit A/D converter: 12 channels Successive approximation type • External interrupt: 2 channels Two channels are independent and capable of wake-up from low-power consumption modes. (Rising edge, falling edge/both edges selectability) –0.3 V to +7.0 V can be applied to INT1 (N-ch open-drain) • Low-power consumption modes Stop mode (Oscillation stops to minimize the current consumption.) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.) Subclock mode Watch mode • Reset output and power-on reset selectability 2 MB89140 Series s PRODUCT LINEUP Part number MB89145 Parameter Classification Mass production products (mask ROM products) ROM size 16 K × 8 bits (internal mask ROM) 512 × 8 bits Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: Note: High-voltage output port (P-ch open-drain): Buzzer output (P-ch open-drain, high-voltage): Output ports (CMOS): Input ports (CMOS): I/O ports (CMOS): I/O ports (N-ch open-drain): Total: Clock timer 8-bit PWM timer (timer 1) 24 K × 8 bits (internal mask ROM) 768 × 8 bits One-time PROM/ EPROM product 32 K × 8 bits (internal PROM) MB89146 MB89P147 MB89PV140 Piggyback/ evaluation product (for evaluation and development) 32 K × 8 bits (external ROM) RAM size CPU functions 1 K × 8 bits 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.5 µs/8 MHz to 8.0 µs/8 MHz, 61 µs/32.768 kHz 4.5 µs/8 MHz to 72.0 µs/8 MHz, 562.5 µs/32.768 kHz The above times change according to the gear function. 8 (P60 to P67, for heavy current) 16 (P40 to P47, P50 to P57 for low current) 1 (heavy current) 4 (P20 to P23) 2 (P70 and P71, function as X0A and XIA pins when dual-clock system is used.) 23 (P00 to P07, P10 to P17, P30, and P32 to P37) 1 (P31) 55 Ports 21 bits × 1 (in main clock mode), 15 bits × 1 (at 32.768 kHz) 8-bit timer operation (toggled output capable, operating clock: 1, 2, 8, 16 system clock cycles) 8-bit resolution PWM operation (conversion cycle: 128 µs to 2.0 ms at 8.0-MHz oscillation, and highest gear speed) 12-bit resolution PWM operation (maximum conversion cycle of 2048.4 µs to 16.4 ms at 8.0 MHz-oscillation, and highest gear speed) 12-bit resolution reload timer operation (toggled output capable) 12-bit resolution PPG operation (minimum resolution of 0.5 µs at 8.0-MHz oscillation, and highest gear speed) 8/16-bit timer operation (operating clock, internal clock, external trigger) 8/16-bit event counter operation (Rising edge/falling edge/both edges selectability) 12-bit MPG (timer 4) 8/16-bit timer counter (timer 2, 3) (Continued) 3 MB89140 Series (Continued) Part number MB89145 Parameter 8-bit serial I/O MB89146 MB89P147 MB89PV140 8 bits LSB first/MSB first selectability One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 4, 8, 16 system clock cycles) 10-bit resolution × 12 channels A/D conversion mode (conversion time of 16.5 µs/8 MHz, and highest gear speed) Sense mode (conversion time of 9.0 µs/8 MHz, and highest gear speed) External activation capable 2 independent channels (edge selection, interrupt vector, source flag) Rising edge/falling edge/both edges selectability Built-in analog noise canceller Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.) Sleep mode, stop mode, watch mode, and subclock mode CMOS 2.7 V to 6.0 V MBM27C256A-20TV MBM27C256A-20CZ 10-bit A/D converter External interrupt Standby mode Process Operating voltage* EPROM for use * : Varies with conditions such as the operating frequency. (See section “s ELECTRICAL CHARACTERISTICS.”) s PACKAGE AND CORRESPONDING PRODUCTS Package DIP-64P-M01 FPT-64P-M06 MDP-64C-P02 MQP-64C-P01 : Available × × MB89145 MB89146 MB89P147 MB89PV140 × × × : Not available Note: For more information about each package, see section “s PACKAGE DIMENSIONS.” 4 MB89140 Series s DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: • On the MB89P147, the program area starts from address 8007H but on the MB89PV140 starts from 8000H. (On the MB89P147, addresses 8000H to 8006H comprise the option setting area, option settings can be read by reading these addresses. On the MB89PV140, addresses 8000H to 8006H could also be used as a program ROM. However, do not use these addresses in order to maintain compatibility of the MB89P147.) • The stack area, etc., is set at the upper limit of the RAM. 2. Current Consumption • In the case of the MB89PV140, add the current consumed by the EPROM which is connected to the top socket. • When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same. (For more information, see section “s ELECTRICAL CHARACTERISTICS.”) 3. Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “s MASK OPTIONS.” Take particular care on the following points: • Options are fixed on the MB89PV140. • On the MB89P147, MB89145, and MB89146, the pull-down resistor option can either be selected for all affected pins, or for no pin; it is not possible to specify the pull-down resistor option for individual pins. 4. Subclock Oscillation Feedback Resistor A built-in oscillation feedback resistor is provided for the subclock oscillator pin on the MB89PV140, but it is not provided for the MB89145, MB89146, MB89P147. Therefor these products should be connected to an external oscillation feedback resistor. 5 MB89140 Series s PIN ASSIGNMENT (Top view) BZ P67 P66 P65 P64 P63 P62 P61 P60 VFDP P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 P43 P42 P41 P40 P23/WDG RST MODA X0 X1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A15/VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS 65 66 67 68 69 70 71 72 73 74 75 76 77 78 92 91 90 89 88 87 86 85 84 83 82 81 80 79 VCC A14 A13 A8 A9 A11 OE A10 CE O8 O7 O6 O5 O4 Each pin inside the dashed line is for the MB89PV140 only. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC AVCC AVSS P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 P10/AN8 P11/AN9 P12/ANA P13/ANB P14 P15 P16 P17/ADST P30/INT0/TRG P31/INT1 P32/SCK P33/SO P34/SI P35/EC P36/PWO1 P37/DTTI P20 P21/PWO0 P22 P70/X0A* P71/X1A* (DIP-64P-M01) (MDP-64C-P02) *: When dual-clock system is selected. 6 MB89140 Series (Top view) P62 P63 P64 P65 P66 P67 BZ VCC AVCC AVSS P00/AN0 P01/AN1 P02/AN2 P61 P60 VFDP P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 P43 P42 P41 P40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 85 86 87 88 89 90 91 92 93 77 76 75 74 73 72 71 70 69 Each pin inside the dashed line is for the MB89PV140 only. 20 21 22 23 24 25 26 27 28 29 30 31 32 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 P10/AN8 P11/AN9 P12/ANA P13/ANB P14 P15 P16 P17/ADST P30/INT0/TRG P31/INT1 P32/SCK P33/SO P34/SI P35/EC • Pin assignment on package top (MB89PV140 only) Pin no. 65 66 67 68 69 70 71 72 Pin name N.C. A15/VPP A12 A7 A6 A5 A4 A3 Pin no. 73 74 75 76 77 78 79 80 Pin name A2 A1 A0 N.C. O1 O2 O3 VSS Pin no. 81 82 83 84 85 86 87 88 Pin name N.C. O4 O5 O6 O7 O8 CE A10 Pin no. 89 90 91 92 93 94 95 96 Pin name OE N.C. A11 A9 A8 A13 A14 VCC N.C.: Internally connected. Do not use. 7 P23/WDG RST MODA X0 X1 VSS P71/X1A* P70/X0A* P22 P21/PWO0 P20 P37/DTTI P36/PWO1 (FPT-64P-M06) (MQP-64C-P01) *: When dual-clock system is selected. 94 95 96 65 66 67 68 84 83 82 81 80 79 78 MB89140 Series s PIN DESCRIPTION Pin no. SDIP*1 MDIP*2 30 31 29 QFP*3 MQFP*4 23 24 22 X0 X1 MODA C Operating mode selection pin Connect directly to VSS in normal operation. This pin functions as the VPP pin in EPROM products. Reset I/O pin This pin is an N-ch open-drain output type with a pull-up resistor, and a hysteresis input type. “L” is output from this pin by an internal reset source when the option is set. The internal circuit is initialized by the input of “L”. This pin is with a noise canceller. General-purpose I/O ports The input is a hysteresis input type and with a built-in noise canceller. Although these ports also serve as an analog input, analog input does not pass through the hysteresis input noise canceller. General-purpose I/O port The input is a hysteresis input type and with a built-in noise canceller. Also serves as an A/D converter external activation. General-purpose I/O ports The input is a hysteresis input type and with a built-in noise canceller. General-purpose I/O ports The input is a hysteresis input type and with a built-in noise canceller. Although these ports also serves as an analog input, analog input does not pass through the hysteresis input noise canceller. General-purpose I/O ports with a built-in noise canceller (single-clock operation) Function as subclock crystal oscillator pins. (dual-clock operation) General-purpose output port General-purpose output port Also serves as a watchdog output. General-purpose output port Also serves as the PWM output for the 8-bit PWM timer. General-purpose output port Pin name Circuit type A Function Main clock crystal oscillator pins 28 21 RST D 54 to 61 47 to 54 P07/AN7 to P00/AN0 G 46 39 P17/ADST J 47 to 49 40 to 42 P16 to P14 J 50 to 53 43 to 46 P13/ANB to P10/AN8 G 34, 33 27, 26 P70/X0A, P71/X1A B/K 35 27 36 37 *1: *2: *3: *4: 28 20 29 30 P22 P23/WDG P21/PWO0 P20 E E E E DIP-64P-M01 MDP-64C-P02 FPT-64P-M06 MQP-64C-P01 (Continued) 8 MB89140 Series Pin no. SDIP MDIP*2 38 *1 QFP*3 MQFP*4 31 Pin name P37/DTTI Circuit type J Function General-purpose I/O port The input is a hysteresis input type and with a built-in noise canceller. When overcurrent is detected, the 12bit MPG output can be inactivated by the external edge input. General-purpose I/O port The input is a hysteresis input type and with a built-in noise canceller. Also serves as a 12-bit MPG output. General-purpose I/O port The input is a hysteresis input type and with a built-in noise canceller. Also serves as the external clock input for the 8/16-bit timer/counter. General-purpose I/O port The input is a hysteresis input type and with a built-in noise canceller. Also serves as the serial data input for the 8-bit serial interface. General-purpose I/O port The input is a hysteresis input type and with a built-in noise canceller. Also serves as the serial data output for the 8-bit serial interface. General-purpose I/O port The input is a hysteresis input type and with a built-in noise canceller. Also serves as the serial transfer clock for the 8-bit serial interface. General-purpose I/O port The output is an N-ch open-drain type. The input is a hysteresis input type and with a built-in noise canceller. Also serves as an external interrupt. The interrupt input is also a hysteresis input type and with a built-in noise canceller. General-purpose I/O port The input is a hysteresis input type and with a built-in noise canceller. Also serve as an external interrupt or as an MPG trigger input. The interrupt input is also a hysteresis input type and with a built-in noise canceller. Buzzer output-only pin P-ch high-voltage open-drain output port Low-current P-ch high-voltage open-drain output ports Products with and without a built-in pull-down resistor between these pins and the VFDP pin are provided. 39 32 P36/PWO1 J 40 33 P35/EC J 41 34 P34/SI J 42 35 P33/SO J 43 36 P32/SCK J 44 37 P31/INT1 F 45 38 P30/INT0/TRG J 1 19 to 26, 11 to 18 *1: *2: *3: *4: 58 12 to 19, 4 to 11 BZ P47 to P40, P57 to P50 I H DIP-64P-M01 MDP-64C-P02 FPT-64P-M06 MQP-64C-P01 (Continued) 9 MB89140 Series (Continued) Pin no. SDIP*1 MDIP*2 2 to 9 QFP*3 MQFP*4 59 to 64 1, 2 Pin name P67 to P60 Circuit type H Function Heavy-current P-ch high-voltage open-drain output port Products with and without a built-in pull-down resistor between these pins and the VFDP pin are provided. Voltage supply pin for connection to a pull-down resistor for ports 4, 5, and 6. In products without a built-in pull-down resistor and in the MB89PV140, this pin should be left open. Power supply pin Power supply (GND) pin A/D converter power supply pin Use this pin at the same voltage as VCC. A/D converter power supply (GND) pin Use this pin at the same voltage as VSS. 10 3 VFDP — 64 32 63 62 *1: *2: *3: *4: 57 25 56 55 VCC VSS AVCC AVSS — — — — DIP-64P-M01 MDP-64C-P02 FPT-64P-M06 MQP-64C-P01 10 MB89140 Series • External EPROM pins (MB89PV140 only) Pin no. SDIP MDIP*4 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 — *3 QFP*1 MQFP*2 66 67 68 69 70 71 72 73 74 75 77 78 79 80 82 83 84 85 86 87 88 89 91 92 93 94 95 96 65 76 81 90 Pin name A15/VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS O4 O5 O6 O7 O8 CE A10 OE A11 A9 A8 A13 A14 VCC N.C. I/O O O “H” level output pin Address output pins Function I Data input pins O I Power supply (GND) pin Data input pins O O O O ROM chip enable pin Outputs “H” during standby. Address output pin ROM output enable pin Outputs “L” at all times. Address output pins O — EPROM power supply pin Internally connected pins Be sure to leave them open. *1: *2: *3: *4: DIP-64P-M01 MDP-64C-P02 FPT-64P-M06 MQP-64C-P01 11 MB89140 Series s I/O CIRCUIT TYPE Type A X1 Circuit Remarks • Crystal or ceramic oscillation type (main clock) • At an oscillation feedback resistor of approximately 1 MΩ/5.0 V X0 Standby control signal B X1A X0A • Crystal or ceramic oscillation type (subclock) • At an oscillation feedback resistor of approximately 4.5 MΩ/5.0 V (The built-in feedback resistor is not provided except on the MB89PV140-102.) Standby control signal C D R P-ch • At an output pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V • CMOS hysteresis input (with noise canceller) N-ch Hysteresis input (with noise canceller) E P-ch • CMOS output N-ch F N-ch • N-ch open-drain output • CMOS hysteresis input (with noise canceller) Hysteresis input (with noise canceller) (Continued) 12 MB89140 Series (Continued) Type G P-ch Circuit Remarks • CMOS output • CMOS hysteresis input (with noise canceller, except analog input) N-ch Port Hysteresis input (with noise canceller) Analog input H P-ch • P-ch high-voltage open-drain output • Products with and without a built-in pull-down resistor are provided (except the MB89PV140). VFDP I P-ch • P-ch high-voltage open-drain output J P-ch • CMOS output • CMOS hysteresis input (with noise canceller) • Pull-up resistor optional N-ch Port Hysteresis input (with noise canceller) K Port Hysteresis input (with noise canceller) • CMOS hysteresis input (with noise canceller) 13 MB89140 Series s HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “s ELECTRICAL CHARACTERISTICS” is applied between VCC and VSS. (However, up to 7.0 V can be applied to P31/INT pin, regardless of VCC) When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 4. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 Hz to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 5. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode. 14 MB89140 Series s PROGRAMMING TO THE EPROM ON THE MB89P147 The MB89P147 is an OTPROM version of the MB89140 series. 1. Features • 32-Kbyte PROM on chip • Options can be set using the EPROM programmer. • Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in each mode such as 32-Kbyte PROM, option area is diagrammed below. Address 0000H I/O 0080H RAM 0480H Not available 8000H Not available 8007H 0007H 0000H Option area Single chip EPROM mode (Corresponding addresses on the EPROM programmer) PROM 32 KB EPROM 32 KB FFFFH 7FFFH 3. Programming to the EPROM In EPROM mode, the MB89P147 functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. When the operating ROM area for a single chip is 32 Kbytes (8007H to FFFFH) the PROM can be programmed as follows: • Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0007H to 7FFFH (note that addresses 8007H to FFFFH while operating as a single chip assign to 0007H to 7FFFH in EPROM mode). Load option data into addresses 0000H to 0006H of the EPROM programmer. (For information about each corresponding option, see “5. Setting OTPROM Options.” in section “s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE” ) (3) Program to 0000H to 7FFFH with the EPROM programmer. 15 MB89140 Series 4. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program. Program, verify Aging +150 ˚C, 48 h Data verification Assembly 5. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 6. EPROM Programmer Socket Adapter Package DIP-64P-M01 FPT-64P-M06 Compatible socket adapter ROM-64SD-28DP-8L4 ROM-64QF-28DP-8L4 Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 16 MB89140 Series s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C256A-20TV, MBM27C256A-20CZ 2. Programming Socket Adapter To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package LCC-32 (Rectangle) LCC-32 (Square) Adapter socket part number ROM-32LC-28DP-YG ROM-32LC-28DP-S Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 3. Memory Space Memory space in each mode, such as 32-Kbyte PROM, option area is diagrammed below. Address 0000H Single chip Corresponding addresses on the EPROM programmer I/O 0080H RAM 0480H Not available 8000H Not available 8007H 0007H 0000H Option area PROM 32 KB EPROM 32 KB FFFFH 7FFFH 4. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0007H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer. 17 MB89140 Series 5. Setting OTPROM Options The programming procedure is the same as that for the PROM. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map: • OTPROM option bit map Bit 7 Vacancy 8000H (0000H) Readable and writable Readable and writable Readable and writable Bit 6 Vacancy Bit 5 Vacancy Bit 4 Single/dualclock system 1: Dual clock 0: Single clock Bit 3 Reset pin output 1: Yes 0: No Vacancy Readable and writable Bit 2 Power-on reset 1: Yes 0: No Vacancy Readable and writable Bit 1 Bit 0 Reserved Reserved (Write 1 bit (Write 1 bit to this bit.) to this bit.) Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable 8001H (0001H) P17 Pull-up 1: No 0: Yes P37 Pull-up 1: No 0: Yes Vacancy P16 Pull-up 1: No 0: Yes P36 Pull-up 1: No 0: Yes Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable P15 Pull-up 1: No 0: Yes P35 Pull-up 1: No 0: Yes Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable P14 Pull-up 1: No 0: Yes P34 Pull-up 1: No 0: Yes Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable 8002H (0002H) P33 Pull-up 1: No 0: Yes Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable P32 Pull-up 1: No 0: Yes Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable Vacancy Readable and writable 8003H (0003H) Readable and writable Vacancy 8004H (0004H) Readable and writable Vacancy 8005H (0005H) Readable and writable Vacancy 8006H (0006H) Readable and writable Notes: • Set each bit to 1 to erase. • Do not write 0 to the vacant bit. The read value of the vacant bit is 1, unless 0 is written to it. • The parenthesized addresses are the corresponding addresses on the EPROM programmer. 18 MB89140 Series s BLOCK DIAGRAM X0 X1 Main clock oscillator Time-base timer Clock controller Buzzer 8 BZ Port 7 CMOS input port CMOS output port Port 2 Internal bus P70, P71 X0A X1A Subclock oscillator (32.768 kHz) High-voltage port 6 P60 to P67 High-voltage port 5 8 P50 to P57 P23/WDG P22 P21/PWO0 P20 High-voltage port 4 8-bit PWM timer 8 P40 to P47 VFDP P32/SCK P33/SO P34/SI MODA Mode control 8-bit serial interface AVCC 10-bit A/D converter AVSS 4 P14 to P16 4 P13/ANB to P10/AN8 8 P07/AN7 to P00/AN0 Port 0 and port 1 P17/ADST Port 3 12-bit MPG P30/TRG/INT0 P37/DTTI P36/PWO1 CMOS I/O port 8/16-bit timer/counter P35/EC RAM External interrupt P31/INT1 (N-ch open-drain) F2MC-8L CPU CMOS I/O port Reset circuit ROM RST Other pins VCC, VSS 19 MB89140 Series s CPU CORE 1. Memory Space The microcontrollers of the MB89140 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89140 series is structured as illustrated below. Memory Space MB89PV140 0000H I/O 0080H 0080H 0000H I/O 0080H MB89145 0000H I/O 0080H MB89146 0000H I/O MB89P147 RAM 0100H Register 0200H 0200H 0280H 0100H RAM 0100H Register 0200H RAM 0100H Register 0200H RAM Register 0380H 0480H Not available Not available 8000H * 8006H A000H C000H 8006H Not available 8000H * 0480H Not available External ROM 32 KB ROM 16 KB ROM 24 KB PROM 32 KB FFFFH FFFFH FFFFH FFFFH *: Since addresses 8000H to 8005H for the MB89P147 comprise an option area, do not use this area for the MB89PV140. 20 MB89140 Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): Accumulator (A): Temporary accumulator (T): Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS): A 16-bit register for indicating instruction storage positions A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register for index modification A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area A 16-bit register for storing a register pointer, a condition code 16 bits PC A T IX EP SP PS : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status Initial value FFFDH Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, 0 = 11 Other bits are undefined. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) Structure of the Program Status Register 15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 3 N 2 Z 1 V 0 C Vacancy Vacancy Vacancy IL1, 0 RP CCR 21 MB89140 Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area RP Lower OP codes b1 ↓ b0 ↓ “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: IL1, 0: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 IL0 0 1 0 1 Interrupt level 1 2 3 High-low High Low = no interrupt N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: V-flag: Set when an arithmetic operation results in 0. Cleared otherwise. Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. 22 MB89140 Series The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 32 banks can be used in the MB89140 series. The bank currently in use is indicated by the register bank pointer (RP). Register Bank Configuration This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area 23 MB89140 Series s I/O MAP Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH (W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) COMR CNTR T3CR T2CR T3DR T2DR SMR SDR ADC1 ADC2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) (R) SYCC STBC WDTC TBCR WPCR PDR3 DDR3 BUZR EIC PDR4 PDR5 PDR6 PDR7 Read/write (R/W) (W) (R/W) (W) (R/W) Register name PDR0 DDR0 PDR1 DDR1 PDR2 Register description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register Port 2 data register Vacancy Vacancy System clock control register Standby control register Watchdog timer control register Time-base timer control register Watch prescaler control register Port 3 data register Port 3 data direction register Buzzer register External interrupt control register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Vacancy Vacancy 8-bit PWM timer compare register 8-bit PWM timer control register Timer 3 control register Timer 2 control register Timer 3 data register Timer 2 data register Serial mode register Serial data register A/D converter control register 1 A/D converter control register 2 (Continued) 24 MB89140 Series (Continued) Address 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H to 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH Note: Do not use vacancies. (W) (W) (W) ILR1 ILR2 ILR3 Read/write (R/W) (R/W) (W) (W) (R/W) (R/W) (W) (W) (W) (W) Register name ADDH ADDL PCR0 PCR1 MCNT INTSTR CMCLBR (H) CMCLBR (L) OUTCBR (H) OUTCBR (L) Register description A/D converter data register (H) A/D converter data register (L) Port input control register 0 Port input control register 1 MPG control register MPG interrupt status register MPG compare clear buffer register H MPG compare clear buffer register L MPG output buffer register H MPG output buffer register L Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Vacancy 25 MB89140 Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Power supply voltage I/O voltage “H” level total average output current Symbol Rating Min. Max. VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS + 7.0 VSS + 7.0 VCC + 0.3 Unit Remarks VCC AVCC VIO1 VIO2 ΣIOH 7 –120 –12 –20 –36 –6 V V V V mA mA mA mA mA *2 — — “H” level maximum output current IOH — — — “H” level average output current IOHAV — — –10 –18 150 12 6 500 +85 +150 mA mA mA mA mA mW °C °C “L” level total average output current “L” level maximum output current “L” level average output current Power consumption Operating temperature Storage temperature ΣIOLAV IOL IOLAV PD TA Tstg — — — — –40 –55 Except P31 P31 Average value (operating current × operating rate) P00 to P07, P10 to P17, P20 to P23, P30, P32 to P37 P40 to P47, P50 to P57 P60 to P67, BZ P00 to P07, P10 to P17, P20 to P23, P30, P32 to P37 Average value (operating current × operating rate)*1 P40 to P47, P50 to P57 Average value (operating current × operating rate)*1 P60 to P67, BZ Average value (operating current × operating rate)*1 Average value (operating current × operating rate)*1 P00 to P07, P10 to P17, P20 to P23, P30 to P37 P00 to P07, P10 to P17, P20 to P23, P30 to P37 Average value (operating current × operating rate)*1 *1: The total average output current is defined as the average current that flows through all of the relevant pins in a 100 ms period. The output peak current is defined as the peak value of any one of the relevant pins. The average output current is defined as the average current that flows through any one of the relevant pins in a 100 ms period. *2: Use AVCC and VCC set at the same voltage. Take care so that AVCC does not exceed VCC, such as when power is turned on. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 26 MB89140 Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Symbol Value Min. 2.7* Max. 6.0* 6.0 6.0 +85 Unit V V V V °C Remarks Normal operation assurance range* In watch mode or subclock operation (Only for the MB89P147, the minimum value is 2.7 V.) Retains the RAM state in stop mode Power supply voltage VCC AVCC VFDP 2.2 1.5 VCC – 40 VCC + 0.3 –40 Operating temperature TA * : These values vary with the operating frequency and analog assurance range. See Figure 1 and “5. A/D Converter Electrical Characteristics.” 6 Operating voltage (V) 5 Operation assurance range 4 3 2 1 2 3 4 5 6 7 8 Main clock operating frequency (at an instruction cycle of 4/FCH) (MHz) 2.0 0.8 0.5 Minimum execution time (instruction cycle) (µs) Figure 1 Operating Voltage vs. Main Clock Operating Frequency Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH. Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 27 MB89140 Series 3. DC Characteristics (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin P00 to P07, Condition Value Min. Typ. Max. Unit Remarks “H” level input voltage P10 to P17, VIHS P30 to P37, P70, P71, X0, X1, RST, MODA P00 to P07, P10 to P17, 0.7 VCC — VSS – 0.3 — VCC + 0.3 V Hysteresis input “L” level input voltage VILS P30 to P37, P70, P71, X0, X1, RST, MODA — 0.2 VCC V Hysteresis input VOH1 “H” level output voltage VOH2 VOH3 VOL1 VOL2 P00 to P07, P10 to P17, P20 to P23, P30, P32 to P37 P40 to P47, P50 to P57 P60 to P67, BZ P00 to P07, P10 to P17, P20 to P23, P30, P32 to P37 RST P00 to P07, P10 to P17, P30 to P37, P70, P71, MODA P14 to P17, P32 to P37 P40 to P47, P50 to P57 P60 to P67, BZ RST P14 to P17, P32 to P37 P40 to P47, P50 to P57, P60 to P67 IOH = –2.0 mA 2.4 — — V IOH = –10 mA IOH = –18 mA IOL = 1.8 mA IOL = 4.0 mA 3.0 3.0 — — — — — — — — 0.4 0.6 V V V V Without pull-up “L” level output voltage Input leakage current ILI1 0.45 V < VI < VCC — — ±5 µA resistor for P14 to P17 and P32 to P37 ILI2 ILO1 ILO2 RPULU VI = 0.0 V VI = VFDP = VCC – 40 V VI = VFDP = VCC – 40 V VI = 0.0 V –200 — — 25 –100 — — 50 –50 –10 –20 100 µA µA µA kΩ With pull-up resistor Output leakage current Pull-up resistance Pull-down resistance With pull-up resistor With pull-down resistor optional RPULD VOH = 5.0 V 50 100 150 kΩ (Continued) 28 MB89140 Series (Continued) Parameter Symbol (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Pin Condition FCH = 8 MHz VCC = 5.0 V tinst*2 = 0.5 µs Output open FCH = 8 MHz VCC = 3.2 V tinst*2 = 8.0 µs Output open Sleep mode FCH = 8 MHz VCC = 5.0 V tinst*2 = 0.5 µs FCH = 8 MHz VCC = 3.2 V tinst*2 = 8.0 µs Value Min. — — — Typ. 9 1.5 2.5 Max. 15 2 5.0 Unit Remarks ICC1 mA mA mA MB89P147 ICC2 ICCS1 — 3 7 mA ICCS2 VCC — — — — 1 50 1 25 1.5 150 3 50 mA µA mA MB89P147 µA Power supply current*1 ICCL Subclock mode FCL = 32.768 kHz VCC = 3.0 V Subclock sleep mode ICCLS FCL = 32.768 kHz VCC = 3.0 V Watch mode FCL = 32.768 kHz VCC = 3.0 V Stop mode TA = +25°C FCH = 8 MHz, when A/D conversion is activated ICCT ICCH IA AVCC IAH Other than AVCC, — — — 3 — 1.5 15 10 4 µA µA mA µA TA = +25°C, when A/D conversion is stopped — 1 5 Input capacitance CIN AVSS, VCC, and VSS f = 1 MHz — 10 — pF *1: The power supply current is measured at the external clock. *2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” Note: FCH indicates the main clock oscillation frequency. When FCH = 8 MHz, the 4/FCH execution time is 0.5 µs, and the 64/FCH execution time is 8 µs. 29 MB89140 Series 4. AC Characteristics (1) Reset Timing (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter RST “L” pulse width RST noise limit width Symbol tZLZH tZLNC Condition — Value Min. 48 tXCYL 30 Typ. — 50 Max. — 80 Unit ns ns Remarks Note: TXCYL is the oscillation cycle (1/FCH) to input to the X0 pin. tZLZH tZLNC RST 0.2 VCC 0.2 VCC (2) Power-on Reset (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Power supply rising time Power supply cut-off time Symbol tR tOFF Condition — Value Min. — 1 Max. 50 — Unit ms ms Remarks Power-on reset function only Due to repeated operations Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR 2.0 V 0.2 V 0.2 V tOFF VCC 0.2 V 30 MB89140 Series (3) Clock Timing (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Clock frequency Clock cycle time Symbol FCH FCL tXCYL tLXCYL PWH PWL PWHL PWLL tCR tCF Pin X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0, X0A Condition Value Min. 2 — 125 — Typ. — 32.768 — 30.5 — 15.2 — Max. 8 — 500 — — — 10 Unit MHz kHz ns µs ns Remarks — 30 — — Input clock pulse width External clock µs ns External clock Input clock rising/falling time X0 and X1 Timing and Conditions tXCYL PWH tCR 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tCF PWL X0 0.2 VCC Main Clock Conditions When a crystal or ceramic resonator is used When an external clock is used X0 X1 X0 X1 Open C0 C1 31 MB89140 Series X0A and X1A Timing and Conditions tLXCYL PWHL tCR 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tCF PWLL X0A 0.2 VCC Subclock Conditions MB89PV140 When a crystal or ceramic resonator is used RF = approx. 2 MΩ X0A X0A X1A RD X1A Open When an external clock is used C0 C1 Mask ROM products and MB89P147 When a crystal or ceramic resonator is used When an external clock is used X0A X1A X0A X1A Open RF RD C0 C1 Note: The subclock oscillator feedback resistor is connected externally in dual-clock mask ROM products and in the MB89P147. (The subclock oscillator feedback resistor is connected internally in the MB89PV140-102.) (4) Instruction Cycle Parameter Instruction cycle (minimum execution time) Symbol Value (typical) 4/FCH, 8/FCH, 16/FCH, 64/FCH tinst 2/FCL µs Unit µs Remarks (4/FCH) tinst = 0.5 µs when operating at FCH = 8 MHz tinst = 61.036 µs when operating at FCL = 32.768 kHz 32 MB89140 Series (5) Serial I/O Timing (AVCC = VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Serial clock cycle time SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin SCK SCK, SO SI, SCK SCK, SI SCK SCK SCK, SO SI, SCK SCK, SI Condition Value Min. 2 tinst* –200 1/2 tinst* 1/2 tinst* 1 tinst* 1 tinst* Max. — 200 — — — — 200 — — Unit µs ns µs µs µs µs ns µs µs Remarks Internal shift clock mode External shift clock mode 0 1/2 tinst* 1/2 tinst* * : For information on tinst, see “(4) Instruction Cycle.” Internal Shift Clock Mode tSCYC 2.4 V 0.8 V tSLOV 2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.3 VCC 0.8 VCC 0.3 VCC 0.8 V SCK SO SI External Shift Clock Mode tSLSH 0.8 VCC 0.2 VCC 0.2 VCC tSLOV 2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.3 VCC 0.8 VCC 0.3 VCC tSHSL 0.8 VCC SCK SO SI 33 MB89140 Series (6) Peripheral Input Timing (AVCC = VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin TRG, DTTI ADST, EC INT0 , INT1 TRG, DTTI ADST, EC INT0 , INT1 Condition Value Min. 2 tinst* Max. — Unit µs Remarks Peripheral input “H” pulse width 1 tILIH1 — Peripheral input “L” pulse width 1 tIHIL1 — 2 tinst* — µs * : For information on tinst, see “(4) Instruction Cycle.” (7) Peripheral Input Noise Limit Width (AVCC = VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Peripheral input “H” level noise limit width 1 Peripheral input “L” level noise limit width 1 Interrupt “H” level noise limit width 2 Interrupt “L” level noise limit width 2 Symbol tIHNC1 tILNC1 tIHNC2 tILNC2 Condition All inputs except INT1 and INT0 All inputs except INT1 and INT0 INT1, INT0 INT1, INT0 Value Min. 7 15 7 15 30 50 30 50 Typ. 15 30 15 30 50 100 50 100 Max. 30 60 30 60 100 250 100 250 Unit ns ns ns ns ns ns ns ns Remarks MB89P147/PV140 Except MB89P147/PV140 MB89P147/PV140 Except MB89P147/PV140 MB89P147/PV140 Except MB89P147/PV140 MB89P147/PV140 Except MB89P147/PV140 tIHIL1 tILIH1 0.8 VCC 0.8 VCC TRG DTTI ADST INT0, INT1 EC 0.2 VCC 0.2 VCC tILNC1 tILNC2 tIHNC1 tIHNC2 0.8 VCC 0.8 VCC P00 to P07, P01 to P17 P30 to P37, P70, P71 TRG, SCK, SI, EC, DTTI, ADST INT1, INT0 0.2 VCC 0.2 VCC 34 MB89140 Series 5. A/D Converter Electrical Characteristics (AVCC = VCC = 5.0 V+10%, FCH = 8 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Interchannel disparity A/D mode conversion time Symbol Pin Value Condition Min. — — — AVCC = VCC = 5.0 V Typ. — — — — AVSS + 0.5 LSB Max. 10 ±3.0 ±2.0 ±1.5 AVSS + 2.5 LSB Unit bit LSB LSB LSB mV mV LSB tinst* µA V Remarks — — — — VOT VFST AN0 to ANB AN0 to ANB — — — AVSS – 1.5 LSB AVCC – 3.5 LSB AVCC – 1.5 LSB AVCC + 0.5 LSB — 33 — 0.0 — — — — 4 — 10 AVCC — — AN0 to ANB AN0 to ANB At 8-MHz oscillation AVCC = VCC = 5.0 V Analog port input current IAIN Analog input voltage — — * : For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” Notes: • The smaller AVCC, the greater the error would become relatively. • The output impedance of the external circuit connected to an analog input block should be no more than several kΩ. If the output impedance is too high, the analog voltage sampling time might be insufficient. Sample hold circuit R ≤ 10 kΩ is recommended. AN C 60 pF Comparator R 3 kΩ Analog channel selector When R > 10 kΩ, it is recommended to connect an external capacitor of approx. 0.1 µF. Close for approx. 15 to 72 instruction cycles after activating A/D conversion. (The close time depends on the register settings.) 35 MB89140 Series (1) A/D Glossary • Resolution Analog changes that are identifiable with the A/D converter • Linearity error The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics • Differential linearity error The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value • Total error The difference between theoretical and actual values This error is caused by the zero transition error, full-scale transition error, linearity error, quantization error and noise. Theoretical I/O characteristics 3FF 3FE 3FD Digital output 1.5 LSB Digital output VFST 3FF 3FE 3FD Total error Actual conversion value {1 LSB × N + 0.5 LSB} 004 003 002 001 0.5 LSB AVSS Analog input AVR 004 VNT 003 Actual conversion value Theoretical value 001 VOT 1 LSB 002 AVSS Analog input AVR 1 LSB = VFST – VOT 1022 (V) Total error for digital output N = VNT – {1 LSB × N + 0.5 LSB} 1 LSB (Continued) 36 MB89140 Series (Continued) Zero transition error 004 Actual conversion value 003 Digital output Digital output 3FE 3FF Full-scale transition error Theoretical value Actual conversion value 002 Actual conversion value 001 VFST (measured value) 3FD Actual conversion value 3FC VOT (measured value) AVSS Analog input Analog input AVR Linearity error 3FF 3FE {1 LSB × N + VOT} 3FD Digital output Digital output VFST (measured value) N Differential linearity error Actual conversion value Theoretical value N+1 Actual conversion value V(N + 1) T VNT 004 003 002 Actual conversion value Theoretical value N–1 VNT Actual conversion value 001 VOT (measured value) AVSS Analog input AVR N–2 AVSS Analog input AVR Linearity error for digital output N = VNT – {1 LSB × N + VOT} 1 LSB V(N + 1) T – VNT Differential linearity error for digital output N = –1 1 LSB 37 MB89140 Series s EXAMPLE CHARACTERISTICS (1) “L” Level Output Voltage (2) “H” Level Output Voltage VOL vs. IOL VOL (V) TA = +25°C 0.5 VCC = 3.0 V 0.4 0.3 0.2 0.1 0.0 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V VCC = 2.5 V VCC – VOH (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) 0.0 0.0 –0.5 VCC – VOH vs. IOH TA = +25°C VCC = 2.5 V VCC = 3.0 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V –1.0 –1.5 –2.0 –2.5 –3.0 IOH (mA) (3) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input) CMOS hysteresis input VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 3 4 5 6 7 VCC (V) VIHS VILS TA = +25°C VIHS: Threshold when input voltage in hysteresis characteristics is set to “H” level VILS: Threshold when input voltage in hysteresis characteristics is set to “L” level 38 MB89140 Series (4) Power Supply Current (External Clock) ICC1 vs. VCC, ICC2 vs. VCC ICC (mA) 16 14 12 10 8 6 4 Divide by 64 (ICC2) 2 0 2.0 3.0 4.0 5.0 6.0 7.0 VCC (V) 0 2.0 3.0 1.0 2.0 FCH = 8 MHz TA = +25°C Divide by 4 (ICC1) 3.0 ICCS (mA) 4.0 ICCS1 vs. VCC, ICCS2 vs. VCC FCH = 8 MHz TA = +25°C Divide by 4 (ICCS1) Divide by 64 (ICCS2) 4.0 5.0 6.0 7.0 VCC (V) ICCL (µA) 200 180 160 140 120 100 80 60 40 20 0 2.0 3.0 ICCL vs. VCC TA = +25°C ICCLS (µA) 50 ICCLS vs. VCC TA = +25°C 40 30 20 10 0 4.0 5.0 6.0 7.0 VCC (V) 2.0 3.0 4.0 5.0 6.0 7.0 VCC (V) (Continued) 39 MB89140 Series (Continued) ICCT (µA) 18 16 14 12 10 8 6 4 2 0 2.0 3.0 ICCT vs. VCC ICCH (µA) 1.8 TA = +25°C 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ICCH vs. VCC TA = +25°C 4.0 5.0 6.0 7.0 VCC (V) 2.0 3.0 4.0 5.0 6.0 7.0 VCC (V) (5) Pull-up Resistance RPULL (kΩ) 1,000 500 RPULL vs. VCC 100 50 TA = +85°C TA = +25°C TA = –40°C 10 1 2 3 4 5 6 7 VCC (V) 40 MB89140 Series s MASK OPTIONS No. Power-on reset MB89PV140 MB89PV140 -101 -102 With power-on reset Without power-on reset Reset pin output Fixed to with power-on reset MB89145V1 MB89146V1 MB89145V2 MB89146V2 MB89P147V1 MB89P147V2 1 Specify when ordering masking Set with EPROM programmer 2 With reset output Without reset output Clock mode selection Fixed to with power-on reset Specify when ordering masking Set with EPROM programmer 3 Single-clock mode Dual-clock mode Pull-up resistors Single clock Dual clock Specify when ordering masking Set with EPROM programmer 4 P14 to P17 P32 to P37 Pull-down resistors Fixed to without pull-up resistor Specify when ordering masking (specify by pin) Set with EPROM programmer (specify by pin) 5 P47 to P40 P57 to P50 P67 to P60 Fixed to without pull-up resistor Without pulldown resistor All pins with pull-down resistor Without pulldown resistor All pins with pull-down resistor s ORDERING INFORMATION Part number MB89145V1P-SH MB89145V2P-SH MB89146V1P-SH MB89146V2P-SH MB89P147V1P-SH MB89P147V2P-SH MB89145V1PF MB89145V2PF MB89146V1PF MB89146V2PF MB89P147V1PF MB89P147V2PF MB89PV140C-101-ES-SH MB89PV140C-102-ES-SH MB89PV140CF-101-ES MB89PV140CF-102-ES Package Remarks 64-pin Plastic SH-DIP (DIP-64P-M01) 64-pin Plastic QFP (FPT-64P-M06) 64-pin Ceramic MDIP (MDP-64C-P02) 64-pin Ceramic MQFP (MQP-64C-P01) 41 MB89140 Series s PACKAGE DIMENSIONS 64-pin Plastic SH-DIP (DIP-64P-M01) 58.00 –0.55 2.283 –.022 +0.22 +.009 INDEX-1 17.00±0.25 (.669±.010) INDEX-2 4.95 –0.20 .195 –.008 +0.70 +.028 0.70 –0.19 .028 –.007 +0.50 +.020 3.30 –0.30 .130 +0.20 +.008 –.012 +0.40 –0.20 +.016 –.008 0.27±0.10 (.011±.004) 1.378 .0543 1.778(.0700) 0.47±0.10 (.019±.004) 0.25(.010) M 19.05(.750) 0~15° 1.00 –0 +0.50 +.020 .039 –.0 C 2001 FUJITSU LIMITED D64001S-c-4-5 Dimensions in mm (inches) 64-pin Plastic QFP (FPT-64P-M06) 24.70±0.40(.972±.016) 20.00±0.20(.787±.008) 0.17±0.06 (.007±.002) 51 33 52 32 18.70±0.40 (.736±.016) 14.00±0.20 (.551±.008) INDEX Details of "A" part 3.00 –0.20 .118 –.008 20 +0.35 +.014 (Mounting height) 64 0~8° 1 19 1.00(.039) 0.42±0.08 (.017±.003) 0.20(.008) M 0.25 –0.20 1.20±0.20 (.047±.008) +0.15 +.006 .010 –.008 (Stand off) "A" 0.10(.004) C 2001 FUJITSU LIMITED F64013S-c-4-4 Dimensions in mm (inches) 42 MB89140 Series 64-pin Ceramic MDIP (MDP-64C-P02) 56.90±0.64 (2.240±.025) 0°~9° 15.24(.600) TYP 18.75±0.30 (.738±.012) 19.05±0.30 (.750±.012) INDEX AREA 2.54±0.25 (.100±.010) 33.02(1.300)REF 0.25±0.05 (.010±.002) 10.16(.400)MAX 1.27±0.25 (.050±.010) 1.778±0.25 (.070±.010) 0.46 –0.08 +.005 .018 –.003 55.12(2.170)REF +0.13 0.90±0.13 (.035±.005) 3.43±0.38 (.135±.015) C 1994 FUJITSU LIMITED M64002SC-1-4 Dimensions in mm (inches) 64-pin Ceramic MQFP (MQP-64C-P01) INDEX AREA 18.70(.736)TYP 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) 12.00(.472)TYP +0.40 +.016 –.008 1.20 –0.20 .047 1.00±0.25 (.039±.010) 1.00±0.25 (.039±.010) 1.27±0.13 (.050±.005) 22.30±0.33 (.878±.013) 24.70(.972) TYP 0.30(.012) TYP 18.12±0.20 12.02(.473) (.713±.008) TYP 10.16(.400) 14.22(.560) TYP TYP 18.00(.709) TYP 1.27±0.13 (.050±.005) 0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP 0.40±0.10 (.016±.004) 0.40±0.10 (.016±.004) 1.20 –0.20 .047 –.008 +0.40 +.016 0.50(.020)TYP 10.82(.426) 0.15±0.05 MAX (.006±.002) Dimensions in mm (inches) C 1994 FUJITSU LIMITED M64004SC-1-3 43 MB89140 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0105 © FUJITSU LIMITED Printed in Japan