MB89538CPFM

FUJITSU SEMICONDUCTOR DATA SHEET DS07-12548-3E 8-bit Original Microcontroller CMOS F2MC-8L MB89530 Series MB89537/537C/538/538C MB89F538L/P538/PV530 s DESCRIPTION The MB89530 series is a one-chip microcontroller featuring the F2MC-8L core supporting low-voltage and highspeed operation. Built-in peripheral functions include timers, serial interface, A/D converter, and external interrupt. This product is an ideal general-purpose one-chip microcontroller for a wide variety of applications from household to industrial equipment, as well as use in portable devices. s FEATURES • Wide range of package options • QFP package (1mm pitch) • Two types of LQFP packages (0.5mm pitch, 0.65mm pitch) • SH-DIP package • BCC package (0.5mm pitch) • Low voltage, high-speed operating capability • Minimum instruction execution time 0.32 µs (at base oscillator 12.5MHz) • F2MC-8L CPU Core • Instruction set optimized for controller operation • Multiplication/division instructions • 16-bit calculation • Branching instructions with bit testing • Bit operation instructions, etc. • Five timer systems • 8-bit PWM timer with 2 channels (usable as either interval timer of PWM timer) • Pulse width count timer (supports continuous measurement or remote control receiving applications) • 16-bit timer counter • 21-bit time base timer • Watch prescaler (17-bit) • UART • Synchronous or asynchronous operation, switchable • 2 serial interfaces (serial I/O) • Selection of transfer direction (specify MSB first or LSB first) for communication with a variety of devices (Continued) MB89530 Series (Continued) • 10-bit A/D converter (8 channels) • External clock input for startup support (except for MB89F538L) • Time base timer output for startup support • Pulse generators (PPG) with 2-program capability • 6-bit PPG with selection of pulse width and pulse period • 12-bit PPG (2 channels) with selection of pulse width and pulse period • I2C interface circuits • External interrupt 1 (single-clock : 4 channels, dual-clock : 3 channels) • 4 or 3 independent inputs, release enabled from standby mode (includes edge detection function) • External interrupt 2 (except for MB89F538L : 8 channels, MB89F538L : 7 channels) • 8 or 7 independent inputs, release enabled form standby mode (includes level edge detection function) • Standby modes (low power consumption modes) • Stop mode (oscillator stops, virtually no power consumed) • Sleep mode (CPU stops, power consumption reduced to one-third) • Sub clock mode • Watch mode • Watchdog timer reset • I/O ports • Maximum port single-clock : except for MB89F538L : 53 MB89F538L : 52 dual-clock : except for MB89F538L : 51 MB89F538L : 50 • 38 general-purpose I/O ports (CMOS) (MB89F538L : 37) • 2 general-purpose I/O ports (N-ch open drain) • 8 general-purpose output ports (N-ch open drain) • General-purpose input ports(CMOS)single-clock : except for MB89F538L : 5 dual-clock : except for MB89F538L : 3 2 MB89530 Series s PACKAGES 64-pin, Plastic SH-DIP 64-pin, Plastic LQFP 64-pin, Plastic QFP (DIP-64P-M01) 64-pin, Plastic LQFP (FPT-64P-M03) 64-pin, Ceramic MDIP (FPT-64P-M06) 64-pin, Ceramic MQFP (FPT-64P-M09) (MDP-64C-P02) 64-pin, Plastic BCC (MQP-64C-P01) (LCC-64P-M19) (LCC-64P-M16) 3 MB89530 Series s PRODUCT LINEUP Part number Parameter Type MB89537/ 537C MB89538/ 538C MB89F538L FLASH 48 K × 8-bit (built-in FLASH memory) (write from general purpose EPROM writer) MB89P538 One-time programmable 48 K × 8-bit (built-in ROM) (write from general purpose EPROM writer) MB89PV530 Evaluation Mass produced (Mask ROM) ROM capacity 32 K × 8-bit (built-in ROM) 48 K × 8-bit (built-in ROM) 48 K × 8-bit (external ROM) *2 RAM capacity Operating voltage 1 K × 8-bit 2.2 V to 3.6 V*1 (MB89537/538/ 537C/538C) Basic instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time Minimum interrupt processing time Input ports 2 K × 8-bit 2.4 V to 3.6 V*1 : 136 : 8-bits : 1 bit to 3 bits : 1, 8, 16-bits : 0.32 µs / 12.5 MHz : 2.88 µs / 12.5 MHz 2.7 V to 5.5 V CPU functions Ports Peripheral functions : single-clock 5 (4 also usable as external interrupts) dual-clock 3 (3 also usable as external interrupts) Output-only ports (N-ch open drain) : 8 (8 also usable as ADC input) I/O ports (N-ch open drain) : 2 (2 also usable as SO2/SDA or SI2/SCL) I/O ports (CMOS) : 38 (21 have no other function) (except for MB89F538L) I/O ports (CMOS) : 37 (21 have no other function) (MB89F538L) Total (except for MB89F538L) : single-clock 53, 2system clock 51 Total (MB89F538L) : single-clock 52, 2system clock 50 21 bits Time base timer Interrupt periods at main clock oscillation frequency of 12.5MHz (approx. 0.655 ms, 2.621 ms, 20.97 ms, 335.5 ms) Watchdog timer Reset period of approx. 167.8 ms to 335.6 ms at mail clock frequency of 12.5 MHz Reset period of approx. 500 ms to 1000 ms at sub clock frequency of 32.768 kHz. 8-bit interval timer operation (supports square wave output, operating clock period : 1, 8, 16, 64 tinst*3) Pulse width measurement with 8-bit resolution (conversion period : 28 tinst*3 to 28 × 64 tinst*3) 2 channels (can also be used as interval timer, can also be used as ch1 output and ch2 count clock) Interval times at 17-bit sub clock base frequency of 32.768 kHz (approx. 31.25 ms, 0.25 s, 0.50 s, 1.00 s, 2.00 s, 4.00 s) PWM timer Watch prescaler (Continued) 4 MB89530 Series (Continued) Part number Parameter MB89537/537C MB89538/538C MB89F538L MB89P538 MB89PV530 Pulse width count timer 8-bit one-shot timer operation (supports underflow output, operating clock period : 1, 4, 32 tinst*3, external) 8-bit reload timer operation (supports square wave output, operating clock period : 1, 4, 32 tinst*3, external) 8-bit pulse width measurement operation (continuous measurement, H width measurement, L width measurement, rise-to-rise, fallto-fall, H width measurement and rise-to-rise) 16-bit timer operation (operating clock period : 1 tinst*3, external) 16-bit event counter operation (select rising, falling, or both edges) 16-bit × 1 ch 8 bit length, Selection of LSB first or MSB first, Transfer clock (2, 8, 32 tinst*3, external) CLK synchronous/CLK asynchronous data transfer capability (8, 9 bit with parity bit, or 7,8 bit without parity bit) . Built-in baud rate generator provides selection of 14 baud rate settings. CLK synchronous/CLK asynchronous data transfer capability (4, 6, 7, 8 bit with parity bit, or 5, 7, 8, 9 bit without parity bit) . Built-in baud rate generator provides selection of 14 baud rate settings. External clock output, 2-channel 8-bit PWM timer output also available for baud rate settings. Single-clock : 4-channel independent, dual-clock : 3-channel independent Selection of rising, falling, or both edge detection. Can be used for recovery from standby mode (edge detection also available in stop mode) . Except for MB89F538L : 8-channel independent L level detection, MB89F538L : 7-channel independent L level detection Can be used for recovery from standby mode. Can generate square wave signals with programmable period. 6-bit × 1 channel or 12-bit × 2 channels. 16-bit timer/ counter Serial I/O UART/SIO Peripheral functions UART External interrupt 1 External interrupt 2 6-bit PPG, 12-bit PPG 1-channel , compatible with Intel System Administrator bus version 1.0 and Philips I2C I2C bus interface specifications. 2-line communications (on MB89PV530/P538/F538L/537C/538C) 10-bit resolution × 8 channels. A/D conversion functions (conversion time : 60 tinst *3) Supports repeated calls from external clock (except for MB89F538L) Supports repeated calls from internal clock. Standard voltage input provided (AVR) Sleep mode, stop mode, sub clock mode, watch mode. CMOS A/D converter Standby modes (power saving modes) Process *1 : Depends on operating frequency. *2 : Using external ROM and MBM27C512. *3 : tinst represents instruction execution time. This can be selected as 1/4, 1/8, 1/16, 1/64 of the main clock cycle or 1/2 of the sub clock cycle. Note : MB89537/538 have no built-in I2C functions. To use I2C functions, choose the MB89PV530/P538/F538L/MB89537C/538C. 5 MB89530 Series s MODEL DIFFERENCES AND SELECTION CONSIDERATIONS Part number Package DIP-64P-M01 FPT-64P-M03 FPT-64P-M06 FPT-64P-M09 LCC-64P-M19 LCC-64P-M16 MDP-64C-P02 MQP-64C-P01 MB89537/537C MB89538/538C O O O O X X X X O O O O X X X X MB89F538L O X O O O X X X MB89P538 O X O O X O* X X MB89PV530 X X X X X X O O O : Model-package combination available X : Model-package combination not available * : Only for ES Conversion sockets for pin pitch conversion (manufactured by Sunhayato Corp.) can be used. Contact : Sunhayato Corp. : TEL : +81-3-3984-7791 FAX : +81-3-3971-0535 E-mail : adapter@sunhayato.co.jp 6 MB89530 Series s DIFFERENCES AMONG PRODUCTS 1. Memory Capacity When this product is used in a piggy-back or other evaluation configuration, it is necessary to carefully confirm the differences between the model being used and the product it is evaluating. Particular attention should be given to the following (see " CPU core 1. Memory Space") . • The program ROM area starts from address 4000H on the MB89P538, MB89F538L and MB89PV530 models. • Note upper limits on RAM, such as stack areas, etc. 2. Current Consumption • On the MB89PV530, the additional current consumed by the EPROM is added at the connecting socket on the back side. • When operating at low speed, the current consumption in the one-time PROM or EPROM models is greater than on the mask ROM models. However, current consumption in sleep or stop modes is identical. For details, refer to “ ELECTRICAL CHARACTERISTICS”. 3. Mask Options The options available for use, and the method of specifying options, differ according to the model. Before use, check the “ MASK OPTIONS” specification section. 4. Wild Register Functions The following table shows areas in which wild register functions can be used. Wild Register Usage Areas Part number MB89PV530 MB89P538 MB89F538L MB89537/537C MB89538/538C Address space 4000H to FFFFH 4000H to FFFFH 4000H to FFFFH 8000H to FFFFH 4000H to FFFFH 7 MB89530 Series s PIN ASSIGNMENTS (TOP VIEW) P36/WTO P37/PTO1 P40/INT20/EC P41/INT21/SCK2 P42/INT22/SO2/SDA P43/INT23/SI2/SCL P44/INT24/UCK2 P45/INT25/UO2 P46/INT26/UI2 P47/INT27/ADST/MOD2*2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT10 P61/INT11 P62/INT12 P63/INT13/X0A*3 P64/X1A*3 RST MOD0 MOD1 X0 X1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 *1 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS 65 66 67 68 69 70 71 72 73 74 75 76 77 78 92 91 90 89 88 87 86 85 84 83 82 81 80 79 VCC A14 A13 A8 A9 A11 OE A10 CE O8 O7 O6 O5 O4 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC P35/PWC P34/PTO2 P33/SI1 (UI1) P32/SO1 (UO1) P31/SCK1 (UCK1) /LMCO P30/PPG03/MCO C/NC *4 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20/PWCK P21/PPG01 P22/PPG02 P23 P24 P25 P26 P27 (DIP-64P-M01) (MDP-64C-P02) *1 : Package top pin assignments (MB89PV530 only) Pin no. Pin name Pin no. Pin name 65 66 67 68 69 70 71 72 A15 A12 A7 A6 A5 A4 A3 A2 73 74 75 76 77 78 79 80 A1 A0 O1 O2 O3 VSS O4 O5 Pin no. 81 82 83 84 85 86 87 88 Pin name O6 O7 O8 CE A10 OE A11 A9 Pin no. 89 90 91 92 Pin name A8 A13 A14 VCC N.C. : Internal connection only. Not for use. *2 : Pin 10 is P47/INT27/ADST pins except for MB89F538L and MOD2 pin for MB89F538L. *3 : Pin 25 and 26 are P63/INT13, P64 pins for single-clock and X0A, X1A pins for dual-clock. *4 : The function of pin 57 depends on the model. For details, see “sPIN DESCRIPTIONS” and “sHANDLING DEVICES”. (Continued) 8 MB89530 Series (TOP VIEW) P45/INT25/UO2 P44/INT24/UCK2 P43/INT23/SI2/SCL P42/INT22/SO2/SDA P41/INT21/SCK2 P40/INT20/EC P37/PTO1 P36/WTO VCC P35/PWC P34/PTO2 P33/SI1 (UI1) P32/SO1 (UO1) P31/SCK1 (UCK1) /LMCO P30/PPG03/MCO C/NC*3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P46/INT26/UI2 P47/INT27/ADST/MOD2*1 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT10 P61/INT11 P62/INT12 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 *1 : Pin 2 is P47/INT27/ADST pins except for MB89F538L and MOD2 pin for MB89F538L. *2 : Pin 17 and 18 are P63/INT13, P64 pins for single-clock and X0A, X1A pins for dual-clock. *3 : The function of pin 49 depends on the model. For details, see “sPIN DESCRIPTIONS” and “sHANDLING DEVICES”. P63/INT13/X0A*2 P64/X1A*2 RST MOD0 MOD1 X0 X1 VSS P27 P26 P25 P24 P23 P22/PPG02 P21/PPG01 P20/PWCK (FPT-64P-M03) (FPT-64P-M09) (Continued) 9 MB89530 Series (TOP VIEW) P44/INT24/UCK2 P43/INT23/SI2/SCL P42/INT22/SO2/SDA P41/INT21/SCK2 P40/INT20/EC P37/PTO1 P36/WTO VCC P35/PWC P34/PTO2 P33/SI1 (U1) P32/SO1/ (UO1) P31/SCK1 (UCK1) /LMCO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P45/INT25/UO2 P46/INT26/UI2 P47/INT27/ADST/MOD2*2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT10 P61/INT11 P62/INT12 P63/INT13/X0A*3 P64/X1A*3 *1 84 83 82 81 80 79 78 85 86 87 88 89 90 91 92 93 77 76 75 74 73 72 71 70 69 P30/PPG03/MCO C/NC*4 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20/PWCK *1 : Package top pin assignments (MB89PV530 only) Pin no. Pin name Pin no. Pin name 65 N.C. 73 A2 66 A15 74 A1 67 A12 75 A0 68 A7 76 N.C. 69 A6 77 O1 70 A5 78 O2 71 A4 79 O3 72 A3 80 VSS RST MOD0 MOD1 X0 X1 VSS P27 P26 P25 P24 P23 P22/PPG02 P21/PPG01 20 21 22 23 24 25 26 27 28 29 30 31 32 (FPT-64P-M06) (MQP-64C-P01) 94 95 96 65 66 67 68 Pin no. 81 82 83 84 85 86 87 88 Pin name N.C. O4 O5 O6 O7 O8 CE A10 Pin no. 89 90 91 92 93 94 95 96 Pin name OE N.C. A11 A9 A8 A13 A14 VCC N.C. : Internal connection only. Not for use. *2 : Pin 3 is P47/INT27/ADST pins except for MB89F538L and MOD2 pin for MB89F538L. *3 : Pin 18 and 19 are P63/INT13, P64 pins for single-clock and X0A, X1A pins for dual-clock. *4 : The function of pin 50 depends on the model. For details, see “sPIN DESCRIPTIONS” and “sHANDLING DEVICES”. (Continued) 10 MB89530 Series (Continued) (TOP VIEW) P45/INT25/UO2 P44/INT24/UCK2 P43/INT23/SI2/SCL P42/INT22/SO2/SDA P41/INT21/SCK2 P40/INT20/EC P37/PTO1 P36/WTO VCC P35/PWC P34/PTO2 P33/SI1 (UI1) P32/SO1 (UO1) P31/SCK1 (UCK1) /LMCO P30/PPG03/MCO C/NC∗3 P46/INT26/UI2 P47/INT27/ADST/MOD2∗1 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT10 P61/INT11 P62/INT12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 *1 : Pin 2 is P47/INT27/ADST pins except for MB89F538L and MOD2 pin for MB89F538L. *2 : Pin 17 and 18 are P63/INT13, P64 pins for single-clock and X0A, X1A pins for dual-clock. *3 : The function of pin 49 depends on the model. For details, see “sPIN DESCRIPTIONS” and “sHANDLING DEVICES”. *4 : Only for ES P63/INT13/X0A∗2 P64/X1A∗2 RST MOD0 MOD1 X0 X1 VSS P27 P26 P25 P24 P23 P22/PPG02 P21/PPG01 P20/PWCK 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (LCC-64P-M19) (LCC-64P-M16) *4 11 MB89530 Series s PIN DESCRIPTIONS Pin no. SH-DIP*1 MDIP*2 30 31 28 29 QFP*3 MQFP*4 23 24 21 22 LQFP*5 BCC*6 22 23 20 21 Pin name X0 X1 MOD0 MOD1 A I/O circuit type Function Connecting pins to crystal oscillator circuit or other oscillator circuit. The X0 pin can connect to an external clock. In that case, X1 is left open. Input pins for memory access mode setting. Connect directly to Vss. Reset I/O pin. This pin has pull-up resistance with CMOS I/O or hysteresis input. At an internal reset request, an ’L’ signal is output. An ’L’ level input initializes the internal circuits. General purpose I/O ports. General purpose I/O ports. General purpose I/O port.Resource I/O pin (hysteresis input).Hysteresis input. This pin also functions as a PWC input. General purpose I/O port.This pin also functions as the PPG01 output. General purpose I/O port.This pin also functions as the PPG02 output. General purpose I/O port. General purpose I/O port. General purpose I/O port. General purpose I/O port. General purpose I/O port. General purpose I/O port.This pin also functions as the PPG03 output. General purpose I/O port.Resource I/O pin (hysteresis input).This pin also functions as the UART/SIO clock input/output pin. General purpose I/O port.This pin also functions as the UART/SIO clock input/output pin. General purpose I/O port.Resource input/output pin (hysteresis input).This pin also functions as the UART/ SIO serial data input pin. General purpose I/O port.This pin also functions as the PWM time 2 output pin. General purpose I/O port.Resource I/O pin (hysteresis input).This pin also functions as a PWC input. B 27 20 19 RST C 56 to 49 48 to 41 40 49 to 42 41 to 34 33 48 to 41 40 to 33 32 P00 to P07 P10 to P17 P20/PWCK P21/ PPG01 P22/ PPG02 P23 P24 P25 P26 P27 P30/ PPG03/ MCO P31/SCK1 (UCK1) / LMCO P32/SO1 (UO1) P33/SI1 (UI1) P34/PTO2 P35/PWC D D E 39 38 37 36 35 34 33 58 32 31 30 29 28 27 26 51 31 30 29 28 27 26 25 50 D D D D D D D D 59 52 51 E 60 53 52 D 61 54 53 E 62 63 55 56 54 55 D E (Continued) 12 MB89530 Series Pin no. SH-DIP* MDIP*2 1 2 1 QFP*3 MQFP*4 58 59 LQFP*5 BCC*6 57 58 Pin name I/O circuit type D D Function General purpose I/O port.Resource output.This pin also functions as the PWC output pin. General purpose I/O port.Resource output.This pin also functions as the PWM timer 1 output pin. General purpose I/O port.Resource I/O pin (hysteresis input)This pin also functions as an external interrupt input or 16-bit timer/counter input. General purpose I/O port.Resource I/O pin (hysteresis input)This pin also functions as an external interrupt input or SIO clock I/O pin. N-ch open drain output. Resource I/O pin (hysteresis only for INT22 input) . This pin also functions as an external interrupt input, SIO serial data output, or I2C data line. N-ch open drain output. Resource I/O pin (hysteresis only for INT23 input) . This pin also functions as an external interrupt, SIO serial data input, or I2C clock I/O pin. General purpose I/O port. Resource I/O pin (hysteresis input) . This pin also functions as an external interrupt input or UART clock I/O pin. General purpose I/O port. Resource I/O pin (hysteresis input) . This pin also functions as an external interrupt input or UART data output pin. General purpose I/O port. Resource I/O pin (hysteresis input) . This pin also functions as an external interrupt input or UART data input pin. except for MB89F 538L General purpose I/O port. Resource I/O pin (hysteresis input) . This pin also functions as an external interrupt input or A/D converter clock input pin. P36/WTO P37/PTO1 P40/INT20/ EC P41/INT21/ SCK2 3 60 59 E 4 61 60 E 5 62 61 P42/INT22/ SO2/SDA G 6 63 62 P43/INT23/ SI2/SCL G 7 64 63 P44/INT24/ UCK2 E 8 1 64 P45/INT25/ UO2 E 9 2 1 P46/INT26/ UI2 E 10 3 2 P47/INT27/ ADST E MOD2 P50/AN0 to P57/AN7 P60/INT10 to P62/INT12 B MB89F Input pin for memory access mode setting. 538L Connect to VSS directly. N-ch open drain output port. This pin also functions as an A/D converter analog input pin. General purpose input port. Resource input pin (hysteresis input) . This pin also functions as an external interrupt input pin. 11 to 18 4 to 11 3 to 10 H 22 to 24 15 to 17 14 to 16 I (Continued) 13 MB89530 Series (Continued) Pin no. SH-DIP* MDIP*2 1 QFP*3 MQFP*4 LQFP*5 BCC*6 Pin name I/O circuit type Function General purpose input port. Resource input pin (hysteresis input) . This pin also functions as an external interrupt. Connected pin for sub clock. General purpose input port. Connected pin for sub clock. 25 18 17 P63/INT13 I Single-clock X0A 26 64 32 19 20 21 19 57 25 12 13 14 18 56 24 11 12 13 P64 X1A VCC VSS AVCC AVR AVSS A J A      Dual-clock Single-clock Dual-clock Power supply pin. Ground pin (GND) . A/D converter power supply pin. A/D converter reference voltage input pin. A/D converter power supply pin. Used at the same voltage level as the Vss supply. MB89P538 Fixed at Vss. MB89PV530 MB89F538L MB89537/537C MB89538/538C 57 50 49 C  N.C. pin *1 : DIP-64P-M01 *2 : MDP-64C-P02 *3 : FPT-64P-M06 *4 : MQP-64C-P01 *5 : FPT-64P-M03/M09 *6 : LCC-64P-M19/M16 14 MB89530 Series External EPROM Socket Pin Function Descriptions (MB89PV530 only) Pin no. I/O Circuit Pin name type 1 2 MQFP* MDIP* 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92  66 67 68 69 70 71 72 73 74 75 77 78 79 80 82 83 84 85 86 87 88 89 91 92 93 94 95 96 65 76 81 90 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS O4 O5 O6 O7 O8 CE A10 OE A11 A9 A8 A13 A14 VCC Function O Address output pins. I O Data input pins. Power supply pin (GND) . I Data input pins. O O O O ROM chip enable pin. Outputs an “H” level signal in standby mode. Address output pin. ROM output enable pin. Outputs “L” at all times. Address output pins. O O O EPROM power supply pin. Internally connected. These pins always left open. N.C. O *1 : MDP-64C-P02 *2 : MQP-64C-P01 15 MB89530 Series s I/O CIRCUIT TYPES Type X1 (X1A) Nch Pch Pch Nch Circuit Remarks Oscillator feedback resistance • High speed side = approx. 1 MΩ • Low speed side = approx. 10 MΩ A X0 (X0A) B • Hysteresis input • Pull-down resistance built-in to MB89537/537C MB89538/538C • Pull-up resistance approx. 50 kΩ • Hysteresis input R Pch C Nch R Pch Pch Pull-up control resistor • CMOS I/O • Software pull-up resistance can be used. Approx. 50 kΩ D Nch R Pch Pch Pull-up control resistors • CMOS I/O • Software pull-up resistance can be used. Approx. 50 kΩ E Nch Port input Resource input (Continued) 16 MB89530 Series (Continued) Type Circuit Remarks • N-ch open drain output • Hysteresis input • CMOS input Resource input Port input • N-ch open drain output • Analog input (A/D converter) G Nch Pch H Nch Analog input • Hysteresis input • CMOS input • Software pull-up resistance can be used. Approx. 50 kΩ R Pch Pull-up control resistors Resource Port I R Pch Pull-up control resistors • CMOS input • Software pull-up resistance can be used. Approx. 50 kΩ J Port 17 MB89530 Series s HANDLING DEVICES 1. Preventing Latchup Care must be taken to ensure that maximum voltage ratings are not exceeded (to prevent latchup) . When CMOS integrated circuit devices are subjected to applied voltages higher than Vcc at input and output pins (other than medium- and high-withstand voltage pins), or to voltages lower than Vss, as well as when voltages in excess of rated levels are applied between Vcc and Vss, the phenomenon known as latchup can occur. When a latchup condition occurs, supply current can increase dramatically and may destroy semiconductor elements. In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings. Also when switching power on or off to analog systems, care must be taken that analog power supplies (AVCC, AVR) and analog input signals do not exceed the level of the digital power supply. 2. Power Supply Voltage Fluctuations Keep supply voltage levels as stable as possible. Even within the warranted operating range of the Vcc supply voltage, sudden changes in supply voltage can cause abnormal operation. As a measure for stability, it is recommended that the Vcc ripple fluctuation (peak to peak value) should be kept within 10% of the reference Vcc value on commercial power supply (50 Hz-60 Hz), and instantaneous voltage fluctuations such as at power-on and shutdown should be kept within a transient variability limit of 0.1V/ms. 3. Treatment of Unused Input Pins If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to pull-up or pull-down resistance. 4. Treatment of N.C. Pins Any pins marked ’NC’ (not connected) must be left open. 5. Treatment of Power Supply Pins on Models with Built-in A/D Converter Even when A/D converters are not in use, pins should be connected so that AVCC = VCC, and AVSS = AVR = VSS. 6. Precautions for Use of External Clock Even when an external clock signal is used, an oscillator stabilization wait period is used after power-on reset, or escape from sub clock mode or stop mode. 7. Execution of Programs on RAM Debugging of programs executed on RAM cannot be performed even when using the MB89PV530. 8. Wild Register Functions Wild registers cannot be debugged with the MB89PV530 and tools. To verify operations, actual in-device testing on the MB89P538 or MB89F538L is advised. 18 MB89530 Series 9. Details on Handling C Terminal of MB89530 Series The MB89530 series contains the following products. The regulator integrated model and the regulator-less model have different performance characteristics. Part No. Operation Voltage integrated model Terminal type Terminal treatments MB89PV530 MB89P538 MB89537/537C MB89538/538C MB89F538L 2.7 V to 5.5 V Not included Included N.C terminal C terminal Not required Fixed to VCC Fixed to VSS Not required 2.2 V to 3.6 V 2.3 V to 3.6 V Not included N.C terminal Although these product models have the same internal resources, the operation sequence after a power-on reset is different between the regulator integrated model and regulator-less model. The operation sequence after a power-on reset of each model is shown below. Power supply (VCC) Voltage step-down circuit stabilization time + oscillation stabilization time (219/Fch) CPU operation of regulator integrated model Oscillation stabilization time (218/Fch) CPU operation of regurator-less model CPU started on regulator-less model (Reset vector) Fch : Crystal oscillator frequency CPU started on regulator integrated model (Reset vector) As above, the regulator integrated model starts the CPU behind the regulator-less model. This is because the regulator requires a settling time for normal operation. The MB89P538 offers a choice of regulator-integrated and regulator-less models selectable depending on the C-terminal treatment. Use the right one for your mask board. 10. Note to Noise In the External Reset Pin (RST) If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST) . 19 MB89530 Series s PROGRAMMING AND ERASING FLASH MEMORY ON THE MB89F538L 1. Flash Memory The flash memory is located between 4000H and FFFFH in the CPU memory map and incorporates a flash memory interface circuit that allows read access and program access from the CPU to be performed in the same way as mask ROM. Programming and erasing flash memory is also performed via the flash memory interface circuit by executing instructions in the CPU. This enables the flash memory to be updated in place under the control of the CPU, providing an efficient method of updating program and data. 2. Flash Memory Features • • • • • • • • 48 K byte×8-bit configuration : (16 K+8 K+8 K+16 K sectors) Automatic programming algorithm (Embedded algorithm* : Equivalent to MBM29LV200) Includes an erase pause and restart function Data polling and toggle bit for detection of program/erase completion Detection of program/erase completion via CPU interrupt Compatible with JEDEC-standard commands Sector Erasing (sectors can be combined in any combination) No. of program/erase cycles : 10,000 (Min) * : Embedded Algorithm is a trademark of Advanced Micro Devices. 3. Procedure for Programming and Erasing Flash Memory Programming and reading flash memory cannot be performed at the same time. Accordingly, to program or erase flash memory, the program must first be copied from flash memory to RAM so that programming can be performed without program access from flash memory. 4. Flash Memory Register • Control status register (FMCS) Address 007AH bit7 INTE R/W bit6 RDYINT R/W bit5 WE R/W bit4 RDY R bit3 bit2 bit1 bit0 Reserved R/W Initial value 000X00-0B ReReserved served R/W R/W 20 MB89530 Series 5. Sector Configuration The table below shows the sector configuration of flash memory and lists the addresses of each sector for both during CPU access a flash memory programming. • Sector configuration of flash memory FLASH Memory 16 K bytes 8 K bytes 8 K bytes 16 K bytes CPU Address FFFFH to C000H BFFFH to A000H 9FFFH to 8000H 7FFFH to 4000H Programmer Address* 1FFFFH to 1C000H 1BFFFH to 1A000H 19FFFH to 18000H 17FFFH to 14000H * : The programmer address is the address to be used instead of the CPU address when programming data from a parallel flash memory programmer. Use the programmer address on programming or erasing using a generalpurpose parallel programmer. 6. ROM Programmer Adaptor and Recommended ROM Programmers Part number MB89F538L-101PF MB89F538L-201PF MB89F538L-101PFM MB89F538L-201PFM MB89F538L-101P-SH MB89F538L-201P-SH MB89F538L-101PV4 MB89F538L-201PV4 Package Adaptor Part No. Sunhayato Corp. FPT-64P-M06 FPT-64P-M09 DIP-64P-M01 LCC-64P-M19 FLASH-64QF-32DP-8LF FLASH-64QF2-32DP-8LF2 FLASH-64SD-32DP-8LF FLASH-64BCC-32DP-8LF Recommended Programmer Manufacturer and Model Ando Electric Co., Ltd. AF9708* AF9709* * : For the version of the programmer, contact the Flash Support Group, Inc. • Enquiries Sunhayato Corp. : TEL FAX E-mail Flash Support Group, Inc. : FAX E-mail : +81-3-3984-7791 : +81-3-3971-0535 : adapter@sunhayato.co.jp : +81-53-428-8377 : support@j-fsg.co.jp 21 MB89530 Series s ONE-TIME WRITING SPECIFICATIONS WITH PROM AND EPROM MICROCONTROLLERS The MB89P538 has a PROM mode with functions equivalent to the MBM27C1001, allowing writing with a general purpose ROM writer using a proprietary adapter. Note, however, that the use of electronic signature mode is not supported. • ROM writer adapters With some ROM writers, stability of writing performance is enhanced by placing an 0.1µF capacitor between the Vcc and Vss pins. The following table lists adapters for use with ROM writers. ROM Writer Adapters Part number MB89P538-101PF MB89P538-201PF MB89P538-101PFM MB89P538-201PFM MB89P538-101P-SH MB89P538-201P-SH MB89P538-101P-PV MB89P538-201P-PV Package FPT-64P-M06 FPT-64P-M09 DIP-64P-M01 LCC-64P-M16*2 Compatible adapter ROM-64QF-32DP-8LA2*1 ROM-64QF2-32DP-8LA ROM-64SD-32DP-8LA2*1 ROM-64BCC-32DP-8LA-FJ Inquiries should be addressed to Sunhayato Corp. : TEL : +81-3-3984-7791 FAX : +81-3-3971-0535 E-mail : adapter@sunhayato.co.jp *1 : Version 3 or later should be used. *2 : Only for ES • Memory map for EPROM mode The following illustration shows a memory map for EPROM mode. There are no PROM options. Normal operating mode 0000H I/O 0080H RAM 0100H 0200H 0880H EPROM mode (corresponding addresses on EPROM writer) 0000H General purpose register Prohibited Prohibited 4000H 4000H ROM FFFFH Program (EPROM) FFFFH Prohibited 1FFFFH 22 MB89530 Series • Recommended screening conditions Before one-time writing of microcontroller programs to PROM, high temperature aging is recommended as a screening process for chips before they are mounted. The following diagram shows the flow of the screening process. Program, verify High temperature aging +150 °C, 48 h Read Mount • About writing yields The nature of chips before one-time writing of microcontroller programs to PROM prevents the use of all-bit writing tests. Therefore it is not possible to guarantee writing yields of 100% in some cases. 23 MB89530 Series s EPROM WRITING TO PIGGY-BACK/EVALUATION CHIPS This section describes methods of writing to EPROM on piggy-back/evaluation chips. • EPROM model MBM27C512-20TV • Writer adapter For writing to EPROM using a ROM writer, use one of the writer adapters shown below (manufactured by Sunhayato Corp.) . Package Adapter socket model LCC-32 (rectangular) Inquiries should be addressed to Sunhayato Corp. : TEL : +81-3-3984-7791 FAX : +81-3-3971-0535 E-mail : adapter@sunhayato.co.jp • Memory Space ROM-32LC-28DP-YG Piggy-back/Evaluation Memory Map Normal operating mode 0000H I/O 0080H RAM 0880H (Corresponding address on ROM writer) 0000H Prohibited Prohibited 4000H 4000H PROM 48 KB EPROM FFFFH FFFFH • Writing to EPROM 1) Set up the EPROM writer for the MBM27C512. 2) Load program data to the ERPOM writer, in the area 4000H - FFFFH. 3) Use the EPROM writer to write to the area 4000H - FFFFH. 24 MB89530 Series s BLOCK DIAGRAM Sub clock P63/INT13/X0A*2 P64/X1A*2 CMOS I/O port Port 0 Port 1 Port 2 N-ch I/O Low voltage oscillator circuit (32.786 kHz) 8 P00 ∼ P07 Clock control P60/INT10 ∼ P62/INT12 8 Watch prescaler Port 6 4 External interrupt 1 P10 ∼ P17 CMOS I/O port (edge) 12-bit PPG01 CMOS I/O port Main clock Oscillator circuit Clock controller P20/PWCK P21/PPG01 P22/PPG02 P23 ∼ P27 12-bit PPG02 Internal databus CMOS I/O port X0 X1 Reset circuit RST SIO UART I2C P40/INT20/EC P41/INT21/SCK2 P42/INT22/ SO2/SDA P43/INT23/ SI2/SCL P44/INT24/UCK2 (watchdog timer) 21-bit time base timer P30/PPG03/MCO P31/SCK1 (UCK1) /LMCO 6-bit PPF03 8-bit PWM timer 2 16-bit timer/ counter 1 External interrupt 2 (level) Port 4 P45/INT25/UO2 P46/INT26/UI2 P47/INT27/ADST*1 Port 3 P32/SO1 (UO1) P33/SI1 (UI1) P34/PTO2 P35/PWC P36/WTO P37/PTO1 8-bit PWM timer 1 UART/SIO PWC CMOS I/O port Port 5 N-ch output CMOS I/O port 1KB RAM/2KB RAM F2MC-8L CPU 8 8 P50/AN0 ∼ P57/AN7 AVCC AVR AVSS 10-bit A/D converter Wild register 32KB ROM/48KB ROM Other pins MOD0, MOD1, MOD2*1, C, VCC, VSS, C/NC *1 : P47/INT27/ADST pins except for MB89F538L, MOD2 pin for MB89F538L *2 : P63/INT13, P64 pins for single-clock, X0A, X1A pins for dual-clock 25 MB89530 Series s CPU CORE 1. Memory Space The MBM89530 series has 64 KB of memory space, containing all I/O, data areas, and program areas. The I/ O area is located at the lowest addresses, with the data area placed immediately above. The data area can be partitioned into register areas, stack areas, or direct access areas depending on the application. The program area is located at the opposite end of memory, closest to the highest addresses, and the highest part of this area is assigned to the tables of interrupt and reset vectors and vector call instructions. The following diagram shows the structure of memory space in the MB89530 series. • Memory Map MB89537/537C 0000H I/O 0080H RAM 0100H 0200H General purpose register 0100H 0200H 0080H 0000H MB89PV530 MB89P538/F538L MB89538/538C I/O RAM General purpose register 0480H Open 0C80H 0C91H 0880H 0C80H Open Wild register Open Wild register Open 0C91H 4000H 8000H ROM ROM FFC0H FFC0H External ROM*1 Vector tables*2 Vector tables*2 FFFFH FFFFH *1 : The external ROM area is on the MBM89PV530 only. *2 : Vector tables (reset, interrupt, vector call instructions) 26 MB89530 Series 2. Registers The F2MC-8L series has two types of registers, dedicated-use registers within the CPU, and general-purpose registers in memory. The dedicated-use registers are the following. Program counter (PC) : 16-bit length, shows the location where instructions are stored. Accumulator (A) : 16-bit length, a temporary memory register for calculation operations. The lower byte is used for 8-bit data processing instructions. Temporary accumulator (T) : 16-bit length, performs calculations with the accumulator. The lower byte is used for 8-bit data processing instructions. Index register (IX) : 16-bit length, a register for index modification. Extra pointer (EP) : 16-bit length, a pointer indicating memory addresses. Stack pointer (SP) : 16-bit length, indicates stack areas. Program status (PS) : 16-bit length, contains register pointer and condition code. 16 bits PC A T IX EP SP PS : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status Initial value FFFDH Not fixed Not fixed Not fixed Not fixed Not fixed I-flag = 0, IL1, 0 = 11 Other bits not fixed In addition, the PS register can be divided so that the upper 8 bits are used as a register bank pointer (RP), and the lower 8 bits as a condition code register (CCR). (See the following illustration.) • Program status register configuration 15 PS 14 13 RP 12 11 10 9 8 7 6 I 5 IL1 4 IL0 3 N 2 Z 1 V 0 C Open Open Open H RP CCR 27 MB89530 Series The RP register shows the address of the register bank currently being used, so that the RP value and the actual address are related by the conversion rule shown in the following illustration. • General purpose register area real address conversion principle RP upper "0" "0" "0" "0" "0" "0" "0" A9 "1" A8 R4 A7 R3 A6 R2 A5 R1 A4 R0 Operation code lower b2 A2 b1 A1 b0 A0 Address generated A15 A14 A13 A12 A11 A10 A3 The CCR register has bits that show the content of results of calculations and transferred data, and bits that control CPU operation during interrupts. H-flag I-flag IL1, 0 : Set to 1 if calculations result in carry or borrow operations from bit 3 to bit 4, otherwise set to 0. This flag is used for decimal correction instructions. : This flag is set to 1 if interrupts are enabled, and 0 if interrupts are prohibited. The default value at reset is 0. : Indicates the level of the currently permitted interrupts. Only interrupt requests having a more powerful level than the value of these bits will be processed. IL1 0 0 1 1 N-flag Z-flag V-flag C-flag : : : : IL0 0 1 0 1 Interrupt level 1 2 3 Weak Strength Strong Set to 1 if the highest bit is 1 after a calculation, otherwise cleared to 0. Set to 1 if a calculation result is 0, otherwise cleared to 0. Set to 1 if a two’s complement overflow results during a calculation, otherwise cleared to 0. Set to 1 if a calculation results in a carry or borrow operation from bit 7, otherwise cleared to 0. This is also the shift-out value in a shift instruction. In addition, the following general purpose registers are available. General purpose registers: 8-bit length, used to contain data. The general purpose registers are 8-bit registers located in memory. There are eight such registers per bank, and the MB89530 series have up to 32 banks for use. The bank currently in use is indicated by the register bank pointer (RP). 28 MB89530 Series •Register bank configuration Address at this location = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area 29 MB89530 Series s I/O MAP Address 00H 01H 02H 03H 04H to 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H to 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H SMC11 SRC1 SSD1 SIDR1/ SODR1 SMC12 CNTR1 CNTR2 CNTR3 COMR1 COMR2 PCR1 PCR2 RLBR SMC21 SMC22 SSD2 SIDR2/ SODR2 SYCC STBC WDTC TBTC WPCR PDR2 DDR2 PDR3 DDR3 PDR4 DDR4 PDR5 PDR6 Standby control register Watchdog control register Time base timer control register Watch prescaler control register Port 2 data register Port 2 direction register Port 3 data register Port 3 direction register Port 4 data register Port 4 direction register Port 5 data register Port 6 data register (Reserved area) Serial mode control register 1 (UART) Serial route control register (UART) Serial status and data register (UART) Serial input/output data register (UART) Serial mode control register 2 (UART) PWM control register 1 PWM control register 2 PWM control register 3 PWM compare register 1 PWM compare register 2 PWC pulse width control register 1 PWC pulse width control register 2 PWC reload buffer register Serial mode control register 1 (UART/SIO) Serial mode control register 2 (UART/SIO) Serial status and data register (UART/SIO) Serial data register (UART/SIO) R/W R/W R/W R/W R/W R/W R/W R/W W W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0B - - 0 1 1 0 0 0B 0 0 1 0 0 - 1XB XXXXXXXXB - - 1 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 - 0 0 0 0B - 0 0 0 - - - -B XXXXXXXXB XXXXXXXXB 0 0 0 - - 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 1 - - -B XXXXXXXXB Register name PDR0 DDR0 PDR1 DDR1 Register description Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (Reserved area) System clock control register R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R X -1 MM1 0 0B 0 0 0 1 0 - - -B 0 - - - XXXXB 0 0 - - - 0 0 0B 0 0 - - 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B XXXX 1 1 XXB 0 0 0 0 - - 0 0B 11111111B XXXXXXXXB Write/Read R/W W R/W W Initial value XXXXXXXXB 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B (Continued) 30 MB89530 Series Address 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H to 48H 49H 4AH to 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH to 6FH 70H 71H 72H 73H 74H 75H Register name SRC2 ADC1 ADC2 ADDL ADDH PPGC2 PRL22 PRL21 PRL23 TMCR TCHR TCLR EIC1 EIC2 DDCR PPGC1 PRL12 PRL11 PRL13 IACR IBSR IBCR ICCR IADR IDAR EIE2 EIF2 RCR1 RCR2 CKR SMR SDR PURR0 PURR1 PURR2 PURR3 Register description Baud rate generator reload register A/D control register 1 A/D control register 2 A/D data register low A/D data register high PPG2 control register (12-bit PPG) PPG2 reload register 2 (12-bit PPG) PPG2 reload register 1 (12-bit PPG) PPG2 reload register 3 (12-bit PPG) 16-bit timer control register 16-bit timer counter register high 16-bit timer counter register low External interrupt 1 control register 1 External interrupt 1 control register 2 (Reserved area) DDC select register (Reserved area) PPG1 control register (12-bit PPG) PPG1 reload register 2 (12-bit PPG) PPG1 reload register 1 (12-bit PPG) PPG1 reload register 3 (12-bit PPG) I C address control register I C bus status register I2C bus control register I C clock control register I C address register I C data register External interrupt 2 control register External interrupt 2 flag register 6-bit PPG control register 1 6-bit PPG control register 2 Clock output control register (Reserved area) Serial mode register (SIO) Serial data register (SIO) Port 0 pull-up resistance register Port 1 pull-up resistance register Port 2 pull-up resistance register Port 3 pull-up resistance register 2 2 2 2 2 Write/Read R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value XXXXXXXXB 0 0 0 0 0 0 - 0B - 0 0 0 0 0 0 1B XXXXXXXXB - - - - - - 0 0B 0 0 0 0 0 0 0 0B 0X0 0 0 0 0 0B XX0 0 0 0 0 0B XX0 0 0 0 0 0B - - 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - - - - 0B 0 0 0 0 0 0 0 0B 0X0 0 0 0 0 0B XX0 0 0 0 0 0B XX0 0 0 0 0 0B - - - - - 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 XXXXXB - XXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B - - - - - - - 0B 0 0 0 0 0 0 0 0B 0X0 0 0 0 0 0B - - - - - - 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 11111111B 11111111B 11111111B 11111111B (Continued) 31 MB89530 Series (Continued) Address 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH C80H C81H C82H C83H C84H C85H C86H C87H C88H C89H C8AH C8BH C8CH C8DH C8EH C8FH C90H C91H Register name PURR4 WREN WROR PURR6 FMCS ILR1 ILR2 ILR3 ILR4 ITR WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 WRARH3 WRARL3 WRDR3 WRARH4 WRARL4 WRDR4 WRARH5 WRARL5 WRDR5 WRARH6 WRARL6 WRDR6 Register description Port 4 pull-up resistance register Wild register enable register Wild register data test register Port 6 pull-up resistance register FLASH control status register Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 Interrupt test register Upper address setting register 1 Lower address setting register 1 Data setting register 1 Upper address setting register 2 Lower address setting register 2 Data setting register 2 Upper address setting register 3 Lower address setting register 3 Data setting register 3 Upper address setting register 4 Lower address setting register 4 Data setting register 4 Upper address setting register 5 Lower address setting register 5 Data setting register 5 Upper address setting register 6 Lower address setting register 6 Data setting register 6 Write/Read R/W R/W R/W R/W R/W W W W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value 1 1 1 1 - -1 1 B - - 0 0 0 0 0 0B - - 0 0 0 0 0 0B ---11111B 000X00 - 0 B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B 1 1 1 1 1 1 1 1B XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Access prohibited XXXXXX0 0B • Description of write/read symbols : R/W : read/write enabled R : Read only W : Write only • Description of initial values : 0 : This bit initialized to “0”. 1 : This bit initialized to “1”. X : The initial value of this bit is not determined. M : The initial value of this bit is a mask option. - : This bit is not used. Note : Do not use reserved spaces. 32 MB89530 Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 − 2.0           −40 −55 Max VSS + 4.0 VSS + 4.0 VSS + 6.0 VSS + 6.0 VCC + 0.3 VSS + 6.0 VCC + 0.3 VSS + 6.0 + 2.0 20 15 4 100 40 −15 −4 −50 −20 300 +85 +150 (AVss = Vss = 0 V) Unit V V V V V V V V mA mA mA mA mA mA mA mA mA mA mW °C °C Average value (operating current × operating duty) Average value (operating current × operating duty) Average value (operating current × operating duty) Average value (operating current × operating duty) Remarks MB89537/538 MB89537C/538C MB89F538L MB89P538 MB89PV530 Other than P42, P43 Only P42, P43 Other than P42, P43 Only P42, P43 *2 *2 Parameter Symbol VCC AVCC *1 Supply voltage AVR VCC AVCC AVR *1 Input voltage Output voltage Maximum clamp current “L” level maximum output current “L” level average output current “L” level maximum total output current “L” level average total output current “H” level maximum output current “H” level average output current “H” level maximum total output current “H” level average total output current Current consumption Operating temperature Storage temperature VI VO ICLAMP Total maximum clamp current ∑| ICLAMP | IOL IOLAV ΣIOL ΣIOLAV IOH IOHAV ΣIOH ΣIOHAV PD TA Tstg *1 : AVcc and Vcc are to be used at the same potential. AVR should not exceed AVcc + 0.3 V. *2 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40, P41, P44 to P47, P50 to P57, P60 to P64 • Use within recommended operating conditions. • Use at DC voltage (current) . (Continued) 33 MB89530 Series (Continued) • The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on result. • Care must be taken not to leave the +B input pin open. • Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. • Sample recommended circuits : • Input/Output Equivalent circuits Protective diode VCC Limiting resistance +B input (0 V to 16 V) P-ch N-ch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 34 MB89530 Series 2. Recommended Operating Conditions Value Min 2.2* 1.5 2.4 1.5 2.7* 1.5 AVR Operating temperature TA 2.4 −40 Max 3.6 3.6 3.6 3.6 5.5 5.5 AVCC +85 (AVss = Vss = 0 V) Unit V V V V V V V °C Remarks Range warranted for normal operation RAM status in stop mode Range warranted for normal operation RAM status in stop mode Range warranted for normal operation RAM status in stop mode MB89537/538 MB89537C/ 538C Parameter Symbol Supply voltage VCC, AVCC MB89F538L MB89P538 MB89PV530 * : Varies according to frequency used, and instruction cycle. See “Operating voltage vs. operating frequency (MB89537/MB89538/MB89537C/MB89538C) and (MB89P538/ MB89PV530) ” and “5. A/D Converter Electrical Characteristics”. Operating voltage vs. operating frequency (MB89537/MB89538/MB89537C/MB89538C) Range of warranted analog precision : VCC = AVCC = 2.4 V to 3.6 V Operating voltage VCC (V) 4.0 3.6 3.0 2.4 2.2 2.0 1.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 12.5 Operating frequency (MHz) (at instruction cycle = 4 / Fc) 4.0 2.0 0.8 0.4 0.32 Minimum instruction execution time (Instruction cycles) (µs) 35 MB89530 Series Operating voltage vs. operating frequency (MB89F538L) Range of warranted analog precision : VCC = AVCC = 2.4 V to 3.6 V Operating voltage VCC (V) 4.0 3.6 3.0 2.4 2.0 1.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 12.5 Operating frequency (MHz) (at instruction cycle = 4 / Fc) 4.0 2.0 0.8 0.4 0.32 Minimum instruction execution time (Instruction cycles) (µs) 36 MB89530 Series Operating voltage vs. operating frequency (MB89P538/MB89PV530) Range of warranted analog precision : VCC = AVCC = 3.5 V to 5.5 V 5.5 5.0 Operating voltage VCC (V) 4.0 3.5 3.0 2.7 2.2 2.0 1.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 12.5 Operating frequency (MHz) (at instruction cycle = 4 / Fc) 4.0 2.0 0.8 0.4 0.32 Minimum instruction execution time (Instruction cycles) (µs) indicates warranted operation at TA = −10 °C to +55 °C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 37 MB89530 Series 3. DC Characteristics Parameter Symbol (AVCC = VCC = 3.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C) Pin name Condition Value Min 0.7 VCC Typ  Max VCC + 0.3 Unit Remarks VIH P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P60 to P64, SI1, SI2 RST, MOD0, MOD1, INT20 to INT27, UCK1, UI1, INT10 to INT13, SCK1, EC, PWCK, PWC, SCK2, UCK2, UI2, ADST  V “H” level input voltage VIHS  0.8 VCC  VCC + 0.3 V VIHSMB SCL, SDA VIHI2C P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P60 to P64, SI1, SI2 RST, MOD0, MOD1, INT20 to INT27, UCK1, UI1, INT10 to INT13, SCK1, EC, PWCK, PWC, SCK2, UCK2, UI2, ADST   VSS + 1.4 0.7 VCC   VSS + 5.5 VSS + 5.5 V V With SMB input buffer selected* With I2C input buffer selected* VIL  VSS − 0.3  0.3 VCC V “L” level input voltage VILS  VSS − 0.3  0.2 VCC V VILSMB SCL, SDA VILI2C Open drain output applied voltage VD1 VD2 P50 to P57 P42, P43    VSS − 0.3 VSS − 0.3 VSS − 0.3    VSS + 0.6 0.3 VCC VCC + 0.3 VSS + 5.5 V V V V With SMB input buffer selected* With I2C input buffer selected* “H” level output voltage VOH P00 to P07, P10 to P17, IOH = P20 to P24, P30 to P37, −2.0 mA P40, P41, P44 to P47 P25 to P27 IOH = −3.0 mA 2.4   V “L” level output voltage Input leak current (Hi-Z output leak current) VOL P00 to P07, P10 to P17, P20 to P27, P30 to P37, IOL = P40 to P47, P50 to P57, 4.0 mA RST P00 to P07, P10 to P17, P20 to P27, P30 to P37, 0.0 V < VI P40 to P47, P50 to P57, < VCC P60 to P64   0.4 V ILI −5  +5 µA With no pull-up resistance specified (Continued) 38 MB89530 Series (Continued) Parameter Open drain output leak current Symbol Pin name P42, P43 (AVCC = VCC = 3.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C) Value Condition Unit Remarks Min Typ Max 0.0 V < VI < VSS + 5.5 V   +5 µA ILIOD Pull-up resistance RPULL P00 to P07, P10 to P17, P20 to P27, VI = 0.0 V P30 to P37, P40, P41, P44 to P47, P60 to P64, RST FCH = 10.0 MHz tinst = 0.4 µs FCH = 10.0 MHz tinst = 6.4 µs FCH = 10.0 MHz tinst = 0.4 µs FCH = 10.0 MHz tinst = 6.4 µs FCL = 32.768 kHz 25 50 100 With pull-up resistance is selected. kΩ The RST signal is excluded. mA Normal operation FLASH memory mA programming/erase MB89F538L mA mA Sleep mode mA Sleep mode mA µA µA Sub mode MB89P538/PV530 Sub mode MB89F538L Sub mode MB89537/538 MB89537C/538C Sub, sleep modes Except MB89F538L Watch mode, main stop MB89F538L Watch mode, main stop Except MB89F538L Sub, sleep modes MB89F538L Sub, stop modes A/D conversion running A/D stopped  ICC1        6  1.5 2 1 1 35 20 10 45 3 4 2 3 90 50 ICC2 ICCS1 ICCS2 ICCL VCC Supply current FCL = 32.768 kHz TA = +25 °C FCL = 32.768 kHz FCL = 32.768 kHz ICCLS FCL = 32.768 kHz TA = +25 °C  15 30 µA  15 30 µA FCL = 32.768 kHz ICCT FCL = 32.768 kHz TA = +25 °C TA = +25 °C AVCC FCH = 10.0 MHz TA = +25 °C Except VCC, VSS, f = 1 MHz AVCC, AVSS  5 15 µA      5 1 1 1 5 15 5 3 5 15 µA µA mA µA pF ICCH IA IAH Input capacitance CIN * : The MB89PV530/P538/F538L/537C/538C have a built-in I2C function, and a choice of input buffers by software setting. The MB89537/538 have no built-in I2C functions, and therefore this standard does not apply. 39 MB89530 Series 4. AC Characteristics (1) Reset Timing (VCC = 3.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C) Symbol tZLZH Condition  Value Min 48 tHCYL Max  Unit ns Remarks Parameter RST “L” pulse width Notes : • tHCYL is the main clock oscillator period. • If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST) . tZLZH RST 0.2 VCC 0.2 VCC (2) Power-on Reset Value Min 0.5 1 (AVss = Vss = 0 V, TA = −40 °C to +85 °C) Symbol tR tOFF Condition   Max 50  Unit ms ms For repeated operation Remarks Parameter Power on time Power shutoff time Note : Be sure that the power supply will come on within the selected oscillator stabilization period. Also, when varying the supply voltage during operation, it is recommended that the supply voltage be increased gradually. tR 2.2 V tOFF VCC 0.2 V 0.2 V 0.2 V 40 MB89530 Series (3) Clock Timing Standards (AVss = Vss = 0 V, TA = −40 °C to +85 °C) Value Min 1  80   20   Typ  32.768  30.5  15.2  Max 12.5  1000    10 Unit Remarks Parameter Clock frequency Clock cycle time Symbol Pin name Condition FCH FCL tHCYL tLCYL PWH PWL PWHH PWLL tCR tCF X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0 MHz Main clock kHz ns µs ns µs ns Sub clock Main clock Sub clock External clock External clock External clock Input clock pulse width Input clock rise, fall time • X0, X1 timing and application conditions tHCYL PWH tCR 0.8 VCC 0.8 VCC tCF PWL X0 0.2 VCC 0.2 VCC 0.2 VCC • Clock application conditions Using a crystal oscillator or ceramic oscillator X0 X1 FCH C1 C2 Using an external clock signal X0 X1 Open FCH 41 MB89530 Series • X0A, X1A timing and application conditions tLCYL PWLH tCR 0.8 VCC 0.8 VCC tCF PWLL X0A 0.2 VCC 0.2 VCC 0.2 VCC • Clock application conditions Using a crystal oscillator or ceramic oscillator X0A X1A FCL C1 C2 Using an external clock signal X0A X1A Open FCL (4) Instruction Cycle Parameter Symbol Rated value 4/FCH, 8/FCH, 16/FCH, 64/FCH tinst 2/FCL (AVss = Vss = 0 V, TA = −40 °C to +85 °C) Unit µs µs Remarks Operating at FCH = 12.5 MHz (4/FCH) tinst = 0.32 µs Operating at FCL = 32.768 kHz tinst = 61.036 µs Instruction cycle (minimum instruction execution time) 42 MB89530 Series (5) Serial I/O Timing (VCC = 3.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C) Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name SCK, UCK SCK, SO, UCK, UO SI, SCK, UI, UCK SCK, SI, UCK, UI SCK, UCK SCK, SO, UCK, UO SI, SCK, UI, UCK SCK, SI, UCK, UI External clock operation Internal clock operation Condition Value Min 2 tinst −200 200 200 1 tinst 1 tinst 0 200 200 Max  +200     200   Unit Remarks µs ns ns ns µs µs ns ns ns Parameter Serial clock cycle time SCK↓→SO Valid SI→SCK↑ SCK↑→ valid SI hold time Serial clock “H” pulse width ÉSerial clock “L” pulse width SCK↓→SO time Valid SI→SCK↑ SCK↑→ valid SI hold time Note : For tinst see “ (4) Instruction Cycle”. Internal shift clock mode tSCYC SCK UCK 0.8 V tSLOV 2.4 V 0.8 V SO UO 2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC SI UI 0.8 VCC 0.2 VCC External shift clock mode tSLSH tSHSL 0.8 VCC 0.2 VCC tSLOV 0.2 VCC 0.8 VCC SCK UCK SO UO 2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC SI UI 0.8 VCC 0.2 VCC 43 MB89530 Series (6) Peripheral Input Timing (VCC = 3.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C) Pin name INT10 to INT13, INT20 to INT27, EC, PWC, PWCK Condition    ADST  Value Min 2 tinst 2 tinst 28 tinst 28 tinst Max     Unit µs µs µs µs Remarks Parameter Peripheral input “H” level pulse width 1 Peripheral input “L” level pulse width 1 Peripheral input “H” level pulse width 2 Peripheral input “L” level pulse width 2 Symbol tILIH1 tIHIL1 tILIH2 tIHIL2 Note : For tinst see “ (4) Instruction Cycle”. tIHIL1 0.8 VCC tILIH1 0.8 VCC EC, INT, PWC, PWCK 0.2 VCC 0.2 VCC ADST tIHIL2 0.8 VCC tILIH2 0.8 VCC 0.2 VCC 0.2 VCC 44 MB89530 Series (7) I2C Timing Pin Condition name SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SCL SDA SDA SCL SCL SDA SDA               (VCC = 3.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C) Symbol Parameter Start condition output Stop condition output Start condition detection Stop condition detection Restart condition output Restart condition detection SCL output “L” width SCL output “H” width SDA output delay time Setup after SDA output interrupt interval SCL input “L” width SCL input “H” width SDA input setup SDA input hold Value Min 1 / 4 tinst × m × n − 20 Max 1 / 4 tinst × m × n + 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks Master only Master only tSTA tSTO tSTA tSTO tSTASU tSTASU tLOW tHIGH tDO tDOSU tLOW tHIGH tSU tHO 1 / 4 tinst × 1 / 4 tinst × (m × n + 8) − 20 (m × n + 8) + 20 1 / 4 tinst × 6 + 40 1 / 4 tinst × 6 + 40   1 / 4 tinst × 1 / 4 tinst × (m × n + 8) − 20 (m × n + 8) + 20 1 / 4 tinst × 4 + 40 1 / 4 tinst × m × n − 20  1 / 4 tinst × m × n + 20 Master only Master only Master only 1 / 4 tinst × 1 / 4 tinst × (m × n + 8) − 20 (m × n + 8) + 20 1 / 4 tinst × 4 − 20 1 / 4 tinst × 4 + 20 1 / 4 tinst × 4 − 20 1 / 4 tinst × 6 + 40 1 / 4 tinst × 2 + 40 40 0      Notes : • For tinst see “ (4) Instruction Cycle”. • The value “m” in the above table is the value from the shift clock frequency setting bits (CS4-CS3) in the clock control register “ICCR”. For details, refer to the register description in the hardware manual. • The value ’n’ in the above table is the value from the shift clock frequency setting bits (CS2-CS0) in the clock control register “ICCR”. For details, refer to the register description in the hardware manual. • tDOSU appears when the interrupt period is longer than the SCL “L” width. • The rated values for SDA and SCL assume a start up time of 0 ns. 45 MB89530 Series • I2C interface [Data sending (master/slave) ] tDO SDA ACK tSTASU SCL tSTA tLOW tHO 1 9 tDO tSU tSU tDOSU • I2C interface [Data sending (master/slave) ] tSU SDA ACK tHIGH SCL 6 7 8 9 tLOW tSTO tHO tDO tDO tDOSU 46 MB89530 Series 5. A/D Converter Electrical Characteristics (1) MB89537/538/537C/538C Parameter Resolution capability Total error Linear error Differential linear error Zero transition voltage Full scale transition voltage Inter-channel variation Conversion time Sampling time Analog input current Analog input voltage Reference voltage Reference voltage supply current * : Includes sampling time (2) MB89F538L Parameter Resolution capability Total error Linear error Differential linear error Zero transition voltage Full scale transition voltage Inter-channel variation Conversion time Sampling time Analog input current Analog input voltage Reference voltage Reference voltage supply current * : Includes sampling time 47 IAIN VAIN  IR IRH AVR A/D running A/D off AN0 to AN7   VOT VFST   Symbol Pin name Symbol Pin name (VCC = 2.4 V to 3.6 V, AVSS = VSS = 0 V, TA = −40 °C to +85 °C) Value Condition Unit Remarks Min Typ Max      AVR = AVCC     10 ±3.0 ±2.5 ±1.9 bit LSB LSB LSB mV mV LSB µs µs µA V V µA µA * AVCC = VCC  VOT VFST  IAIN VAIN  IR IRH  AVSS − 1.5 AVSS + 0.5 AVSS + 2.5 LSB LSB LSB AVR − 3.5 AVR − 1.5 AVR + 1.5 LSB LSB LSB     60 tinst 16 tinst    200  4.0   10 AVR AVCC  5 AN0 to AN7 AVR   AVSS AVSS + 2.4 A/D running A/D off   (VCC = 2.4 V to 3.6 V, AVSS = VSS = 0 V, TA = −40 °C to +85 °C) Value Condition Unit Remarks Min Typ Max          10 ±3.0 ±2.5 ±1.9 bit LSB LSB LSB mV mV LSB µs µs µA V V µA µA * AVCC = VCC AVR = AVCC AVSS − 1.5 AVSS + 0.5 AVSS + 2.5 LSB LSB LSB AVR − 3.5 AVR − 1.5 AVR + 1.5 LSB LSB LSB     0 AVSS + 2.4    60 tinst 16 tinst    200  4.0   10 AVR AVCC  5 MB89530 Series (3) MB89P538/PV530 Parameter Resolution capability Total error Linear error Differential linear error Zero transition voltage Full scale transition voltage Inter-channel variation Conversion time Sampling time Analog input current Analog input voltage Reference voltage Reference voltage supply current * : Includes sampling time IAIN VAIN  IR IRH AVR A/D running A/D off AN0 to AN7   VOT VFST  AVR = AVCC  Symbol Pin name (VCC = 2.4 V to 3.6 V, AVSS = VSS = 0 V, TA = −40 °C to +85 °C) Value Condition Unit Remarks Min Typ Max          10 ±3.0 ±2.5 ±1.9 bit LSB LSB LSB mV mV LSB µs µs µA V V µA µA * AVCC = VCC AVSS − 1.5 AVSS + 0.5 AVSS + 2.5 LSB LSB LSB AVR − 3.5 AVR − 1.5 AVR + 1.5 LSB LSB LSB     0 AVSS + 3.5    60 tinst 16 tinst    400  4.0   10 AVR AVCC  5 48 MB89530 Series (4) A/D Converter Terms and Definitions • Resolution The level of analog variation that can be distinguished by the A/D converter. • Linear error (unit : LSB) The deviation between the value along a straight line connecting the zero transition point (“00 0000 0000”←→“00 0000 0001”) of a device and the full-scale transition point (“11 1111 1110”←→“11 1111 1111”) , compared with the actual conversion values obtained. • Differential linear error (Unit : LSB) The deviation from the theoretical input voltage required to produce a change of 1 LSB in output code. • Total error (Unit : LSB) The difference between theoretical conversion value and actual conversion value. Theoretical input/output characteristics 3FF 3FE VFST 3FF 3FE Total error Actual conversion characteristics (1 LSB I N + 0.5 LSB) Digital output 004 003 002 001 0.5 LSB AVSS AVR VOT 1 LSB Digital output 3FD 1.5 LSB 3FD 004 VNT 003 002 001 AVSS Actual conversion characteristics Theoretical characteristics AVR Analog input VFST − VOT 1022 Analog input VNT − {1 LSB × N + 0.5 LSB} 1 LSB 1 LSB = (V) Total error in digital output N = (Continued) 49 MB89530 Series (Continued) Zero transition error 004 Full-scale transition error Theoretical characteristics 3FF Actual conversion characteristics Digital output 003 Actual conversion characteristics Digital output 3FE 002 001 Actual conversion characteristics VOT (actual measurement value) 3FD VFST (actual measurement value) Actual conversion characteristics 3FC AVSS Analog input Analog input AVR Linear error 3FF 3FE Differential linear error Theoretical characteristics N+1 Actual conversion characteristics (1 LSB × N + VOT) Digital output VFST (actual VNT measure004 003 002 001 Digital output 3FD Actual conversion characteristics V (N + 1) T N ment value) Actual conversion characteristics Theoretical characteristics VOT (actual measurement value) AVR N−1 VNT N−2 AVSS Actual conversion characteristics AVSS Analog input Analog input linear = error in digital output N VNT − {1 LSB × N + VOT} 1 LSB Analog input AVR Differential linear = V (N + 1) T − VNT −1 1 LSB error in digital output N 50 MB89530 Series (5) Precautionary Information • Input Impedance of Analog Input Pins The A/D converter has a sample & hold circuit as shown below, which uses a sample-and-hold capacitor to obtain the voltage at the analog input pin for 8 instruction cycles following the start of A/D conversion. For this reason if the external circuits providing the analog input signal have high output impedance, the analog input voltage may not stabilize within the analog input sampling time. It is therefore recommended that the output impedance of external circuits be reduced to 10 kΩ or less. • MB89537/537C/538/538C/F538L Analog Input Equivalent Circuit Sample-and-hold circuit C = 49 pF Analog input pin If analog input impedance is 10 kΩ or more, the use of a capacitor of approximately 0.1 µF is recommended. R = 7.1 kΩ Comparator Closes 8 instruction cycles after the start of A/D conversion Analog channel selector • MB89P538 and MB89PV530 Analog Input Equivalent Circuit Sample-and-hold circuit C = 64 pF Analog input pin R = 3 kΩ Comparator Closes 8 instruction cycles after the start of A/D conversion Analog channel selector If analog input impedance is 10 kΩ or more, the use of a capacitor of approximately 0.1 µF is recommended. • About error The smaller the absolute value |AVR - AVss| is, the greater the relative error becomes. 51 MB89530 Series 6. Flash Memory • Flash memory programming/erase characteristics Parameter Conditions Value Min  Typ Max Unit Remarks Per 1 sector, Sector erase Constant value indetime pendent with sector caTA = +25 °C, pacitance VCC = 3.3 V ProgramPer 1 byte ming time Chip erase time Program/Erase cycle  1 15 s *   10,000 8 5  3600   µs s cycle * * : Excludes internal programming time before erase. 52 MB89530 Series s EXAMPLE CHARACTERISTICS (1) Power Supply Current (External Clock) MB89538 ICC1 vs. VCC 7 (TA = 25 ˚C) 6 5 ICC1 (mA) 12.5 MHz 10 MHz 8 MHz MB89538 ICCS1 vs. VCC 2.5 (TA = 25 ˚C) 2 ICCS1 (mA) 10 MHz 12.5 MHz 4 3 2 1 0 1 2 3 VCC (V) 4 1.5 1 0.5 0 8 MHz 5 MHz 2 MHz 1 MHz 5 MHz 2 MHz 1 MHz 5 1 2 3 VCC (V) 4 5 (2) “H” Level Input Voltage/ “L” Level Input Voltage (CMOS Input) MB89538 VIN vs. VCC 4 (TA = 25 ˚C) 3 VIN (V) 2 1 0 2 2.5 3 VCC (V) 3.5 4 (3) “H” Level Input Voltage / ”L” Level Input Voltage (Hysteresis Input) MB89538 VIN vs. VCC 3 (TA = 25 ˚C) VIH 2 VIN (V) VIL 1 0 2 2.5 3 VCC (V) 3.5 4 53 MB89530 Series (4) AD Converter Characteristic Example MB89538 Linearity Error 3 2.5 2 1.5 1 (VCC = AVR = 3 V, Fc = 10 MHz) Error (LSB) 0.5 0 -0.5 -1 -1.5 -2 -2.5 -3 0 128 256 384 512 640 768 896 1024 Conversion characteristic MB89538 Differential linearity error 2.5 2 1.5 (VCC = AVR = 3 V, Fc = 10 MHz) Error (LSB) 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 128 256 384 512 640 768 896 1024 Conversion characteristic MB89538 Total Error 4 3 (VCC = AVR = 3 V, Fc = 10 MHz) Error (LSB) 2 1 0 -1 -2 -3 -4 0 128 256 384 512 640 768 896 1024 Conversion characteristic 54 MB89530 Series s MASK OPTIONS Part number No Method of specification MB89537 MB89537C MB89538 MB89538C Specify at time of mask order MB89F538L-101 MB89F538L-201 Setting not possible MB89P538-101 MB89P538-201 Setting not possible MB89PV530-101 MB89PV530-201 Setting not possible 1 Main clock Select oscillator stabilization wait period (FCH * = 10 MHz) approx.214/FCH * 218/FCH * 218/FCH * 218/FCH * Selection available (approx.1.6 ms) (approx. 26.2 ms) (approx. 26.2 ms) (approx. 26.2 ms) approx.217/FCH * (approx.13.1 ms) approx.218/FCH * (approx.26.2 ms) Clock mode selection • 2-system clock mode • 1-system clock mode Selection available • 101 : 1-system clock mode • 201 : 2-system clock mode 2 * : FCH : Main clock frequency 55 MB89530 Series s ORDERING INFORMATION Part number MB89537P MB89537CP MB89538P MB89538CP MB89F538L-101P MB89F538L-201P MB89P538-101P MB89P538-201P MB89537PF MB89537CPF MB89538PF MB89538CPF MB89F538L-101PF MB89F538L-201PF MB89P538-101PF MB89P538-201PF MB89537PFM MB89537CPFM MB89538PFM MB89538CPFM MB89F538L-101PFM MB89F538L-201PFM MB89P538-101PFM MB89P538-201PFM MB89537PFV MB89537CPFV MB89538PFV MB89538CPFV MB89F538L-101PV4 MB89F538L-201PV4 MB89F538-101PV* MB89F538-201PV* MB89PV530C-101 MB89PV530C-201 MB89PV530CF-101 MB89PV530CF-201 * : Only for ES Package Remarks DIP-64P-M01 MB89537P and MB89538P do not have I2C functions. FPT-64P-M06 MB89537PF and MB89538PF do not have I2C functions. FPT-64P-M09 MB89537PFM and MB89538PFM do not have I2C functions. FPT-64P-M03 MB89537PFV and MB89538PFV do not have I2C functions. LCC-64P-M19 LCC-64P-M16* MDP-64C-P02 MQP-64C-P01 56 MB89530 Series s PACKAGE DIMENSIONS 64-pin, Plastic SH-DIP (DIP-64P-M01) 58.00 –0.55 2.283 –.022 +0.22 +.009 Note: Pins width and pins thickness include plating thickness. INDEX-1 17.00±0.25 (.669±.010) INDEX-2 4.95 –0.20 .195 –.008 +0.70 +.028 0.70 –0.19 .028 –.007 +0.50 +.020 3.30 –0.30 .130 +0.20 +.008 –.012 +0.40 +.016 0.27±0.10 (.011±.004) 1.378 –0.20 .0543 –.008 1.778(.0700) 0.47±0.10 (.019±.004) 0.25(.010) M 19.05(.750) 0~15° 1.00 –0 +0.50 +.020 .039 –.0 C 2001 FUJITSU LIMITED D64001S-c-4-5 Dimensions in mm (inches). Note: The values in parentheses are reference values (Continued) 57 MB89530 Series 64-pin, Plastic LQFP (FPT-64P-M03) 12.00±0.20(.472±.008)SQ * 10.00±0.10(.394±.004)SQ 48 33 Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 0.145±0.055 (.006±.002) 49 32 Details of "A" part 0.08(.003) 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) INDEX 64 17 0˚~8˚ "A" 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) LEAD No. 1 16 0.50(.020) 0.20±0.05 (.008±.002) 0.08(.003) M C 2003 FUJITSU LIMITED F64009S-c-5-8 Dimensions in mm (inches). Note: The values in parentheses are reference values (Continued) 58 MB89530 Series 64-pin, Plastic QFP (FPT-64P-M06) 24.70±0.40(.972±.016) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. * 20.00±0.20(.787±.008) 51 33 0.17±0.06 (.007±.002) 52 32 18.70±0.40 (.736±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 3.00 –0.20 .118 –.008 +0.35 +.014 (Mounting height) 64 20 0~8˚ 1 19 1.00(.039) 0.42±0.08 (.017±.003) 0.20(.008) M 0.25 –0.20 1.20±0.20 (.047±.008) +0.15 +.006 .010 –.008 (Stand off) "A" 0.10(.004) C 2003 FUJITSU LIMITED F64013S-c-5-5 Dimensions in mm (inches). Note: The values in parentheses are reference values (Continued) 59 MB89530 Series 64-pin, Plastic LQFP (FPT-64P-M09) 14.00±0.20(.551±.008)SQ Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. * 12.00±0.10(.472±.004)SQ 48 33 0.145±0.055 (.0057±.0022) 49 32 0.10(.004) Details of "A" part 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) 0.25(.010) INDEX 0~8˚ 64 17 1 16 "A" 0.65(.026) 0.32±0.05 (.013±.002) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) (Stand off) 0.13(.005) M C 2003 FUJITSU LIMITED F64018S-c-3-5 Dimensions in mm (inches). Note: The values in parentheses are reference values (Continued) 60 MB89530 Series 64-pin, Ceramic MDIP (MDP-64C-P02) 56.90±0.64 (2.240±.025) 0°~9° 15.24(.600) TYP 18.75±0.30 (.738±.012) 19.05±0.30 (.750±.012) INDEX AREA 2.54±0.25 (.100±.010) 33.02(1.300)REF 0.25±0.05 (.010±.002) 10.16(.400)MAX 1.27±0.25 (.050±.010) 1.778±0.25 (.070±.010) 0.46 –0.08 +.005 .018 –.003 55.12(2.170)REF +0.13 0.90±0.13 (.035±.005) 3.43±0.38 (.135±.015) C 1994 FUJITSU LIMITED M64002SC-1-4 Dimensions in mm (inches). Note: The values in parentheses are reference values (Continued) 61 MB89530 Series 64-pin, Ceramic MQFP (MQP-64C-P01) 18.70(.736)TYP 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) 12.00(.472)TYP +0.40 +.016 –.008 INDEX AREA 1.20 –0.20 .047 1.00±0.25 (.039±.010) 1.00±0.25 (.039±.010) 1.27±0.13 (.050±.005) 22.30±0.33 (.878±.013) 24.70(.972) TYP 0.30(.012) TYP 18.12±0.20 12.02(.473) (.713±.008) TYP 10.16(.400) 14.22(.560) TYP TYP 18.00(.709) TYP 1.27±0.13 (.050±.005) 0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP 0.40±0.10 (.016±.004) 0.40±0.10 (.016±.004) 1.20 –0.20 .047 –.008 +0.40 +.016 0.50(.020)TYP 10.82(.426) 0.15±0.05 MAX (.006±.002) C 1994 FUJITSU LIMITED M64004SC-1-3 Dimensions in mm (inches). Note: The values in parentheses are reference values (Continued) 62 MB89530 Series 64-pin, Plastic BCC (LCC-64P-M19) (0.80(.031)MAX) (Mount height) 33 33 8.20(.323)TYP 8.10(.319)TYP 0.50(.020) TYP 0.50±0.10 (.020±.004) 49 9.00±0.10(.354±.004) 49 0.50(.020) TYP 8.25(.325) REF INDEX AREA 9.00±0.10 (.354±.004) 7.00(.276) REF 8.20(.323) TYP 8.10(.319) TYP 0.50±0.10 (.020±.004) "A" 1 17 0.075±0.025 17 "C" (.003±.001) (Stand off) Details of "A" part 0.14(.006)MIN. 0.70±0.06 (.028±.002) 7.00(.276)REF 8.25(.325)REF Details of "B" part 0.55±0.06 (.022±.002) C0.2(.008) "B" 1 Details of "C" part 0.55±0.06 (.022±.002) 0.05(.002) 0.60±0.06 (.024±.002) C 2002 FUJITSU LIMITED C64019S-c-1-1 0.30±0.06 (.012±.002) 0.30±0.06 (.012±.002) 0.55±0.06 (.022±.002) 0.55±0.06 (.022±.002) Dimensions in mm (inches). Note: The values in parentheses are reference values (Continued) 63 MB89530 Series (Continued) 64-pin, Plastic BCC (LCC-64P-M16) 8.20(.323)TYP 7.00(.276)REF 9.00±0.10(.354±.004) 49 33 (0.80(.031)MAX) (Mount height) 0.50(.020) TYP 33 0.50±0.10 (.020±.004) 49 0.50(.020) TYP 8.15(.321) REF 7.00(.276) REF 0.50±0.10 (.020±.004) 9.00±0.10 (.354±.004) INDEX AREA 8.20(.323) TYP 1 17 17 0.075±0.025 (.003±.001) (Stand off) Details of "A" part "C" "A" 8.15(.321)REF "B" 1 Details of "B" part 0.40±0.06 (.016±.002) C0.2(.008) 0.45±0.06 (.018±.002) Details of "C" part 0.45±0.06 (.018±.002) 0.14(.006) MIN 0.05(.002) 0.30±0.06 (.012±.002) C 0.45±0.06 (.018±.002) 0.45±0.06 (.018±.002) 2001 FUJITSU LIMITED C64016S-c-2-1 Dimensions in mm (inches). Note: The values in parentheses are reference values 64 MB89530 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0303 © FUJITSU LIMITED Printed in Japan