MB89816APF

FUJITSU SEMICONDUCTOR DATA SHEET DS07-12507-3E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89810A Series MB89816A/P817A s DESCRIPTION The MB89810A series is a line of single-chip microcontrollers based on the F2MC*-8L CPU core which can operate at low voltage but at high speed. The microcontrollers contain peripheral function such as timer, serial interface, a UART, and an external interrupt. The MB89810A series is applicable to a wide range of applications from welfare products to industrial equipment, including portable devices. *: F2MC stands for FUJITSU Flexible Microcontroller. s FEATURES High speed processing at low voltage Minimum execution time: 0.8 µs/3.0 V, 1.33 µs/2.2 V • F2MC-8L family CPU core Instruction set optimized for controllers : Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc. • Four types of timers 8-bit PWM timer: 2 channels (also serve as reload timers) 16-bit timer/counter 21-bit time-base timer (Continued) s PACKAGE 64-pin Plastic QFP (FPT-64P-M06) MB89810A Series (Continued) • Two serial interface 8-bit synchronous serial (Switchable transfer direction allows communication with various equipment.) UART (5-, 7-, or 8-bit transfer capable) • External interrupt: 8 channels Eight channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). • Low-power consumption modes Stop mode (Oscillation stops to minimize the current consumption) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal) 2 MB89810A Series s PRODUCT LINEUP Part number Parameter Classification ROM size MB89816A Mass-production product (mask ROM products) 24 K × 8 bits (internal mask ROM) MB89P817A One-time PROM product (for evaluation and development) 32 K × 8 bits (internal PROM, programming with general-purpose EPROM programmer) 2048 × 8 bits Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: Input ports: Output ports: I/O ports (N-ch open-drain): I/O ports (CMOS): Total: 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.8 µs/5 MHz 7.2 µs/5 MHz 8 (All also serve as peripherals.) 8 5 (for LED driving) 32 (14 ports also serve as peripherals.) 53 RAM size CPU functions Ports 8-bit PWM timer Two internal channels 8-bit reload timer operation (toggled output capable, operating clock cycle: 3 different cycles) 8-bit resolution PWM operation (conversion cycle: 3 different cycles) 16-bit timer operation 16-bit event counter operation 5-, 7-, or 8-bit transfer capable Built-in baud rate generator Clock synchronous/asynchronous data transfer capable 8-bits LSB-first/MSB first selectability One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks) 8 independent channels (edge selection, interrupt vector, source flag) 4 channels: Level detection (level selectable) 4 channels: Edge detection (edge selectable) Used also for wake-up from the stop/sleep mode. (Edge detection is also permitted in stop mode.) 8-bit timer/counter UART 8-bit Serial I/O External interrupt (Continued) 3 MB89810A Series (Continued) Part number Parameter Watch interrupt Watchdog timer reset Standby mode Process Package Operating voltage 2.2 V to 6.0 V* MB89816A MB89P817A Interrupt cycles: 4 different cycles (subclock) Reset occurrence cycle: 839 ms/5 MHz Sleep mode, stop mode CMOS FPT-64P-M06 2.7 V to 6.0 V* *: Varies with conditions such as the operating frequency. (See section “s Electrical Characteristics.”) s DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the OTPROM (one-time PROM) products, verify its differences from the product that will actually be used. 2. Current Consumption When operated at low speed, the product with an OTPROM will consume more current than the product with a mask ROM. However, the same is current consumption in sleep/stop modes (For more information, see “s ELECTRICAL CHARACTERISTICS”) . 3. Mask Options Functions that can be selected as options and how to designate these options vary with product. Before using options, check “s MASK OPTIONS”. Take particular care on the following point: For MB89816A, pull-up resistor option can be set for P50 to P54. 4 MB89810A Series s PIN ASSIGNMENT (Top view) P47/SCL2 P46/RXD2 P45/TXD2 P44/SCL1 P43/RXD1 P42/TXD1 P41/EC VCC P40 P54 P53 P52 P51 P30/PWE P31/SCK P32/SO P33/SI P34/PWO P35/PWI P36/PTO1 P37/PTO2 P60/INT0 P61/INT1 P62/INT2 VCC P63/INT3 P64/INT4 P65/INT5 P66/INT6 P67/INT7 X0A X1A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P50 VSS P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 RST MOD0 MOD1 X0 X1 VSS P27 P26 P25 P24 P23 P22 P21 (FPT-64P-M06) 5 MB89810A Series s PIN DESCRIPTION Pin no. 23 24 18 19 21 22 20 Pin name X0 X1 X0A X1A MOD0 MOD1 RST C B Operating mode selection pins Connect directly these pins directly to VSS. Reset I/O pin This pin is an N-ch open-drain output type with a pull-up resistor and a hysteresis input type. “L” is output from this pin by an internal reset source. The internal circuit is initialized by the input of “L”. General-purpose I/O ports A pull-up resistor option is provided. These ports have the port output inverting function. General-purpose I/O ports A pull-up resistor option is provided. These ports have the port output inverting function. General-purpose output ports These ports have the port output inverting function. General-purpose output ports General-purpose I/O port A pull-up resistor option is provided. Also serves as a pulse width detection enable input (PWE). PWE input is hysteresis input. General-purpose I/O port A pull-up resistor option is provided. Also serves as the clock I/O for the 8-bit serial I/O (SCK). SCK input is hysteresis input. General-purpose I/O port A pull-up resistor option is provided. Also serves as the data output for the 8-bit serial I/O (SO). General-purpose I/O port A pull-up resistor option is provided. Also serves as the data input for the 8-bit serial I/O (SI). SI input is hysteresis input. General-purpose I/O port A pull-up resistor option is provided. Also serves as a pulse width detection output (PWO). General-purpose I/O port A pull-up resistor option is provided. Also serves as a pulse width detection input (PWI). PWI input is hysteresis input. General-purpose I/O port A pull-up resistor option is provided. Also serves as the toggle output for the 8-bit PWM timer 1 (PTO1). I Subclock crystal oscillator pins Circuit type A Main clock oscillator pins Function 49 to 42 P00 to P07 D 41 to 34 P10 to P17 D 33 to 30 29 to 26 1 P20 to P23 P24 to P27 P30 /PWE F F E 2 P31/SCK E 3 P32/SO D 4 P33/SI E 5 P34/PWO D 6 P35/PWI E 7 P36/PTO1 D (Continued) 6 MB89810A Series (Continued) Pin no. 8 Pin name P37/PTO2 Circuit type D Function General-purpose I/O port A pull-up resistor option is provided. Also serves as the toggle output for the 8-bit PWM timer 2 (PTO2). General-purpose I/O port A pull-up resistor option is provided. General-purpose I/O port A pull-up resistor option is provided. Also serves as a 16-bit timer/counter input (EC). EC input is hysteresis input. General-purpose I/O port A pull-up resistor option is provided. Also serves as the data output 1 for the UART (TXD1). General-purpose I/O port A pull-up resistor option is provided. Also serves as the data input 1 for the UART (RXD1). RXD1 input is hysteresis input. General-purpose I/O port A pull-up resistor option is provided. Also serves as the clock I/O 1 for the UART (SCL1). SCL1 input is hysteresis input. General-purpose I/O port A pull-up resistor option is provided. Also serves as the data output 2 for the UART (TXD2). General-purpose I/O port A pull-up resistor option is provided. Also serves as the data input 2 for the UART (RXD2). RXD2 input is hysteresis input. General-purpose I/O port A pull-up resistor option is provided. Also serves as the clock I/O 2 for the UART (SCL2). SCL2 input is hysteresis input. N-channel open-drain I/O ports A pull-up resistor option is provided only for the MB89816A. General-purpose I/O ports A pull-up resistor option is provided. Also serve as an external interrupt input (INT0 to INT2). These ports are a hysteresis input type. General-purpose I/O ports A pull-up resistor option is provided. Also serve as an external interrupt input (INT3 to INT7). These ports are a hysteresis input type. Power supply pin Power supply (GND) pin 56 58 P40 P41/EC D E 59 P42/TXD1 D 60 P43/RXD1 E 61 P44/SCL1 E 62 P45/TXD2 D 63 P46/RXD2 E 64 P47/SCL2 E 51 to 55 9 to 11 P50 to P54 P60/INT0 to P62/INT2 G H 13 to 17 P63/INT3 to P67/INT7 H 12, 57 25, 50 VCC VSS – – 7 MB89810A Series s I/O CIRCUIT TYPE Type A X1 Circuit Remarks • Main clock • At an oscillation feedback resistor of approximately 1 MΩ (1 to 5 MHz) • CR oscillator circuit selectability X0 Standby control signal B C R P-ch • At an output pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V • Hysteresis input N-ch D R P-ch P-ch • CMOS output • CMOS input N-ch • Pull-up resistor optional E R P-ch P-ch • CMOS output • CMOS input • Hysteresis input (resource input) N-ch • Pull-up resistor optional (Continued) 8 MB89810A Series (Continued) Type F P-ch Circuit • CMOS output Remarks N-ch G R P-ch • N-ch open-drain output • CMOS input N-ch • Pull-up resistor optional (only for the MB89816A) H • Hysteresis input • Pull-up resistor optional I X1A X0A • Subclock (30 to 40 kHz) • At an oscillation feedback resistor of approximately 10 MΩ 9 MB89810A Series s HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “s Electrical Characteristics” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 4. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode. 10 MB89810A Series s PROGRAMMING TO THE EPROM ON THE MB89P817A In EPROM mode, the MB89P817A functions equivalent to the MBM27C256A. This allows the OTPROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. • Writing Procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0007H to 7FFFH (note that addresses 8007H to FFFFH while operating as operating mode assign to 0007H to 7FFFH in EPROM mode). Load option data into addresses 0000H to 0006H of the EPROM programmer. (For information about each corresponding option, see “• OTPROM Option Bit Map.”) (3) Program with the EPROM programmer. • Memory Space Memory space is diagrammed below. Normal operating mode 0000H I/O 0080H 0100H 0200H EPROM mode (Corresponding address on the EPROM programmer) Register RAM 0880H External area 8000H 0000H Option area 8007H 0007H Option area ROM Program area (PROM) FFFFH 7FFFH 11 MB89810A Series • Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM (one-time PROM) microcomputer program. Program, verify Aging +150 °C, 48 h Data verification Assembly • Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. • EPROM Programmer Socket Adapter Package FPT-64P-M06 Compatible socket adapter ROM-64QF-28DP-8L Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 Note: Connect the jumper pin to VSS when using. Depending on the EPROM programmer, inserting a capacitor of approx. 0.1 µF between VPP and VSS or VCC and VSS can stabilize programming operations. 12 MB89810A Series • OTPROM Option Bit Map Bit 7 Vacancy 000 Readable 0H and writable P07 000 Pull-up 1H 1: No 0: Yes P17 000 Pull-up 2H 1: No 0: Yes P37 000 Pull-up 3H 1: No 0: Yes P47 000 Pull-up 4H 1: No 0: Yes Vacancy 000 Readable 5H and writable Vacancy 000 Readable 6H and writable Bit 6 Vacancy Readable and writable P06 Pull-up 1: No 0: Yes P16 Pull-up 1: No 0: Yes P36 Pull-up 1: No 0: Yes P46 Pull-up 1: No 0: Yes Vacancy Readable and writable Vacancy Readable and writable Bit 5 Vacancy Readable and writable P05 Pull-up 1: No 0: Yes P15 Pull-up 1: No 0: Yes P35 Pull-up 1: No 0: Yes P45 Pull-up 1: No 0: Yes Vacancy Readable and writable Vacancy Readable and writable Bit 4 Single-clock setting 1: Dualclock 0: Singleclock P04 Pull-up 1: No 0: Yes P14 Pull-up 1: No 0: Yes P34 Pull-up 1: No 0: Yes P44 Pull-up 1: No 0: Yes P64 Pull-up 1: No 0: Yes Vacancy Readable and writable Bit 3 Reset pin output 1: Enabled 0: Disabled Bit 2 Bit 1 Bit 0 Power-on Oscillation stabilization time reset 4/F 14 1: Enabled 00 217 CH 01 218/FCH 0: Disabled 10 2 /FCH 11 2 /FCH P03 Pull-up 1: No 0: Yes P13 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes P43 Pull-up 1: No 0: Yes P63 Pull-up 1: No 0: Yes Oscillator type 1: Crystal 0: CR P02 Pull-up 1: No 0: Yes P12 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P42 Pull-up 1: No 0: Yes P62 Pull-up 1: No 0: Yes P67 Pull-up 1: No 0: Yes P01 Pull-up 1: No 0: Yes P11 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes P41 Pull-up 1: No 0: Yes P61 Pull-up 1: No 0: Yes P66 Pull-up 1: No 0: Yes P00 Pull-up 1: No 0: Yes P10 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes P40 Pull-up 1: No 0: Yes P60 Pull-up 1: No 0: Yes P65 Pull-up 1: No 0: Yes Note: • Each bit is set to ’1‘ as the initialized value. • Do not write ’0‘ to the vacant bit. 13 MB89810A Series s BLOCK DIAGRAM X0 X1 Main clock oscillator Time-base timer Clock controlletr 8-bit PWM timer 2 P37/PTO2 X0A X1A Subclock oscillator 8-bit PWM timer 1 Port 3 P36/PTO1 RST Reset circuit (WDT) Internal bus 8-bit serial I/O 1 P31/SCK P33/SI P32/SO 8 P0 0 t o P07 8 P1 0 t o P17 Port 0 and port 1 CMOS I/O port Pulse width detection P 3 0 / P WE P 3 5 / P WI P 3 4 / P WO 8 P2 0 t o P27 Port 2 CMOS output port CMOS I/O port UART P44/SCL1 P47/SCL2 P43/RXD1 P46/RXD2 P42/TXD1 P45/TXD2 RAM (2048 × 8 bits) 16-bit timer/counter Port 4 P41/EC F2MC-8L CPU CMOS I/O port P40 ROM (24 K × 8 bits) Port 5 N-ch open-drain I/O port 5 P50 to P54 Other pins VCC × 2, VSS × 2 MOD0, MOD1 Input port 14 Port 6 External interrupt 8 8 P60/INT0 to P67/INT7 MB89810A Series s CPU CORE 1. Memory Space The microcontrollers of the MB89810A series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89810A series is structured as illustrated below. Memory Space MB89816A 0000H I/O 0080H 0100H Register MB89P817A 0000H I/O 0080H 0100H Register 0200H RAM 2 KB 0880H 0200H RAM 2 KB 0880H Not available Not available 8000H Optional PROM 8007H A000H ROM 24 KB PROM 32 KB FFFFH FFFFH 15 MB89810A Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): Accumulator (A): Temporary accumulator (T): Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS): A 16-bit register for indicating instruction storage positions A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register for index modification A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area A 16-bit register for storing a register pointer, a condition code 16 bits PC A T IX EP SP PS : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status Initial value FFFDH Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, 0 = 11 Other bits are undefined. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) Structure of the Program Status Register 15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 3 N 2 Z 1 V 0 C Vacancy Vacancy Vacancy IL1, 0 RP CCR 16 MB89810A Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area RP Lower OP codes b1 ↓ b0 ↓ “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag:Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag:Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. IL1, 0:Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 IL0 0 1 0 1 Interrupt level 1 2 3 Low = no interrupt High-low High N-flag:Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag:Set when an arithmetic operation results in 0. Cleared otherwise. V-flag:Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag:Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. 17 MB89810A Series The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 32 banks can be used on the MB89816A. The bank currently in use is indicated by the register bank pointer (RP). Register Bank Configuration This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area 18 MB89810A Series s I/O MAP Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH (R/W) (R/W) SMR SDR (R/W) (R/W) (R/W) (R/W) PIVE TMCR TCHR TCLR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (W) (R/W) (R) SYCC STBC WDTC TBCR WPCR PDR3 DDR3 PDR4 DDR4 PDR5 PDR6 Read/write (R/W) (W) (R/W) (W) (R/W) Register name PDR0 DDR0 PDR1 DDR1 PDR2 Register description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register Port 2 data register Vacancy Vacancy System clock control register Standby control register Watchdog timer control register Time-base timer control register Watch prescaler control register Port 3 data register Port 3 data direction register Port 4 data register Port 4 data direction register Port 5 data register Port 6 data register Vacancy Vacancy Vacancy Vacancy Vacancy Port inverting operation enable register 16-bit timer count register 16-bit timer count register (H) 16-bit timer count register (L) Vacancy Serial I/O mode register Serial I/O data register Vacancy Vacancy (Continued) 19 MB89810A Series (Continued) Address 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H to 7AH 7BH 7CH 7DH 7EH 7FH (W) (W) (W) Not available ILR1 ILR2 ILR3 ITR (R/W) (R/W) (R/W) (R/W) (R/W) PWCR EIC1 EIC2 EI2E EI2F (R/W) (R/W) (R/W) (W) (W) CNTR1 CNTR2 CNTR3 COMR2 COMR1 Read/write (R/W) (R/W) (R/W) (R/W) (R/W) Register name SMC1 SRC SSD SIDR/SODR SMC2 Register description UART serial I/O mode control register 1 UART serial I/O rate control register UART serial I/O status/data control register UART serial I/O data control register UART serial I/O mode control register 2 Vacancy Vacancy Vacancy PWM timer control register 1 PWM timer control register 2 PWM timer control register 3 PWM timer compare register 2 PWM timer compare register 1 Vacancy Vacancy Pulse width detection control register External interrupt 1 control register 1 External interrupt 1 control register 2 External interrupt 2 enable register External interrupt 2 flag register Vacancy Vacancy Vacancy Interrupt level register 1 Interrupt level register 2 Interrupt level register 3 Interrupt test register Note: Do not use vacancies. 20 MB89810A Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = 0.0 V) Parameter Power supply voltage Input voltage Output voltage “L” level maximum output current “L” level average output current “L” level total maximum output current “L” level total average output current “H” level maximum output current “H” level average output current “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature Symbol VCC VI1 VI2 VO1 VO2 IOL IOLAV1 IOLAV2 ∑IOL ∑IOLAV IOH IOHAV ∑IOH ∑IOHAV PD TA Tstg Value Min. VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 — — — — — — — — — — –40 –55 Max. VSS + 7.0 VCC + 0.3 VSS + 7.0 VCC + 0.3 VSS + 7.0 20 4 10 100 40 –20 –4 –50 –20 300 +85 +150 Unit V V V V V mA mA mA mA mA mA mA mA mA mW °C °C Remarks Except P50 to P54 P50 to P54 Except P50 to P54 P50 to P54 Peak value Average value except pins other than P50 to P54 Average value for P50 to P54 Peak value Average value Peak value Average value Peak value Average value WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 21 MB89810A Series 2. Recommended Operating Conditions (VSS = 0.0 V) Parameter Symbol Value Min. 2.2* Max. 6.0 6.0 6.0 VSS + 6.0 +85 Unit V V V V °C Remarks Normal operation assurance range MB89816A Normal operation assurance range MB89P817A Retains the RAM state in stop mode P50 to P54 (without pull-up resistor) Power supply voltage VCC 2.7* 1.5 Open-drain output pin application voltage Operating temperature VD TA VSS – 0.3 –40 *: These values vary with the operating frequency. See Figure 1. 6 Operating voltage (V) 5 Operating assurance range 4 3 2 1 2.0 5.0 1.0 3.0 4.0 Main clock operating frequency (MHz) (at an instruction cycle of 4/FCH) Note: The shaded area is assured only for the MB89816A Figure 1 Operating Voltage vs. Main Clock Operating Frequency (for MB89816A) WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 22 MB89810A Series 3. DC Characteristics (VCC = +5.0 V, VSS = 0.0 V, TA = –40 °C to +85 °C) Parameter Symbol Value Pin P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P54 (with pull-up resistor) RST, MOD0, MOD1, P60 to P67, Peripheral input for port 3 and port 4 P50 to P54 (without pull-up resistor) P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P54 RST, MOD0, MOD1, P60 to P67, Peripheral input for port 3 and port4 Condition Min. Typ. Max. Unit Remarks VIH — 0.7 VCC — VCC + 0.3 V “H” level input voltage VIHS — 0.8 VCC — VCC + 0.3 V VIHS2 — 0.8 VCC — VSS + 6.0 V VIL “L” level input voltage VILS — VSS – 0.3 — 0.3 VCC V — VSS – 0.3 — 0.2 VCC V “H” level output voltage VOH P00 to P07, P10 to P17, P20 to P27, P30 to P37, IOH = –2.0 mA P40 to P47 P00 to P07, P10 to P17, P20 to P27, P30 to P37, IOL = 1.8 mA P40 to P47, P50 to P54 P60 to P67 P50 to P54 RST IOL = 6 mA VCC = 3 V IOL = 4.0 mA 2.4 — — V VOL1 “L” level output voltage — — 0.4 V VOL2 VOL3 — — — — 0.5 0.4 V V Input leakage current (Hi-z output leakage current) Pull-up resistance ILI1 P00 to P07, P10 to P17, P20 to P27, P30 to P37, 0.45 V < VI < P40 to P47, P50 to P54, VCC P60 to P67, MOD0, MOD1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, VI = 0.0 V P50 to P54, P60 to P67, RST — — ±5 µA Without pullup resistor RPULL 25 50 100 kΩ With pull-up resistor (Continued) 23 MB89810A Series (Continued) (VCC = +5.0 V, VSS = 0.0 V, TA = –40 °C to +85 °C) Value Parameter Symbol Pin Condition Min. FCH = 5 MHz VCC = 5.0 V tinst = 0.8 µs FCH = 5 MHz VCC = 3.0 V tinst = 6.4 µs FCH = 5 MHz VCC = 5.0 V tinst = 0.8 µs FCH = 5 MHz VCC = 3.0 V tinst = 12.8 µs FCL = 32.768 kHz VCC = 3.0 V FCL = 32.768 kHz VCC = 3.0 V — — — — Typ. 4 4.8 0.4 1.0 Max. 6 7.5 0.6 1.5 mA mA mA mA MB89816A MB89P817A MB89816A MB89P817A Unit Remarks ICC1 ICC2 ICCS1 VCC — 1.2 1.8 mA Sleep mode ICCS2 — 0.3 0.5 mA Subclock mode MB89P817A Subclock sleep mode Watch mode Main clock stop mode at dual-clock system Subclock stop mode Main clock stop mode at single-clock system Power supply current* — — 50 500 15 100 700 50 µA µA µA ICCL ICCLS — ICCT VCC FCL = 32.768 kHz VCC = 3.0 V — — 15 µA ICCH FCL = 32.768 kHz VCC = 3.0 V — — 10 µA Input capacitance CIN Other than VCC and VSS f = 1 MHz — 10 — pF *: The measurement conditions of power supply current are as follows: the external clock and TA = +25 °C. 24 MB89810A Series 4. AC Characteristics (1) Reset Timing (VCC = +5.0 V±10 %, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C) Parameter RST “L” pulse width Symbol tZLZH Condition — Value Min. 48 tCH Max. — Unit ns Remarks Note: tCH is the cycle time of the main clock. tZLZH RST 0.2 VCC 0.2 VCC (2) Power-on Reset (AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C) Parameter Power supply rising time Power supply cut-off time Symbol tR tOFF Condition — Value Min. — 1 Max. 50 — Unit ms ms Remarks Power-on reset function only Due to repeated operations Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR 2.0 V 0.2 V tOFF 0.2 V 0.2 V VCC Note that a sudden increase in supply voltage may result in a power-on reset. When increasing the supply voltage during operation, voltage variation should be within twice the intended increment so that the voltage rises as smoothly as possible. 25 MB89810A Series (3) Clock Timing (AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C) Parameter Clock frequency Clock cycle time Symbol FCH FCL tCH tCL PWH PWL PWHL PWLL tCR tCF Pin X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0 Condition Value Min. 1 — 200 — Typ. — 32.768 — 30.5 — 15.2 — Max. 5 — 1000 — — — 10 Unit MHz kHz ns µs ns µs ns Remarks — Input clock pulse width Input clock rising/ falling time 20 — — External clock External clock X0 and X1 Timing and Conditions tCH PWH tCR 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC tCF PWL Main Clock Conditions When a crystal or ceramic resonator is used when an external clock is used X0 X1 X0 X1 Open When a CR oscillator is used X0 X1 26 MB89810A Series X0A and X1A Timings and Conditions tCL PWHL tCR 0.8 VCC X0A 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC tCF PWLL Subclock Conditions When a crystal or ceramic resonator is used when an external clock is used X0A X1A X0A X1A Open (4) Instruction Cycle Parameter Instruction cycle (Minimum execution time) Symbol Value (typ) 4/FC, 8/FC, 16/FC, 64/FC tinst 2/FCL µs Unit µs Remarks tinst = 0.8 µs when operating at FC = 5 MHz (4/FC) tinst = 61.036 µs when operating at FCL = 32.768 kHz Note: When operating at 5 MHz, the cycle varies with the set execution time. (5) Serial I/O Timings (VCC = +5.0 V±10 %, AVSS = VSS= 0.0 V, TA = –40 °C to +85 °C) Parameter Serial clock cycle time SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Symbol tSCYC1 tSLOV1 tIVSH1 tSHIX1 tSHSL tSLSH tSLOV2 tIVSH2 tSHIX2 Pin SCK SCK, SO SI, SCK SCK, SI SCK SCK, SO SI, SCK SCK, SI Condition Value Min. 2 tinst –200 1/2 tinst 1/2 tinst 1 tinst 1 tinst Max. — 200 — — — — 200 — — Unit Remarks ns ns ns ns ns ns ns ns ns Internal shift clock mode External shift clock mode 0 1/2 tinst 1/2 tinst Note: For information on tinst, see “ (4) Instruction Cycle”. 27 MB89810A Series (6) UART Timings (VCC = +5.0 V±10 %, AVSS = VSS= 0.0 V, TA = –40 °C to +85 °C) Parameter Serial clock cycle time SCL ↓ → TXDx time Valid RXDx → SCLx ↑ SCLx ↑ → valid RXDx hold time Serial clock “H” pulse width Serial clock “L” pulse width SCLx ↓ → TXDx time Valid RXDx → SCLx ↑ SCLx ↑ → valid RXDx hold time Notes: • • Symbol tSCYC tSLOV1 tIVSH1 tSHIX1 tSHSL tSLSH tSLOV2 tIVSH2 tSHIX2 Pin SCL1, SCL2 SCLx, TXDx RXDx, SCLx SCL1, RXD2 SCL1, SCL2 SCLx, TXDx RXDx, SCLx SCL1, RXD2 Condition Value Min. 2 tinst –200 Max. — 200 — — — — 200 — — Unit ns ns ns ns ns ns ns ns ns Remarks Internal shift clock mode 1/2 tinst 1/2 tinst 1 tinst 1 tinst External shift clock mode 0 1/2 tinst 1/2 tinst For information on tinst, see “ (4) Instruction Cycle”. The edge polarity for the SLCx input is assumed when LSEL bit = 0 for SMC2. The polarity is inverted when LSEL = 1. Internal Shift Clock Mode tSCYC SCK/SCLx 2.4 V 0.8 V t SLOV1 2.4 V 0.8 V tIVSH1 SI/RXDx 0.8 VCC 0.2 VCC tSHIX1 0.8 VCC 0.2 VCC 0.8 V SO/TXDx External Shift Clock Mode tSLSH SCK/SCLx 0.8 VCC 0.2 VCC 0.2 VCC tSLOV2 SO/TXDx 2.4 V 0.8 V tIVSH2 SI/RXDx 0.8 VCC 0.2 VCC tSHIX2 0.8 VCC 0.2 VCC tSHSL 0.8 VCC 28 MB89810A Series (7) Peripheral Input Timings (VCC = +5.0 V±10 %, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C) Parameter Symbol Pin EC, INT0 to INT7 EC, INT0 to INT7 Condition — — Value Min. 2 tinst 2 tinst 512 tCL + 200 or 480 tCL + 200 512 tCL + 200 or 480 tCL + 200 Max. — — Unit Remarks ns ns Peripheral input “H” pulse tILIH width Peripheral input “L” pulse width “H” input pulse width of pulse width detection enable signal “L” input pulse width of pulse width detection enable signal Notes: • • • tIHIL tPWEH PWE tPWEL — — ns — — ns For information on tinst, see “ (4) Instruction Cycle”. tCL represents the subclock cycle time. The PWE pulse width value varies with the first divider selection bit of the watch prescaler. The pulse width is “512 tCL + 200” when divide by 16 is selected; or “480 tCL + 200” when divide by 15 is selected. EC, INT0 to INT7 0.2 VCC tIHIL 0.8 VCC 0.2 VCC tILIH 0.8 VCC tPWEH 0.8 VCC PWE 0.2 VCC 0.2 VCC tPWEL 0.8 VCC 29 MB89810A Series s MASK OPTIONS Part number No. Specifying procedure MB89816A Specify when ordering masking MB89P817A Set with EPROM programmer 1 Pull-up resistors •P00 to P07, P10 to P17, •P30 to P37, P40 to P47, •P50 to P54, P60 to P67 Power-on reset selection •With power-on reset •Without power-on reset Main clock oscillation (5 MHz) stabilization time selection* •approx. 218/FCH (approx. 52.4 ms) •approx. 217/FCH (approx. 26.2 ms) •approx. 214/FCH (approx. 3.2 ms) •approx. 24/FCH (approx. 0 ms) Reset pin output selection •With reset output •Without reset output Selection either single- or dual-clock system •Single clock •Dual clock Main clock oscillator type selection •Crystal or ceramic oscillator •CR Specify by pin Can be set per pin. (P50 to P54 are available only for without a pull-up resistor.) Setting possible 2 Selectable 3 Selectable Setting possible 4 Selectable Setting possible 5 Selectable Setting possible 6 Selectable Setting possible FCH: Main clock frequency *: The main clock oscillation setting time is generated by dividing the main clock frequency. Note that the oscillation cycle is not stable immediately after oscillation is started. The settling time value in this data sheet should be used as a reference. s ORDERING INFORMATION Part number MB89816APF MB89P817APF Package 64-pin Plastic QFP (FPT-64P-M06) Remarks 30 MB89810A Series s PACKAGE DIMENSION 64-pin Plastic QFP (FPT-64P-M06) 24.70±0.40(.972±.016) 20.00±0.20(.787±.008) 51 33 0.17±0.06 (.007±.002) 52 32 18.70±0.40 (.736±.016) 14.00±0.20 (.551±.008) INDEX Details of "A" part 3.00 –0.20 .118 –.008 20 +0.35 +.014 (Mounting height) 64 0~8° 1 19 1.00(.039) 0.42±0.08 (.017±.003) 0.20(.008) M 0.25 –0.20 1.20±0.20 (.047±.008) +0.15 +.006 .010 –.008 (Stand off) "A" 0.10(.004) C 2001 FUJITSU LIMITED F64013S-c-4-4 Dimensions in mm (inches) 31 MB89810A Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0105 © FUJITSU LIMITED Printed in Japan