FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12526-1E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89920 Series
MB89923/925/P928/PV920
s DESCRIPTION
The MB89920 series is a line of single-chip microcontrollers using the F2MC*-8L CPU core which can operate at low voltage but at high speed. The microcontrollers in this series contain peripheral functions such as a PWM timer, an input capture/output compare control counter, an LCD controller/driver, an A/D converter, and a UART. The MB89920 series can suit a wide range of applications such as analog input conversion, pulse input measurement/pulse output control, serial communications control, and display control. *: F2MC stands for FUJITSU Flexible Microcontroller.
s FEATURES
• High speed processing at low voltage Minimum execution time: 0.5 µs/8.0 MHz • F2MC-8L family CPU core Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc.
Instruction set optimized for controllers
• 8-bit PWM timer: 2 channels (also usable as a reload timer) • 16-bit input capture: 2 channels / 16-bit output compare: 2 channels
(Continued)
s PACKAGE
80-pin Plastic QFP 80-pin Ceramic MQFP
(FPT-80P-M06)
(MQP-80C-P01)
MB89920 Series
(Continued) • 20-bit time-base counter • UART: 1 channel (with asynchronous transfer mode and 8-bit synchronous serial mode) • 8-bit serial interface: 1 channel (LSB first/MSB first selectability) • 10-bit A/D converter: 8 channels • LCD controller/driver: 28 segments × 4 commons (max. 112 pixels) • Low-voltage detection reset • Watchdog timer reset • External interrupt: 4 channels Four channels are independent and capable of wake-up from the low-power consumption mode (with edge detection function) • Buzzer output/clock output • Low-power consumption modes: Stop mode (The software stops oscillation to minimize the current consumption.) Sleep mode (The CPU stops to reduce current consumption to approx. 1/3 of normal.) Hardware standby mode (The pin input stops oscillation.)
2
MB89920 Series
s PRODUCT LINEUP
Part number Parameter
MB89923
MB89925
MB89P928
One-time PROM product (for development)
MB89PV920
Piggyback/evaluation product (for development)
Classification ROM size RAM size CPU functions
Ports Options 20-bit time-base timer Real-time I/O
Mass production products (mask ROM products) 8 K × 8 bits 16 K × 8 bits (internal mask ROM) (internal mask ROM) 256 × 8 bits 512 × 8 bits Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: I/O ports (CMOS): I/O ports (N-ch open-drain): Total: Specify with mask options
48 K × 8 bits 48 K × 8 bits (internal PROM) (external ROM) 1024 × 8 bits 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.5 µs/8 MHz 4.5 µs/8 MHz 35 (25 ports also serve as peripherals.) 34 (All also serve as peripherals.) 69 Set with EPROM programmer None
20 bits (interval time selection: 4.10 ms, 16.38 ms, 65.54 ms, 262 ms/8 MHz) 16-bit timer: operating clock cycle (0.5 µs, 1.0 µs, 2.0 µs, 4.0 µs), overflow interrupt Input capture: 16 bits × 2 channels, external trigger edge selectability Output compare: 16 bits × 2 channels Common output: 4 (selectable from 2 to 4 by software) Segment output: 28 (can be switched to ports in 4-pin unit by software) Bias power supply pins: 3 LCD display RAM size: 14 × 8 bits Dividing resistor for LCD driving: bult-in (external resistor selectability) 8 bits × 2-channel reload timer operation 8 bits × 2-channel PWM operation (4 cycles selectable) 8 bits × 1-channel PPG operation (4 oscillation clocks selectable) Variable data length (7 or 8 bits), internal baud rate generator, error detection function, full-duplex with internal double buffer, NRZ transmission formation, Clock synchronous/asynchronous transfer capable 8 bits, LSB first/MSB first selectability, One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 1.0 µs, 4.0 µs, 16.0 µs) 10-bit resolution × 8 channels A/D conversion mode (conversion time: 16.5 µs (33 instruction cycles)) Sense mode (conversion time: 9.0 µs (18 instruction cycles)) Continuous activation by an internal clock capable Interval time: approx. 130 to 260 ms Reset activation voltage: 3.0 to 4.3 V Reset release voltage: 3.1 to 4.5 V Stop the clock oscillation by pin input 1 channel (output a frequency from 1 KHz, 2 KHz, 4 KHz, and divided clock frequency) 4 channels (rising edge/falling edge selectability) QFP-80 MQFP-80 2.2 to 6.0 V* 2.7 to 6.0 V* 2.7 to 6.0 V* MBM27C512-20TV (LCC package)
LCD controller/ driver
8-bit PWM timer
UART
8-bit serial I/O
10-bit A/D converter
Watchdog timer Low-voltage detection reset Hardware standby
Buzzer/clock output
External interrupt Package Operating voltage EPROM for use
* : The minimum operating voltage varies with conditions such as the operating frequencies, functions, and development tool. 3
MB89920 Series
s PACKAGE AND CORRESPONDING PRODUCTS
Package FPT-80P-M06 MQP-80C-P01 : Available × MB89923 MB89925 MB89P928 MB89PV920 ×
× : Not available
Note: For more information about each package, see section “s Package Dimensions.”
s DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: • The stack area, etc., is set at the upper limit of the RAM. • The external area is used.
2. Current Consumption
• In the case of the MB89PV920, add the current consumed by the EPROM which is connected to the top socket. • When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same. (For more information, see section “s Electrical Characteristics.”)
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “s Mask Options.”
4
MB89920 Series
s PIN ASSIGNMENT
(Top view)
P72/SEG18 P73/SEG19 P74/SEG20 P75/SEG21 P76/SEG22 P77/SEG23 P80/SEG24 P81/SEG25 P82/SEG26 P83/SEG27 P90/RTO0 P91/RTO1 P92/CLK P93/PWM0 VSS MODA X1 X0 P94/PWM1 HST RST P95/SCK P96/SO P97/SI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P71/SEG17 P70/SEG16 P67/SEG15 P66/SEG14 P65/SEG13 P64/SEG12 P63/SEG11 P62/SEG10 P61/SEG9 P60/SEG8 P57/SEG7 P56/SEG6 P55/SEG5 P54/SEG4 P53/SEG3 P52/SEG2
(Lead pitch: 0.80 mm) (Body size: 20 mm × 14 mm)
P51/SEG1 P50/SEG0 P40/COM0 P41/COM1 P42/COM2 P43/COM3 P44/V1 P45/V2 V3 VCC AVCC AVR AVSS P10/AN0 P11/AN1 P12/AN2 P13/AN3 P14/AN4 P15/AN5 P16/AN6 P17/AN7 P00/INT0 P01/INT1 P02/INT2
(Only for mass production or one-time PROM products)
P32/UCK P31/UO P30/UI P27 P26 P25 P24 P23/RTI1 P22 P21 P20/RTI0 P07 P06 P05 P04 P03/INT3 (FPT-80P-M06)
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
5
MB89920 Series
(Top view) P71/SEG17 P70/SEG16 P67/SEG15 P66/SEG14 P65/SEG13 P64/SEG12 P63/SEG11 P62/SEG10 P61/SEG9 P60/SEG8 P57/SEG7 P56/SEG6 P55/SEG5 P54/SEG4 P53/SEG3 P52/SEG2 P72/SEG18 P73/SEG19 P74/SEG20 P75/SEG21 P76/SEG22 P77/SEG23 P80/SEG24 P81/SEG25 P82/SEG26 P83/SEG27 P90/RTO0 P91/RTO1 P92/CLK P93/PWM0 VSS MODA X1 X0 P94/PWM1 HST RST P95/SCK P96/SO P97/SI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
101 102 103 104 105 106 107 108 109
93 92 91 90 89 88 87 86 85
P51/SEG1 P50/SEG0 P40/COM0 P41/COM1 P42/COM2 P43/COM3 P44/V1 P45/V2 V3 V CC AV CC AVR AVSS P10/AN0 P11/AN1 P12/AN2 P13/AN3 P14/AN4 P15/AN5 P16/AN6 P17/AN7 P00/INT0 P01/INT1 P02/INT2
• Pin assignment on package top (only for piggyback/evaluation product) Pin no. 81 82 83 84 85 86 87 88 Pin name N.C. A15 A12 AD7 AD6 AD5 AD4 AD3 Pin no. 89 90 91 92 93 94 95 96 Pin name AD2 AD1 AD0 N.C. O1 O2 O3 VSS Pin no. 97 98 99 100 101 102 103 104 Pin name N.C. O4 O5 O6 O7 O8 CE A10 Pin no. 105 106 107 108 109 110 111 112 Pin name OE/VPP N.C. A11 A9 A8 A13 A14 VCC
N.C.: Internally connected. Do not use. (Only for piggyback/evaluation product) 6
P32/UCK P31/UO P30/UI P27 P26 P25 P24 P23/RTI1 P22 P21 P20/RTI0 P07 P06 P05 P04 P03/INT3 (MQP-80C-P01)
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
110 111 112 81 82 83 84
100 99 98 97 96 95 94
MB89920 Series
s PIN DESCRIPTION
Pin no. 17 18 16 20 21 X1 X0 MODA HST RST B B C Operation mode selection input pin Connect this pin to VSS (GND). Hardware standby input pin Reset I/O pin This pin is an N-ch open-drain output type with a pull-up resistor, and a hysteresis input type. “L” is output from this pin by an internal reset source. The internal circuit is initialized by the input of “L”. General-purpose I/O ports A pull-up resistor option is provided. Also serve as an output compare data output. General-purpose I/O port Also serves as a buzzer/clock output. General-purpose I/O port A pull-up resistor option is provided. Also serves as an 8-bit PWM output. General-purpose I/O port A pull-up resistor option is provided. Also serves as an 8-bit PWM output. General-purpose I/O port A pull-up resistor option is provided. Also serves as the clock I/O (SCK) for the serial I/O. The SCK input is a hysteresis input. The output type can be switched between N-ch open-drain and CMOS. General-purpose I/O port A pull-up resistor option is provided. Also serves as the data output (SO) for the serial I/O. The output type can be switched between N-ch open-drain and CMOS. General-purpose I/O port A pull-up resistor option is provided. Also serves as the data input (SI) for the serial I/O. General-purpose I/O port A pull-up resistor option is provided. Also serves as a UART clock I/O (UCK). The UCK input is hysteresis input. The output type can be switched between N-ch open-drain and CMOS. General-purpose I/O port A pull-up resistor option is provided. Also serves as a UART data output (UO). The output type can be switched between N-ch open-drain and CMOS. Pin name Circuit type A Clock oscillator pins Function
11, 12 13 14
P90/RTO0, P91/RTO1 P92/BUZ/CLK P93/PWM0
D
D D
19
P94/PWM1
D
22
P95/SCK
E
23
P96/SO
D
24
P97/SI
E
25
P32/UCK
E
26
P31/UO
D
(Continued)
7
MB89920 Series
(Continued)
Pin no. 27 Pin name P30/UI Circuit type E Function General-purpose I/O port A pull-up resistor option is provided. Also serves as a UART data input (UI). General-purpose I/O ports A pull-up resistor option is provided. General-purpose I/O port A pull-up resistor option is provided. Also serves as an input capture data input. General-purpose I/O ports A pull-up resistor option is provided. General-purpose I/O port A pull-up resistor option is provided. Also serves as an input capture data input. General-purpose I/O ports A pull-up resistor options is provided. General-purpose I/O ports A pull-up resistor options is provided. Also serve as an external interrupt input (INT0 to INT3). CMOS I/O ports Also serve as an A/D converter analog input. LCD driving power supply pins These pins can be used as an N-ch open-drain general-purpose I/O when not used as an LCD driving power supply. LCD common output pins These pins can be used as an N-ch open-drain general-purpose I/O when not used as an LCD common output. LCD segment output pins These pins can be used as an N-ch open-drain general-purpose I/O when not used as an LCD segment output. LCD segment output pins These pins can be used as an N-ch open-drain general-purpose I/O when not used as an LCD segment output. LCD segment output pins These pins can be used as an N-ch open-drain general-purpose I/O when not used as an LCD segment output. LCD segment output pins These pins can be used as an N-ch open-drain general-purpose I/O when not used as an LCD segment output. LCD segment output pins These pins can be used as an N-ch open-drain general-purpose I/O when not used as an LCD segment output. A/D converter power supply (GND) pin A/D converter reference power supply pin A/D converter power supply pin Power supply pin LCD driving power supply pin Power supply (GND) pin
28 to 31 32
P27 to P24 P23/RTI1
D E
33, 34 35
P22, P21 P20/RTI0
D E
36 to 39 40 to 43
P07 to P04 P03/INT3 to P00/INT0 P17/AN7 to P10/AN0 P45/V2, P44/V1 P43/COM3 to P40/COM0 P50/SEG0 to P57/SEG7 P60/SEG8 to P67/SEG15 P70/SEG16, P71/SEG17 P72/SEG18 to P77/SEG23 P80/SEG24 to P83/SEG27 AVSS AVR AVCC VCC V3 VSS
D E
44 to 51 57, 58 59 to 62
G F
F
63 to 70
F
71 to 78
F
79, 80 1 to 6
F
F
7 to 11
F
52 53 54 55 56 15 8
MB89920 Series
• External EPROM pins (the MB89PV920 only) Pin no. 82 83 84 85 86 87 88 89 90 91 93 94 95 96 98 99 100 101 102 103 104 105 107 108 109 110 111 112 81 92 97 106 Pin name A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS O4 O5 O6 O7 O8 CE A10 OE/VPP A11 A9 A8 A13 A14 VCC N.C. I/O O Address output pins Function
I
Data input pins
O I
Power supply (GND) pin Data input pins
O O O O
ROM chip enable pin Outputs “H” during standby. Address output pin ROM output enable pin Outputs “L” at all times. Address output pins
O O O —
Address output pin Address output pin EPROM power supply pin Internally connected pins Be sure to leave them open.
9
MB89920 Series
s I/O CIRCUIT TYPE
Type A
X1
Circuit
Remarks • At an oscillation feedback resistor of approximately 1 MΩ (1 to 8 MHz)
X0
Standby control signal
B • At an output pull-up resistor of approximately 50 KΩ (5.0 V) • Hysteresis input
C
R P-ch
N-ch
D
R P-ch P-ch
• CMOS output • CMOS input
N-ch
• Pull-up resistor optional E
R P-ch P-ch
• CMOS output • CMOS input • Hysteresis input (peripheral input)
N-ch
• Pull-up resistor optional
(Continued)
10
MB89920 Series
(Continued)
Type F
N-ch
Circuit
Remarks • N-ch open-drain I/O • Also serves as LCD controller/driver common/ segment output.
P-ch N-ch P-ch N-ch
G
P-ch
• CMOS I/O • Analog input
N-ch
Analog input
11
MB89920 Series
s HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “s Electrical Characteristics” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode.
12
MB89920 Series
s PROGRAMMING TO THE EPROM ON THE MB89P928
The MB89P928 is an OTPROM version of the MB89920 series.
1. Features
• 48-Kbyte PROM on chip • Options can be set using the EPROM programmer. • Equivalency to the MBM27C1001A in EPROM mode (when programmed with the EPROM programmer)
2. Memory Space
Memory space in the EPROM mode is diagrammed below.
Address
Normal operating mode
EPROM mode (Corresponding addresses on the EPROM programmer) 0000H
0000H I/O 0080H 0100H 0200H 0480H
Vacancy Register RAM
(Read value undefined)
0FE4H Not available 1000H Vacancy
(Read value undefined)
Option area
4000H
4000H
ROM
Program area (EPROM)
FFFFH
FFFFH Vacancy
(Read value undefined)
1FFFH
13
MB89920 Series
3.Programming to the EPROM
In EPROM mode, the MB89P928 functions equivalent to the MBM27C1001A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. • Programming procedure (1) Set the EPROM programmer to the MBM27C1001A. (2) Load program data into the EPROM programmer at 0FE4H to FFFFH. (3) Program with the EPROM programmer.
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program.
Program, verify
Aging +150 °C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter
Package FPT-80P-M06 Compatible socket adapter ROM-80QF-32DP-8LA
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 Note: Depending on the EPROM programmer, inserting a capacitor of about 0.1 µF between VPP and VSS or VCC and VSS can stabilize programming operations.
14
MB89920 Series
7. PROM Option Bit Map
Bit 7 Vacancy 0FE4H Readable P07 Pull-up 1: No 0: Yes Readable P06 Pull-up 1: No 0: Yes P26 Pull-up 1: No 0: Yes Vacancy Readable P96 Pull-up 1: No 0: Yes Vacancy Readable Readable P05 Pull-up 1: No 0: Yes P25 Pull-up 1: No 0: Yes Vacancy Readable P95 Pull-up 1: No 0: Yes Bit 6 Vacancy Bit 5 Vacancy Bit 4 Oscillation stabilization time 1: Crystal 0: Ceramic P04 Pull-up 1: No 0: Yes P24 Pull-up 1: No 0: Yes Vacancy Readable P94 Pull-up 1: No 0: Yes Bit 3 Reset pin output 1: Yes 0: No P03 Pull-up 1: No 0: Yes P23 Pull-up 1: No 0: Yes Vacancy Readable P93 Pull-up 1: No 0: Yes Bit 2 Power-on reset 1: Yes 0: No P02 Pull-up 1: No 0: Yes P22 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P92 Pull-up 1: No 0: Yes Bit 1 Vacancy Readable P01 Pull-up 1: No 0: Yes P21 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes P91 Pull-up 1: No 0: Yes Bit 0 Vacancy Readable P00 Pull-up 1: No 0: Yes P20 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes P90 Pull-up 1: No 0: Yes
0FE8H
P27 Pull-up 0FECH 1: No 0: Yes Vacancy 0FF0H Readable P97 Pull-up 1: No 0: Yes Vacancy 0FF8H Readable
0FF4H
WDT/lowLow-voltage detection voltage voltage control 1: Register 00: — 01: 3.3 V 0: Option 11: 4.0 V EPROM 10: 3.6 V Vacancy Readable Vacancy Readable Vacancy Readable
Low-voltage Low-voltage Watchdog reset detection timer (WDT) 1: Yes 0: No 1: Automatic 0: Prohibited Vacancy Readable 1: Automatic 0: Prohibited Vacancy Readable
Vacancy 0FFCH Readable
Vacancy Readable
Vacancy Readable
Notes: • Set each bit to 1 to erase. • Do not write 0 to the vacant bit. The read value of the vacant bit is 1, unless 0 is written to it. • Write the same value as each option register to the 3-byte vacant address that follows above option registers. Example: In the case of 0FE4H, write the same value to 0FE5H, 0FE6H and 0FF7H. • This optional information is taken into the OTPROM while the oscillation is being reset. Therefore, if the hardware state is initially shifted to standby state after the power supply is turned on, the optional information will not be valid during the transition (in a state of the initial value 1). After the hardware standby state is cleared, the oscillation starts and the optional information becomes valid. Note that if the hardware is shifted to the standby or stop state in the course of a normal operation (oscillation), the contents of the optional register are valid since the option data has already been taken into the OTPROM.
15
MB89920 Series
s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C512-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package LCC-32(Rectangle) LCC-32(Square) Adapter socket part number ROM-32LC-28DP-YG ROM-32LC-28DP-S
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760
3. Memory Space
Memory space in each mode is diagrammed below.
Address
0000H I/O 0080H RAM 0480H
Normal operating mode
Corresponding addresses on the EPROM programmer
0000H
Not available
Not available
4000H
4000H
PROM 48 KB
EPROM 48 KB
FFFFH
FFFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C512. (2) Load program data into the EPROM programmer at 4000H to FFFFH. (3) Program to 4000H to FFFFH with the EPROM programmer.
16
MB89920 Series
s BLOCK DIAGRAM
X0 X1 HST
Oscillator Clock control Watchdog timer
Operating mode control Time-base timer CMOS I/O port
MODA
RST
Reset circuit Low-voltage detection
RAM
Output compare 16-bit free run counter Input capture
P91/RTO1 P90/RTO0
F2MC-8L CPU
P23/RTI1 P20/RTI0 P32/UCK P31/UO P30/UI P95/SCK P96/SO P97/SI
UART
ROM
P80/SEG24 to P83/SEG27 P70/SEG16 to P77/SEG23 P60/SEG8 to P67/SEG15 P50/SEG0 to P57/SEG7 V3 P44/V1, P45/V2 P40/COM0 to P43/COM3
4 8 8 8
N-ch open-drain I/O port
Internal bus
Serial I/O
28
2-channel 8-bit PWM timer 8-bit timer #2
P94/PWM1 P93/PWM0
LCD controller /driver
2 4 2 4
8-bit timer #1
AVR
10-bit A/D converter N-ch open-drain I/O port
8
8
P10/AN0 to P17/AN7
P21 to P22 P24 to P27
6
CMOS I/O port
4
Buzzer/clock output CMOS I/O port
P92/CLK
P04 to P07 P00/INT0 to P03/INT3 4
4
External interrupt
CMOS I/O port
17
MB89920 Series
s CPU CORE
1. Memory Space
The microcontrollers of the MB89920 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89920 series is structured as illustrated below. Memory Space
MB89923 0000H 0080H 0100H 0180H 0200H 0280H 0480H 0480H I/O RAM Register 0000H 0080H 0100H I/O RAM Register 0200H MB89925 0000H 0080H 0100H I/O RAM Register 0200H MB89P928 0000H 0080H 0100H I/O RAM Register MB89PV920
Not available
Not available
Not available
Not available
4000H
4000H
C000H Program ROM E000H ROM ROM Program ROM
FFFFH
FFFFH
FFFFH
FFFFH
18
MB89920 Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided:
Program counter (PC): Accumulator (A):
A 16-bit register for indicating instruction storage positions A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS): A 16-bit register for index modification A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area A 16-bit register for storing a register pointer, a condition code
16 bits PC A T IX EP SP PS : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status
Initial value FFFDH Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, 0 = 11 Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 3 N 2 Z 1 V 0 C
Vacancy Vacancy Vacancy
IL1, 0
RP
CCR
19
MB89920 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP Lower OP codes b1 ↓ b0 ↓
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: IL1, 0: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit.
IL1 0 0 1 1
IL0 0 1 0 1
Interrupt level 1 2 3
High-low High
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: V-flag: Set when an arithmetic operation results in 0. Cleared otherwise. Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction.
20
MB89920 Series
The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 16 banks can be used on the MB89925. Up to a total of 16 banks can be used on the MB89923. The bank currently in use is indicated by the register bank pointer (RP). Note: The number of register banks that can be used varies with the RAM size. Register Bank Configuration
This address = 0100H + 8 × (RP)
R0 R1 R2 R3 R4 R5 R6 R7
32 banks Memory area
21
MB89920 Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH (W) ICR1 (R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) STBC WDTE TBCR LVRC PDR3 DDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 DDR9 PDR2 DDR2 BUZR ADC1 ADC2 ADCH ADCL SMR SDR Read/write (R/W) (W) (R/W) (W) Register PDR0 DDR0 PDR1 DDR1 Register description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register Vacancy Vacancy Vacancy Vacancy Standby control register Watchdog timer control register Time-base timer control register Low-voltage detection reset control register Port 3 data/peripheral I/O control register Port 3 data direction register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port 9 data direction register Port 2 data register Port 2 data direction register Buzzer control register AD converter control register 1 AD converter control register 2 AD converter data register “H” AD converter data register “L” Serial mode register Serial data register Vacancy Port 1 input control register 0000 0000B 0001 XXXXB XXXX XXXXB XXX0 0000B 0X11 X00XB 0000 –XXXB –––– –000B ––11 1111B 1111 1111B 1111 1111B 1111 1111B –––– 1111B XXXX XXXXB 0000 0000B XXXX XXXXB 0000 0000B XXXX 0000B 0000 0000B X000 0001B –––– ––XXB XXXX XXXXB 0000 0000B XXXX XXXXB Intial value XXXX XXXXB 0000 0000B XXXX XXXXB 0000 0000B
–: Unused X: Undefined Note: Do not use vacancies
(Continued)
22
MB89920 Series
Address 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH
Read/write (R/W) (R/W) (R/W) (W) (W)
Register CNTR1 CNTR2 CNTR3 COMR2 COMR1
Register description PWM timer control register 1 PWM timer control register 2 PWM timer control register 3 PWM timer compare register 2 PWM timer compare register 1 Vacancy Vacancy Vacancy
Initial value 0000 0000B 0000 0000B 000X 0000B XXXX XXXXB XXXX XXXXB
(R/W) (R) (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R) (R) (R) (R)
TMCR TCHR TCLR OPCR CPR0H CPR0L CPR1H CPR1L ICCR ICIC ICR0H ICR0L ICR1H ICR1L
Timer control register Timer count register (H) Timer count register (L) Output control register Output compare register 0 (H) Output compare register 0 (L) Output compare register 1 (H) Output compare register 1 (L) Input capture control register Input capture interrupt control register Input capture register 0 (H) Input capture register 0 (L) Input capture register 1 (H) Input capture register 1 (L) Vacancy Vacancy
00XX 0000B 0000 0000B 0000 0000B 0000 0000B 0000 0000B 0000 0000B 0000 0000B 0000 0000B X000 X000B X000 0X00B XXXX XXXXB XXXX XXXXB XXXX XXXXB XXXX XXXXB
(R/W) (R/W)
EIC1 EIC2
External interrupt control register 1 External interrupt control register 2 Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy
0000 0000B 0000 0000B
–: Unused X: Undefined Note: Do not use vacancies
(Continued)
23
MB89920 Series
(Continued)
Address 40H 41H 42H 43H 44H 45H 46H 47H 48 to 5FH 60 to 6DH 70H 71H 72H 73 to 7BH 7CH 7DH 7EH 7FH –: Unused X: Undefined Note: Do not use vacancies (W) (W) (W) ILR1 ILR2 ILR3 (R/W) (R/W) (R/W) (R/W) VRAM LCR1 LCR2 LCR3 (R/W) RRDR Read/write (R/W) (R/W) (R/W) (R) (W) Register USMR USCR USTR RXDR TXDR Register description UART mode register UART control register UART status register UART receiver data register UART transmitter data register Vacancy Baud rate generator/reload data register Vacancy Vacancy Vacancy Display data RAM LCD controller/driver control register 1 LCD controller/driver control register 2 LCD controller/driver control register 3 Vacancy Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Vacancy 1111 1111B 1111 1111B 1111 1111B XXXX XXXXB 0000 0000B 000– ––––B 0000 0000B XXXX XXXXB Initial value 0000 0000B 0000 0000B 0000 1XXXB XXXX XXXXB XXXX XXXXB
24
MB89920 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = 0.0 V)
Parameter
Symbol VCC
Value Min. VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 –40 –55 Max. VSS + 7.0 VCC + 0.3 VSS + 7.0 VSS + 7.0 VCC + 0.3 VCC + 0.3 VSS + 7.0 20 4 100 40 –20 –4 –50 –20 300 +85 +150
Unit V V V V V V V mA mA mA mA mA mA mA mA mW °C °C *1
Remarks
Power supply voltage
AVCC AVR
AVR must not exceed AVCC + 0.3 V. V1 ≤ V2 ≤ V3 *2 P00 to P07, P10 to P17, P20 to P27, P30 to P32, P90 to P97 P40 to P45, P50 to P57, P60 to P67, P70 to P77, P80 to P83 Must not exceed “V3 + 0.3 V” Peak value Average value Peak value Average value Peak value Average value Peak value Average value
LCD power supply voltage Input voltage
V1 to V3 VI1 VO1
Output voltage VO2 “L” level maximum output current “L” level average output current “L” level total maximum output current “L” level total average output current “H” level maximum output current “H” level average output current “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature IOL IOLAV ∑IOL ∑IOLAV IOH IOHAV ∑IOH ∑IOHAV PD TA Tstg
*1: Use AVCC and VCC set at the same voltage. Take care so that AVCC does not exceed VCC, such as when power is turned on. *2: VCC must not exceed V3. Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
25
MB89920 Series
2. Recommended Operating Conditions
(VSS = 0.0 V)
Parameter
Symbol
Value Min. 2.2*1 Max. 6.0 6.0 6.0 AVCC VSS + 6.0 +85
Unit V V V V V °C
Remarks Normal operation assurance range MB89PV920/P928 Retains the RAM state in stop mode
Power supply voltage
VCC
2.7*1 1.5
A/D converter reference input voltage LCD power supply voltage Operating temperature
AVR V1 to V3 TA
3.0 VSS –40
V1 ≤ V2 ≤ V3*2
*1: These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1 and “5. A/D Converter Electrical Characteristics.” *2: VCC must not exceed V3.
6 Analog accuracy assured in the AVCC = 3.5 V to 6.0 V range 5
Operation assurance range Operating voltage (V)
4
3
2
1
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
Clock operating frequency (at an instruction cycle of 4/FC) (MHz)
4.0 2.0 0.8 0.5 Minimum execution time (instruction cycle) (µs) Note: The shaded area is assured only for the MB89923/925.
Figure 1
Operating Voltage vs. Clock Operating Frequency
Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FC. Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. 26
MB89920 Series
3. DC Characteristics
(VCC = 5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol
Pin
P00 to P07, P10 to P17, P20 to P27, P30 to P32, P40 to P45, P50 to P57, P60 to P67, P70 to P77, P80 to P83, P90 to P97 RST, MODA, HST P00 to P07, P10 to P17, P20 to P27, P30 to P32, P40 to P45, P50 to P57, P60 to P67, P70 to P77, P80 to P83, P90 to P97 RST, MODA, HST
Condition
Value Min. Typ. Max. VCC + 0.3 VCC + 0.3
Unit
Remarks
VIH “H” level input voltage VIHS
—
0.7 VCC
—
V
—
0.8 VCC
—
V
Peripheral input of the port 0, 2, 3, and 9
VIL “L” level input voltage VILS Open-drain output pin application voltage “H” level output voltage
—
VSS − 0.3 VSS − 0.3 VSS − 0.3 4.0 2.4
—
0.3 VCC
V
—
—
0.2 VCC
V
Peripheral input of the port 0, 2, 3, and 9
VD
P40 to P45, P50 to P57, P60 to P67, P70 to P77, P80 to P83*1 P00 to P07, P10 to P17, P30 to P32, P90 to P97 P20 to P27 P00 to P07, P10 to P17, P30 to P32, P40 to P45, P50 to P57, P60 to P67, P70 to P77, P80 to P83, P90 to P97 P20 to P27 RST P00 to P07, P10 to P17, P20 to P27, P30 to P32, P40 to P45, P50 to P57, P60 to P67, P70 to P77, P80 to P83, P90 to P97, MODA P00 to P07, P20 to P27, P30 to P32, P90 to P97
—
—
VSS + 6.0 — —
V
VOH1 VOH2
IOH = –2.0 mA IOH = –5.0 mA
— —
V V
VOL1 “L” level output voltage VOL2 VOL3 Input leakage current (Hi-z output leakage current) Pull-up resistance
IOL = 4.0 mA
—
—
0.4
V
IOL = 5.0 mA IOL = 4.0 mA
— —
— —
0.4 0.4
V V
ILI1
0.45 V < VI < VCC
—
—
±5
µA
Without pullup resistor
RPULU
VI = 0.0 V
25
50
100
kΩ
Without pullup resistor
(Continued)
27
MB89920 Series
(VCC = 5.0 V, VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol ICC ICCS ICCH VCC
Pin
Condition VCC = 5.0 V VCC = 5.0 V TA = +25°C when A/D conversion is activated
Value Min. — — — — Typ. 12 3 — 6 Max. 20 7 1 8
Unit
Remarks
mA tinst = 0.5 µs mA µA mA Sleep mode tinst = 0.5 µs Stop mode
Power supply current*2
IA AVCC IAH
when A/D conversion is stopped TA = +25°C
—
—
1
µA
LCD divided resistance
RLCD
Between V3 and VSS COM0 to 3 V1 to V 3 = 5.0 V
200 —
300 —
450 2.5
kΩ kΩ kΩ
COM0 to 3 output RVCOM impedance SEG0 to 27 output impedance LCD controller/ driver leakage current RVSEG
SEG0 to 27 V1 to V3, COM0 to 3, SEG0 to 27 Other than AVCC, AVSS, VCC, and VSS
V1 to V 3 = 5.0 V
—
—
15
ILCDL
V1 to V 3 = 5.0 V
—
—
±1
µA
Input capacitance CIN *1: VD must not exceed V3.
f = 1 MHz
—
10
—
pF
*2: The measurement conditions of power supply current are as follows: the external clock and TA = +25°C. In the case of the MB89PV920, the current consumed by the connected EPROM and ICE is not included. Note: For pins which serve as the LCD and ports (P40 to P45, P50 to P57, P60 to P67, P70 to P77, and P80 to P83), see the port parameter when these pins are used as ports and the LCD parameter when they are used as LCD pins.
28
MB89920 Series
4. AC Characteristics
(1) Reset Timing
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter RST “L” pulse width
Symbol tZLZH
Condition —
Value Min. 48 tHCYL Max. —
Unit ns
Remarks
tZLZH
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter Power supply rising time Power supply cut-off time
Symbol tR tOFF
Condition —
Value Min. — 1 Max. 50 —
Unit ms ms
Remarks Power-on reset function only Due to repeated operations
Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR 2.0 V 0.2 V
tOFF
VCC
0.2 V
0.2 V
29
MB89920 Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time
Symbol FC tXCYL PWH PWL tCR tCF
Pin X0, X1 X0, X1 X0 X0
Condition
Value Min. 1 125 Max. 8 1000 — 10
Unit MHz ns ns ns
Remarks
—
20 —
External clock External clock
X0 and X1 Timing and Conditions
tXCYL PWH tCR 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC tCF PWL
Clock Conditions
When a crystal or ceramic resonator is used
When an external clock is used
X0 FC
X1
X0
X1
Open
C1
C2
(4) Instruction Cycle Parameter Symbol Value (typical) 4/FC Unit µs Remarks (4/FC) tinst = 0.5 µs when operating at FC = 8 MHz
Instruction cycle tinst (minimum execution time)
30
MB89920 Series
(5) Serial I/O Timing
(AVCC = VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Parameter Serial clock cycle time SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time
Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
Pin SCK SCK, SO SI, SCK SCK, SI SCK SCK SCK, SO SI, SCK SCK, SI
Condition
Value Min. 2 tinst* –200 1/2 tinst* 1/2 tinst* 1 tinst* 1 tinst* Max. — 200 — — — — 200 — —
Unit µs ns µs µs µs µs ns µs µs
Remarks
Internal shift clock mode
External shift clock mode
0 1/2 tinst* 1/2 tinst*
* : For information on tinst, see “(4) Instruction Cycle.” Internal Shift Clock Mode
tSCYC SCK 2.4 V 0.8 V 0.8 V
tSLOV 2.4 V SO 0.8 V
tIVSH 0.8 VCC SI 0.2 VCC
tSHIX 0.8 VCC 0.2 VCC
External Shift Clock Mode
tSLSH SCK 0.8 VCC 0.2 VCC 0.2 VCC 0.8 VCC tSHSL
tSLOV 2.4 V SO 0.8 V
tIVSH 0.8 VCC SI 0.2 VCC
tSHIX 0.8 VCC 0.2 VCC
31
MB89920 Series
(6) Peripheral Input Timing
(VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Parameter Peripheral input “H” pulse width 1 Peripheral input “L” pulse width 1
Symbol tILIH1 tIHIL1
Pin INT0 to INT3, RTI0, 1 INT0 to INT3, RTI0, 1
Value Min. 2 tinst* 2 tinst* Max. — —
Unit — —
Remarks
* : For information on tinst, see “(4) Instruction Cycle.”
tIHIL1 RTI0, 1 INT0 to 3 0.2 VCC
tILIH1
0.8 VCC 0.2 VCC
0.8 V CC
32
MB89920 Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = +3.5 V to +6.0 V, FC = 8 MHZ, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter Resolution Linearity error
Differential linearity error
Symbol
Pin
Condition
Value Min. — — — —
AVSS – 1.5 LSB AVR – 3.5 LSB
Typ. — — — —
AVSS + 0.5 LSB AVR – 1.5 LSB
Max. 10 ±2.0 ±1.5 ±3.0
AVSS + 2.5 LSB AVR + 0.5 LSB
Unit bit LSB LSB LSB mV mV LSB µs µA V V µA
—
— AVCC = AVR = VCC
Differential total error Zero transition voltage VOT Full-scale transition voltage Interchannel disparity
A/D mode conversion time Analog port input current AN0 to AN7 AN0 to AN7
VFST — VAIN — IR
—
AN0 to AN7 AN0 to AN7 At 8-MHZ oscillattion
— — — 0.0 0.0 AVR = 5.0 V —
— — — — — 200
4 16.5 10 AVR AVCC
Analog input voltage Reference voltage Reference voltage supply current
AVR AVR
Precautions: • The smaller | AVR – AVSS |, the greater the error would become relatively. • The output impedance of the external circuit for the analog input must satisfy the following conditions: Output impedance of the external circuit < Approx. 10 kΩ If the output impedance of the external circuit is too high, an analog voltage sampling time might be insufficient (sampling time = 7.5 µs at 8 MHz oscillation). An analog input equivalent circuit is shown below.
Sample hold circuit R ≤ 10 kΩ is recommended. AN . C = 60 pF . . R =. 3 kΩ ( If R > 10 kΩ, it is recommended to connect an external capacitor of approx. 0.1 µF. ) Analog channel selector Close for approx. 15 instruction cycles after activating A/D conversion. Microcontroller’s internal circuit Comparator
Since the A/D converter contains sample hold circuit, the level of the analog input pin might not stabilize within the sampling period after A/D activation, resulting in inaccurate A/D conversion values, if the input impedance to the analog pin is too high. Be sure to maintain an appropriate input impedance to the analog pin. It is recommended to keep the input impedance to the analog pin not exceed 10 kΩ. If it exceeds 10 kΩ, it is recommended to connect a capacitor of about 0.1 µF for the analog input pin. Except for the sampling period after A/D activation, the input leakage current of the analog input pin is less than 10 µA. 33
MB89920 Series
(1) A/D Converter Glossary • Resolution Analog changes that are identifiable with the A/D converter. • Linearity error The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics • Differential linearity error The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value • Total error The difference between theoretical and actual conversion values, caused by the zero transition error, full-scale transition error, linearity error, quantization error, and noise.
Theoreticall I/O characteristics 3FF 3FE 3FD Digital output 1.5 LSB Digital output VFST 3FF 3FE 3FD
Total error
Actual conversion value {1 LSB × N + 0.5 LSB}
004 003 002 001 0.5 LSB AVSS Analog input AVR
004 VNT 003 Actual conversion value Theoretical value 001
VOT 1 LSB
002
AVSS Analog input
AVR
1 LSB =
VFST − VOT 1022
(V)
Total error of digital output N =
VNT − {1 LSB × N + 0.5 LSB} 1 LSB
(Continued)
34
MB89920 Series
(Continued)
Zero transition error 004 Actual conversion value 003 Digital output Digital output 3FE 3FF
Full-scale transition error Theoretical value
Actual conversion value
002 Theoretical value 001
VFST (Actual measured value) 3FD Actual conversion value 3FC
Actual conversion value
VOT (Actual measured value) AVSS Analog input Analog input AVR
Linearity error 3FF 3FE {1 LSB × N + VOT} 3FD Digital output Digital output VFST (Actual measured value) N Actual conversion value N+1
Differential linearity error Theoretical value
Actual conversion value
V(N + 1)T
VNT 004 003 002 001
Actual conversion value Theoretical value
N–1
VNT Actual conversion value
N–2 VOT (Actual measured value) AVSS Analog input AVR AVSS Analog input AVR
Linearity error of digital output N =
VNT – {1 LSB × N + VOT} 1 LSB
Differential linearity error of digital output N =
V(N+1)T – VNT 1 LSB
–1
35
MB89920 Series
6. Low-voltage Detection Reset
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol VDL1
Condition
Value Min. 3.00 3.30 3.70 3.10 3.40 3.80 0.10 0.3 16 tXCYL — — Max. 3.60 3.90 4.30 3.80 4.10 4.50 — — — 2.0 0.10
Unit V V V V V V V µs ns µs V/µs
Remarks
Voltage detected at power supply voltage drop
VDL2 VDL3 VDH1
*1
Voltage detected at power supply voltage rise Hysteresis width Reset ignore time Reset sense time Reset detection deley time Voltage regulation (V∆/t∆)
VDH2 VDH3 ∆V tL tLW tD VCR
*1: VDH and VDL can be set for the MB89923 and MB89925 by mask options; for the MB89PV920 and MB89P928 by registers.
Power supply voltage VCC VDH* VDL* t∆ V∆
∆V
tOSC RUN RESET
tD
tOSC
tD
tOSC oscillation stabilization time 219 = 65.5 ms (f = 8 MHz) Power supply voltage VCC less than tL VDH* VDL* over than tLW
t RUN RESET
Not reset
Reset
t
36
MB89920 Series
s INSTRUCTIONS (136 INSTRUCTIONS)
Execution instructions can be divided into the following four groups: • Transfer • Arithmetic operation • Branch • Others Table 1 lists symbols used for notation of instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX EP PC SP PS dr CCR RP Ri × (×) (( × )) Instruction Symbols Meaning Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: The number of instructions #: The number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: • “–” indicates no change. • dH is the 8 upper bits of operation description data. • AL and AH must become the contents of AL and AH prior to the instruction executed. • 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ← This indicates 48, 49, ... 4F. 37
MB89920 Series
Table 2 Mnemonic MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC Note ~ 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 # 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 Transfer Instructions (48 instructions) Operation (dir) ← (A) ( (IX) +off ) ← (A) (ext) ← (A) ( (EP) ) ← (A) (Ri) ← (A) (A) ← d8 (A) ← (dir) (A) ← ( (IX) +off) (A) ← (ext) (A) ← ( (A) ) (A) ← ( (EP) ) (A) ← (Ri) (dir) ← d8 ( (IX) +off ) ← d8 ( (EP) ) ← d8 (Ri) ← d8 (dir) ← (AH),(dir + 1) ← (AL) ( (IX) +off) ← (AH), ( (IX) +off + 1) ← (AL) (ext) ← (AH), (ext + 1) ← (AL) ( (EP) ) ← (AH),( (EP) + 1) ← (AL) (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir + 1) (AH) ← ( (IX) +off), (AL) ← ( (IX) +off + 1) (AH) ← (ext), (AL) ← (ext + 1) (AH) ← ( (A) ), (AL) ← ( (A) ) + 1) (AH) ← ( (EP) ), (AL) ← ( (EP) + 1) (A) ← (EP) (EP) ← d16 (IX) ← (A) (A) ← (IX) (SP) ← (A) (A) ← (SP) ( (A) ) ← (T) ( (A) ) ← (TH),( (A) + 1) ← (TL) (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ↔ (AL) (dir): b ← 1 (dir): b ← 0 (AL) ↔ (TL) (A) ↔ (T) (A) ↔ (EP) (A) ↔ (IX) (A) ↔ (SP) (A) ← (PC) TL – – – – – AL AL AL AL AL AL AL – – – – – – – – – AL AL AL AL AL AL – – – – – – – – – – – – – – – AL AL – – – – TH – – – – – – – – – – – – – – – – – – – – – AH AH AH AH AH AH – – – – – – – – – – – – – – – – AH – – – – AH – – – – – – – – – – – – – – – – – – – – – dH dH dH dH dH dH dH – – dH – dH – – – dH – – AL – – – dH dH dH dH dH NZVC –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++++ –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– OP code 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 D4 D7 E3 E4 C5 C6 C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0
During byte transfer to A, T ← A is restricted to low bytes. Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family)
38
MB89920 Series
Table 3 Mnemonic ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir ~ 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 # 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation (A) ← (A) + (Ri) + C (A) ← (A) + d8 + C (A) ← (A) + (dir) + C (A) ← (A) + ( (IX) +off) + C (A) ← (A) + ( (EP) ) + C (A) ← (A) + (T) + C (AL) ← (AL) + (TL) + C (A) ← (A) − (Ri) − C (A) ← (A) − d8 − C (A) ← (A) − (dir) − C (A) ← (A) − ( (IX) +off) − C (A) ← (A) − ( (EP) ) − C (A) ← (T) − (A) − C (AL) ← (TL) − (AL) − C (Ri) ← (Ri) + 1 (EP) ← (EP) + 1 (IX) ← (IX) + 1 (A) ← (A) + 1 (Ri) ← (Ri) − 1 (EP) ← (EP) − 1 (IX) ← (IX) − 1 (A) ← (A) − 1 (A) ← (AL) × (TL) (A) ← (T) / (AL),MOD → (T) (A) ← (A) ∧ (T) (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL) − (AL) (T) − (A) → C→A C ← A← (A) − d8 (A) − (dir) (A) − ( (EP) ) (A) − ( (IX) +off) (A) − (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ( (EP) ) (A) ← (AL) ∀ ( (IX) +off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) TL – – – – – – – – – – – – – – – – – – – – – – – dL – – – – – – – – – – – – – – – – – – – – – – – TH – – – – – – – – – – – – – – – – – – – – – – – 00 – – – – – – – – – – – – – – – – – – – – – – – AH – – – – – dH – – – – – – dH – – – – dH – – – dH dH 00 dH dH dH – – – – – – – – – – – – – – – – – – – – NZVC ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++– –––– –––– ++–– +++– –––– –––– ++–– –––– –––– ++R– ++R– ++R– ++++ ++++ ++–+ ++–+ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– OP code 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65
(Continued)
39
MB89920 Series
(Continued) Mnemonic
AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP
~ 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3
# 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1
Operation (A) ← (AL) ∧ ( (EP) ) (A) ← (AL) ∧ ( (IX) +off) (A) ← (AL) ∧ (Ri) (A) ← (AL) ∨ (TL) (A) ← (AL) ∨ d8 (A) ← (AL) ∨ (dir) (A) ← (AL) ∨ ( (EP) ) (A) ← (AL) ∨ ( (IX) +off) (A) ← (AL) ∨ (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ← (SP) + 1 (SP) ← (SP) – 1 Table 4
TL – – – – – – – – – – – – – – –
TH – – – – – – – – – – – – – – –
AH – – – – – – – – – – – – – – –
NZVC ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++++ ++++ ++++ ++++ –––– ––––
OP code 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1
Branch Instructions (17 instructions) Operation TL – – – – – – – – – – – – – – – – – TH – – – – – – – – – – – – – – – – – AH – – – – – – – – – – – – – – dH – – NZVC –––– –––– –––– –––– –––– –––– –––– –––– –+–– –+–– –––– –––– –––– –––– –––– –––– Restore OP code FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30
Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI
~ 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6
# 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1
If Z = 1 then PC ← PC + rel If Z = 0 then PC ← PC + rel If C = 1 then PC ← PC + rel If C = 0 then PC ← PC + rel If N = 1 then PC ← PC + rel If N = 0 then PC ← PC + rel If V ∀ N = 1 then PC ← PC + rel If V ∀ N = 0 then PC ← PC + reI If (dir: b) = 0 then PC ← PC + rel If (dir: b) = 1 then PC ← PC + rel (PC) ← (A) (PC) ← ext Vector call Subroutine call (PC) ← (A),(A) ← (PC) + 1 Return from subrountine Return form interrupt Table 5
Other Instructions (9 instructions) Operation TL – – – – – – – – – TH – – – – – – – – – AH – dH – – – – – – – NZVC –––– –––– –––– –––– –––– –––R –––S –––– –––– OP code 40 50 41 51 00 81 91 80 90
Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI
~ 4 4 4 4 1 1 1 1 1
# 1 1 1 1 1 1 1 1 1
40
H
3 RETI PUSHW POPW MOV MOVW CLRI A A A,ext A,PS SETC SETI CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC 4 5 6 7 8 9 A B C D E F
L
0
1
2
0
NOP
SWAP
RET
1
MULU
DIVU
A SUBC A A A, T A A A XCH XOR AND OR
A
JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A
CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP
2
ROLC
CMP
ADDC
s INSTRUCTION MAP
A
A
MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX
3
RORC
CMPW
A XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS
A
ADDCW SUBCW XCHW XORW ANDW ORW MOVW MOVW CLRB BBC INCW DECW MOVW MOVW A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC
4
MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8
5
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP
6
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX
7
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8 @EP,#d8 dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 R7 R6 R5 R4 R3 R2 R1 R0 CALLV BNC #0 rel CALLV BC #1 CALLV BP #2 CALLV BN #3
8
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel
9
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel
rel
A
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel
rel
B
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel
rel CALLV BNZ #4 rel CALLV BZ #5
C
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel
D
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel
rel CALLV BGE #6 rel CALLV BLT #7
E
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel
F
MB89920 Series
MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel
rel
41
MB89920 Series
s MASK OPTIONS
Part number No. Specifying procedure Pull-up resistors P00 to P07, P20 to P27, P30 to P32, P90 to P97 Power-on reset Power-on reset provided No power-on reset
Oscillation stabilization time slection (at 8 HZ)
MB89923 MB89925 Specify when ordering masking
P00 to P07, P20 to P27, P30 to P32, P90 to P97
MB89P928 Set with EPROM programmer
MB89PV920 Setting not possible
1
Can be set per pin
No pull-up resistor
: Selectable by pin Selectable Can be set With power-on reset
2
3
Cystal oscillator (32.8 ms/8MHZ) Ceramic oscillator (2.05 ms/8 MHZ) Reset pin output Reset output provided No reset output Watchdog timer Activation prohibited Automatic activation Low-voltage detection reset circuit Activation prohibited Automatic activation Low-voltage detection reset output Output disabled Output enabled Low-voltage detection voltage 3.3 V ± 0.3 V 3.6 V ± 0.3 V 4.0 V ± 0.3 V Low-voltage detection reset/watchdog timer function selection Register setting valid Option setting valid
Selectable
Can be set
Crystal oscillator (32.8 ms/8 MHZ)
4
Selectable
Can be set
With reset output Inactive by default (Can be activated by software) Inactive by default (Can be activated by software) Inactive by default (Can be activated by software) Register setting
5
Selectable
Can be set
6
Selectable
Can be set
7
Selectable
Can be set
8
Selectable
Can be set
9
Selectable
Can be set
Fixed to register setting
42
MB89920 Series
s ORDERING INFORMATION
Part number MB89923PF MB89925PF MB89P928PF MB89PV920CF Package 80-pin Plastic QFP (FPT-80P-M06) 80-pin Ceramic MQFP (MQP-80C-P01) Remarks
43
MB89920 Series
s PACKAGE DIMENSIONS
80-pin Plastic QFP (FPT-80P-M06)
23.90±0.40(.941±.016)
64 65
20.00±0.20(.787±.008)
41 40
3.35(.132)MAX 0.05(.002)MIN (STAND OFF)
14.00±0.20 (.551±.008)
INDEX
80 25
17.90±0.40 (.705±.016)
12.00(.472) REF
16.30±0.40 (.642±.016)
"A" LEAD No.
1 24
0.80(.0315)TYP
0.35±0.10 (.014±.004)
0.16(.006)
M
0.15±0.05(.006±.002)
Details of "A" part 0.25(.010) "B" 0.10(.004) 18.40(.724)REF 22.30±0.40(.878±.016) 0.30(.012) 0.18(.007)MAX 0.58(.023)MAX
Details of "B" part
0 10° 0.80±0.20 (.031±.008)
C
1994 FUJITSU LIMITED F80010S-3C-2
Dimensions in mm (inches)
44
MB89920 Series
80-pin Ceramic MQFP (MQP-80C-P01)
18.70(.736)TYP 12.00(.472)TYP 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) 1.50(.059)TYP 1.00(.040)TYP 4.50(.177) TYP 1.20 –0.20 +.016 .047 –.008
+0.40
INDEX AREA
0.80±0.25 (.0315±.010) 0.80±0.25 (.0315±.010)
1.27±0.13 (.050±.005) 22.30±0.33 (.878±.013) 24.70(.972) TYP 0.30(.012) TYP 18.12±0.20 12.02(.473) (.713±.008) TYP 10.16(.400) 14.22(.560) TYP TYP
INDEX AREA 18.40(.724) REF
INDEX 6.00(.236) TYP 0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP 0.40±0.10 (.016±.004) 1.50(.059) TYP 1.00(.040) TYP
1.27±0.13 (.050±.005)
0.40±0.10 (.016±.004)
1.20 –0.20 +.016 .047 –.008
+0.40
0.15±0.05 8.70(.343) (.006±.002) MAX
C
1994 FUJITSU LIMITED M80001SC-4-2
Dimensions in mm (inches)
45
MB89920 Series
FUJITSU LIMITED
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