MB89935BPFV

FUJITSU SEMICONDUCTOR DATA SHEET DS07-12541-6E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89930A Series MB89935A/935B/P935B/PV930A s DESCRIPTION The MB89930A series is a line of single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such, timers, a serial interface, an A/D converter and an external interrupt. s FEATURES • • • • • • • • • • • • • Models that support + 125 °C MB89600 Series CPU core Maximum memory space : 64 Kbytes Minimum execution time : 0.4 µs/10 MHz Interrupt processing time : 3.6 µs/10 MHz I/O ports : Max 21channels 21-bit timebase timer 8-bit PWM timer 8/16-bit capture timer/counter 10-bit A/D converter : 8 channels UART8-bit serial I/O External interrupt 1 : 3 channels External interrupt 2 : 8 channels (Continued) s PACKAGES 30-pin plastic SSOP 48-pin ceramic MQFP (FPT-30P-M02) (MQP-48C-P01) MB89930A Series (Continued) • Wild Register : 2 bytes • Low-power consumption modes ( sleep mode, and stop mode) • SSOP-30 and MQFP-48 package • CMOS Technology s PRODUCT LINEUP Part number Parameter MB89935A MB89935B MB89P935B One-time PROM product (for small-scale production) 16 K × 8 bits (internal PROM) 512 × 8 bits 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.4 µs to 6.4 µs (10 MHz) 3.6 µs to 57.6 µs (10 MHz) MB89PV930A Piggyback/evaluation product (for development) 32 K × 8 bits (external EPROM) Classification ROM size RAM size Mass production product (mask ROM product) 16 K × 8 bits (internal mask ROM) Number of instructions : Instruction bit length : Instruction length : Data bit length : Minimum execution time : Interrupt processing time : CPU functions Ports 21-bit time base timer Watching timer General-purpose I/O ports (CMOS) : 21 (also serve as peripherals ) (4 ports are also an N-ch open-drain type.) 21-bit Interrupt cycle : 0.82 ms, 3.3 ms, 26.2 ms, or 419.4 ms with 10-MHz main clock Reset generation cycle : 419.4 ms minimum with 10-MHz main clock 8-bit interval timer operation (square output capable, operating clock cycle : 0.4 µs , 3.2 µs, 6.4 µs, 25.6 µs) 8-bit resolution PWM operation (conversion cycle : 102.4 µs to 26.84 s : in the selection of internal shift clock of 8/16-bit capture timer) Count clock selectable between 8-bit and 16-bit timer/counter outputs 8-bit capture timer/counter × 1 channel + 8-bit timer or 16-bit capture timer/counter × 1 channel Capable of event count operation and square wave output using external clock input with 8-bit timer 0 or 16-bit counter Transfer data length : 6/7/8 bits 8 bits LSB first/MSB first selectable One clock selectable from four operation clocks (one external shift clock, three internal shift clocks : 0.8 µs, 6.4 µs, 25.6 µs) Output frequency : Pulse width and cycle selectable 3 channels (Interrupt vector, request flag, request output enabled) Edge selectable (Rising edge, falling edge, or both edges) Also available for resetting stop/sleep mode (Edge detectable even in stop mode) 1 channel with 8 inputs (Independent L-level interrupt and input enable) Also available for resetting stop/sleep mode (Level detectable even in stop mode) 8-bit PWM timer 8/16-bit capture, timer/counter UART 8-bit Serial I/O 12-bit PPG timer External interrupt 1 (wake-up function) External interrupt 2 (wake-up function) (Continued) 2 MB89930A Series (Continued) Part number Parameter MB89935A MB89935B MB89P935B MB89PV930A 10-bit A/D converter Wild Register Standby mode *Power supply Voltage 10-bit precision × 8 channels A/D conversion function (Conversion time : 15.2 µs/10 MHz) Continuous activation by 8/16-bit timer/counter output or time-base timer counter 8-bit × 2 Sleep mode, and Stop mode 2.2 V to 5.5 V 3.0 V to 5.5 V 2.7 V to 5.5 V * : The minimum operating voltage varies with the operating frequency, the function, and the connected ICE. s PACKAGE AND CORRESPONDING PRODUCTS Package FPT-30P-M02 MQP-48C-P01 : Available × × : Not available × × MB89935A MB89935B MB89P935B MB89PV930A ×* * : Adapter for 48-pin to 30-pin conversion (manufactured by Sunhayato Corp.) Part number : 48QF-30SOP-8L Inquiry : Sunhayato Corp. : TEL : (81) -3-3984-7791 FAX : (81) -3-3971-0535 E-mail : adapter@sunhayato.co.jp s DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. 2. Current Consumption In the case of the MB89PV930A, add the current consumed by the EPROM which is connected to the top socket. 3. Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “s MASK OPTIONS” Take particular care on the following points : Options are fixed on the MB89PV930A and MB89P935B. 4. Difference between MB89935A and MB89935B MB89935B is different from MB89935A in that the internal circuit and oscillator have been changed and the radiated noise and current consumption while oscillation is active is reduced. For details of the characteristics of current consumption, see “s EXAMPLE CHARACTERISTICS”. 3 MB89930A Series s PIN ASSIGNMENT (TOP VIEW) P04/INT24 P05/INT25 P06/INT26 P07/INT27 MOD0 MOD1 RST X0 X1 VSS P37/BZ/PPG P36/INT12 P35/INT11 P34/TO/INT10 P33/EC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VCC P03/INT23/AN7 P02/INT22/AN6 P01/INT21/AN5 P00/INT20/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 AVSS P50/PWM P30/UCK/SCK P31/UO/SO P32/UI/SI C (FPT-30P-M02) (Continued) 4 MB89930A Series (Continued) (TOP VIEW) P35/INT11 N.C. N.C. N.C. N.C. N.C. VSS P34/TO/INT10 P33/EC P32/UI/SI P31/UO/SO P30/UCK/SCK P40/AN0 P41/AN1 P42/AN2 P43/AN3 P00/INT20/AN4 P01/INT21/AN5 P02/INT22/AN6 1 3 4 5 6 7 8 9 10 11 12 69 70 71 72 73 74 75 76 48 47 46 45 44 43 42 41 40 39 38 37 36 68 67 66 65 64 63 62 61 35 34 60 59 58 57 56 55 54 53 77 78 79 80 49 50 51 52 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 N.C. N.C. N.C. N.C. N.C. N.C. P36/INT12 P37/BZ/PPG X1 X0 RST MOD1 MOD0 P07/INT27 P06/INT26 P05/INT25 P04/INT24 2 P03/INT23/AN7 AVSS N.C. N.C. N.C. VCC (MQP-48C-P01) Pin no. 49 50 51 52 53 54 55 56 Pin name VPP A12 A7 A6 A5 A4 A3 N.C. Pin no. 57 58 59 60 61 62 63 64 Pin name N.C. A2 A1 A0 O1 O2 O3 VSS N.C. N.C. N.C. N.C. N.C. P50/PWM Pin no. 65 66 67 68 69 70 71 72 Pin name O4 O5 O6 O7 O8 CE A10 N.C. Pin no. 73 74 75 76 77 78 79 80 Pin name OE N.C. A11 A9 A8 A13 A14 VCC N.C. : Internally connected. Do not use. 5 MB89930A Series s PIN DESCRIPTION Pin No. SSOP*1 MQFP*2 Pin name X0 X1 MOD0 MOD1 Circuit type A B Function Pins for connecting the crystal resonator for the main clock. To use an eternal clock, input the signal to X0 and leave X1 open. Memory access mode setting input pins. Connect the pin directly to Vss. Reset I/O pin. This pin serves as an N-channel open-drain output with pull-up resistor and a hysteresis input as well. The pin outputs the “L” signal (optionally) in response to an internal reset request. Also, it initializes the internal circuit upon input of the “L” signal. General-purpose CMOS I/O ports. These pins also serve as an input (wake-up input) of external interrupt 2 or as an A/D converter analog input. The input of external interrupt 2 is a hysteresis input. General-purpose CMOS I/O ports. These pins also serve as an input (wake-up input) of external interrupt 2. The input of external interrupt 2 is a hysteresis input. General-purpose CMOS I/O ports. This pin also serves as the clock I/O pin for the UART or 8-bit serial I/O. The resource is a hysteresis input. General-purpose CMOS I/O ports. This pin also serves as the data output pin for the UART or 8-bit serial I/O. General-purpose CMOS I/O ports. This pin also serves as the data input pin for the UART or 8-bit serial I/O. General-purpose CMOS I/O ports. This pin also serves as the external clock input pin for the 8/16bit capture timer/counter. The resource is a hysteresis input. General-purpose CMOS I/O ports. This pin also serves as the output pin for the 8/16-bit capture timer/counter or as the input pin for external interrupt 1. The resource is a hysteresis input. General-purpose CMOS I/O ports. These pins also serve as the input pin for external interrupt 1. The resource is a hysteresis input. 8 9 5 6 32 33 29 30 7 31 RST C 26 to 29 10 to 13 P00/INT20/AN4 to P03/INT23/AN7 G 1 to 4 25 to 28 P04/INT24 to P07/INT27 D 19 5 P30/UCK/SCK D 18 4 P31/UO/SO E 17 3 P32/UI/SI E 15 2 P33/EC D 14 1 P34/TO/INT10 D 13, 12 48, 35 P35/INT11, P36/INT12 D (Continued) *1 : FPT-30P-M02 *2 : MQP-48C-P01 6 MB89930A Series (Continued) Pin No. SSOP*1 MQFP*2 Pin name Circuit type E Function General-purpose CMOS I/O ports. This pin also serves as the buzzer output pin or the 12-bit programmable pulse generator output. General-purpose CMOS I/O ports. This pin also serves as the 8-bit PWM output pin. The pin is a hysteresis input. General-purpose CMOS I/O ports. These pins can also be used as N-channel open-drain ports. The pins also serve as A/D converter analog input pins. Power supply pin Power (GND) pin Power supply pin for the A-D converter. Apply equal potential to this pin and the VSS pin. MB89P935B: Capacitance pin for regulating the power supply. Connect an external ceramic capacitor of about 0.1 µF. MB89935A/B: This pin is not internally connedted. It is unnecessary to connect a capacitor. 11 34 P37/BZ/PPG 20 24 P50/PWM E 22 to 25 30 10 21 6 to 9 18 42 14 P40/AN0 to P43/AN3 VCC VSS AVSS F    16  C   15,16,17, 19,20,21, 22,23,36, 37,38,39, 40,41,43, 44,45,46, 47 N.C.  Internally connected pins Be sure to leave them open. *1 : FPT-30P-M02 *2 : MQP-48C-P01 7 MB89930A Series s EXTERNAL EPROM PIN DESCRIPTION (MB89PV930A only) Pin No. 49 50 51 52 53 54 55 58 59 60 61 62 63 64 65 66 67 68 69 70 71 73 75 76 77 78 79 80 56 57 72 74 Pin name VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS O4 O5 O6 O7 O8 CE A10 OE A11 A9 A8 A13 A14 VCC I/O O “H” level output pin Function O Address output pins I O Data input pins Power supply (GND) pin I Data input pins O O O ROM chip enable pin Outputs “H” during standby. Address output pin ROM output enable pin Outputs “L” at all times. O Address output pins O  EPROM power supply pin Internally connected pins Be sure to leave them open. N.C. 8 MB89930A Series s I/O CIRCUIT TYPE Type Circuit Remarks • At an oscillation feedback resistance of approximately 1 MΩ X1 A X0 Standby control signal • Hysteresis input B • At an output pull-up resister (P-ch) of approximately 50 kΩ/5.0 V • Hysteresis input P-ch C N-ch P-ch • • • • P-ch CMOS output CMOS input Hysteresis input (Resource input) Pull-up resistor optional D N-ch (Continued) 9 MB89930A Series (Continued) Type Circuit Remarks • CMOS output • CMOS input • Pull-up resistor optional P-ch E P-ch N-ch P-ch open-drain control • • • • CMOS output CMOS input Analog input N-ch open-drain output available F N-ch Analog input A/D enable P-ch • • • • P-ch CMOS output CMOS input Hysteresis input (Resource input) Analog input G N-ch Analog input A/D enable 10 MB89930A Series s HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “s ELECTRICAL CHARACTERISTICS” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input terminals open may lead to permanent damage due to malfunction and latchup; pull up or pull down the terminals through the resistors of 2 kΩ or more. Make the unused I/O terminal in a state of output and leave it open and if it is in an input state, handle it with the same procedure as the input terminals. 3. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 4. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 5. Treatment of Power Supply Pins on Microcontrollers with A/D Converters Connect to be AVSS = VSS even if the A/D converters are not in use. 6. Precautions when Using an External Clock When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode. 7. About the Wild Register Function No wild register can be debugged on the MB89PV930A. For the operation check, test the MB89P935B installed on a target system. 8. Program Execution in RAM When the MB89PV930A is used, no program can be executed in RAM. 9. Note to Noise in the External Reset Pin (RST) If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST). 11 MB89930A Series 10. Voltage Step-down Circuit Stabilization Time MB89930A series contains the following products and the operating characteristics vary with whether they contain the internal step-down circuit. Part number Operating voltage Voltage step-down circuit MB89935A MB89935B MB89P935B MB89PV930A 2.2 V to 5.5 V 2.2 V to 5.5 V 3.0 V to 5.5 V 2.7 V to 5.5 V Not included Not included Included Not included The same built-in resources are used for the above product types; operating sequences after the power-on reset are different depending on whether they have the internal voltage step-down circuit. The operating sequences after the power-on reset with the different models will be described below. • Operating sequences after the power-on reset with the different models Power supply (VCC) CPU operation of the product having the internal voltage step-down circuit (MB89P935B) Voltage step-down oscillation circuit stabilization + stabilization time time (217/FCH*) (218/FCH*) CPU operation of the product not having the internal voltage step-down circuit (MB89935A/ 935B, MB89PV930A) oscillation stabilization time (218/FCH*) Start of CPU operation for the product not having the internal voltage stepdown circuit (reset vector) * : FCH : Crystal oscillator frequency Start of CPU operation for the product not having the internal voltage stepdown circuit (reset vector) As described above, CPU starts at delayed time with the product having the internal voltage step-down circuit compared with the product not having the internal voltage step-down circuit. This is because the time should be allowed for the stabilization time for voltage step-down circuit for normal operation. 11. If used exceeding Ta = +85 °C, be sure to contact us for reliability limitations. 12 MB89930A Series s PROGRAMMING TO THE OTPROM WITH MB89P935B 1. Memory Space Normal operating mode Address 0000H I/O 0080H RAM 512 B 0280H Not available Corresponding adresses on the ROM programmer Address C000H C000H PROM 16 KB PROM 16 KB FFFFH FFFFH 2. Programming to the OTPROM To program to the OTPROM using an EPROM programmer AF220/AF210/AF120/AF110 (manufacturer : Yokogawa Digital Computer Corp.) . Inquiry : Yokogawa Digital Computer Corp. : TEL (81) -42-333-6222 Note : Programming to the OTPROM with MB89P935B is serial programming mode only. 3. Programming Adaptor for OTPROM To program to the OTPROM using an EPROM programmer AF220/AF210/AF120/AF110, use the programming adapter (manufacturer : Sunhayato Corp.) listed below. Adaptor socket : ROM3-FPT30M02-8L Inquiry : Sunhayato Corp. : TEL : (81) -3-3984-7791 FAX : (81) -3-3971-0535 E-mail : adapter@sunhayato.co.jp 4. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 13 MB89930A Series s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C256A-20TVM 2. Programming Socket Adapter To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer : Sunhayato Corp.) listed below. Package Compatible socket part number LCC-32 ROM-32LC-28DP-S Inquiry : Sunhayato Corp. : TEL : (81) -3-3984-7791 FAX : (81) -3-3971-0535 E-mail : adapter@sunhayato.co.jp 3. Memory Space Normal operating mode Address 0000H I/O 0080H RAM 512 B 0280H Not available Corresponding adresses on the ROM programmer Address 8000H 0000H PROM 32 KB EPROM 32 KB FFFFH 7FFFH 4. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0000H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer. 14 MB89930A Series s BLOCK DIAGRAM X0 X1 Main clock oscillator Timebase timer Clock controller CMOS I/O port Port 5 RST Reset circuit 8 bit PWM P50 / PWM CMOS I/O port UART prescaler UART Serial function switching Internal bus P04 / INT24 to P07 / INT27 4 Port 0 8 External interrupt2 (wake-up) P00 / INT20 / AN4 4 to P03 / INT23 / AN7 4 P30 / UCK / SCK P31 / UO / SO P32 / UI / SI 8 bit serial I/O AVSS 10 bit A/D Converter 8/16 bit capture timer/ counter P33 / EC Port 3 P34 / TO / INT10 4 P40 / AN0 4 to P43 / AN3 Port 4 CMOS I/O port (N-ch OD) Exernal interrupt 1 3 2 P35 / INT11 to P36 / INT12 512 byte RAM 12 bit PPG F2MC - 8 L CPU Other pins VCC, VSS, MOD1, MOD0, C Buzzer output 16 Kbyte ROM P37 / BZ / PPG Wild register CMOS I/O port 15 MB89930A Series s CPU CORE 1. Memory Space The microcontrollers of the MB89930A series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89930A series is structured as illustrated below. • Memory Space MB89935A/B 0000H I/O 0080H RAM 512 B 0100H Register 0100H Register 0080H RAM 512 B 0100H Register 0200H 0280H Not available 8000H C000H ROM 16 KB FFFFH FFFFH C000H PROM 16 KB FFFFH External EPROM 32 KB 0000H I/O 0080H RAM 512 B MB89P935B 0000H I/O MB89PV930A 0200H 0280H 0200H 0280H Not available Not available 16 MB89930A Series 2. Registers The MB89930A series has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided : Program counter (PC) : A 16-bit register for indicating instruction storage positions Accumulator (A) : A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX) : A 16-bit register for index modification Extra pointer (EP) : A 16-bit pointer for indicating a memory address Stack pointer (SP) : A 16-bit register for indicating a stack area Program status (PS) : A 16-bit register for storing a register pointer, a condition code 16 bit PC A T IX EP SP RP PS CCR Initial value : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFDH Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate I-flag = 0, IL1, 0 = 11 The other bit values are indeterminate. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR) . (See the diagram below.) • Structure of the Program Status Register RP bit15 bit14 bit13 bit12 bit11 bit10 bit9 R4 R3 R2 R1 R0 − − H-flag I-flag IL1,0 N-flag Z-flag bit8 − bit7 H bit6 I bit5 IL1 CCR bit4 IL0 bit3 N bit2 Z bit1 V bit0 C CCR initial value X011XXXXB PS × : Undefined V-flag C-flag 17 MB89930A Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. • Rule for Conversion of Actual Addresses of the General-purpose Register Area RP "0" Generated addresses "0" "0" "0" "0" "0" "0" A9 "1" A8 R4 A7 R3 A6 R2 A5 R1 A4 R0 A3 Low OP codes b2 A2 b1 A1 b0 A0 A15 A14 A13 A12 A11 A10 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. This flag is for decimal adjustment instructions. I-flag : Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when the flag is cleared to “0”. Cleared to “0” at the reset. IL1, 0 : Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 N-flag : Z-flag : V-flag : C-flag : IL0 0 1 0 1 Interrupt level 1 2 3 Low = no interrupt High-low High Set to “1” if the MSB becomes to “1” as the result of an arithmetic operation. Cleared to “0” when the bit is cleared to “0”. Set to “1” when an arithmetic operation results in 0. Cleared otherwise. Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0” if the overflow does not occur. Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. Set to the shift-out value in the case of a shift instruction. 18 MB89930A Series The following general-purpose registers are provided : General-purpose registers : An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 16 banks can be used on the MB89930A series. The bank currently in use is indicated by the register bank pointer (RP) . • Register Bank Configuration This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 16 banks Memory area 19 MB89930A Series s I/O MAP Address 0000H 0001H 0002H to 00006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 00024H CNTR COMR EIC1 PWM control register PWM compare register External interrupt 1 Control register 1 PDR3 DDR3 RSFR PDR4 DDR4 OUT4 PDR5 DDR5 RCR21 RCR22 RCR23 RCR24 BZCR TCCR TCR1 TCR0 TDR1 TDR0 TCPH TCPL TCR2 Port 3 data register Port 3 data direction register Reset flag register Port 4 data register Port 4 data direction register Port 4 output format register Port 5 data register Port 5 data direction register 12-bit PPG control register 1 12-bit PPG control register 2 12-bit PPG control register 3 12-bit PPG control register 4 Buzzer register Capture control register Timer 1 control register Timer 0 control register Timer 1 data register Timer 0 data register Capture data register H Capture data register L Timer output control register Vacancy R/W W R/W 0 - 0000 0 0 X X XXXX X X 000000 0 0 SYCC STBC WDTC TBTC Register name PDR0 DDR0 Register description Port 0 data register Port 0 data direction register Vacancy System clock control register Standby control register Watchdog timer control register Timebase timer control register Vacancy R/W W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W X X XXXX X X 000000 0 0 XXXX- - - - - - - XXXX - - - - 0000 - - - - 0000 -------X -------0 000000 0 0 - - 0000 0 0 0 - 0000 0 0 - - 0000 0 0 - - ---000 000000 0 0 000000 0 0 000- 0000 X X XXXX X X X X XXXX X X X X XXXX X X X X XXXX X X ------00 R/W R/W W R/W 1 - - MM 1 0 0 00010 - - 0 - - - XXXX 00---000 Read/write R/W W Initial value X X XXXX X X 000000 0 0 (Continued) 20 MB89930A Series Address 0025H 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH to 0002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH to 003FH 0040H 0041H 0042H 0043H 0044H 0045H 0046H 0047H 0048H to 006FH 0070H Register name EIC2 Register description External interrupt 1 Control register 2 Vacancy Read/write R/W Initial value - - - - 0000 SMC SRC SSD SIDR SODR UPC ADC1 ADC2 ADDH ADDL ADEN EIE2 EIF2 SMR SDR SSEL WRARH0 WRARL0 WRDR0 WRARH1 WRARL1 WRDR1 WREN WROR PUL0 Serial mode control register Serial rate control register Serial status and data register Serial input data register Serial output data register Clock division selection register Vacancy A/D converter control register 1 A/D converter control register 2 A/D converter data register H A/D converter data register L A/D enable register Vacancy External interrupt 2 control register1 External interrupt 2 control register2 Vacancy Serial mode register Serial data register Serial function switching register Vacancy Upper-address setting register Lower-address setting register Data setting register 0 Upper-address setting register Lower-address setting register Data setting register 1 Address comparison EN register Wild-register data test register Vacancy Port-0 pull-up setting register R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R/W W R/W R/W R/W 00000 - 0 0 - - 0110 0 0 00100 - 1X X X XXXX X X X X XXXX X X - - - - 0010 - 00000 0 0 - 00000 0 1 - - - - - - XX X X XXXX X X 000000 0 0 000000 0 0 -------0 000000 0 0 X X XXXX X X -------0 X X XXXX X X X X XXXX X X X X XXXX X X X X XXXX X X X X XXXX X X X X XXXX X X X X XXXX 0 0 ------00 000000 0 0 (Continued) 21 MB89930A Series (Continued) Address 0071H 0072H 0073H to 007AH 007BH 007CH 007DH 007EH 007FH ILR1 ILR2 ILR3 ILR4 ITR Register name PUL3 PUL5 Register description Port-3 pull-up setting register Port-5 pull-up setting register Vacancy Interrupt level setting register1 Interrupt level setting register2 Interrupt level setting register3 Interrupt level setting register4 Interrupt test register Read/write R/W R/W W W W W Not available Initial value 000000 0 0 -------0 111111 1 1 111111 1 1 111111 1 1 111111 1 1 ------00 - : Unused, X : Undefined, M : Set using the mask option Note : Do not use vacancies. 22 MB89930A Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage Input voltage Output voltage Maximum clamp current Maximum total clamp current “L” level maximum output current “L” level average output current “L” level total maximum output current “H” level maximum output current “H” level average output current “H” level total maximum output current Power consumption Operating temperature Storage temperature Symbol VCC VI VO ICLAMP ∑ |ICLAMP| IOL1 IOL2 IOLAV ΣIOL IOH IOHAV ΣIOH Pd Ta Tstg Value Min VSS − 0.3 VSS − 0.3 VSS − 0.3 – 2.0          −40 −40 −55 Max VSS + 6.0 VCC + 0.3 VCC + 6.0 + 2.0 20 20 10 4 100 −10 −2 −50 200 +85 +125 +150 Unit V V V mA mA mA mA mA mA mA mA mA mW °C °C °C *3 Average value (operating current × operating rate) *2 *2 Pins P40 to P43 Pins excluding P40 to P43 Average value (operating current × operating rate) *1 Remarks *1 : If the maximum current to /from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *2 : • • • • • • • • • • Applicable to pins : P00 to P07, P30 to P37, P40 to P43, P50 Use within recommended operating conditions. Use at DC voltage (current) The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instaneously or for prolonged periods. Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potentional may pass through the protective diode and increase the potentional at the VCC pin, and this may affect other devices. Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on result. Care must be taken not to leave the +B input pin open. Note that analog system input pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signl input. 23 MB89930A Series • Sample recommended circuits : • Input/Output Equivalent circuits Protective diode VCC + B input (0 V to 16 V) Limiting resistance P-ch N-ch R *3 : If used exceeding Ta = +85 °C, be sure to contact us for reliability limitations. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 24 MB89930A Series 2. Recommended Operating Conditions Parameter Symbol Value Min 2.2 1.5 VIH “H” level input voltage VIHS VIL “L” level input voltage VILS Open-drain output pin application voltage Operating temperature VD Ta VSS − 0.3 VSS − 0.3 −40 −40 0.2 VCC VCC + 0.3 +85 +125 V V °C °C * 0.8 VCC VSS − 0.3 VCC + 0.3 0.3 VCC V V 0.7 VCC Max 5.5 6.0 VCC + 0.3 Unit V V V Remarks Normal operation assurance range MB89935A/B Retains the RAM state in stop mode P00 to P07, P30 to P37, P40 to P43, P50, UI/SI MOD0/1, RST, EC, INT20 to INT27, UCK/SCK, INT10 to INT12 P00 to P07, P30 to P37, P40 to P43, P50, UI/SI MOD0/1, RST, EC, INT20 to INT27, UCK/SCK, INT10 to INT12 P40 to P43 Power supply voltage VCC * : If used exceeding Ta = +85 °C, be sure to contact us for reliability limitations. 6 5 Operating voltage (V) Analog accuracy assurance range Operation assurance range 4 3 2 : Area is assured only for the MB89935A/B 1 0 1 2 3 5 6 7 4 Operating Frequency (MHz) 8 9 10 WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 25 MB89930A Series 3. DC Characteristics (VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, FCH = 10 MHz (External clock) , Ta = −40 °C to +85 °C) Parameter Symbol VIH “H” level input voltage VIHS Pin name P00 to P07, P30 to P37, P40 to P43, P50 , UI/SI RST, MOD0/1, UCK/SCK, EC, INT20 to INT27, INT10 to INT12 P00 to P07, P30 to P37, P40 to P43, P50 , UI/SI RST, MOD0/1, UCK/SCK, EC, INT20 to INT27, INT10 to INT12 Condition Value Min 0.7 VCC Typ Max VCC + 0.3 Unit Remarks   V  0.8 VCC  VCC + 0.3 V VIL “L” level input voltage VILS  VSS − 0.3  0.3 VCC V  VSS − 0.3  0.2 VCC V Open-drain output pin application voltage “H” level output voltage “L” level output voltage Input leakage current Pull-up resistance VD P40 to P43  VSS − 0.3  VCC + 0.3 V VOH VOL1 VOL2 ILI P00 to P07, P30 to P37, IOH = −4.0 mA P40 to P43, P50 P00 to P07, P30 to P37, IOL = 4.0 mA P50, RST P40 to P43 IOL = 12.0 mA P00 to P07, P30 to P37, P40 to P43, P50 , 0.45 V < VI < VCC MOD0/1 P00 to P07, P30 to P37, VI = 0.0 V P40 to P43, P50 Normal operation mode (External clock, highest gear speed) Sleep mode (External clock, highest gear speed) Stop mode VCC Ta = +25 °C (External clock) Other than AVSS, VCC, VSS When A/D converter stops When A/D converter starts When A/D converter stops VCC − 0.5    25              50 8 6 10 8 4 3   5  0.4 0.4 ±5 100 12 9 15 12 6 5 1 10 15 V V V Without µA pull-up resistor kΩ mA MB89935A/B mA MB89P935B mA MB89935A/B mA MB89P935B mA MB89935A/B mA MB89P935B µA MB89935A/B µA MB89P935B pF MB89P935B RPULL ICC VCC Power supply current ICCS ICCH Input capacitance 26 When A/D converter stops  CIN MB89930A Series 4. AC Characteristics (1) Reset Timing (AVSS = VSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter RST “L” pulse width tHCYL : 1 oscillating clock cycle time Symbol tZLZH Condition  Value Min 48 tHCYL Max  Unit ns Remarks tZLZH RST 0.2 VCC 0.2 VCC Notes: •When the power-on reset option is not on, leave the external reset on until oscillation becomes stable. •If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST). (2) Power-on Reset (AVSS = VSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Power supply rising time Power supply cutoff time Symbol tR tOFF Condition  Value Min  1 Max 50  Unit ms ms Due to repeated operations Remarks tR 2.0 V tOFF VCC 0.2 V 0.2 V 0.2 V Note : The supply voltage must be set to the minimum value required for operation within the prescribed default oscillation settling time. 27 MB89930A Series (3) Clock Timing (AVSS = VSS = 0.0 V, Ta = –40°C to +85°C) Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time Symbol FCH tXCYL tWH tWL tCR tCF  Condition Value Min 1 100 20  Max 10 1000  10 Unit MHz ns ns ns Remarks • X0 and X1 Timing and Conditions tXCYL tWH tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tWL X0 • Main Clock Conditions When a crystal or ceramic resonator is used When an exernal clock is used X0 X1 X0 X1 open (4) Instruction Cycle Parameter Instruction cycle (minimum execution time) Symbol tINST Value (typical) 4/FCH, 8/FCH, 16/FCH, 64/FCH (AVSS = VSS = 0.0 V, Ta = –40°C to +85°C) . Unit µs Remarks tINST = 0.4 µs when operating at FCH = 10 MHz (4/FCH) 28 MB89930A Series (5) Recommended Resonator Manufactures • Sample application of ceramic resonator X0 R X1 C1 C2 Resonator manufacturer Resonator CSTS0400MG06 CSTCC4.00MG0H6 CSTS0800MG06 CSTCC8.00MG0H6 CST10.0MTW CSTCC10.0MG0H6 Frequency (MHz) 4.00 4.00 8.00 8.00 10.00 10.00 C1 Built-in Built-in Built-in Built-in Built-in Built-in C2 Built-in Built-in Built-in Built-in Built-in Built-in R 330 Ω 330 Ω Not required Not required Not required Not required Murata Mfg. Co., Ltd. Inquiry : Murata Mfg. Co., Ltd. • Murata Electronics North America, Inc. : TEL1-404-436-1300 • Murata Europe Management GmbH : TEL 49-911-66870 • Murata Electronics Singapore (Pte.) : TEL 65-758-4233 29 MB89930A Series (6) Peripheral Input Timing (VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, Ta = −40 °C to +85 °C) Symbol tILIH tIHIL Pin name INT10 to INT12, INT20 to INT27, EC Value Min 2 tINST* 2 tINST* Max   Unit µs µs Remarks Parameter Peripheral input “H” pulse width Peripheral input “L” pulse width * : For information on tINST see “ (4) Instruction Cycle”. tILIH tIHIL INT10 to INT12, INT20 to INT27, EC 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC (VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Peripheral input “H” noise limit Peripheral input “L” noise limit Symbol tIHNC tILNC Pin name INT10 to INT12, EC Value Min 7 7 Typ 15 15 Max 23 23 Unit ns ns Remarks tIHNC tILNC INT10 to INT12, EC 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 30 MB89930A Series (7) UART, Serial I/O Timing (VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, Ta = −40 °C to +85 °C) Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name UCK/SCK UCK/SCK, SO Internal shift UCK/SCK, SI clock mode UCK/SCK, SI UCK/SCK UCK/SCK UCK/SCK, SO UCK/SCK, SI UCK/SCK, SI External shift clock mode Condition Value Min 2 tINST* −200 1/2 tINST* 1/2 tINST* tINST* tINST* 0 1/2 tINST* 1/2 tINST* Max  200     200   Unit Remarks µs ns µs µs µs µs ns µs µs Parameter Serial clock cycle time UCK/SCK ↓ → SO time Valid SI → UCK/SCK↑ UCK/SCK ↑ → Valid SI hold time Serial clock “H” pulse width Serial clock “L” pulse width UCK/SCK ↓ → SO time Valid SI → UCK/SCK UCK/SCK ↑ → Valid SI hold time * : For information on tinst, see “ (4) Instruction Cycle”. • Internal Shift Clock Mode tSCYC 2.4 V UCK/SCK 0.8 V tSLOV 0.8 V SO 2.4 V 0.8 V tIVSH tSHIX SI 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External Shift Clock Mode tSLSH tSHSL 0.8 VCC 0.8 VCC UCK/SCK 0.2 VCC 0.2 VCC tSLOV SO 2.4 V 0.8 V tIVSH tSHIX SI 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 31 MB89930A Series 5. A/D Converter (1) A/D Converter Electrical Characteristics (VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, Ta = −40 °C to +85 °C) Value Min   −5.0 −3.0 −2.5 VOT VFST IAIN  VCC − 6.5 LSB   0 Typ     VCC − 1.5 LSB    Max 10 +5.0 +3.0 +2.5 VCC + 2.0 LSB 38 tINST* 10 VCC Unit bit LSB LSB LSB V V µs µA V Remarks Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage A/D mode conversion time Analog port input current Analog input voltage range Symbol AVSS − 3.5 LSB AVSS + 0.5 LSB AVSS + 4.5 LSB * : For information on tinst, see “ (4) Instruction Cycle” in “4. AC Characteristics.” (2) A/D Converter Glossary • Resolution Analog changes that are identifiable with the A/D converter When the number of bits is 10, analog voltage can be divided into 210 = 1024. • Linearity error (unit : LSB) The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics • Differential linearity error (unit : LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value • Total error (unit : LSB) The difference between theoretical and actual conversion values Theoretical I/O characteristics 3FF 3FE 3FD 1.5 LSB VFST 3FF 3FE 3FD Actual conversion value {1 LSB × N + 0.5 LSB} Total error Digital output 004 003 002 001 0.5 LSB AVSS VCC VOT 1 LSB Digital output 004 003 002 001 AVSS VNT Actual conversion value Theoretical value VCC Analog input Analog input 1 LSB = VFST − VOT 1022 (V) Total error of digital output N = VNT − {1 LSB × N + 0.5 LSB} 1 LSB 32 MB89930A Series Zero transition error 004 Actual conversion value 003 3FF Full-scale transition error Theoretical value Actual conversion value Digital output Digital output 3FE VFST (Measured value) Actual conversion value 002 Theoretical conversion value 001 VOT (Measured value) AVSS Actual conversion value 3FD 3FC VCC Analog input Analog input Linearity error 3FF 3FE Actual conversion value {1 LSB × N + VOT} N+1 Differential linearity error Theoretical conversion value Digital output 3FD Actual conversion value Digital output VNT 004 003 002 001 AVSS VFST (Measured value) V (N + 1) T N Actual conversion value Theoretical conversion value VOT (Measured value) VCC N−1 VNT Actual conversion value N−2 AVSS VCC Analog input Analog input Linearity error of digital output N = VNT − {1 LSB × N + VOT} 1 LSB V (N + 1) T − VNT −1 1 LSB Differential linearity of error digital output N = 33 MB89930A Series (3) Notes on Using A/D Converter • Input impedance of the analog input pins The A/D converter used for the MB89930A series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for 16 instruction cycles after activating A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low (below 4 kΩ) . Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 µF for the analog input pin. • Analog Input Equivalent Circuit Analog input pin Sample hold circuit Comparator R C If the analog input impedance is higher than 4 kΩ, it is recommended to connect an external capacitor of approx. 0.1 µF. MB89935A/B R = approx. 2.2 kΩ, C = approx. 45 pF MB89P935B R = approx. 3.2 kΩ, C = approx. 30 pF Close for 16 instruction cycles after activating A/D conversion Analog channel selector • Error The smaller the | VCC − AVSS |, the greater the error would become relatively. 34 MB89930A Series s EXAMPLE CHARACTERISTICS • Power supply current (MB89935A/MB89935B/MB89P935B : 8 MHz ( when FAR resonator [NM8000] / external clock are used) MB89935A Normal operation mode (ICC1 − VCC, ICC2 − VCC) ICC (mA) (FCH = 8 MHz, Ta = +25 °C) 8 MB89935B Normal operation mode (ICC1 − VCC, ICC2 − VCC) ICC (mA) (FCH = 8 MHz, Ta = +25 °C) 8 MB89935A/MB89935B/ MB89P935B MB89P935B Normal operation mode (ICC1 − VCC, ICC2 − VCC) Only clock oscillation circuit FAR : [NM8000] ICC (mA) ICC (mA) (FCH = 8 MHz, Ta = +25 °C) (FCH = 8 MHz, Ta = +25 °C) 8 2 6 ICC1 (gear : 4 divide) 6 ICC1 (gear : 4 divide) 4 6 4 ICC2 (gear : 64 divide) 4 ICC1 (gear : 4 divide) 1 MB89935A MB89P935B 2 2 ICC2 (gear : 64 divide) 2 ICC2 (gear : 64 divide) MB89935B 0 3 4 5 VCC (V) 6 0 3 4 5 VCC (V) 6 0 3 4 5 VCC (V) 6 0 3 4 5 VCC (V) 6 FAR : [NM8000] External clock MB89935A Sleep mode (ICCs1 − VCC, ICCs2 − VCC) ICCs (mA) (FCH = 8 MHz, Ta = +25 °C) 4 MB89935B Sleep mode (ICCs1 − VCC, ICCs2 − VCC) ICCs (mA) (FCH = 8 MHz, Ta = +25 °C) 4 MB89935A/MB89935B/ MB89P935B MB89P935B Sleep mode Only clock oscillation circuit (ICCs1 − VCC, ICCs2 − VCC) FAR : [NM8000] ICCs (mA) ICCs (mA) (FCH = 8 MHz, Ta = +25 °C) (FCH = 8 MHz, Ta = +25 °C) 4 2 3 ICCs1 (gear : 4 divide) 2 3 3 2 ICCs1 (gear : 4 divide) 2 ICCs1 (gear : 4 divide) 1 MB89935A 1 ICCs2 (gear : 64 divide) 1 ICCs2 (gear : 64 divide) 1 ICCs2 (gear : 64 divide) 0 3 4 5 VCC (V) 6 3 4 5 VCC (V) 6 0 3 4 5 VCC (V) MB89P935B MB89935B 6 0 3 4 5 VCC (V) 6 0 FAR : [NM8000] External clock 35 MB89930A Series • MB89935A/MB89935B/MB89P935B : 4 MHz (when FAR resonator [NM4000] / external clock are used) MB89935A Normal operation mode (ICC1 − VCC, ICC2 − VCC) ICC (mA) (FCH = 4 MHz, Ta = +25 °C) 4 ICC1 (gear : 4 divide) MB89935B Normal operation mode (ICC1 − VCC, ICC2 − VCC) ICC (mA) (FCH = 4 MHz, Ta = +25 °C) 4 MB89935A/MB89935B/ MB89P935B MB89P935B/ Normal operation mode (ICC1 − VCC, ICC2 − VCC) Only clock oscillation circuit FAR : [NM4000] ICC (mA) ICC (mA) (FCH = 4 MHz, Ta = +25 °C) (FCH = 4 MHz, Ta = +25 °C) 4 2 3 3 ICC1 (gear : 4 divide) 3 ICC1 (gear : 4 divide) 2 2 ICC2 (gear : 64 divide) 2 1 MB89935A 1 ICC2 (gear : 64 divide) 1 1 ICC2 (gear : 64 divide) 3 4 5 VCC (V) 6 MB89P935B MB89935B 0 3 4 5 VCC (V) 6 0 3 4 5 VCC (V) 6 0 3 4 5 VCC (V) 6 0 FAR : [NM4000] External clock MB89935A Seep mode (ICCs1 − VCC, ICCs2 − VCC) ICCs (mA) (FCH = 4 MHz, Ta = +25 °C) 4 MB89935B Seep mode (ICCs1 − VCC, ICCs2 − VCC) ICCs (mA) (FCH = 4 MHz, Ta = +25 °C) 4 MB89P935B MB89935A/MB89935B/ Seep mode MB89P935B/ (ICCs1 − VCC, ICCs2 − VCC) Only clock oscillation circuit FAR : [NM4000] ICCs (mA) ICC (mA) (FCH = 4 MHz, Ta = +25 °C) (FCH = 4 MHz, Ta = +25 °C) 4 2 3 3 3 2 ICCs1 (gear : 4 divide) 2 ICCs1 (gear : 4 divide) 2 ICCs1 (gear : 4 divide) 1 ICCs2 (gear : 64 divide) 4 5 6 VCC (V) ICCs2 (gear : 64 divide) 3 4 5 VCC (V) 6 1 MB89935A MB89P935B 1 1 ICCs2 (gear : 64 divide) 0 3 4 5 VCC (V) 6 3 MB89935B 0 3 4 5 VCC (V) 6 0 0 FAR : [NM4000] External clock 36 MB89930A Series • MB89935A/MB89935B : 10 MHz (when external clock is used) MB89935A/B Normal operation mode (ICC1 − VCC, ICC2 − VCC) ICC (mA) 8 (FCH = 10 MHz, Ta = +25 °C) MB89935A/B Normal operation mode (ICCs1 − VCC, ICCs2 − VCC) ICCs (mA) (FCH = 10 MHz, Ta = +25 °C) 4 MB89935A/B Normal operation mode (ICCh − VCC) ICCh (µA) (FCH = 10 MHz, Ta = +25 °C) 0.4 6 ICC1 (gear : 4 divide) 4 3 0.3 2 ICCs1 (gear : 4 divide) 0.2 2 ICC2 (gear : 64 divide) 1 0.1 ICCs2 (gear : 64 divide) 0 0 3 4 5 VCC (V) 6 0 0 3 4 5 VCC (V) 6 0 0 3 4 5 VCC (V) 6 MB89935A/MB89935B Stop mode (ICCh − VCC) ICCh (µA) 10 (FCH = 10 MHz, VCC = 5.5 V) ICCh (µA) 10 MB89P935B Stop mode (ICCh − VCC) (FCH = 10 MHz, VCC = 5.5 V) 8 8 6 6 4 4 2 2 0 −50 −25 0 25 50 75 100 125 150 0 −50 −25 0 25 50 75 100 125 150 Temperature (°C) Temperature (°C) 37 MB89930A Series (2) “L” level output voltage VOL vs. IOL1 VOL (V) 0.6 VCC = 2.0 V VOL (V) 0.6 VOL vs. IOL2 VCC = 2.0 V 0.5 VCC = 2.5 V 0.4 VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VCC = 6.0 V 0.5 VCC = 2.5 V 0.4 VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VCC = 6.0 V 0.3 0.3 0.2 0.2 0.1 0.1 0.0 1 2 3 4 5 6 IOL1 (mA) 0.0 4 6 8 10 12 14 16 IOL2 (mA) (3) “H” level output voltage (VCC − VOH) vs. IOH VCC − VOH (V) 0.8 0.7 VCC = 2.5 V 0.6 0.5 0.4 0.3 0.2 0.1 0.0 −1 VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VCC = 6.0 V VCC = 2.0 V −2 −3 −4 −5 −6 IOH (mA) 38 MB89930A Series s MASK OPTIONS Part number No Specifying procedure Selection of initial value of main clock oscillation settling time* (with FCH = 10 MHz) 01 : 214/FCH (Approx.1.63 ms) 10 : 217/FCH (Approx.13.1 ms) 11 : 218/FCH (Approx.26.2 ms) Power-on reset selection With power-on reset Without power-on reset Reset pin output With reset output Without reset output MB89935A/B Specify when ordering masking MB89P935B MB89PV930A Setting not possible 1 Selectable Fixed to 218/FCH (Approx. 26.2 ms) Fixed to 218/FCH (Approx. 26.2 ms) 2 Selectable Available Available 3 Selectable With reset output With reset output FCH : Main clock oscillation frequency * : Initial value to which the oscillation settling time bit (SYCC : WT1, WT0) in the system clock control register is set s ORDERING INFORMATION Part number MB89935APFV MB89935BPFV MB89P935BPFV MB89PV930ACFV Package 30-pin Plastic SSOP (FPT-30P-M02) 48-pin Ceramic MQFP (MQP-48C-P01) Remarks 39 MB89930A Series s PACKAGE DIMENSIONS 30-pin plastic SSOP (FPT-30P-M02) *1 9.70±0.10(.382±.004) 30 16 Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max). Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. 0.17±0.03 (.007±.001) INDEX *2 5.60±0.10 (.220±.004) 7.60±0.20 (.299±.008) Details of "A" part 1.25 –0.10 .049 –.004 1 15 +0.20 +.008 (Mounting height) 0.65(.026) 0.24 –0.07 .009 +0.08 +.003 –.003 "A" 0.25(.010) 0~8˚ 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10(.004) 0.10±0.10 (.004±.004) (Stand off) C 2003 FUJITSU LIMITED F30003S-c-3-4 Dimensions in mm (inches) Note: The values in parentheses are reference values (Continued) 40 MB89930A Series (Continued) 48-pin ceramic MQFP (MQP-48C-P01) 17.20(.677)TYP 15.00±0.25 (.591±.010) 14.82±0.35 (.583±.014) 1.50(.059)TYP 1.00(.040)TYP 8.80(.346)REF 0.80±0.22 (.0315±.0087) PIN No.1 INDEX PIN No.1 INDEX 1.02±0.13 (.040±.005) 10.92 –0.0 .430 –0 +0.13 +.005 7.14(.281) 8.71(.343) TYP TYP PAD No.1 INDEX 0.30(.012)TYP 4.50(.177)TYP 1.10 –0.25 .043 –.010 +0.45 +.018 0.40±0.08 (.016±.003) 0.60(.024)TYP 8.50(.335)MAX 0.15±0.05 (.006±.002) C 1994 FUJITSU LIMITED M48001SC-4-2 Dimensions in mm (inches) Note: The values in parentheses are reference values 41 MB89930A Series FUJITSU LIMITED All Rights Reserved. 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