MB89F202

FUJITSU SEMICONDUCTOR DATA SHEET DS07-12561-1E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89202 Series MB89202/F202/V201 ■ DESCRIPTION The MB89202 series is a line of single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such, timers, a serial interface, an A/D converter and an external interrupt. ■ FEATURES • • • • • • • • • • • • • • F2MC-8L family CPU core Maximum memory space : 64 Kbytes Minimum execution time : 0.32 µs/12.5 MHz Interrupt processing time : 2.88 µs/12.5 MHz I/O ports : Max 26 channels 21-bit time-base timer 8-bit PWM timer 8/16-bit capture timer/counter 10-bit A/D converter : 8 channels UART 8-bit serial I/O External interrupt 1 : 3 channels External interrupt 2 : 8 channels Wild Register : 2 bytes (Continued) ■ PACKAGES 32-pin plastic SH-DIP 34-pin plastic SSOP (DIP-32P-M06) (FPT-34P-M03) MB89202 Series (Continued) • MB89F202 : Flash (at least 10,000 program / erase cycles) with read protection • Low-power consumption modes ( sleep mode, and stop mode) • SH-DIP-32, SSOP-34 package • CMOS Technology ■ PRODUCT LINEUP Part number Parameter MB89202 Mask ROM product 16 K × 8 bits (internal mask ROM) Number of instructions : Instruction bit length : Instruction length : Data bit length : Minimum execution time : Interrupt processing time : MB89F202 Flash memory product (read protection) 16 K × 8 bits (internal flash) 512 × 8 bits 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.32 µs to 5.1 µs (12.5 MHz) 2.88 µs to 46.1 µs (12.5 MHz) MB89V201 Evaluation product (for development) 32K x 8 bits (external EPROM) Classification ROM size RAM size CPU functions Ports 21-bit time-base timer Watchdog timer General-purpose I/O ports (CMOS) : 26 (also serve as peripherals ) (4 ports are also an N-ch open-drain type.) 21-bit Interrupt cycle : 0.66 ms, 2.64 ms, 21 ms, or 335.5 ms with 12.5 MHz main clock Reset generation cycle : 335.5 ms minimum with 12.5 MHz main clock 8-bit interval timer operation (square output capable, operating clock cycle : 0.32 µs , 2.56 µs, 5.1 µs, 20.5 µs) 8-bit resolution PWM operation (conversion cycle : 81.9 µs to 21.47 s : in the selection of internal shift clock of 8/16-bit capture timer) Count clock selectable between 8-bit and 16-bit timer/counter outputs 8-bit capture timer/counter × 1 channel + 8-bit timer or 16-bit capture timer/counter × 1 channel Capable of event count operation and square wave output using external clock input with 8-bit timer 0 or 16-bit counter Transfer data length : 6/7/8 bits 8 bits LSB first/MSB first selectable One clock selectable from four operation clocks (one external shift clock, three internal shift clocks : 0.8 µs, 6.4 µs, 25.6 µs) Output frequency : Pulse width and cycle selectable 3 channels (Interrupt vector, request flag, request output enabled) Edge selectable (Rising edge, falling edge, or both edges) Also available for resetting stop/sleep mode (Edge detectable even in stop mode) 1 channel with 8 inputs (Independent L-level interrupt and input enable) Also available for resetting stop/sleep mode (Level detectable even in stop mode) (Continued) 8-bit PWM timer 8/16-bit capture, timer/counter UART 8-bit Serial I/O 12-bit PPG timer External interrupt 1 (wake-up function) External interrupt 2 (wake-up function) 2 MB89202 Series (Continued) Part number Parameter MB89202 MB89F202 MB89V201 10-bit A/D converter Wild Register Standby mode 10-bit precision × 8 channels A/D conversion function (Conversion time : 12.16 µs/12.5 MHz) Continuous activation by 8/16-bit timer/counter output or time-base timer counter 8-bit × 2 Sleep mode, and Stop mode Power-on reset : Oscillation stabillization wait*1 External reset : a few µs Software reset : a few µs Power-on reset : Voltage regulator and oscillation stabillization wait (31.5 ms/12.5 MHz) External reset : Oscillation stabillization wait (21.0 ms/12.5 MHz) Software reset : a few µs 3.5 V to 5.5 V Power-on reset : Oscillation stabillization wait (21.0 ms / 12.5 MHz) External reset : Oscillation stabillization wait (21.0 ms / 12.5 MHz) Software reset : a few µs 2.7 V to 5.5 V Overhead time from reset to the first instruction execution Power supply voltage*2 2.2 V to 5.5 V *1 : Check section “■ MASK OPTIONS” *2 : The minimum operating voltage varies with the operating frequency, the function, and the connected ICE. (The operating voltage of the A/D converter is assured separately. Check section “■ ELECTRICAL CHARACTERISTICS.”) ■ PACKAGE AND CORRESPONDING PRODUCTS Package DIP-32P-M06 FPT-34P-M03 FPT-64P-M03 : Available × × : Not available × MB89202 MB89F202 MB89V201 × × ■ DIFFERENCES AMONG PRODUCTS • Memory Size Before evaluating using the evaluation product, verify its differences from the product that will actually be used. • Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “■ MASK OPTIONS”. 3 MB89202 Series ■ PIN ASSIGNMENTS (TOP VIEW) P04/INT24 P05/INT25 P06/INT26 P07/INT27 P60 P61 RST X0 X1 VSS P37/BZ/PPG P36/INT12 P35/INT11 P34/TO/INT10 P33/EC C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC P03/INT23/AN7 P02/INT22/AN6 P01/INT21/AN5 P00/INT20/AN4 P43/AN3* P42/AN2* P41/AN1* P40/AN0* P72* P71* P70* P50/PWM P30/UCK/SCK P31/UO/SO P32/UI/SI * : Large-current drive type (DIP-32P-M06) (Continued) 4 MB89202 Series (Continued) (TOP VIEW) P04/INT24 P05/INT25 P06/INT26 P07/INT27 P60 P61 RST X0 X1 VSS P37/BZ/PPG P36/INT12 P35/INT11 P34/TO/INT10 P33/EC N.C. C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 VCC P03/INT23/AN7 P02/INT22/AN6 P01/INT21/AN5 P00/INT20/AN4 P43/AN3 * P42/AN2 * P41/AN1 * P40/AN0 * P72 * P71 * P70 * N.C. P50/PWM P30/UCK/SCK P31/UO/SO P32/UI/SI *: Large-current drive type N.C. : Internally connected. Do not use. (FPT-34P-M03) 5 MB89202 Series ■ PIN DESCRIPTION Pin No. SH-DIP32*1 SSOP34*2 Pin name 8 9 X0 X1 P60, P61 Circuit type A H/E Function Pins for connecting the crystal for the main clock. To use an external clock, input the signal to X0 and leave X1 open. General-purpose CMOS input port for MB89F202. General-puspose CMOS I/O port for MB89202/MB89V201. Reset I/O pin. This pin serves as an N-channel open-drain reset output with pull-up resistor (not available for MB89F202) and a reset input as well. The reset is a hysteresis input. It outputs the “L” signal in response to an internal reset request. Also, it initializes the internal circuit upon input of the “L” signal. General-purpose CMOS I/O ports. These pins also serve as an input (wake-up input) of external interrupt 2 or as an 10-bit A/D converter analog input. The input of external interrupt 2 is a hysteresis input. General-purpose CMOS I/O ports. These pins also serve as an input (wake-up input) of external interrupt 2. The input of external interrupt 2 is a hysteresis input. General-purpose CMOS I/O ports. This pin also serves as the clock I/O pin for the UART or 8-bit serial I/O. The resource is a hysteresis input. General-purpose CMOS I/O ports. This pin also serves as the data output pin for the UART or 8-bit serial I/O. General-purpose CMOS I/O ports. This pin also serves as the data input pin for the UART or 8-bit serial I/O. The resource is a hysteresis input. General-purpose CMOS I/O ports. This pin also serves as the external clock input pin for the 8/16-bit capture timer/counter. The resource is a hysteresis input. General-purpose CMOS I/O ports. This pin also serves as the output pin for the 8/16-bit capture timer/ counter or as the input pin for external interrupt 1. The resource is a hysteresis input. General-purpose CMOS I/O ports. These pins also serve as the input pin for external interrupt 1. The resource is a hysteresis input. General-purpose CMOS I/O ports. This pin also serves as the buzzer output pin or the 12-bit PPG output. General-purpose CMOS I/O ports. This pin also serves as the 8-bit PWM timer output pin. (Continued) 8 9 5, 6 5, 6 7 7 RST C P00/INT20/ AN4 28 to 31 30 to 33 to P03/ INT23/AN7 1 to 4 1 to 4 P04/INT24 to P07/INT27 P30/UCK/ SCK G D 19 20 B 18 19 P31/UO/SO E 17 18 P32/UI/SI B 15 15 P33/EC B 14 14 P34/TO/ INT10 B 13, 12 13, 12 P35/INT11, P36/INT12 P37/BZ/ PPG P50/PWM B 11 20 11 21 E E 6 MB89202 Series (Continued) Pin No. SH-DIP32*1 SSOP34*2 Pin name P40/AN0 to P43/ AN3 VCC VSS Circuit type F E ⎯ ⎯ Function General-purpose CMOS I/O ports. These pins can also be used as N-channel open-drain ports. These pins also serve as 10-bit A/D converter analog input pins. General-purpose CMOS I/O ports. Power supply pin Power (GND) pin MB89F202: Capacitance pin for regulating the power supply. Connect an external ceramic capacitor of about 0.1µF. MB89202: This pin is not internally connected. It is unnecessary to connect a capacitor. Internally connected pins Be sure to leave it open. 24 to 27 26 to 29 21 to 23 23 to 25 P70 to P72 32 10 34 10 16 17 C ⎯ ⎯ 16, 22 N.C. ⎯ *1 : DIP-32P-M06 *2 : FPT-34P-M03 7 MB89202 Series ■ I/O CIRCUIT TYPE Type Circuit Remarks • At an oscillation feedback resistance of approximately 500 kΩ X1 A X0 Standby control signal P-ch • CMOS output • Hysteresis input • Pull-up resistor optional P-ch B N-ch Input enable Port input / Resource input P-ch (not available for MB89F202) C N-ch • At an output pull-up resister (P-ch) of approximately 50 kΩ/5.0 V (not available for MB89F202) • N-ch open-drain reset output • Hysteresis input Reset P-ch • • • • P-ch CMOS output CMOS input Hysteresis input (Resource input) Pull-up resistor optional D N-ch Input enable Input enable Port input Resource input (Continued) 8 MB89202 Series (Continued) Type Circuit • • • • P-ch Remarks CMOS output CMOS input Pull-up resistor optional P70-P72 are large-current drive type P-ch E N-ch Input enable Port input P-ch Open-drain control F Input enable N-ch Analog input Port input A/D enable • • • • • CMOS output CMOS input Analog input N-ch open-drain output available P40-P43 are large-current drive type P-ch • • • • P-ch CMOS output CMOS input Hysteresis input (Resource input) Analog input G N-ch Input enable Input enable Analog input A/D enable Port input Resource input • CMOS input H Input enable Port input 9 MB89202 Series ■ HANDLING DEVICES • Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “■ ELECTRICAL CHARACTERISTICS” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. • Treatment of Unused Input Pins Leaving unused input terminals open may lead to permanent damage due to malfunction and latchup; pull up or pull down the terminals through the resistors of 2 kΩ or more. Make the unused I/O terminal in a state of output and leave it open or if it is in an input state, handle it with the same procedure as the input terminals. • Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. • Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 Hz to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. • Precautions when Using an External Clock When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode. • About the Wild Register Function No wild register can be debugged on the MB89V201. For the operation check, test the MB89F202 installed on a target system. • Program Execution in RAM When the MB89V201 is used, no program can be executed in RAM. • Note to Noise in the External Reset Pin (RST) If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST). • External pullup for the External Reset Pin (RST) of MB89F202 Internal pullup control for RST pin is not available for MB89F202. To ensure proper external reset control in MB89F202, an external pullup (recommend 100 kΩ) for RST pin must be required. (Continued) 10 MB89202 Series (Continued) • Notes on selecting mask option Please select “With reset output” by the mask option when power-on reset is generated at the power supply ON, and the device is used without inputting external reset. 11 MB89202 Series ■ PROGRAMMING AND ERASE FLASH MEMORY ON THE MB89F202 1. Flash Memory The flash memory is located between C000H and FFFFH in the CPU memory map and incorporates a flash memory interface circuit that allows read access and program access from the CPU to be performed in the same way as mask ROM. Programming and erasing flash memory is also performed via the flash memory interface circuit by executing instructions in the CPU. This enables the flash memory to be updated in place under the control of the CPU, providing an efficient method of updating program and data. 2. Flash Memory Features • • • • • • 16 K byte × 8-bit configuration Automatic programming algorithm (Embedded Algorithm*) Data polling and toggle bit for detection of program/erase completion Detection of program/erase completion via CPU interrupt Compatible with JEDEC-standard commands No. of program / erase cycles : Minimum 10,000 * : Embedded Algorithm is a trademark of Advanced Micro Devices. 3. Procedure for Programming and Erasing Flash Memory Programming and reading flash memory cannot be performed at the same time. Accordingly, to program or erase flash memory, the program must first be copied from flash memory to RAM so that programming can be performed without program access from flash memory. 4. Flash Memory Control Status Register (FMCS) bit 7 Address 0079H INTE R/W RDYINT bit 6 bit 5 WE R/W bit 4 RDY R bit 3 bit 2 bit 1 bit 0 Initial value 000X----B R/W 5. Memory Space The memory space for the CPU access and for the flash programmer access is listed below. Memory size 16 K bytes • Parallel programmer Part number MB89F202P-SH MB89F202PFV Package DIP-32P-M06 FPT-34P-M03 Adapter Part number TEF200-89F202-PSH TEF200-89F202-PFV Programmer Part number * AF9708, AF9709/B, AF9723 + AF9834 CPU address FFFFH to C000H Programmer address FFFFH to C000H 6. Flash Programmer Adapter and Recommended Flash Programmers * : For the programmer and the version of the programmer,contact the Flash Support Group, Inc. Inquiry : Flash Support Group, Inc. : FAX : 81-(53)-428-8377 : E-mail : support@j-fsg.co.jp • Serial programmer (PC programmer) Part number MB89F202P-SH MB89F202PFV Inquiries : Adapter Package DIP-32P-M06 FPT-34P-M03 Adapter Part number ROM3-DIP32PM06-8L ROM3-FPT34PM03-8L : Sunhayato Corp. : FAX : 81-(3)-3971-0535 E-mail : adapter@sunhayato.co.jp PC programmer software : FUJITSU LIMITED 12 MB89202 Series 7. Flash Content Protection Flash content can be read using parallel / serial programmer if the flash content protection mechanism is not activated. One predefined area of the flash (FFFCH) is assigned to be used for preventing the read access of flash content. If the protection code "01H" is written in this address (FFFCH), the flash content cannot be read by any parallel/ serial programmer. Note : The program written into the flash cannot be verified once the flash protection code is written ("01H" in FFFCH). It is advised to write the flash protection code at last. ■ PROGRAMMING TO THE EPROM WITH EVALUATION PRODUCT DEVICE 1. EPROM for Use MBM27C256A (DIP-28) 2. Memory Space. Normal operating mode Address 0000H I/O 0080H RAM 512 bytes 0280H Not available Corresponding adresses on the ROM programmer Address 8000H 0000H PROM 32 Kbytes EPROM 32 Kbytes FFFFH 7FFFH 3. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0000H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer. 13 MB89202 Series ■ BLOCK DIAGRAM X0 X1 Main clock oscillator Time-base timer Clock controller CMOS I/O port Port 5 Port 6 RST 2 P60 ,P61 P70* to P72* Reset circuit 8-bit PWM P50 / PWM CMOS I/O port UART prescaler Port 7 3 CMOS I/O port UART Serial function switching Internal bus CMOS I/O port P04 / INT24 to P07 / INT27 4 Port 0 8 External interrupt2 (wake-up) P30 / UCK / SCK P31 / UO / SO P32 / UI / SI 8-bit serial I/O P00 / INT20 / AN4 4 to P03 / INT23 / AN7 4 4 Port 3 10-bit A/D Converter 8/16-bit capture timer/ counter P33 / EC P34 / TO / INT10 P40 / AN0* 4 to P43 / AN3* Port 4 CMOS I/O port (N-ch OD) Exernal interrupt 1 3 2 P35 / INT11, P36 / INT12 512 bytes RAM 12-bit PPG F2MC - 8 L CPU Other pins VCC, VSS, C Buzzer output 16 Kbytes ROM P37 / BZ / PPG Wild register CMOS I/O port * : Large-current drive type 14 MB89202 Series ■ CPU CORE 1. Memory Space The microcontrollers of the MB89202 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89202 series is structured as illustrated below. • Memory Space MB89202 0000H I/O 0080H RAM 512 Bytes 0100H 0100H 0080H RAM 512 Bytes 0100H 0000H I/O 0080H RAM 512 Bytes MB89F202 0000H I/O MB89V201 Register Register 0200H 0280H 0200H 0280H 0200H 0280H Not available Not available 8000H C000H ROM 16 KBytes FFFFH FFFFH C000H FLASH 16 KBytes FFFFH External EPROM 32 KBytes Register Not available 15 MB89202 Series 2. Registers The MB89202 series has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided : Program counter (PC) : Accumulator (A) : A 16-bit register for indicating instruction storage positions A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX) : Extra pointer (EP) : Stack pointer (SP) : Program status (PS) : A 16-bit register for index modification A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area A 16-bit register for storing a register pointer, a condition code Initial value : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer CCR PS 16 bits PC A T IX EP SP RP FFFDH Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, 0 = 11 The other bit values are undefined. : Program status The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR) . (See the diagram below.) • Structure of the Program Status Register RP bit15 bit14 bit13 bit12 bit11 bit10 bit9 R3 R2 R1 R0 − − PS R4 H-flag I-flag IL1,0 N-flag Z-flag bit8 − bit7 H bit6 I bit5 IL1 CCR bit4 IL0 bit3 N bit2 Z bit1 V bit0 C CCR initial value X011XXXXB × : Undefined V-flag C-flag 16 MB89202 Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. • Rule for Conversion of Actual Addresses of the General-purpose Register Area RP "0" Generated addresses "0" "0" "0" "0" "0" "0" A9 "1" A8 R4 A7 R3 A6 R2 A5 R1 A4 R0 A3 Lower OP codes b2 A2 b1 A1 b0 A0 A15 A14 A13 A12 A11 A10 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag : I-flag : IL1, 0 : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. This flag is for decimal adjustment instructions. Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when the flag is cleared to “0”. Cleared to “0” at the reset. Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL0 0 1 0 1 Interrupt level 1 2 3 Low = no interrupt High-low High IL1 0 0 1 1 N-flag : Z-flag : V-flag : C-flag : Set to “1” if the MSB becomes to “1” as the result of an arithmetic operation. Cleared to “0” when the bit is cleared to “0”. Set to “1” when an arithmetic operation results in 0. Cleared to “0” otherwise. Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0” if the overflow does not occur. Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to “0” otherwise. Set to the shift-out value in the case of a shift instruction. 17 MB89202 Series The following general-purpose registers are provided : General-purpose registers : An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 16 banks can be used on the MB89202 series. The bank currently in use is indicated by the register bank pointer (RP) . • Register Bank Configuration This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 16 banks Memory area 18 MB89202 Series ■ I/O MAP Address 0000H 0001H 0002H to 00006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 0024H CNTR COMR EIC1 PWM control register PWM compare register External interrupt 1 Control register 1 PDR3 DDR3 RSFR PDR4 DDR4 OUT4 PDR5 DDR5 RCR21 RCR22 RCR23 RCR24 BZCR TCCR TCR1 TCR0 TDR1 TDR0 TCPH TCPL TCR2 Port 3 data register Port 3 data direction register Reset flag register Port 4 data register Port 4 data direction register Port 4 output format register Port 5 data register Port 5 data direction register 12-bit PPG control register 1 12-bit PPG control register 2 12-bit PPG control register 3 12-bit PPG control register 4 Buzzer register Capture control register Timer 1 control register Timer 0 control register Timer 1 data register Timer 0 data register Capture data register H Capture data register L Timer output control register Reserved R/W W R/W 0 - 0000 0 0 X X XXXX X X 000000 0 0 (Continued) SYCC STBC WDTC TBTC Register name PDR0 DDR0 Register description Port 0 data register Port 0 data direction register Reserved System clock control register Standby control register Watchdog timer control register Time-base timer control register Reserved R/W W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W X X XXXX X X 000000 0 0 XXXX- - - - - - - XXXX - - - - 0000 - - - - 0000 -------X -------0 000000 0 0 - - 0000 0 0 0 - 0000 0 0 - - 0000 0 0 - - ---000 000000 0 0 000- 0000 000000 0 0 X X XXXX X X X X XXXX X X X X XXXX X X X X XXXX X X ------00 R/W R/W R/W R/W 1 - - MM 1 0 0 00010- - 0 - - - XXXX 00---000 Read/write R/W W Initial value X X XXXX X X 000000 0 0 19 MB89202 Series Address 0025H 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH to 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH to 003FH 0040H 0041H 0042H 0043H 0044H 0045H 0046H 0047H 0048H to 005FH Register name EIC2 Register description External interrupt 1 Control register 2 Reserved Read/write R/W Initial value - - - - 0000 SMC SRC SSD SIDR SODR UPC ADC1 ADC2 ADDH ADDL ADEN EIE2 EIF2 SMR SDR SSEL WRARH0 WRARL0 WRDR0 WRARH1 WRARL1 WRDR1 WREN WROR Serial mode control register Serial rate control register Serial status and data register Serial input data register Serial output data register Clock division selection register Reserved A/D converter control register 1 A/D converter control register 2 A/D converter data register H A/D converter data register L A/D enable register Reserved External interrupt 2 control register1 External interrupt 2 control register2 Reserved Serial mode register Serial data register Serial function switching register Reserved Upper-address setting register Lower-address setting register Data setting register 0 Upper-address setting register Lower-address setting register Data setting register 1 Address comparison EN register Wild-register data test register Reserved R/W R/W R/W R W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00000- 0 0 - - 0110 0 0 00100- 1X X X XXXX X X X X XXXX X X - - - - 0010 - 00000 0 0 - 00000 0 1 - - - - - - XX X X XXXX X X 000000 0 0 000000 0 0 -------0 000000 0 0 X X XXXX X X -------0 X X XXXX X X X X XXXX X X X X XXXX X X X X XXXX X X X X XXXX X X X X XXXX X X X X XXXX 0 0 ------00 (Continued) 20 MB89202 Series (Continued) Address 0060H 0061H 0062H 0063H 0064H 0065H 0066H to 006FH 0070H 0071H 0072H 0073H to 0078H 0079H 007AH 007BH 007CH 007DH 007EH 007FH ILR1 ILR2 ILR3 ILR4 ITR FMCS PUL0 PUL3 PUL5 Register name PDR6 DDR6 PUL6 PDR7 DDR7 PUL7 Register description Port 6 data register Port 6 data direction register* Port 6 pull-up setting register Port 7 data register Port 7 data direction register Port 7 pull-up setting register Reserved Port-0 pull-up setting register Port-3 pull-up setting register Port-5 pull-up setting register Reserved Flash memory control status register Reserved Interrupt level setting register1 Interrupt level setting register2 Interrupt level setting register3 Interrupt level setting register4 Interrupt test register Read/write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W W W Not available Initial value - - - - - - XX ------00 ------00 - - - - - XXX - - ---000 - - ---000 000000 0 0 000000 0 0 -------0 0 0 0 X- - - 111111 1 1 111111 1 1 111111 1 1 111111 1 1 ------00 - : Unused, X : Undefined, M : Set using the mask option * : No used in MB89F202 Note : Do not use prohibited areas. 21 MB89202 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage* Input voltage* Output voltage* “L” level maximum output current Symbol VCC VI VO IOL Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 ⎯ ⎯ Max VSS + 6.0 VCC + 0.3 VCC + 6.0 15 Unit V V V mA Average value (operating current × operating rate) Pins excluding P40 to P43, P70 to P72 Average value (operating current × operating rate) Pins P40 to P43, P70 to P72 Pins excluding P60, P61 Average value (operating current × operating rate) Remarks IOLAV1 “L” level average output current IOLAV2 “L” level total maximum output current “H” level maximum output current “H” level average output current “H” level total maximum output current Power consumption Operating temperature Storage temperature * : This parameter is based on VSS = 0.0 V. ΣIOL IOH IOHAV ΣIOH Pd Ta Tstg 4 mA ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ −40 −55 12 100 −10 −4 −50 200 +85 +150 mA mA mA mA mA mW °C °C WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 22 MB89202 Series 2. Recommended Operating Conditions (Vss = 0.0V) Parameter Symbol Value Min 2.2 Power supply voltage VCC 3.5 2.7 1.5 VIH “H” level input voltage VIHS VIL “L” level input voltage VILS Open-drain output pin application voltage Operating temperature VD VSS − 0.3 VSS − 0.3 −40 0.2 VCC VCC + 0.3 +85 V V °C 0.8 VCC VSS − 0.3 VCC + 0.3 0.3 VCC V V 0.7 VCC Max 5.5 5.5 5.5 5.5 VCC + 0.3 Unit V V V V V MB89202 MB89F202 MB89V201 Retains the RAM state in stop mode P00 to P07, P31, P37, P40 to P43, P50, P60, P61, P70 to P72 RST, EC, INT20 to INT27, UCK/SCK, INT10 to INT12, P30, P32 to P36, UI/SI P00 to P07, P31, P37, P40 to P43, P50, P60, P61, P70 to P72 RST, EC, INT20 to INT27, UCK/SCK, INT10 to INT12, P30, P32 to P36, UI/SI P40 to P43, RST Room temperature is recommended for programming the flash memory on MB89F202 Remarks Ta 23 MB89202 Series Operating Assurance for MB89202 and MB89V201 6 5.5 5 Operating voltage (V) 4.5 4 3.5 3 2.7 2.2 2 : Area is assured only for the MB89202 Operation assurance range Analog accuracy assurance range 1 0 1 2 3 4 5 6 7 8 Operating Frequency (MHz) 9 10 11 12.5 Operating Assurance for MB89F202 6 5.5 5 Operating voltage (V) 4.5 4 3.5 3 Operation assurance range Analog accuracy assurance range 2 1 0 1 2 3 4 5 6 7 8 Operating Frequency (MHz) 9 10 11 12.5 WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 24 MB89202 Series 3. DC Characteristics (VCC = 5.0 V ± 10%, VSS = 0.0 V, FCH = 12.5 MHz (External clock) , Ta = −40 °C to +85 °C) Parameter Symbol Pin name P00 to P07, P31, P37, P40 to P43, P50, P60, P61, P70 to P72 P30, P32 to P36, RST UCK/SCK, UI/SI, EC, INT20 to INT27, INT10 to INT12 P00 to P07, P31, P37, P40 to P43, P50, P60, P61, P70 to P72 P30, P32 to P36, RST, UCK/SCK, UI/SI, EC, INT20 to INT27, INT10 to INT12 Condition Value Min Typ ⎯ Max VCC + 0.3 Unit Remarks VIH “H” level input voltage VIHS ⎯ 0.7 VCC V ⎯ 0.8 VCC ⎯ VCC + 0.3 V VIL “L” level input voltage VILS ⎯ VSS − 0.3 ⎯ 0.3 VCC V ⎯ VSS − 0.3 ⎯ 0.2 VCC V Open-drain output pin application voltage “H” level output voltage “L” level output voltage VD P40 to P43, RST ⎯ VSS − 0.3 ⎯ VCC + 0.3 V VOH P00 to P07, P30 to P37, P40 to P43, P50, IOH = −4.0 mA P70 to P72 P00 to P07, P30 to P37, IOL = 4.0 mA P50, RST P40 to P43, P70 to P72 IOL = 12.0 mA P00 to P07, P30 to P37, P40 to P43, P50 , 0.45 V < VI < VCC P60, P61, RST, P70 to P72 P00 to P07, P30 to P37, P50, RST, P70 to P72 P00 to P07, P30 to P37, P50, P70 to P72 4.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.4 0.4 ±5 V VOL1 VOL2 V V Without µA pull-up resistor MB89202 Input leakage current ILI Pull-up resistance RPULL VI = 0.0 V 25 50 100 kΩ MB89F202 (Continued) 25 MB89202 Series (Continued) Parameter Symbol Pin name Normal operation mode (External clock, highest gear speed) VCC Sleep mode (External clock, highest gear speed) Stop mode Ta = +25 °C (External clock) Other than C, VCC, VSS Condition When A/D converter stops When A/D converter starts When A/D converter stops When A/D converter stops ⎯ Value Min ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Typ Max 12 9 15 12 6 5 1 10 ⎯ Unit Remarks 8 6 10 8 4 3 ⎯ ⎯ 10 mA MB89202 mA MB89F202 mA MB89202 mA MB89F202 mA MB89202 mA MB89F202 µA MB89202 µA MB89F202 pF ICC Power supply current ICCS ICCH Input capacitance CIN 26 MB89202 Series 4. AC Characteristics (1) Reset Timing (VSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter RST “L” pulse width Internal reset pulse extension * : tHCYL 1 oscillating clock cycle time Symbol tZLZH tirst Condition ⎯ ⎯ Value Min 45 48 tHCYL* Max ⎯ ⎯ Unit ns ns Remarks tZLZH 0.8 VCC 0.2 VCC RST 0.2 VCC Internal reset signal tirst Notes: • When the power-on reset option is not on, leave the external reset on until oscillation becomes stable. • If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST). (2) Power-on Reset (VSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Power supply rising time Power supply cut-off time Symbol tR tOFF Condition ⎯ Value Min ⎯ 1 Max 50 ⎯ Unit ms ms Due to repeated operations Remarks tR 3.5 V tOFF VCC 0.2 V 0.2 V 0.2 V Note : The supply voltage must be set to the minimum value required for operation within the prescribed default oscillation settling time. 27 MB89202 Series (3) Clock Timing (VSS = 0.0 V, Ta = –40°C to +85°C) Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time Symbol FCH tXCYL tWH tWL tCR tCF ⎯ Condition Value Min 1 80 20 ⎯ Max 12.5 1000 ⎯ 10 Unit MHz ns ns ns Remarks • X0 and X1 Timing and Conditions tXCYL tWH tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC tWL X0 • Main Clock Conditions When a crystal or ceramic resonator is used When an exernal clock is used X0 X1 X0 X1 open (4) Instruction Cycle Parameter Instruction cycle (minimum execution time) Symbol tINST Value (typical) 4/FCH, 8/FCH, 16/FCH, 64/FCH Unit µs Remarks tINST = 0.32 µs when operating at FCH = 12.5 MHz (4/FCH) 28 MB89202 Series (5) Peripheral Input Timing (VCC = 5.0 V ± 10%, VSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Peripheral input “H” pulse width Peripheral input “L” pulse width Symbol tILIH tIHIL Pin name INT10 to INT12, INT20 to INT27, EC Value Min 2 tINST* 2 tINST* Max ⎯ ⎯ Unit µs µs Remarks * : For information on tINST see “ (4) Instruction Cycle”. tILIH tIHIL INT10 to INT12, INT20 to INT27, EC 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC (VCC = 5.0 V ± 10%, VSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Peripheral input “H” noise limit Symbol tIHNC Pin name P00 to P07, P30 to P37, P40 to P43, P50,P60,P61, P70 to P72, RST, EC, INT20 to INT27, INT10 to INT12 Value Min ⎯ Typ 45 Max ⎯ Unit ns Remarks Peripheral input “L” noise limit tILNC ⎯ 45 ⎯ ns P00 to P07, P30 to P37, P40 to P43, P50, P60, P61, P70 to P72, RST, EC, INT20 to INT27, INT10 to INT12 tIHNC tILNC 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 29 MB89202 Series (6) UART, Serial I/O Timing (VCC = 5.0 V ± 10%, VSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Serial clock cycle time UCK/SCK ↓ → SO time Valid SI → UCK/SCK↑ UCK/SCK ↑ → Valid SI hold time Serial clock “H” pulse width Serial clock “L” pulse width UCK/SCK ↓ → SO time Valid SI → UCK/SCK UCK/SCK ↑ → Valid SI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name UCK/SCK UCK/SCK, SO Internal shift UCK/SCK, SI clock mode UCK/SCK, SI UCK/SCK UCK/SCK UCK/SCK, SO UCK/SCK, SI UCK/SCK, SI External shift clock mode Condition Value Min 2 tINST* −200 1/2 tINST* 1/2 tINST* tINST* tINST* 0 1/2 tINST* 1/2 tINST* Max ⎯ 200 ⎯ ⎯ ⎯ ⎯ 200 ⎯ ⎯ Unit Remarks µs ns µs µs µs µs ns µs µs * : For information on tinst, see “ (4) Instruction Cycle”. • Internal Shift Clock Mode tSCYC 2.4 V UCK/SCK 0.8 V tSLOV 0.8 V SO 2.4 V 0.8 V tIVSH tSHIX SI 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External Shift Clock Mode tSLSH tSHSL 0.8 VCC 0.8 VCC UCK/SCK 0.2 VCC 0.2 VCC tSLOV SO 2.4 V 0.8 V tIVSH tSHIX SI 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 30 MB89202 Series 5. A/D Converter (1) A/D Converter Electrical Characteristics (VSS = 0.0 V, Ta = −40 °C to +85 °C) Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage A/D mode conversion time Analog port input current Analog input voltage range Power supply voltage for A/D accuracy assurance VOT VFST ⎯ IAIN ⎯ VCC ⎯ Symbol Value Min ⎯ −5.0 −3.0 −2.5 VSS − 3.5 LSB VCC − 6.5 LSB ⎯ ⎯ 0 4.5 Typ ⎯ ⎯ ⎯ ⎯ VSS + 0.5 LSB VCC − 1.5 LSB ⎯ ⎯ ⎯ ⎯ Max 10 +5.0 +3.0 +2.5 VSS + 4.5 LSB VCC + 2.0 LSB 38 tINST* 10 VCC 5.5 Unit bit LSB LSB LSB V V µs µA V V Remarks * : For information on tinst, see “ (4) Instruction Cycle” in “4. AC Characteristics.” 31 MB89202 Series (2) A/D Converter Glossary • Resolution Analog changes that are identifiable with the A/D converter When the number of bits is 10, analog voltage can be divided into 210 = 1024. • Linearity error (unit : LSB) The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics • Differential linearity error (unit : LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value • Total error (unit : LSB) The difference between theoretical and actual conversion values Theoretical I/O characteristics 3FFH 3FEH 3FDH 1.5 LSB VFST 3FFH 3FEH 3FDH Actual conversion value {1 LSB × N + 0.5 LSB} Total error Digital output 004H 003H 002H 001H 0.5 LSB AVSS VCC VOT 1 LSB Digital output 004H 003H 002H 001H AVSS VNT Actual conversion value Theoretical value VCC Analog input Analog input 1 LSB = VFST − VOT 1022 (V) Total error of digital output N = VNT − {1 LSB × N + 0.5 LSB} 1 LSB Zero transition error 004H Actual conversion value 003H 3FFH Full-scale transition error Theoretical value Actual conversion value Digital output Digital output 3FEH VFST (Measured value) Actual conversion value 002H Theoretical conversion value 001H VOT (Measured value) AVSS Actual conversion value 3FDH 3FCH VCC Analog input Analog input (Continued) 32 MB89202 Series (Continued) Linearity error 3FFH 3FEH Actual conversion value {1 LSB × N + VOT} VFST (Measured value) N+1 Actual conversion value Differential linearity error Theoretical conversion value Digital output Digital output 3FDH V (N + 1) T N VNT 004H 003H 002H 001H AVSS Actual conversion value Theoretical conversion value VOT (Measured value) VCC N−1 VNT Actual conversion value N−2 AVSS VCC Analog input Analog input Linearity error of digital output N = VNT − {1 LSB × N + VOT} 1 LSB V (N + 1) T − VNT −1 1 LSB Differential linearity error of digital output N = 33 MB89202 Series (3) Notes on Using A/D Converter • About the external impedance of analog input and its sampling time • A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. • Analog input circuit model R Analog input ↑ During sampling : ON Comparator C R 2.2 kΩ (Max) 2.0 kΩ (Max) C 45 pF (Max) 16 pF (Max) Note : The values are reference values. MB89202 MB89F202 • To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. • The relationship between the external impedance and minimum sampling time [External impedance = 0 kΩ to 100 kΩ] 100 [External impedance = 0 kΩ to 20 kΩ] 20 18 MB89F202 MB89202 External impedance (kΩ) MB89F202 MB89202 External impedance (kΩ) 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 Minimum sampling time (µs) Minimum sampling time (µs) • If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. • About errors As |VCC − AVSS| becomes smaller, values of relative errors grow larger. 34 MB89202 Series 6. MB89F202 Flash Memory Program / Erase Characteristics Value Min ⎯ ⎯ 10,000 Typ 0.5*1 32 ⎯ Max 7.5*2 3600 ⎯ Parameter Chip erase time (16 KB) Byte programming time Program / Erase cycle Unit s µs cycle Remarks Excludes programming prior to erasure Excludes system-level overhead *1: Ta = + 25 °C, Vcc = 3.0 V, 10,000 cycles *2: Ta = + 85 °C, Vcc = 2.7 V, 10,000 cycles 35 MB89202 Series ■ EXAMPLE CHARACTERISTICS 1. Power supply current • MB89202/F202 : 4 MHz (when external clock are used) MB89202 Normal operation mode (ICC1 − VCC, ICC2 − VCC) 4.0 (FCH = 4 MHz, Ta = +25 ˚C) MB89F202 Normal operation mode (ICC1 − VCC, ICC2 − VCC) 3.0 (FCH = 4 MHz, Ta = +25 ˚C) 3.0 ICC1 (gear : 4 divide) 2.0 ICC (mA) ICC (mA) ICC1 (gear : 4 divide) 2.0 1.0 1.0 ICC2 (gear : 64 divide) ICC2 (gear : 64 divide) 0.0 1 2 3 4 VCC (V) 0.0 5 6 7 1 2 3 4 VCC (V) 5 6 7 MB89202 Sleep mode (ICCs1 − VCC, ICCs2 − VCC) (FCH = 4 MHz, Ta = +25 ˚C) MB89F202 Sleep mode (ICCs1 − VCC, ICCs2 − VCC) (FCH = 4 MHz, Ta = +25 ˚C) 1.5 1.5 1.0 1.0 ICCS (mA) ICCS1 (gear : 4 divide) 0.5 ICCS (mA) ICCS1 (gear : 4 divide) 0.5 ICCS2 (gear : 64 divide) 0.0 1 2 3 4 5 6 7 ICCS2 (gear : 64 divide) 0.0 VCC (V) 1 2 3 4 5 VCC (V) 6 7 36 MB89202 Series • MB89202/F202 : 8 MHz ( when external clock are used) MB89202 Normal operation mode (ICC1 − VCC, ICC2 − VCC) 8.0 (FCH = 8 MHz, Ta = +25 ˚C) MB89F202 Normal operation mode (ICC1 − VCC, ICC2 − VCC) 5.0 (FCH = 8 MHz, Ta = +25 ˚C) 4.0 6.0 ICC1 (gear : 4 divide) ICC (mA) 4.0 ICC (mA) 3.0 ICC1 (gear : 4 divide) 2.0 ICC2 (gear : 64 divide) 2.0 ICC2 (gear : 64 divide) 1.0 0.0 1 2 3 4 VCC (V) 0.0 5 6 7 1 2 3 4 VCC (V) 5 6 7 MB89202 Sleep mode (ICCs1 − VCC, ICCs2 − VCC) (FCH = 8 MHz, Ta = +25 ˚C) MB89F202 Sleep mode (ICCs1 − VCC, ICCs2 − VCC) (FCH = 8 MHz, Ta = +25 ˚C) 2.5 2.0 2.0 ICCS1 (gear : 4 divide) ICCS (mA) ICCS (mA) 1.5 1.5 ICCS1 (gear : 4 divide) 1.0 1.0 0.5 0.5 ICCS2 (gear : 64 divide) 0.0 1 2 3 4 5 6 7 ICCS2 (gear : 64 divide) 0.0 1 2 3 VCC (V) 4 5 VCC (V) 6 7 37 MB89202 Series • MB89202/F202 : 12.5 MHz (when external clock is used) MB89202 Normal operation mode (ICC1 − VCC, ICC2 − VCC) 10.0 9.0 8.0 7.0 ICC (mA) ICC (mA) ICC1 (gear : 4 divide) (FCH = 12.5 MHz, Ta = +25 ˚C) MB89F202 Normal operation mode (ICC1 − VCC, ICC2 − VCC) 5.0 (FCH = 12.5 MHz, Ta = +25 ˚C) 4.0 ICC1 (gear : 4 divide) 6.0 5.0 4.0 3.0 2.0 1.0 0.0 1 3.0 2.0 1.0 ICC2 (gear : 64 divide) ICC2 (gear : 64 divide) 0.0 7 2 3 VCC (V) 4 5 6 1 2 3 VCC (V) 4 5 6 7 MB89202 Sleep mode (ICCs1 − VCC, ICCs2 − VCC) (FCH = 12.5 MHz, Ta = +25 ˚C) MB89F202 Sleep mode (ICCs1 − VCC, ICCs2 − VCC) (FCH = 12.5 MHz, Ta = +25 ˚C) 3.0 2.0 2.5 ICCS1 (gear : 4 divide) 1.5 2.0 ICCs (mA) ICCs (mA) ICCS1 (gear : 4 divide) 1.5 1.0 1.0 0.5 0.5 ICCS2 (gear : 64 divide) ICCS2 (gear : 64 divide) 0.0 1 2 3 4 5 6 7 0.0 1 2 3 VCC (V) 4 5 VCC (V) 6 7 38 MB89202 Series • MB89202/F202 : 12.5 MHz (when external clock is used) MB89202 Stop mode (ICCH − Ta) (FCH = 12.5 MHz, VCC = 5.5 V) 4.0 MB89F202 Stop mode (ICCH − Ta) (FCH = 12.5 MHz, VCC = 5.5 V) 4.0 3.5 3.5 3.0 3.0 2.5 ICCH (µA) ICCH (µA) 2.5 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0.5 0.0 -40 -15 10 35 60 85 0.0 -40 -15 10 35 60 85 Ta ( °C) Ta ( °C) 39 MB89202 Series 2. “L” level output voltage MB89202 VOL vs. IOL1 0.6 VCC = 2.0 V 0.6 MB89202 VOL vs. IOL2 VCC = 2.0 V 0.5 VCC = 2.5 V 0.4 VOL (V) VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VCC = 6.0 V VOL (V) 0.5 VCC = 2.5 V 0.4 VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VCC = 6.0 V 0.3 0.3 0.2 0.2 0.1 0.1 0.0 1 2 3 4 IOL1 (mA) 5 6 0.0 4 6 8 10 12 14 16 IOL2 (mA) 3. “H” level output voltage MB89202 (VCC − VOH) vs. IOH 0.8 0.7 VCC = 2.5 V 0.6 0.5 0.4 0.3 0.2 0.1 0.0 −1 VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VCC = 6.0 V VCC = 2.0 V VCC − VOH (V) −2 −3 −4 −5 −6 IOH (mA) 40 MB89202 Series ■ MASK OPTIONS Part number No. Specifying procedure Selection of initial value of main clock oscillation settling time* (with FCH = 12.5 MHz) 01 : 214/FCH (Approx.1.31 ms) 10 : 217/FCH (Approx.10.5 ms) 11 : 218/FCH (Approx.21.0 ms) Reset pin output With reset output Without reset output Power on reset selection With power on reset Without power on reset MB89202 Specify when ordering masking MB89F202 MB89V201 Specify by part number 1 Selectable Fixed to 218/FCH Fixed to 218/FCH 2 Selectable With reset output With reset output 3 Selectable With power on reset With power on reset FCH : Main clock oscillation frequency * : Initial value to which the oscillation settling time bit (SYCC : WT1, WT0) in the system clock control register is set Note • Notes on selecting mask option Please select “With reset output” by the mask option when power-on reset is generated at the power supply ON, and the device is used without inputting external reset. ■ ORDERING INFORMATION Part number MB89202P-SH MB89F202P-SH MB89202PFV MB89F202PFV MB89V201PFV Package 32-pin plastic SH-DIP (DIP-32P-M06) 34-pin plastic SSOP (FPT-34P-M03) 64-pin plastic LQFP (FPT-64P-M03) Remarks 41 MB89202 Series ■ PACKAGE DIMENSIONS 32-pin plastic SH-DIP (DIP-32P-M06) +0.20 +.008 –.012 Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. *28.00 –0.30 1.102 INDEX *8.89±0.25 (.350±.010) 1.02 .040 –.008 4.70 –0.20 +0.70 +.028 +0.30 –0.20 +.012 .185 –.008 0.51(.020) MIN. 3.30 .130 +0.20 –0.30 +.008 –.012 0.27 –0.07 1.27(.050) MAX. 1.778(.070) 0.48 .019 +0.08 –0.12 +.003 –.005 +0.03 +.001 .011 –.003 0.25(.010) M 10.16(.400) 0~15˚ C 2003 FUJITSU LIMITED D32018S-c-1-1 Dimensions in mm (inches). Note: The values in parentheses are reference values (Continued) 42 MB89202 Series (Continued) 34-pin plastic SSOP (FPT-34P-M03) Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max). Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. 0.17±0.03 (.007±.001) *1 11.00±0.10(.433±.004) 34 18 *2 6.10±0.10 INDEX (.240±.004) 8.10±0.20 (.319±.008) Details of "A" part 1.25 –0.10 .049 –.004 +0.20 +.008 (Mounting height) 0.25(.010) 0~8˚ +0.08 –0.07 +.003 –.003 1 17 0.65(.0265) "A" 0.10(.004) M 0.24 .009 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) (Stand off) 0.10(.004) C 2003 FUJITSU LIMITED F34003S-c-2-3 Dimensions in mm (inches). Note: The values in parentheses are reference values 43 MB89202 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0503 © 2005 FUJITSU LIMITED Printed in Japan