FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12560-1E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89490 Series
MB89498/F499/PV490
s DESCRIPTION
The MB89490 series has been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit single-chip microcontrollers. In addition to a compact instruction set, the general-purpose, single-chip microcontroller contains a variety of peripheral functions such as 21-bit timebase timer, watch prescaler, PWM timer, 8/16-bit timer/counter, remote receiver circuit, LCD controller/driver, external interrupt 0 (edge) , external interrupt 1 (level) , 10-bit A/D converter, UART/SIO, SIO, I2C and watchdog timer reset. The MB89490 series is designed suitable for compact disc/radio receiver controller as well as in a wide range of applications for consumer product. * : “F2MC”, an abbreviation for FUJITSU Flexible Microcontroller, is a registered trademark of FUJITSU Ltd.
s FEATURES
• Package QFP, LQFP package for MB89F499, MB89498 MQFP package for MB89PV490
(Continued)
s PACKAGES
100-pin Plastic QFP 100-pin Plastic LQFP 100-pin Ceramic MQFP
(FTP-100P-M06)
(FTP-100P-M05)
(MQP-100C-P01)
MB89490 Series
(Continued) • High speed operating capability at low voltage • Minimum execution time : 0.32 µs/12.5 MHz • F2MC-8L family CPU core
Multiplication and division instructions 16-bit arithmetic operations Branch instructions by test bit Bit manipulation instructions, etc.
Instruction set optimized for controllers
• PLL circuit for sub-clock • Embedded for PLL clock multiplication circuit for sub-clock • Operating clock (PLL for sub-clock) can be selected from no multiplication or 4 times of the sub-clock oscillation frequency. • 6 timers PWM timer × 2 8/16-bit timer/counter × 2 21-bit timebase timer Watch prescaler • External interrupt Edge detection (selectable edge) : 8 channels Low level interrupt (wake-up function) : 8 channels • 10-bit A/D converter (8 channels) 10-bit successive approximation type • UART/SIO Synchronous/asynchronous data transfer capability • SIO Switching of synchronous data transfer capability • LCD controller/driver Max 32 segments output × 4 commons • I2C interface circuit • Remote receiver circuit • Low-power consumption mode Stop mode (oscillation stops so as to minimize the current consumption.) Sleep mode (CPU stops so as to reduce the current consumption to approx. 1/3 of normal.) Watch mode (operation except the watch prescaler stops so as to reduce the power comsumption to an extremely low level.) Sub-clock mode • Watchdog timer reset • I/O ports : Max 66 channels
2
MB89490 Series
s PRODUCT LINEUP
Part number Parameter Classification MB89498 Mass production products (mask ROM product) 48 K × 8-bit (internal ROM) 2 K × 8-bit Number of instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time Minimum interrupt processing time General-purpose I/O ports (CMOS) Input ports (CMOS) N-channel open drain I/O ports Total MB89F499 MB89PV490 Piggy-back (For evaluation or development) 60 K × 8-bit (external ROM) *1 2 K × 8-bit
FLASH 60 K × 8-bit (internal FLASH) 2 K × 8-bit : 136 : 8-bit : 1 to 3 bytes : 1-bit, 8-bit, 16-bit : 0.32 µs/12.5 MHz : 2.88 µs/12.5 MHz : 56 pins : 2 pins : 8 pins : 66 pins
ROM size RAM size
CPU functions
Ports
21-bit timebase timer Watchdog timer PWM timer 0, 1
Interrupt generation cycle (0.66 ms, 2.6 ms, 21.0 ms, 335.5 ms) at 12.5 MHz Reset generation cycle (167.8 ms to 335.5 ms) at 12.5 MHz 8-bit reload timer operation (supports square wave output and operating clock period : 1 tinst, 8 tinst, 16 tinst, 64 tinst ) 8-bit accuracy PWM operation Can be operated either as a 2-channel 8-bit timer/counter (timer 00 and timer 01, each with its own independent operating clock) , or as one 16-bit timer/counter. In timer 00 or 16-bit timer/counter operation, event counter operation by external clock input and square wave output capability Can be operated either as a 2-channel 8-bit timer/counter (timer 10 and timer 11, each with its own independent operating clock) , or as one 16-bit timer/counter. In timer 10-bit or 16-bit timer/counter operation, event counter operation by external clock input and square wave output capability 8 independent channels (selectable edge, interrupt vector, request flag) 8 channels (low level interrupt) 10-bit accuracy × 8 channels A/D conversion function (conversion time : 30 tinst ) Supports repeated activation by internal clock Common output Segment output LCD driving power (bias) pins LCD display RAM size : 4 (Max) : 32 (Max) :3 : 32 × 4 bits
8/16-bit timer/counter 00, 01
8/16-bit timer/counter 10, 11 External interrupt 0 (edge) External interrupt 1 (level) A/D converter
LCD controller/driver
(Continued)
3
MB89490 Series
(Continued) Part number Parameter
UART/SIO
MB89498
MB89F499
MB89PV490
Synchronous/asynchronous data transfer capability (Max baud rate : 97.656 Kbps at 12.5 MHz) (7-bit and 8-bit with parity bit; 8-bit and 9-bit without parity bit) 8-bit serial I/O with LSB first/MSB first selectability 1 clock selectable from 4 operation clock (1 external shift clock and 3 internal shift clock : 0.64 µs, 2.56 µs, 10.24 µs at 12.5 MHz) 1 channel (Use a 2-wire protocol to communicate with other device) Selectable maximum noise width removal Reversible input polarity Sleep mode, stop mode, watch mode and sub-clock mode CMOS 2.2 V to 3.6 V 2.7 V to 3.6 V 2.7 V to 3.6 V
SIO
I2C*2 Remote receiver circuit Standby mode Process Operating voltage
*1 : Use MBM27C512 as the external ROM. *2 : I2C is complied to Philips I2C specification.
4
MB89490 Series
s PACKAGE AND CORRESPONDING PRODUCTS
Part number Parameter FPT-100P-M06 FPT-100P-M05 MQP-100C-P01 O : Availabe × : Not available MB89498 O O × MB89F499 O O × MB89PV490 × × O
s DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggy-back product, verify its differences from the product that will be actually used. Take particular care on the following point : The stack area is set at the upper limit of the RAM.
2. Current Consumption
• For the MB89PV490, add the current consumed by the EPROM mounted in the piggy-back socket. • When operating at low speed, the current consumed by the FLASH product is greater than that for the mask ROM product. However, the current consumption is roughly the same in sleep and stop mode. • For more information, see “s ELECTRICAL CHARACTERISTICS.”
3. Oscillation Stabilization Wait Time after Power-on Reset
• For MB89PV490 and MB89F499, the power-on stabilization wait time cannot be selected after power-on reset. • For MB89498, the power-on stabilization wait time can be selected after power-on reset. • For more information, please refer to “s MASK OPTIONS”.
5
MB89490 Series
s PIN ASSIGNMENTS
(TOP VIEW)
VSS X0 X1 MOD0 RST P84 P83 P82/SCK1 P81/SO1 P80/SI1 P77/SEG31 P76/SEG30 P75/SEG29 P74/SEG28 P73/SEG27 P72/SEG26 P71/SEG25 P70/SEG24 P67/SEG23 P66/SEG22 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VCC *P00 *P01 *P02 *P03 *P04 *P05 *P06 *P07 P10/INT00 P11/INT01 P12/INT02 P13/INT03 P14/INT04 P15/INT05 P16/INT06 P17/INT07 P20/TO0 P21/RMC P22EC0 P23 P24/TO1 P25/EC1 P26/PWM0 P27/PWM1 P50/SI0 P51/SO0 P52/SCK0 AVR AVCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P65/SEG21 P64/SEG20 P63/SEG19 P62/SEG18 P61/SEG17 P60/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 P54/COM3 P53/COM2 COM1 COM0 V1 V2 V3 VCC
* : High current pins
AVSS P30/AN0/INT10 P31/AN1/INT11 P32/AN2/INT12 P33/AN3/INT13 P34/AN4/INT14 P35/AN5/INT15 P36/AN6/INT16 P37/AN7/INT17 *P40 *P41 *P42 *P43 *P44 *P45 *P46/SCL *P47/SDA X1A X0A VSS
(FPT-100P-M06)
(Continued)
6
MB89490 Series
(TOP VIEW)
*P01 *P00 VCC VSS X0 X1 MOD0 RST P84 P83 P82/SCK1 P81/SO1 P80/SI1 P77/SEG31 P76/SEG30 P75/SEG29 P74/SEG28 P73/SEG27 P72/SEG26 P71/SEG25 P70/SEG24 P67/SEG23 P66/SEG22 P65/SEG21 P64/SEG20 *P02 *P03 *P04 *P05 *P06 *P07 P10/INT00 P11/INT01 P12/INT02 P13/INT03 P14/INT04 P15/INT05 P16/INT06 P17/INT07 P20/TO0 P21/RMC P22/EC0 P23 P24/TO1 P25/EC1 P26/PWM0 P27/PWM1 P50/SI0 P51/SO0 P52/SCK0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P63/SEG19 P62/SEG18 P61/SEG17 P60/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 P54/COM3 P53/COM2 COM1 COM0 V1
* : High current pins
AVR AVCC AVSS P30/AN0/INT10 P31/AN1/INT11 P32/AN2/INT12 P33/AN3/INT13 P34/AN4/INT14 P35/AN5/INT15 P36/AN6/INT16 P37/AN7/INT17 *P40 *P41 *P42 *P43 *P44 *P45 *P46/SCL *P47/SDA X1A X0A VSS VCC V3 V2
(FPT-100P-M05)
(Continued)
7
MB89490 Series
(Continued)
(TOP VIEW)
VSS X0 X1 MOD0 RST P84 P83 P82/SCK1 P81/SO1 P80/SI1 P77/SEG31 P76/SEG30 P75/SEG29 P74/SEG28 P73/SEG27 P72/SEG26 P71/SEG25 P70/SEG24 P67/SEG23 P66/SEG22 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
VCC *P00 *P01 *P02 *P03 *P04 *P05 *P06 *P07 P10/INT00 P11/INT01 P12/INT02 P13/INT03 P14/INT04 P15/INT05 P16/INT06 P17/INT07 P20/TO0 P21/RMC P22EC0 P23 P24/TO1 P25/EC1 P26/PWM0 P27/PWM1 P50/SI0 P51/SO0 P52/SCK0 AVR AVCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
121 122 123 124 125 126 127 128 129
113 112 111 110 109 108 107 106 105
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P65/SEG21 P64/SEG20 P63/SEG19 P62/SEG18 P61/SEG17 P60/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 P54/COM3 P53/COM2 COM1 COM0 V1 V2 V3 VCC
* : High current pins
Pin assignment on package top (MB89PV490 only) Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name 101 102 103 104 105 106 107 N.C. A15 A12 A7 A6 A5 A4 108 109 110 111 112 113 114 A3 A2 A1 A0 N.C. O1 O2 115 116 117 118 119 120 121 O3 VSS N.C. O4 O5 O6 O7 122 123 124 125 126 127 128 O8 CE A10 OE N.C. A11 A9 129 130 131 132 A8 A13 A14 VCC
N.C. : As connected internally, do not use. 8
AVSS P30/AN0/INT10 P31/AN1/INT11 P32/AN2/INT12 P33/AN3/INT13 P34/AN4/INT14 P35/AN5/INT15 P36/AN6/INT16 P37/AN7/INT17 *P40 *P41 *P42 *P43 *P44 *P45 *P46/SCL *P47/SDA X1A X0A VSS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(MQP-100C-P01)
130 131 132 101 102 103 104
120 119 118 117 116 115 114
MB89490 Series
s PIN DESCRIPTION
Pin number MQFP*1/ LQFP*3 QFP*2 99 98 49 48 97 95, 94 96 95 46 45 94 92, 91 Pin name X0 X1 X0A X1A MOD0 P84, P83 A A I/O circuit type Function Connection pins for a crystal or other oscillator circuit. An external clock can be connected to X0. In this case, leave X1 open. Connection pins for a crystal or other oscillator circuit. An external clock can be connected to X0A. In this case, leave X1A open. Input pin for setting the memory access mode. Connect directly to VSS. General-purpose CMOS input port. Reset I/O pin. The pin is an N-ch open-drain type with pull-up resistor and hysteresis input. The pin outputs an “L” level when an internal reset request is present. Inputting an “L” level initializes internal circuits. General-purpose CMOS I/O port. General-purpose CMOS I/O port. The pin is shared with external interrupt 0 input. General-purpose CMOS I/O port. The pin is shared with 8/16-bit timer/counter 00 and 01 output. General-purpose CMOS I/O port. The pin is shared with remote receiver input. General-purpose CMOS I/O port. The pin is shared with 8/16-bit timer/counter 00 and 01 input. General-purpose CMOS I/O port. General-purpose CMOS I/O port. The pin is shared with 8/16-bit timer/counter 10 and 11 output. General-purpose CMOS I/O port. The pin is shared with 8/16-bit timer/counter 10 and 11 input. General-purpose CMOS I/O port. The pin is shared with PWM0 output. General-purpose CMOS I/O port. The pin is shared with PWM1 output. General-purpose CMOS I/O port. The pin is shared with external interrupt 1 input and A/D converter input. General-purpose N-ch open-drain I/O port. General-purpose N-ch open-drain I/O port. The pin is shared with I2C clock I/O.
B J
96
93
RST
C
2 to 9
99 to 6
P00 to P07 P10/INT00 to P17/INT07 P20/TO0 P21/RMC P22/EC0 P23 P24/TO1 P25/EC1 P26/PWM0 P27/PWM1 P30/AN0/INT10 to P37/AN7/INT17 P40 to P45 P46/SCL
D E
10 to 17 7 to 14
18 19 20 21 22 23 24 25
15 16 17 18 19 20 21 22
F E E F F E F F
32 to 39 29 to 36 40 to 45 37 to 42 46 43
G H H
(Continued)
9
MB89490 Series
(Continued) Pin number
MQFP*1/ LQFP*3 QFP*2 47 26 27 28 57 58 44 23 24 25 54 55 Pin name
I/O circuit type H E F E F/I F/I
Function General-purpose N-ch open-drain I/O port. The pin is shared with I2C data I/O. General-purpose CMOS I/O port. The pin is shared with SIO data input. General-purpose CMOS I/O port. The pin is shared with SIO data output. General-purpose CMOS I/O port. The pin is shared with SIO clock I/O. General-purpose CMOS I/O port. The pin is shared with the LCD common output. General-purpose CMOS I/O port. The pin is shared with the LCD common output. General-purpose CMOS I/O port. The pin is shared with LCD segment output. General-purpose CMOS I/O port. The pin is shared with LCD segment output. General-purpose CMOS I/O port. The pin is shared with UART/SIO data input. General-purpose CMOS I/O port. The pin is shared with UART/SIO data output. General-purpose CMOS I/O port. The pin is shared with UART/SIO clock I/O. LCD segment output-only pin. LCD common output-only pin. LCD driving power supply pin. Power supply pin. Power supply pin (GND) . A/D converter power supply pin. A/D converter reference voltage input pin. A/D converter power supply pin. Use at the same voltage level as VSS.
P47/SDA P50/SI0 P51/SO0 P52/SCK0 P53/COM2 P54/COM3 P60/SEG16 to P67/SEG23 P70/SEG24 to P77/SEG31 P80/SI1 P81/SO1 P82/SCK1 SEG0 to SEG15 COM0, COM1 V1 to V3 VCC VSS AVCC AVR AVSS
75 to 82 72 to 79
F/I
83 to 90 80 to 87
F/I
91 92 93
88 89 90
E F E I I
59 to 74 56 to 71 55, 56 54, 53, 52 1, 51 50, 100 30 29 31 52, 53 51, 50, 49 98, 48 47, 97 27 26 28
*1 : MQP-100C-P01 *2 : FPT-100P-M06 *3 : FPT-100P-M05 10
MB89490 Series
• External EPROM Socket (MB89PV490 only) Pin number Pin name I/O MQFP* 102 131 130 103 127 124 128 129 104 105 106 107 108 109 110 111 122 121 120 119 118 115 114 113 101 112 117 126 116 123 125 132 * : MQP-100C-P01 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O8 O7 O6 O5 O4 O3 O2 O1
Function
O
Address output pins.
I
Data input pins.
N.C.
O O O O
Internally connected pins. Always leave open.
VSS CE OE VCC
Power supply pin (GND) . Chip enable pin for the EPROM. Outputs “H” in standby mode. Output enable pin for the EPROM. Always outputs “L”. Power supply pin for the EPROM.
11
MB89490 Series
s I/O CIRCUIT TYPE
Type
X1 (X1A) N-ch P-ch
Circuit
Remarks • Main/Sub-clock circuit
A
X0 (X0A)
P-ch N-ch N-ch
Stop mode control signal
B
R
• Hysteresis input (CMOS input in MB89F499) • The pull-down resistor (not available in MB89F499) Approx. 50 kΩ
R P-ch
• The pull-up resistor (P-channel) Approx. 50 kΩ • Hysteresis input
C
N-ch
R P-ch P-ch
pull-up resistor register
• • • •
D
N-ch
CMOS output IOH = − 4 mA, IOL = 12 mA CMOS input Selectable pull-up resistor Approx. 50 kΩ
port
R P-ch P-ch
pull-up resistor register
• • • • •
E
N-ch
CMOS output IOH = − 2 mA, IOL = 4 mA CMOS port input Hysteresis resource input Selectable pull-up resistor Approx. 50 kΩ
port resource
(Continued)
12
MB89490 Series
(Continued) Type
Circuit
pull-up resistor register P-ch
Remarks • • • • CMOS output IOH = − 2 mA, IOL = 4 mA CMOS input Selectable pull-up resistor Approx. 50 kΩ
R P-ch
F
N-ch
port
R P-ch P-ch
pull-up resistor register
G
N-ch
• • • • • •
CMOS output IOH = − 2 mA, IOL = 4 mA CMOS port input VIH = 0.85 VCC, VIL = 0.5 VCC resource input Analog input Selectable pull-up resistor Approx. 50 kΩ
port resource analog
H
N-ch
port/resource
• • • • •
N-ch open-drain output IOL = 15 mA CMOS port input CMOS resource input 5 V tolerance
• LCD segment output
P-ch N-ch
I
P-ch N-ch
• CMOS input J
13
MB89490 Series
s HANDLING DEVICES
1. Preventing Latch-up
Latch-up may occur on CMOS IC if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in “s ELECTRICAL CHARACTERISTICS” is applied between VCC and VSS. When latch-up occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D
Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D is not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Stabilization
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. As stabilization guidelines, it is recommended to control voltage fluctuation so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 Hz to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up from stop mode.
7. Treatment of Unused dedicated LCD pins
When dedicated LCD pins are not in use, keep them open.
14
MB89490 Series
s PROGRAMMING AND ERASING FLASH MEMORY ON THE MB89F499
1. Flash Memory
The flash memory is located between 1000H and FFFFH in the CPU memory map and incorporates a flash memory interface circuit that allows read access and program access from the CPU to be performed in the same way as mask ROM. Programming and erasing flash memory is also performed via the flash memory interface circuit by executing instructions in the CPU. This enables the flash memory to be updated in place under the control of the internal CPU, providing an efficient method of updating program and data.
2. Flash Memory Features
• • • • • • • •
60K bytes × 8-bit configuration (16 K + 8 K + 8 K + 28 K sectors) Automatic algorithm (Embedded algorithm* : Equivalent to MBM29LV200) Includes an erase pause and erase restart function Data polling and toggle bit for detection of program/erase completion Detection of program/erase completion via CPU interrupt Compatible with JEDEC-standard commands Sector Protection (sectors can be combined in any combination) No. of program/erase cycles : 10,000 (Min)
* : Embedded Algorithm is a trademark of Advanced Micro Devices.
3. Procedure for Programming and Erasing Flash Memory
Programming and reading flash memory cannot be performed at the same time. Accordingly, to program or erase data to the flash memory, the program must first be copied from flash memory to RAM so that programming can be performed without program access from flash memory.
4. Flash Memory Register
• Flash memory control status register (FMCS)
Bit 7 INTE R/W Bit 6 RDYINT R/W Bit 5 WE R/W Bit 4 RDY R Bit 3 Bit 2 Bit 1 Bit 0 Reserved R/W
Address 007AH
Reserved Reserved R/W R/W
Initial value 000X00-0B
15
MB89490 Series
5. Sector Configuration
The table below shows the sector configuration of flash memory and lists the addresses of each sector during CPU access and a flash memory programming. • Sector configuration of flash memory Flash Memory CPU Address Programmer Address* 16 K bytes 8 K bytes 8 K bytes 28 K bytes FFFFH to C000H BFFFH to A000H 9FFFH to 8000H 7FFFH to 1000H 1FFFFH to 1C000H 1BFFFH to 1A000H 19FFFH to 18000H 17FFFH to 11000H
* : The programmer address is the address to be used instead of the CPU address when programming data from a parallel flash memory programmer. Use the programmer address on programming or erasing using a generalpurpose programmer.
6. ROM Programmer Adaptor and Recommended ROM Programmers
Package FPT-100P-M06 FPT-100P-M05 Applicable adapter model Sunhayato Corp. FLASH-100QF-32DP-8LF2 FLASH-100SQF-32DP-8LF Recommended writer Ando Electric Co. Ltd. AF9708 (ver 1.60 or later) * AF9709 (ver 1.60 or later) *
* : For the programmer and the version of the programmer,contact the Flash Support Group, Inc. Inquirues : Sunhayato Corp. : TEL : 81-(3)-3984-7791 FAX : 81-(3)-3971-0535 E-mail : adapter@sunhayato.co.jp Flash Support Group, Inc. : FAX : 81-(53)-428-8377 E-mail : support@j-fsg.co.jp
16
MB89490 Series
s PROGRAMMING TO THE EPROM WITH PIGGY-BACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C512-20TV
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer : Sunhayato Corp.) . Package Adapter socket part number LCC-32 (Rectangle) ROM-32LC-28DP-YG
Inquiry : Sunhayato Corp. : TEL : 81-3-3984-7791 FAX : 81-3-3971-0535 E-mail : adapter@sunhayato.co.jp
3. Memory Space
Memory space corresponding to EPROM writer is shown in the diagram below. Address Normal operating mode
0000H I/O 0080H RAM 0880H Not available 1000H 1000H
Corresponding addresses on the EPROM programmer
PROM 60 KB
EPROM 60 KB
FFFFH
FFFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C512. (2) Load program data into the EPROM programmer at 1000H to FFFFH. (3) Program to 1000H to FFFFH with the EPROM programmer.
s ICE PROBE POD ADAPTOR OF PIGGY-BACK/EVA CHIP
The following conversion adapter is required to achieve the same pin layout as the FPT-100P-M05.
Adaptor part number: 100QF-100SQF-8L
Inquiry : Sunhayato Corp. : TEL FAX
: 81-3-3984-7791 : 81-3-3971-0535
E-mail : adapter@sunhayato.co.jp 17
MB89490 Series
s BLOCK DIAGRAM
X0 X1
Main clock oscillator circuit Clock controller
21-bit timebase timer AVCC AVSS AVR 10-bit A/D converter CMOS I/O port External interrupt 1 (level) 8 8 P37/AN7/INT17 8 to P30/AN0/INT10
X0A X1A
Sub-clock oscillator circuit Reset circuit (Watchdog timer) Watch prescaler
RST
P23 P26/PWM0 Port2 P27/PWM1 P21/RMC P22/EC0 P20/TO0 P25/EC1 P24/TO1 P17/INT07 to P10/INT00 8 Port1
CMOS I/O port 8-bit PWM timer 0 Internal data bus 8-bit PWM timer 1
Remote receiver circuit
Port3
I2C N-ch open-drain I/O port CMOS I/O port UART/SIO SIO CMOS I/O port 2
Port4*
P47/SDA P46/SCL 6 P45 to P40 P84 P83 P82/SCK1 P81/SO1 P80/SI1 P52/SCK0 P51/SO0 P50/SI0
8/16-bit timer/counter 10, 11 8 External interrupt 0 (edge) CMOS I/O port CMOS I/O port
Port5 2 P54/COM3, P53/COM2 16 SEG0 to SEG15 2 COM0, COM1 3 Port6, 7 V1 to V3 8 P67/SEG23 to P60/SEG16 8 P77/SEG31 to P70/SEG24
P07 to P00
8 Port0* LCD controller/driver
RAM (2 K bytes) F2MC-8L CPU
32 × 4-bit display RAM (16 bytes) 16
ROM 48 K bytes/FLASH 60 K bytes Other pins VCC × 2, VSS × 2, MOD0 CMOS I/O port
* : High current I/O port.
18
Port8
8/16-bit timer/counter 00, 01
MB89490 Series
s CPU CORE
1. Memory Space
The microcontrollers of the MB89490 series offer a memory space of 64K bytes for storing all of I/O, data, and program areas. The I/O area is located the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt/reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89490 series is structured as illustrated below. Memory Space
MB89498 0000H I/O 0080H RAM 0100H Generalpurpose registers 0100H 0080H 0000H
MB89F499 0000H I/O 0080H RAM 0100H Generalpurpose registers Vacant
MB89PV490
I/O
RAM Generalpurpose registers Vacant
0200H 0880H
0200H 0880H 1000H
0200H 0880H 1000H
Vacant FLASH (60 K) 4000H External ROM (60 K)
FFC0H FFFFH
ROM
FFC0H FFFFH
FFC0H FFFFH
Vector table (reset, interrupt, vector call instruction)
19
MB89490 Series
2. Registers
The F2MC-8L family has 2 types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following registers are provided : Program counter (PC) : A 16-bit register for indicating instruction storage positions. Accumulator (A) : A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T) : A 16-bit register for performing arithmetic operations with the accumulator. When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX) : A 16-bit register for index modification. Extra pointer (EP) : A 16-bit pointer for indicating a memory address. Stack pointer (SP) : A 16-bit register for indicating a stack area. Program status (PS) : A 16-bit register for storing a register pointer and condition code.
16-bit PC A T IX EP SP PS : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status
Initial value FFFDH Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, 0 = 11 Other bits are undefined.
The PS can further be divided into higher 8-bit for use as a register bank pointer (RP) and the lower 8-bit for use as a condition code register (CCR) . (See the diagram below.) Structure of the Program Status Register
15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 3 N 2 Z 1 V 0 C
Va- Va- Vacancy cancy cancy
IL1, 0
RP
CCR
20
MB89490 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Conversion rule for Actual Addresses of the General-purpose Register Area
RP Lower OP codes b1 b0
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2
Generated addresses
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for controlling the CPU operations at the time of an interrupt. H-flag : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Clear to “0” otherwise. This flag is for decimal adjustment instructions. I-flag : Interrupt is allowed when this flag is set to “1”. Interrupt is prohibited when the flag is set to “0”. Clear to “0” at reset. IL1, 0 : Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request is higher than the value indicated by this bit. IL1 0 0 1 1 IL0 0 1 0 1 Interrupt level 1 2 3 Low High-low High
N-flag : Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Clear to “0” otherwise. Z-flag : Set to “1” when an arithmetic operation results in “0”. Clear to “0” otherwise. V-flag : Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Clear to “0” if the overflow does not occur. C-flag : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Clear to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
21
MB89490 Series
The following general-purpose registers are provided : General-purpose registers : An 8-bit register for storing data The general-purpose registers are 8-bit and located in the register banks of the memory. 1 bank contains 8 registers. Up to a total of 32 banks can be used on the MB89490 series. The bank currently in use is indicated by the register bank pointer (RP) .
Register Bank Configuration
This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area
22
MB89490 Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H DDR2 SYCC STBC WDTC TBTC WPCR PDR3 DDR3 RSFR PDR4 PDR5 DDR5 PDR6 DDR6 PDR7 DDR7 PDR8 DDR8 EIC0 EIC1 EIC2 EIC3 EIE1 EIF1 SMR SDR T01CR T00CR T01DR Port 2 direction register System clock control register Standby control register Watchdog timer control register Timebase timer control register Watch prescaler control register Port 3 data register Port 3 direction register Reset flag register Port 4 data register Port 5 data register Port 5 direction register Port 6 data register Port 6 direction register Port 7 data register Port 7 direction register Port 8 data register Port 8 direction register External interrupt 0 control register 0 External interrupt 0 control register 1 External interrupt 0 control register 2 External interrupt 0 control register 3 External interrupt 1 enable register External interrupt 1 flag register Serial mode register Serial data register Timer 01 control register Timer 00 control register Timer 01 data register Register name PDR0 DDR0 PDR1 DDR1 PDR2 Register description Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register Port 2 data register (Reserved) R/W R/W R/W W* R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00000000B X-1MM100B 00010XXXB 0---XXXXB 00---000B 00--0000B XXXXXXXXB 11111111B XXXX----B 11111111B ---XXXXXB ---00000B XXXXXXXXB 00000000B XXXXXXXXB 00000000B ---XXXXXB ---00000B 00000000B 00000000B 00000000B 00000000B 00000000B -------0B 00000000B XXXXXXXXB 000000X0B 000000X0B XXXXXXXXB Read/Write R/W W* R/W W* R/W Initial value XXXXXXXXB 00000000B XXXXXXXXB 00000000B 00000000B
(Continued)
23
MB89490 Series
Address 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH to 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H
Register name T00DR T11CR T10CR T11DR T10DR ADER ADC0 ADC1 ADDH ADDL CNTR0 COMR0 SMC0 SMC1 SSD SIDR/SODR SRC CNTR1 COMR1 IBSR IBCR ICCR IADR IDAR PLLCR RMN RMC RMS RMD RMCD0 RMCD1 RMCD2 RMCD3 RMCD4
Register description Timer 00 data register Timer 11 control register Timer 10 control register Timer 11 data register Timer 10 data register A/D input enable register A/D control register 0 A/D control register 1 A/D data register (Upper byte) A/D data register (Lower byte) PWM 0 timer control register PWM 0 timer compare register UART/SIO serial mode control register UART/SIO serial mode control register UART/SIO serial status/data register UART/SIO serial data register UART/SIO serial rate control register PWM 1 timer control register PWM 1 timer compare register I C bus status register I C bus control register I2C clock control register I2C address register I C data register Sub PLL control register (Reserved) Remote control counter register Remote control control register Remote control status register Remote control FIFO data register Remote control compare register 0 Remote control compare register 1 Remote control compare register 2 Remote control compare register 3 Remote control compare register 4
2 2 2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R R R/W W* R/W R/W R/W R/W R/W R/W W* R R/W R/W R/W R/W R/W R R/W R/W R R/W R/W R/W R/W R/W
Initial value XXXXXXXXB 000000X0B 000000X0B XXXXXXXXB XXXXXXXXB 11111111B -00000X0B -0000001B ------XXB XXXXXXXXB 0-000000B XXXXXXXXB 00000000B 00000000B 00001---B XXXXXXXXB XXXXXXXXB 0-000000B XXXXXXXXB 00000000B 00000000B 000XXXXXB -XXXXXXXB XXXXXXXXB ----0000B XXXXXXXXB 00000000B 0X000001B X----XXXB 11111111B 11111111B 11111111B 11111111B 11111111B
(Continued)
24
MB89490 Series
(Continued) Address
49H 4AH 4BH to 5DH 5EH 5FH 60H to 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H to 79H 7AH 7BH 7CH 7DH 7EH 7FH * : Bit manipulation instruction cannot be used. • Read/write access symbols R/W : Readable and writable R: Read-only W : Write-only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. - : Unused bit. M : The initial value of this bit is determined by mask option. FMCS ILR1 ILR2 ILR3 ILR4 LOCR LCR VRAM PUCR0 PUCR1 PUCR2 PUCR3 PUCR5 PUCR6 PUCR7 PUCR8
Register name RMCD5 RMCI
Register description Remote control compare register 5 Remote interrupt register (Reserved) LCD controller output control register LCD controller control register LCD data RAM Port 0 pull up resistor control register Port 1 pull up resistor control register Port 2 pull up resistor control register Port 3 pull up resistor control register Port 5 pull up resistor control register Port 6 pull up resistor control register Port 7 pull up resistor control register Port 8 pull up resistor control register (Reserved) Flash memory control status registger Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 (Reserved)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W* W* W* W*
Initial value 11111111B 0000-000B -0000000B 00010000B XXXXXXXXB 11111111B 11111111B 11111111B 11111111B ---11111B 11111111B 11111111B -----111B 000X00-0B 11111111B 11111111B 11111111B 11111111B
25
MB89490 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol VCC AVCC AVR LCD power supply voltage V1 to V3 Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 Input voltage *1 VI VSS − 0.3 VSS − 0.3 Output voltage*
1
Max VSS + 4.0 VSS + 4.0 VCC VCC + 0.3 VSS + 6.0 VSS + 5.5 VCC + 0.3 + 2.0 20 15 4 100 40 − 15 −4 − 50 − 20 300 + 85 + 150
Unit V V V V V V V mA mA mA mA mA mA mA mA mA mA mW °C °C *2 *2
Remarks AVCC must be equal to VCC
Power supply voltage*1
Except P40 to P47 P40 to P47 in MB89PV490 and MB89498 P40 to P47 in MB89F499
VO ICLAMP Σ|ICLAMP|
VSS − 0.3 − 2.0 − 40 − 55
Maximum clamp current Total maximum clamp current
“L” level maximum output current IOL “L” level average output current “L” level total maximum output current “L” level total average output current IOLAV ΣIOL ΣIOLAV
Average value (operating current × operating rate)
Average value (operating current × operating rate) Average value (operating current × operating rate)
“H” level maximum output current IOH “H” level average output current “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature *2 : • • • • IOHAV ΣIOH ΣIOHAV PD TA Tstg
Average value (operating current × operating rate)
*1 : The parameter is based on AVSS = VSS = 0.0 V. Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P50 to P52, P80 to P82 Use within recommended operating conditions. Use at DC voltage (current) . The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. (Continued)
26
MB89490 Series
(Continued) • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on result. • Care must be taken not to leave the +B input pin open. • Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. • Sample recommended circuits :
• Input/Output Equivalent circuits Protective diode
VCC
Limiting resistance +B input (0 V to 16 V)
P-ch
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
27
MB89490 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V) Parameter Symbol Value Min 2.7* Power supply voltage VCC AVCC 2.2* 1.5 AVR LCD power supply voltage Operating temperature V1 to V3 TA 2.7 Vss −40 Max 3.6 3.6 3.6 3.6 Vcc +85 Unit V V V V V °C Normal operation assurance range Normal operation assurance range Remarks MB89PV490 and MB89F499 MB89498
Retains the RAM state in stop mode
* : These values depend on the operating conditions and the analog assurance range. See Figure 1, 2 and “5. A/D Converter Electrical Characteristics.” WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
Operating voltage (V) 3.6 3.0 2.7 2.2 2.0 Analog accuracy assurance range : VCC = AVCC = 2.7 V to 3.6 V
Main clock operating freq. (MHz) 1.0 4.0 2.0 2.0 3.0 1.33 4.0 1.0 5.0 0.8 6.0 0.66 7.0 0.57 8.0 0.50 9.0 0.44 10.0 11.0 12.0 12.5 0.4 0.36 0.33 0.32 Min execution time (inst. cycle) (µs)
Note : The shaded area is not assured for MB89F499
Figure1 Operating Voltage vs. Main Clock Operating Frequency (MB89F499/498)
28
MB89490 Series
Operating voltage (V)
3.6 3.5 3.0 2.7
Analog accuracy assurance range : VCC = AVCC = 2.7 V to 3.6 V
Main clock operating freq. (MHz) 1.0 4.0 2.0 2.0 3.0 1.33 4.0 1.0 5.0 0.8 6.0 0.66 7.0 0.57 8.0 0.50 9.0 0.44 10.0 11.0 12.0 12.5 0.4 0.36 0.33 0.32 Min execution time (inst. cycle) (µs)
Figure2 Operating Voltage vs. Main Clock Operating Frequency (MB89PV490) Figure 1 and 2 indicate the operating frequency of the external oscillator at an instruction cycle of 4/FCH. Since the operating voltage range is dependent on the instruction cycle, see figure 1 and 2 if the operating speed is switched using a gear.
29
MB89490 Series
3. DC Characteristics
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Pin Condition Value Min Typ Max Unit Remarks
Parameter Symbol
VIH “H” level input voltage
P00 to P07, P10 to P17, P20 to P27, P30 to P37, P50 to P54, P60 to P67, P70 to P77, P80 to P84, SCL, SDA, P40 to P47 RST, MOD0, EC0, EC1, SCK0, SI0, SCK1, SI1, RMC, INT00 to INT07 INT10 to INT17 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P54, P60 to P67, P70 to P77, P80 to P84, SCL, SDA, RST, MOD0, EC0, EC1, SCK0, SI0, SCK1, SI1, RMC, INT00 to INT07 INT10 to INT17
0.7 VCC
VCC + 0.3
V
0.7 VCC 0.7 VCC
VSS + 6.0 VSS + 5.5 VCC + 0.3 VCC + 0.3
V V
MB89498 MB89F499
VIHS
0.8 VCC
V
VIHA
0.85 VCC
V
VIL “L” level input voltage
VSS − 0.3
0.3 VCC
V
VILS
VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3
0.2 VCC
V
VILA Open-drain output pin application voltage
0.5 VCC VSS + 6.0 VSS + 5.5
V V V MB89498 MB89F499
VD
P40 to P47
(Continued)
30
MB89490 Series
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin P10 to P17, P20 to P27, P30 to P37, P50 to P54, P60 to P67, P70 to P77, P80 to P82 P00 to P07 Condition Value Min Typ Max Unit Remarks
“H” level VOH output voltage
IOH = −2.0 mA
2.2
V
IOH = −4.0 mA
2.2
V
“L” level VOL output voltage
P10 to P17, P20 to P27, P30 to P37, P50 to P54, IOL = 4.0 mA P60 to P67, P70 to P77, P80 to P82, RST P00 to P07 P40 to P47 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P54, P60 to P67, P70 to P77, P80 to P84 P40 to P47 IOL = 12.0 mA IOL = 15.0 mA
0.4
V
0.4 0.4
V V
Input leakage current
ILI
0.45 V < VI < VCC
−5
+5
µA
Without pull-up resistor
Open-drain output leakage ILOD current Pull-down resistance RDOWN
0.0 V < VI < VCC VI = VCC
−5 25
50
+5 100
µA kΩ Except MB89F499
MOD0 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P50 to P54, P60 to P67, P70 to P77, P80 to P82, RST COM0 to COM3
Pull-up resistance
RPULL
VI = 0.0 V
25
50
100
kΩ
When pull-up resistor is selected (except RST)
Common output impedance
RVCOM
V1 to V3 = +3.0 V
2.5
kΩ
(Continued)
31
MB89490 Series
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Segment output impedance LCD divided resistance LCD controller/ driver leakage current Symbol Pin Condition Value Min 300 Typ 500 Max 15 Unit Remarks
RVSEG
SEG0 to SEG31 V1 to V3 = +3.0 V V1 to V3, COM0 to COM3, SEG0 to SEG31 Between VCC and VSS
kΩ kΩ
RLCD
750
ILCDL
−1
+1
µA
ICC1
FCH = 12.5 MHz tinst = 0.33 µs Main clock run mode FCH = 12.5 MHz tinst = 5.33 µs Main clock run mode FCH = 12.5 MHz tinst = 0.33 µs Main clock sleep mode FCH = 12.5 MHz tinst = 5.33 µs Main clock sleep mode VCC FCL = 32.768 kHz Sub-clock mode TA = +25 °C FCL = 32.768 kHz Sub-clock mode TA = +25 °C sub PLL × 4 FCL = 32.768 kHz Sub-clock sleep mode TA = +25 °C FCL = 32.768 kHz Watch mode Main clock stop mode TA = +25 °C
8.0 7.0 1.0
12 12.0 3.0
mA MB89F499 mA MB89498 mA MB89F499 MB89498
ICC2
ICCS1
3.0
5.0
mA
MB89F499 MB89498
ICCS2 Power supply current ICCL
0.6
2.0
mA
MB89F499 MB89498
40.0
60.0
µA
MB89F499 MB89498
ICCLPLL
180.0
250.0
µA
MB89F499 MB89498
ICCLS
14.0
30.0
µA
MB89F499 MB89498
ICCT
1.5
13.0
µA
MB89F499 MB89498
(Continued)
32
MB89490 Series
(Continued)
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol ICCH Power supply IA current IAH Input capacitance CIN VCC Pin Condition TA = +25 °C Sub-clock stop mode AVCC = 3.0 V, TA = +25 °C TA = +25 °C Except VCC, VSS, AVCC, f = 1 MHz AVSS, AVR Value Min Typ 0.8 1.2 0.8 10.0 Max 4.0 4.4 4.0 Unit µA mA Remarks MB89F499 MB89498 A/D converting
Parameter
AVCC
µA A/D stop pF
33
MB89490 Series
4. AC Characteristics
(1) Reset Timing (AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol tZLZH Condition Value Min 48 tHCYL Max Unit ns Remarks
Parameter RST “L” pulse width
Note : tHCYL is the oscillation cycle (1/FCH) to input to the X0 pin. The MCU operation is not guaranteed when the “L” pulse width is shorter than tZLZH.
tZLZH RST
0.2 VCC
0.2 VCC
(2) Power-on Reset Value Min 1 Max 50
(AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol tR tOFF Condition Unit ms ms Due to repeated operations Remarks
Parameter Power supply rising time Power supply cut-off time
Note : Make sure that power supply rises within the selected oscillation stabilization time. Rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR 1.5 V 0.2 V
tOFF
VCC
0.2 V
0.2 V
34
MB89490 Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol FCH FCL tHCYL tLCYL PWH PWL PWHL PWLL tCR tCF Pin X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0, X0A Value Min 1 80 13.3 20 Typ 32.768 30.5 15.2 Max 12.5 75 1000 10 Unit MHz kHz ns µs ns µs ns External clock Remarks
Parameter Clock frequency Clock cycle time
Input clock pulse width
Input clock rising/falling time
X0 and X1 Timing and Conditions
tHCYL PWH tCR 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tCF PWL
X0
0.2 VCC
Main Clock Conditions
When a crystal or ceramic resonator is used
When an external clock is used
X0
X1 FCH C1 C2
X0
X1 open
FCH
35
MB89490 Series
Sub-clock Timing and Conditions
tLCYL 0.8 VCC 0.2 VCC PWHL tCF PWLL tCR
X0A
Sub-clock Conditions
When a crystal or ceramic resonator is used
When an external clock is used
When an subclock is not used
X0A FCL
X1A Rd
X0A
X1A
X0A
X1A Open
FCL C0 C1
Open
(4) Instruction Cycle Parameter Instruction cycle (minimum execution time) Symbol Value (typical) 4/FCH, 8/FCH, 16/FCH, 64/FCH tinst 2/FCL, 1/2FCL µs Unit µs Remarks (4/FCH) tinst = 0.32 µs when operating at FCH = 12.5 MHz (2/FCL) tinst = 61.036 µs when operating at FCL = 32.768 kHz
36
MB89490 Series
• PLL operation guarantee range (sub PLL × 4)
Relationship between internal operating clock frequency and power supply voltage
Operating voltage (V) subPLL operating guarantee range 3.6 3.0 2.7 2.5 2.0 Internal operating clock freq. (kHz) 131.072 15.625 Not assured for MB89F499 and MB89PV490. 300 6.67
Min execution time (inst. cycle) (µs)
Relationship between sub-clock oscillating frequency and instruction cycle when sub PLL is enabled
Instruction cycle, tinst (min. exec. time) (µs)
15.625
Multiplied by 4
6.67
75 Oscillation clock FCL (kHz)
32.768
37
MB89490 Series
(5) Serial I/O Timing
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX SCK0, SCK1 SCK0, SCK1, SO0, SO1 SI0, SI1, SCK0, SCK1 SCK0, SCK1, SI0, SI1 SCK0, SCK1 SCK0, SCK1, SO0, SO1 SI0, SI1, SCK0, SCK1 SCK0, SCK1, SI0, SI1 External shift clock mode Internal shift clock mode Pin Condition Value Min 2 tinst* −200 1/2 tinst* 1/2 tinst* 1 tinst* 1 tinst* 0 1/2 tinst* 1/2 tinst* Max 200 200 Unit µs ns µs µs µs µs ns µs µs
Parameter Serial clock cycle time SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time
* : For information on tinst, see “ (4) Instruction Cycle.” Internal Clock Operation
tSCYC
SCK0, SCK1
2.4 V 0.8 V tSLOV 0.8 V
SO0, SO1
2.4 V 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SI0, SI1
0.2 VCC
External Clock Operation
tSLSH tSHSL 0.8 VCC 0.2 VCC tSLOV 0.2 VCC 0.8 VCC
SCK0, SCK1
SO0, SO1
2.4 V 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SI0, SI1
0.2 VCC
38
MB89490 Series
(6) I2C Timing (VCC = 3.0V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol tSTA tSTO tSTA tSTO tSTASU tSTASU tLOW tHIGH tDO tDOSU tLOW tHIGH tSU tHO Pin SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SCL SDA SDA SCL SCL SDA SDA Value Min 1/4 tinst*1 × M × N − 20 1/4 tinst × (M × N + 8) − 20 1/4 tinst × 6 + 40 1/4 tinst × 6 + 40 1/4 tinst × (M × N + 8) − 20 1/4 tinst × 4 + 40 1/4 tinst × M × N − 20 1/4 tinst × (M × N + 8) − 20 1/4 tinst × 4 − 20 1/4 tinst × 4 − 20 1/4 tinst × 6 + 40 1/4 tinst × 2 + 40 40 0 Max 1/4 tinst × M × N + 20 1/4 tinst × (M*2 × N*3 + 8) + 20 1/4 tinst × (M × N + 8 ) + 2 0 1/4 tinst × M × N + 20 1/4 tinst × (M × N + 8 ) + 2 0 1/4 tinst × 4 + 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns *4 At master mode At master mode At master mode Remarks At master mode At master mode
Parameter Start condition output Stop condition output Start condition detect Stop condition detect Re-start condition output Re-start condition detect SCL output LOW width SCL output HIGH width SDA output delay SDA output setup time after interrupt SCL input LOW pulse width SCL input HIGH pulse width SDA input setup time SDA hold time
*1 : For information in tinst, see “ (4) Instruction Cycle”. *2 : M is defined in the I2C clock control register ICCR bit 4 and bit 3 (CS4 and CS3). For details, please refer to the H/W manual register explanation. *3 : N is defined in the I2C clock control register ICCR bit 2 to bit 0 (CS2 to CS0). *4 : When the interrupt period is greater than SCL “L” width, SDA and SCL output (Standard) value is based on hypothesis when rising time is 0 ns.
39
MB89490 Series
Data transmit (master/slave)
tDO SDA tSTASU SCL tSTA tLOW tHO 1 9 tDO tSU ACK tHO tDOSU
Data receive (master/slave)
tSU SDA tHIGH SCL 6 7 tLOW 8 9 tHO tDO ACK tSTO tDO tDOSU
40
MB89490 Series
(7) Peripheral Input Timing
(AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol tILIH1 tIHIL1 Pin EC0, EC1, INT00 to INT07, INT10 to INT17 Value Min 2 tinst* 2 tinst* Max Unit µs µs Remarks
Parameter Peripheral input “H” pulse width 1 Peripheral input “L” pulse width 1
* : For information on tinst, see “ (4) Instruction Cycle.”
tIHIL1
tILIH1
EC0, EC1, INT00 to INT07
0.2 VCC
0.8 VCC 0.2 VCC
0.8 VCC
tIHIL1
tILIH1
INT10 to INT17
0.85 VCC 0.5 VCC 0.5 VCC 0.85 VCC
41
MB89490 Series
5. A/D Converter Electrical Characteristics
(1) A/D Converter Electrical Characteristics (AVCC = VCC = 2.7 V to 3.6 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage A/D mode conversion time Analog port input current Analog input voltage Reference voltage Reference voltage supply current VOT VFST IAIN VAIN IR IRH AVR AN0 to AN7 Symbol Pin Value Min AVSS − 1.5 LSB AVCC − 3.5 LSB 30 tinst* AVSS AVSS + 2.7 Typ 10 AVSS + 0.5 LSB AVCC − 1.5 LSB 95.0 Max ±3.0 ±2.5 ±1.9 AVSS + 2.5 LSB AVCC − 0.5 LSB 10 AVR AVCC 170.0 4.0 Unit bit LSB LSB LSB mV mV µs µA V V µA µA A/D is activated A/D is stopped Remarks
* : For information on tinst, see “ (4) Instruction Cycle” in “4. AC Characteristics”.
42
MB89490 Series
(2) A/D Converter Glossary • Resolution Analog changes that are identifiable with the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. • Linearity error (unit : LSB) The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics. • Differential linearity error (unit : LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value. • Total error (unit : LSB) The difference between theoretical and actual conversion values.
Theoretical I/O characteristics
3FFH 3FEH 3FDH 1.5 LSB VFST 3FFH 3FEH 3FDH
Total error
Actual conversion characteristics
{1 LSB × N + VOT}
Digital output
004H 003H 002H 001H 0.5 LSB AVSS AVCC
Digital output
004H 003H 002H 001H AVSS
VNT Actual conversion characteristics Ideal characteristics
VOT 1 LSB
AVCC
Analog input
Analog input
1 LSB =
VFST − VOT 1022
(V)
Total error = VNT − {1 LSB × N + 0.5 LSB} 1 LSB
Zero transition error
004H Actual conversion characteristics 003H 3FFH
Full-scale transition error
Theoretical characteristics
Actual conversion characteristics
Digital output
Digital output
3FEH VFST (Actual measurement value) Actual conversion characteristics
002H Actual conversion characteristics 001H VOT (Actual measurement value) AVSS
3FDH
3FCH AVCC
Analog input
Analog input
(Continued)
43
MB89490 Series
(Continued)
Linearity error
3FFH 3FEH 3FDH
Digital output
Differential linearity error
Ideal value N+1 Actual conversion characteristics VFST (Actual value) N V(N + 1)T
Actual conversion characteristics {1 LSB × N + VOT}
Digital output
VNT measurement
004H 003H 002H 001H AVSS Actual conversion characteristics Ideal value VOT (Actual measurement value) AVCC
N–1
VNT Actual conversion characteristics
N–2 AVSS AVCC
Analog input
Analog input
Linearity error =
VNT − {1 LSB × N + VOT} 1 LSB
Differential linearity error =
V(N + 1)T − VNT 1 LSB
−1
44
MB89490 Series
(3) Notes on Using A/D Converter • About the external impedance of the analog input and its sampling time • A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. • Analog input circuit model
R
Analog input
C
Comparator During sampling : ON MB89498 MB89F499 R 2.4 kΩ (Max) 2.4 kΩ (Max) C 44.0 pF (Max) 28.6 pF (Max)
Note : The values are reference values.
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value.
• The relationship between external impedance and minimum sampling time (External impedance = 0 kΩ to 100 kΩ)
MB89F499 100 MB89498 20
(External impedance = 0 kΩ to 20 kΩ)
MB89F499 MB89498
External impedance [kΩ]
80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35
External impedance [kΩ]
90
18 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8
Minimum sampling time [µs]
Minimum sampling time [µs]
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. • About errors As |AVRH − AVSS| becomes smaller, values of relative errors grow larger.
45
MB89490 Series
s EXAMPLE CHARACTERISTICS
(1) “L” level output voltage
VOL vs IOL (MB89F499)
VCC = 2.0 V VCC = 2.5 V VCC = 2.7 V VCC = 3.0 V VCC = 3.3 V VCC = 3.5 V VCC = 4.0 V
VOL vs IOL (MB89498)
0.30 TA = + 25˚C 0.20 VCC = 2.0 V 0.25 VCC = 2.5 V VCC = 2.7 V VCC = 3.0 V VCC = 3.3 V VCC = 3.5 V VCC = 4.0 V
0.25
TA = + 25˚C
0.20
0.15
VOL [V]
VOL [V]
0.15
0.10 0.10 0.05
0.05
0.00 0 2 4 6 8 10
0.00 0 2 4 6 8 10
IOL [mA]
Port 0
IOL [mA]
Port 0
VOL vs IOL (MB89498)
VOL vs IOL (MB89F499)
0.20 TA = + 25˚C 0.16 VCC = 2.0 V 0.12 VCC = 2.5 V VCC = 2.7 V VCC = 3.0 V VCC = 3.3 V VCC = 3.5 V VCC = 4.0 V
0.20 TA = + 25˚C 0.16 VCC = 2.0 V
0.12
0.08
0.08
VCC = 2.5 V VCC = 2.7 V VCC = 3.0 V VCC = 3.3 V VCC = 3.5 V VCC = 4.0 V
VOL [V]
0.02
VOL [V]
0.04
0.00 0 2 4 6 8 10
0.00 0 2 4 6 8 10
IOL [mA]
Port 4
IOL [mA]
Port 4
(Continued)
46
MB89490 Series
(Continued)
VOL vs IOL (MB89F499)
VCC = 2.0 V TA = + 25˚C VCC = 2.5 V VCC = 2.7 V VCC = 3.0 V VCC = 3.3 V VCC = 3.5 V VCC = 4.0 V
VOL vs IOL (MB89498)
0.8 TA = + 25˚C 0.6 VCC = 2.5 V VCC = 2.7 V VCC = 3.0 V VCC = 3.3 V VCC = 3.5 V VCC = 4.0 V VCC = 2.0 V
0.8
0.6
VOL [V]
VOL [V]
0.4
0.4
0.2
0.2
0.0 0 2 4 6 8 10
0.0 0 2 4 6 8 10
IOL [mA] Other than port 0, port 4
IOL [mA] Other than port 0, port 4
(2) “H” level output voltage
VCC - VOH vs IOH (MB89498)
0.7 TA = + 25˚C 0.6 0.8 0.5 1.0
VCC − VOH vs IOH (MB89F499)
VCC = 2.0 V TA = + 25˚C
VCC = 2.0 V
VCC - VOH [V]
0.4 0.3 0.2
VCC = 2.5 V VCC = 2.7 V VCC = 3.0 V VCC = 3.3 V VCC = 3.5 V VCC = 4.0 V
VCC - VOH [V]
0.6
VCC = 2.5 V VCC = 2.7 V VCC = 3.0 V VCC = 3.3 V VCC = 3.5 V VCC = 4.0 V
0.4
0.2 0.1 0.0 0 −2 −4 −6 −8 −10 0.0 0 −2 −4 −6 −8 −10
IOH [mA]
Port 0
IOH [mA]
Port 0
(Continued)
47
MB89490 Series
(Continued)
VCC - VOH vs IOH (MB89498)
VCC = 2.0 V TA = + 25˚C 1.2 VCC = 2.5 V 1.0 1.0 VCC = 2.7 V 0.8 0.6 0.4 0.2 0.0 0 −2 −4 −6 −8 −10 VCC = 3.0 V VCC = 3.3 V VCC = 3.5 V VCC = 4.0 V 1.2 1.4
VCC - VOH vs IOH (MB89F499)
VCC = 2.0 V VCC = 2.5 V VCC = 2.7 V TA = + 25˚C VCC = 3.0 V VCC = 3.3 V VCC = 3.5 V VCC = 4.0 V
1.4
VCC - VOH [V]
VCC - VOH [V]
0.8 0.6 0.4 0.2 0.0 0 −2 −4 −6 −8 −10
IOH [mA]
Other than port 0
IOH [mA]
Other than port 0
(3) Power supply current (External clock)
ICC1 vs VCC (MB89498)
10.0 TA = + 25˚C 8.0 FCH = 10.0 MHz 8.0 FCH = 12.5 MHz 10.0 12.0
ICC1 vs VCC (MB89F499)
TA = + 25˚C FCH = 12.5 MHz
FCH = 10.0 MHz
ICC1 [mA]
FCH = 8.0 MHz
ICC1 [mA]
6.0
FCH = 8.0 MHz 6.0
4.0 FCH = 4.0 MHz 2.0 FCH = 2.0 MHz FCH = 1.0 MHz 0.0 1 2 3 4 5
4.0 FCH = 4.0 MHz 2.0 FCH = 2.0 MHz FCH = 1.0 MHz 0.0 1 2 3 4 5
VCC [V]
VCC [V]
(Continued)
48
MB89490 Series
ICCS1 vs VCC (MB89498)
4.5 4.0 3.5 3.0 FCH = 10.0 MHz TA = + 25˚C FCH = 12.5 MHz 3.5 3.0 2.5 2.0 1.5 4.0
ICCS1 vs VCC (MB89F499)
TA = + 25˚C
FCH = 12.5 MHz
FCH = 10.0 MHz
ICCS1 [mA]
ICCS1 [mA]
2.5 2.0 1.5
FCH = 8.0 MHz
FCH = 8.0 MHz
FCH = 4.0 MHz 1.0 FCH = 2.0 MHz 0.5 0.0 1 2 3 4 5 FCH = 1.0 MHz
FCH = 4.0 MHz 1.0 FCH = 2.0 MHz 0.5 FCH = 1.0 MHz 0.0 1 2 3 4 5
VCC [V]
VCC [V]
ICC2 vs VCC (MB89498)
1.4 TA = + 25˚C 1.2 1.0 0.8 0.6 FCH = 4.0 MHz 0.4 FCH = 2.0 MHz 0.2 0.0 1 2 3 4 5 FCH = 1.0 MHz 0.2 0.0 1 0.4 FCH = 12.5 MHz 1.2 1.0 1.4
ICC2 vs VCC (MB89F499)
TA = + 25˚C
FCH = 12.5 MHz
FCH = 10.0 MHz FCH = 8.0 MHz
FCH = 10.0 MHz FCH = 8.0 MHz
ICC2 [mA]
ICC2 [mA]
0.8 0.6
FCH = 4.0 MHz FCH = 2.0 MHz FCH = 1.0 MHz
2
3
4
5
VCC [V]
VCC [V]
(Continued)
49
MB89490 Series
ICCS2 vs VCC (MB89498)
1.0 TA = + 25˚C 0.8 FCH = 10.0 MHz FCH = 12.5 MHz 0.8 1.0
ICCS2 vs VCC (MB89F499)
TA = + 25˚C FCH = 12.5 MHz
FCH = 10.0 MHz
ICCS2 [mA]
0.6
FCH = 8.0 MHz
ICCS2 [mA]
0.6 FCH = 8.0 MHz
0.4 FCH = 4.0 MHz 0.2 FCH = 2.0 MHz FCH = 1.0 MHz
0.4 FCH = 4.0 MHz 0.2 FCH = 2.0 MHz FCH = 1.0 MHz 0.0
0.0 1 2 3 4 5
1
2
3
4
5
VCC [V]
VCC [V]
ICCLPLL vs VCC (MB89498)
0.30 TA = + 25˚C 0.25 FCH = 12.5 MHz FCH = 10.0 MHz 0.25 0.30
ICCLPLL vs VCC (MB89F499)
TA = + 25˚C FCH = 12.5 MHz FCH = 10.0 MHz FCH = 8.0 MHz 0.15 FCH = 4.0 MHz FCH = 2.0 MHz FCH = 1.0 MHz
ICCLPLL [mA]
0.20 FCH = 8.0 MHz FCH = 4.0 MHz 0.15 FCH = 2.0 MHz FCH = 1.0 MHz
0.10
ICCLPLL [mA]
0.20
0.10
0.05
0.05
0.00 1 2 3 4 5
0.00 1 2 3 4 5
VCC [V]
VCC [V]
(Continued)
50
MB89490 Series
ICCL vs VCC (MB89498)
60.0 TA = + 25˚C 50.0 FCL = 32.768 kHz 40.0 40.0 50.0 60.0
ICCL vs VCC (MB89F499)
TA = + 25˚C
FCL = 32.768 kHz
ICCL [µA]
ICCL [µA]
30.0
30.0
20.0
20.0
10.0
10.0
0.0 1 2 3 4 5
0.0 1 2 3 4 5
VCC [V]
VCC [V]
ICCLS vs VCC (MB89498)
20.0 TA = + 25˚C 16.0 FCL = 32.768 kHz 16.0 20.0
ICCLS vs VCC (MB89F499)
TA = + 25˚C
FCL = 32.768 kHz
ICCLS [µA]
ICCLS [µA]
12.0
12.0
8.0
8.0
4.0
4.0
0.0 1 2 3 4 5
0.0 1 2 3 4 5
VCC [V]
VCC [V]
(Continued)
51
MB89490 Series
(Continued)
ICCT vs VCC (MB89498)
2.0 TA = + 25˚C 1.6 FCL = 32.768 kHz 1.6 2.0
ICCT vs VCC (MB89F499)
TA = + 25˚C
FCL = 32.768 kHz
ICCT [µA]
0.8
ICCT [µA]
1 2 3 4 5
1.2
1.2
0.8
0.4
0.4
0.0
0.0 1 2 3 4 5
VCC [V]
VCC [V]
(4) Pull-up resistance
RPULL vs VCC (MB89498)
200 TA = + 25˚C 100 160 80 120
RPULL vs VCC (MB89F499)
TA = + 25˚C
RPULL [kΩ]
120
RPULL [kΩ]
60 TA = + 110 ˚C 40 TA = + 25 ˚C TA = - 40 ˚C
80
45
TA = + 110 ˚C TA = + 25 ˚C TA = - 40 ˚C
20
0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
0 2.0 2.5 3.0 3.5 4.0 4.5
VCC [V]
VCC [V]
52
MB89490 Series
s MASK OPTIONS
Part number Specifying procedure Main clock oscillation stabilizationtime selection 210/FCH 214/FCH 218/FCH MB89498 Specify when ordering mask MB89F499 MB89PV490
Setting not possible
Selectable
Fixed to oscillation stabilization wait time of 218/FCH
s ORDERING INFORMATION
Part number MB89498PF MB89F499PF MB89498PFV MB89F499PFV MB89PV490CF Package 100-pin Plastic QFP (FPT-100P-M06) 100-pin Plastic LQFP (FPT-100P-M05) 100-pin Ceramic MQFP (MQP-100C-P01) Remarks
53
MB89490 Series
s PACKAGE DIMENSIONS
100-pin Ceramic MQFP (MQP-100C-P01)
18.70(.736)TYP 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) 12.35(.486)TYP
+0.40 +.016 –.008
INDEX AREA
1.20 –0.20 .047
0.65±0.15 (.0256±.0060)
0.65±0.15 (.0256±.0060)
1.27±0.13 (.050±.005) 22.30±0.33 (.878±.013) 24.70(.972) TYP 0.30(.012) TYP 18.12±0.20 12.02(.473) (.713±.008) TYP 10.16(.400) 14.22(.560) TYP TYP
18.85(.742) TYP
1.27±0.13 (.050±.005)
0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP
0.30±0.08 (.012±.003)
0.30±0.08 (.012±.003)
1.20 –0.20 .047 –.008
+0.40 +.016
10.82(.426) 0.15±0.05 MAX (.006±.002)
C
1994 FUJITSU LIMITED M100001SC-1-2
Dimensions in mm (inches) . Note : The values in parentheses are reference values.
(Continued)
54
MB89490 Series
100-pin Plastic QFP (FPT-100P-M06)
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
51
81
50
0.10(.004) 17.90±0.40 (.705±.016)
*14.00±0.20 (.551±.008)
INDEX Details of "A" part
100 31
1
30
0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8˚ 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off)
0.65(.026)
0.32±0.05 (.013±.002)
0.13(.005)
M
"A"
C
2002 FUJITSU LIMITED F100008S-c-5-5
Dimensions in mm (inches) . Note : The values in parentheses are reference values.
(Continued)
55
MB89490 Series
(Continued)
100-pin Plastic LQFP (FPT-100P-M05)
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
75 51
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
76
50
0.08(.003) Details of "A" part
INDEX
1.50 –0.10 .059 –.004 (Mounting height)
26
+0.20
+.008
100
0.10±0.10 (.004±.004) (Stand off) 0.25(.010)
0˚~8˚ "A" 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006)
1
25
0.50(.020)
0.20±0.05 (.008±.002)
0.08(.003)
M
0.145±0.055 (.0057±.0022)
C
2003 FUJITSU LIMITED F100007S-c-4-6
Dimensions in mm (inches) . Note : The values in parentheses are reference values.
56
MB89490 Series
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0410 © 2004 FUJITSU LIMITED Printed in Japan
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