MB89P475-202P-SH

FUJITSU SEMICONDUCTOR DATA SHEET DS07-12552-1E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89470 Series MB89475/P475/PV470 s DESCRIPTION The MB89470 series has been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to a compact instruction set, the microcontroller contains a variety of peripheral functions such as 21bit time-base timer, watch prescaler, PWC timer, PWM timer, 8/16-bit timer/counter, external interrupt 1 (edge) , external interrupt 2 (level) , 10-bit A/D converter, UART/SIO, buzzer, watchdog timer reset. The MB89470 series is designed suitable for home appliance as well as in a wide range of applications for consumer product. * : F2MC stands for FUJITSU Flexible Microcontroller. s FEATURES • Package used QFP package, LQFP package and SH-DIP package for MB89P475, MB89475 MQFP package for MB89PV470 (Continued) s PACKAGES 48-pin Plastic SH-DIP 48-pin Plastic LQFP 48-pin Plastic QFP 48-pin Ceramic MQFP (DIP-48P-M01) (FPT-48P-M05) (FPT-48P-M13) (MQP-48C-P01) MB89470 Series (Continued) • High-speed operating capability at low voltage • Minimum execution time : 0.32 µs/12.5 MHz • F2MC-8L family CPU core Multiplication and division instructions 16-bit arithmetic operations Instruction set optimized for controllers Bit test and branch instructions Bit manipulation instructions, etc. • Six timers PWC timer (also usable as an interval timer) PWM timer 8/16-bit timer/counter × 2 21-bit timebase timer Watch prescaler • Buzzer 7 frequency types are selectable by software • External interrupts Edge detection (Selectable edge) : 4 channels Low-level interrupt (Wake-up function) : 5 channels • A/D converter (8 channels) 10-bit successive approximation type • UART/SIO Synchronous/asynchronous data transfer capable • Low-power consumption modes Stop mode (Oscillation stops to minimize the current consumption.) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.) Subclock mode (for dual clock product) Watch mode (for dual clock product) • Watch dog timer reset • I/O ports : Max 39 channels 2 MB89470 Series s PRODUCT LINEUP Part number Parameter Classification MB89475 Mass production products (mask ROM product) 16 K × 8-bit (internal ROM) MB89P475 OTP 16 K × 8-bit (internal PROM, can be written to by FLASH programmer) MB89PV470 Piggy-back 32 K × 8-bit (external ROM) 1 K × 8 bits : 136 : 8 bits : 1 to 3 bytes : 1, 8, 16 bits : 0.32 µs/12.5 MHz : 2.88 µs/12.5 MHz : 7 pins : 3 pins (1 pin in product with dual clock) : 29 pins : 39 pins ROM size RAM size 512 × 8 bits Number of instructions Instruction bit length Instruction length Data bit length Minimum execution time Minimum interrupt processing time Output-only ports (N-channel open drain) Input-only ports I/O ports (CMOS) Total CPU functions Ports 21-bit Time-base timer Watchdog timer Watch prescaler Interrupt period (0.82 ms, 3.3 ms, 26.2 ms, 419.4 ms) at 10 MHz Interrupt period (0.66 ms, 2.6 ms, 21.0 ms, 335.5 ms) at 12.5 MHz Reset period (209.7 ms to 419.4 ms) at 10 MHz Reset period (167.8 ms to 335.5 ms) at 12.5 MHz 17 bits Interrupt cycle : 31.25 ms, 0.25 ms, 0.5 s, 1.00 s, 2.00 s, 4.00 s/32.768 kHz for subclock 2 channels 8-bit one-shot timer operation (supports underflow output, operating clock period : 1, 4, 32 tinst*, external) 8-bit reload timer operation (supports square wave output, operating clock period : 1, 4, 32 tinst*, external) 8-bit pulse width measurement operation (supports continuous measurement, H width, L width, rising edge to rising edge, falling edge to falling edge measurement and both edge measurement) 8-bit reload timer operation (supports square wave output, operating clock period : 1, 4, 32 tinst*, external) 8-bit resolution PWM operation Can be operated either as a 2-channel 8-bit timer/counter (Timer 1 and Timer 2, each with its own independent operating clock cycle) , or as one 16-bit timer/counter In Timer 1 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capable Can be operated either as a 2-channel 8-bit timer/counter (Timer 3 and Timer 4, each with its own independent operating clock cycle) , or as one 16-bit timer/counter In Timer 3 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capable 4 independent channels (selectable edge, interrupt vector, request flag) 5 channels (low level interrupt) Pulse width count timer PWM timer 8/16-bit timer/ counter 1, 2 8/16-bit timer/ counter 3, 4 External interrupt (Continued) 3 MB89470 Series (Continued) Part number Parameter A/D converter MB89475 MB89P475 MB89PV470 10-bit resolution × 8 channels A/D conversion function (conversion time : 60 tinst*) Supports repeated activation by internal clock. Synchronous/asynchronous data transfer capable (Max baud rate : 78.125 Kbps at 10 MHz) (7 and 8 bits with parity bit ; 8 and 9 bits without parity bit) 7 frequency types (FCH/212, FCH/211, FCH/210, FCH/29, FCL/25, FCL/24, FCL/23) are selectable by software. Sleep mode, stop mode, subclock mode (dual clock product) and watch mode (dual clock product) CMOS 2.2 V to 5.5 V 3.5 V to 5.5 V 2.7 V to 5.5 V UART/SIO Buzzer output Standby mode Process Operating Voltage * : tinst is one instruction cycle (execution time) , which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock. s PACKAGE AND CORRESPONDING PRODUCTS Package Part number MB89475 O O O X MB89P475 O O O X MB89PV470 X X X O DIP-48P-M01 FPT-48P-M05 FPT-48P-M13 MQP-48C-P01 O : Available X : Not available s DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following point : • The stack area, etc., is set at the upper limit of the RAM. 2. Current Consumption • For the MB89PV470, add the current consumed by the EPROM mounted in the piggy-back socket. • When operating at low speed, the current consumed by the one-time PROM product is greater than that for the mask ROM product. However, the current consumption are roughly the same in sleep or stop mode. • For more information, see “s ELECTRICAL CHARACTERISTICS”. 3. Oscillation stabilization time after power-on reset • • • • For MB89PV470, there is no power-on stabilization time after power-on reset. For MB89P475, there is power-on stabilization time after power-on reset. For MB89475, the power-on stabilization time can be select. For more information, refer to “s MASK OPTIONS”. 4 MB89470 Series s PIN ASSIGNMENTS (TOP VIEW) VSS C*1 P40/X0A P41/X1A P17/TO2 P16/EC2 P15/TO1 P14/EC1 P13/INT13 P12/INT12 P11/INT11 P10/INT10 P07/AN7 P06/AN6 P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AVSS AVCC P54/INT24 P53/INT23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 X1 X0 MODE P42 RST P20/SCK1 P21/SO1 P22/SI1 P23/PWC P24/PWM P25/SI2 VCC P26/SO2 P27/SCK2 P30/BUZ*2 P31*2 P32*2 P33*2 P34*2 P35*2 P36*2 P50/INT20 P51/INT21 P52/INT22 (DIP-48P-M01) *1 : For pin no. 2, connect this pin to an external 0.1 µF capacitor to ground (for MB89P475 only) . For MB89PV470 and MB89475, this pin should be left unconnected. *2 : High current drive type (Continued) 5 MB89470 Series (TOP VIEW) P33*2 P32*2 P31*2 P30/BUZ*2 P27/SCK2 P26/SO2 VCC P25/SI2 P24/PWM P23/PWC P22/SI1 P21/SO1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P34*2 P35*2 P36*2 P50/INT20 P51/INT21 P52/INT22 P53/INT23 P54/INT24 AVCC AVSS P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 P10/INT10 P11/INT11 P12/INT12 P13/INT13 P14/EC1 P15/TO1 *1 : For pin no. 20, connect this pin to an external 0.1 µF capacitor to ground (for MB89P475 only) . For MB89PV470 and MB89475, this pin should be left unconnected. *2 : High current drive type P20/SCK1 RST P42 MODE X0 X1 VSS C *1 P40/X0A P41/X1A P17/TO2 P16/EC2 (FPT-48P-M05) (FPT-48P-M13) (Continued) 6 MB89470 Series (Continued) (TOP VIEW) P33*3 P32*3 P31*3 P30/BUZ*3 P27/SCK2 P26/SO2 VCC P25/SI2 P24/PWM P23/PWC P22/SI1 P21/SO1 1 2 3 4 5 6 7 8 9 10 11 12 *1 68 67 66 65 64 63 62 61 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P34*3 P35*3 P36*3 P50/INT20 P51/INT21 P52/INT22 P53/INT23 P54/INT24 AVCC AVSS P00/AN0 P01/AN1 69 70 71 72 73 74 75 76 77 78 79 80 49 50 51 52 60 59 58 57 56 55 54 53 P02/AN2 P03/AN3 P04/AN4 P05/AN5 P06/AN6 P07/AN7 P10/INT10 P11/INT11 P12/INT12 P13/INT13 P14/EC1 P15/TO1 *1 : Package upper-side pin assignment ( MB89PV470 only) Pin no. Pin name Pin no. Pin name Pin no. 49 50 51 52 53 54 55 56 Vpp A12 A7 A6 A5 A4 A3 N.C. 57 58 59 60 61 62 63 64 N.C. A2 A1 A0 O1 O2 O3 Vss 65 66 67 68 69 70 71 72 P20/SCK1 RST P42 MODE X0 X1 VSS C*2 P40/X0A P41/X1A P17/TO2 P16/EC2 13 14 15 16 17 18 19 20 21 22 23 24 (MQP-48C-P01) Pin name O4 O5 O6 O7 O8 CE A10 N.C. Pin no. 73 74 75 76 77 78 79 80 Pin name OE N.C. A11 A9 A8 A13 A14 Vcc N.C. : As connected internally, do not use. *2 : Pin no. 20 should be left unconnected. *3 : High current drive type 7 MB89470 Series s PIN DESCRIPTION Pin no. LQFP/QFP/ SDIP*1 MQFP*2 17 18 16 47 48 46 Pin name X0 X1 MODE A I/O circuit Function Connection pins for a crystal or other oscillator. An external clock can be connected to X0. In this case, leave X1 open. Input pins for setting the memory access mode. Connect directly to VSS. Reset I/O pin. The pin is a N-ch open-drain type with pull-up resistor and a hysteresis input. The pin outputs an “L” level when an internal reset request is present. Inputting an “L” level initializes internal circuits. General-purpose I/O port. The pins are shared with the analog inputs for the A/D converter. General-purpose I/O port. A hysteresis input for INT10 to INT13. The pin is shared with an external interrupt 1 input. General-purpose I/O port. A hysteresis input for EC1. The pin is shared with the 8/16 bit timer 1 input. General-purpose I/O port. The pin is shared with the output of 8/16-bit timer 1. General-purpose I/O port. A hysteresis input for EC2. The pin is shared with the 8/16 bit timer 2 input. General-purpose I/O port. The pin is shared with the output of 8/16-bit timer 2. General-purpose I/O port. A hysteresis input for SCK1. The pin is shared with the clock I/O of UART/SIO 1. General-purpose I/O port. The pin is shared with the serial data output of UART/SIO 1. General-purpose I/O port. A hysteresis input for SI1. The pin is shared with the serial data input of UART/SIO 1. General-purpose I/O port. A hysteresis input for PWC. This pin is shared with PWC input. General-purpose input port. This pin is shared with PWM output. General-purpose I/O port. A hysteresis input for SI2. The pin is shared with the serial data input of UART/SIO 2. B 14 44 RST C 38 to 31 20 to 13 P00/AN0 to P07/AN7 P10/INT10 to P13/INT13 P14/EC1 D 30 to 27 12 to 9 E 26 8 E 25 7 P15/TO1 F 24 6 P16/EC2 E 23 5 P17/TO2 F 13 43 P20/SCK1 E 12 42 P21/SO1 F 11 41 P22/SI1 E 10 40 P23/PWC E 9 39 P24/PWM F 8 38 P25/SI2 E (Continued) 8 MB89470 Series (Continued) Pin no. LQFP/QFP/ SDIP*1 MQFP*2 6 36 Pin name I/O circuit F Function General-purpose I/O port. The pin is shared with the serial data output of UART/SIO 2. General-purpose I/O port. A hysteresis input for SCK2. The pin is shared with the clock I/O of UART/SIO 2. N-channel open-drain output. The pin is shared with buzzer output. N-channel open-drain output. General-purpose input port. (single clock system) Connection pins for a crystal or other oscillator. (dual clock system) An external clock can be connected to X0A. In this case, leave X1A open. General-purpose input port. (single clock system) Connection pins for a crystal or other oscillator. (dual clock system) An external clock can be connected to X0A. In this case, leave X1A open. General-purpose input port. General-purpose I/O port. A hysteresis input for INT20 to INT24. The pin is shared with an external interrupt 2 input. Capacitor connection pin *3 Power supply pin (+5 V) . Power supply pin (GND) . A/D converter power supply pin. A/D converter power supply pin. Use at the same voltage level as VSS. P26/SO2 5 35 P27/SCK2 E 4 3 to 1, 48 to 46 34 33 to 28 P30/BUZ P31 to P36 G G H 21 3 P40/X0A A H 22 4 P41/X1A A H E      15 45 to 41 20 7 19 40 39 45 27 to 23 2 37 1 22 21 P42 P50/INT20 to P54/INT24 C VCC VSS AVCC AVSS *1 : DIP-48P-M01 *2 : FPT-48P-M05/FPT-48P-M13/MQP-48C-P01 *3 : When MB89475 or MB89PV470 is used, this pin will become a N.C. pin without internal connection. When MB89P475 is used, connect this pin to an external 0.1 µF capacitor to ground. 9 MB89470 Series • External EPROM Socket (MB89PV470 only) Pin no. Pin I/O name MQFP* 49 50 51 52 53 54 55 58 59 60 61 62 63 64 65 66 67 68 69 70 71 73 75 76 77 78 79 80 56 57 72 74 Vpp A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS O4 O5 O6 O7 O8 CE A10 OE A11 A9 A8 A13 A14 VCC O “H” level output pin Function O Address output pins. I O Data input pins. Power supply pin (GND) . I Data input pins. O O O Chip enable pin for the ROM. Outputs “H” in standby mode. Address output pin. Output enable pin for the ROM. Always outputs “L”. O Address output pins. O  Power supply pin for the EPROM. N.C. Internally connected pins. Always leave open. * : MQP-48C-P01 10 MB89470 Series s I/O CIRCUIT TYPE Type X1 (X1A) Nch Pch Circuit Remarks • Main and sub-clock circuits • Oscillation feedback resistance is approx. 500 kΩ for main clock circuit and 5 MΩ for sub-clock circuit. A X0 (X0A) Pch Nch Stop mode control signal B • Hysteresis input • The pull-down resistor is approx. 50 kΩ. (No pull-down resistor in MB89P475) • The pull-up resistance (P-channel) is approx. 50 kΩ. • Hysteresis input R Pch C Nch R Pch pull-up resistor register • CMOS output • CMOS input • Selectable pull-up resistor Approx. 50 kΩ D Nch ADIN R Pch pull-up resistor register • CMOS output • CMOS input • Selectable pull-up resistor Approx. 50 kΩ E Nch port resources (Continued) 11 MB89470 Series (Continued) Type Circuit pull-up resistor regsiter Pch Remarks • CMOS output • CMOS input • Selectable pull-up resistor Approx. 50 kΩ R F Nch R pull-up resistor register Pch • N-channel open-drain output • Selectable pull-up resistor Approx. 50 kΩ G Nch • CMOS input H port 12 MB89470 Series s HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in “s ELECTRICAL CHARACTERISTICS” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D Converter Connect to be AVCC = VCC and AVSS = VSS even if the A/D converter is not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 Hz to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode. 7. Note to noise in the External Reset Pin (RST) If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use causion so that the reset pulse less than the specifications will not be fed to the external reset pin (RST). 13 MB89470 Series s PROGRAMMING OTPROM IN MB89P475 WITH SERIAL PROGRAMMER 1. Programming the OTPROM with serial programmer • All OTP products can be programmed with serial programmer. 2. Programming the OTPROM • To program the OTPROM using FUJITSU MCU programmer MB91919-001. Inquiry : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65) -2810770 FAX (65) -2810220 3. Programming Adapter for OTPROM • To program the OTPROM using FUJITSU MCU programmer MB91919-001, use the programming adapter listed below. Package Compatible socket adapter DIP-48P-M01 FPT-48P-M05 FPT-48P-M13 MB91919-805+MB91919-800 MB91919-806+MB91919-800 MB91919-807+MB91919-800 Inquiry : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65) -2810770 FAX (65) -2810220 4. OTPROM Content Protection For product with OTPROM content protection feature (MB89P475-102, MB89P475-202) , OTPROM content can be read using serial programmer if the OTPROM content protection mechanism is not activated. One predefined area of the OTPROM (FFFCH) is assigned to be used for preventing the read access of OTPROM content. If the protection code “00H” is written in this address (FFFCH) , the OTPROM content cannot be read by any serial programmer. Note : The program written into the OTPROM cannot be verified once the OTPROM protection code is written (“00H” in FFFCH) . It is advised to write the OTPROM protection code at last. 5. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 14 MB89470 Series s PROGRAMMING OTPROM IN MB89P475 WITH PROGRAMMER 1. Programming OTPROM with parallel programmer • Only products without protection feature (i.e. MB89P475-101 and MB89P475-201) can be programmed with parallel programmer. Product with protection feature (i.e. MB89P475-102 and MB89P475-202) cannot be programmed with parallel programmer. 2. ROM Writer Adapters and Recommended ROM Writers • The following shows ROM writer adapters and recommended ROM writers. Ando Electric Co., Ltd. (Parallel programmer) Package Applicable adapter model DIP-48P-M01 FPT-48P-M05 FPT-48P-M13 ROM2-48SD-32DP-8LA ROM2-48LQF-32DP-8LA2 ROM2-48QF-32DP-8LA2 Recommended writer AF9708* AF9709* AF9723* * : For the version of the programmer, contact the Flash Support Group, Inc. Fujitsu Microelectronics Asia Pte Ltd. (Serial programmer) Package Applicable adapter model DIP-48P-M01 FPT-48P-M05 FPT-48P-M13 MB91919-601 MB91919-602 MB91919-603 MB91919-001 Recommended writer Inquiries : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65) -2810770 Sunhayato Corp. : TEL 81-(3)-3984-7791 FAX 81-(3)-3971-0535 E-mail : adapter@sunhayato.co.jp Flash Support Group, Inc : FAX 81-(53)-428-8377 E-mail : support@j-fsg.co.jp 3. Writing data to the OTPROM (1) Set the OTPROM writer for the CU50-OTP (device code : cdB6DC) . (2) Load the program data to the OTPROM writer. (3) Write data using the OTPROM writer. 4. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 15 MB89470 Series s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C256A-20TVM 2. Programming Socket Adapter To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer : Sunhayato Corp.) listed below. Package Adapter socket part number LCC-32 (Square) ROM-32LC-28DP-S Inquiry : Sunhayato Corp. : TEL 81-(3)-3984-7791 FAX 81-(3)-3971-0535 E-mail : adapter@sunhayato.co.jp 3. Memory Space Memory space in each mode is diagrammed below. Address 0000H Normal operating mode I/O Corresponding addresses on the EPROM programmer 0080H RAM 0880H 8000H Not available 0000H PROM 32 KB EPROM 32 KB FFFFH 7FFFH 4. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C256. (2) Load program data into the EPROM programmer at 0000H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer. 16 MB89470 Series s BLOCK DIAGRAM X0 X1 Oscillator Clock Controller CMOS I/O port 0 8 8 10-bit A/D converter 4 4 P10/INT10 to P13/INT13 P14/EC1 P15/TO1 P16/EC2 P17/TO2 P00/AN0 to P07/AN7 AVCC AVSS P40/X0A*3 P41/X1A*3 P42 Sub-clock Oscillator Watch Prescaler CMOS Input port 4 External interrupt 1 (Level) Internal data bus 8/16-bit Timer 1, 2 8/16-bit Timer 3, 4 CMOS I/O port 1 RST Reset circuit (Watchdog timer) 21-bit Time-base timer P50/INT20 to P54/INT24 5 5 External interrupt 2 (Level) CMOS I/O port 5 UART/SIO 1 8-bit PWC P20/SCK1 P21/SO1 P22/SI1 P23/PWC P24/PWM P25/SI2 P26/SO2 P27/SCK2 1 Kbyte RAM/512 Byte RAM 8-bit PWM UART/SIO 2 CMOS I/O port 2 F2MC-8L CPU 16 Kbyte ROM Other pins MODE, VCC, VSS, C*2 Buzzer 6 N-ch open-drain output port 3 P31*1 to P36*1 P30/BUZ*1 *1 : High Current Pins *2 : Unconnected pin for MB89PV470 and MB89475 *3 : P40, P41 pins for single-clock system and X01A, X1A pins for dual-clock system 17 MB89470 Series s CPU CORE 1. Memory Space The microcontrollers of the MB89470 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89470 series is structured as illustrated below. Memory Map MB89475 0000H I/O 0080H RAM 0100H Generalpurpose registers 0100H 0080H RAM Generalpurpose registers 0100H 0000H I/O 0080H RAM Generalpurpose registers MB89P475 0000H I/O MB89PV470 0200H 0280H 0200H 0280H 0200H 0480H Vacant Vacant Vacant 8000H C000H FFC0H FFFFH C000H FFC0H FFFFH External ROM (32 K) ROM ROM FFC0H FFFFH Vector table (reset, interrupt, vector call instruction) 18 MB89470 Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following registers are provided : Program counter (PC) : A 16-bit register for indicating instruction storage positions Accumulator (A) : A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator. When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX) : A 16-bit register for index modification Extra pointer (EP) : A 16-bit pointer for indicating a memory address Stack pointer (SP) : A 16-bit register for indicating a stack area Program status (PS) : A 16-bit register for storing a register pointer, a condition code 16 bits PC A T IX EP SP PS : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status Initial value FFFDH Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, 0 = 11 Other bits are undefined. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR) . (See the diagram below.) Structure of the Program Status Register 15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 3 N 2 Z 1 V 0 C Vacancy Vacancy Vacancy IL1, 0 RP CCR 19 MB89470 Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area RP "0" Generated addresses "0" "0" "0" "0" "0" "0" A9 "1" A8 R4 A7 R3 A6 R2 A5 R1 A4 R0 A3 Lower OP codes b2 A2 b1 A1 b0 A0 A15 A14 A13 A12 A11 A10 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag : I-flag : IL1, 0 : Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL0 0 1 0 1 Interrupt level 1 2 3 Low = no interrupt High-low High IL1 0 0 1 1 N-flag : Z-flag : V-flag : C-flag : Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Set when an arithmetic operation results in 0. Cleared otherwise. Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out vallue in the case of a shift instruction. 20 MB89470 Series The following general-purpose registers are provided : General-purpose registers : An 8-bit resister for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers. Up to a total of 32 banks can be used on the MB89470 series. The bank currently in use is indicated by the register bank pointer (RP) . Register Bank Configuration This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area 21 MB89470 Series s I/O MAP Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H, 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH to 1FH 20H 21H 22H 23H 24H 25H 26H SMC11 ADC1 ADC2 ADDH ADDL ADER T4CR T3CR T4DR T3DR T2CR T1CR T2DR T1DR DDR2 SYCC STBC WDTC TBTC WPCR PDR3 PDR4 RSFR BUZR PDR5 DDR5 Register name PDR0 DDR0 PDR1 DDR1 PDR2 Register Description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register Port 2 data register (Reserved) Port 2 data direction register System clock control register Standby control register Watchdog timer control register Timebase timer control register Watch prescaler control register Port 3 data register Port 4 data register Reset flag register Buzzer register Port 5 data register Port 5 data direction register (Reserved) Timer 4 control register Timer 3 control register Timer 4 data register Timer 3 data register Timer 2 control register Timer 1 control register Timer 2 data register Timer 1 data register (Reserved) A/D control register 1 A/D control register 2 A/D data register (Upper byte) A/D data register (Lower byte) A/D input enable register (Reserved) UART/SIO serial mode control register 11 R/W 00000000B R/W R/W R R R/W -00000X0B -0000001B ------XXB XXXXXXXXB 11111111B R/W R/W R/W R/W R/W R/W R/W R/W 000000X0B 000000X0B XXXXXXXXB XXXXXXXXB 000000X0B 000000X0B XXXXXXXXB XXXXXXXXB R/W R/W R/W W* R/W R/W R/W R R R/W R/W R/W 00000000B -XXMM-00B 0001XXXXB 0---XXXXB 00---000B 00--0000B -1111111B -----XXXB XXXX----B -----000B ---XXXXXB ---00000B Read/Write R/W W* R/W W* R/W Initial value XXXXXXXXB 00000000B XXXXXXXXB 00000000B 00000000B (Continued) 22 MB89470 Series (Continued) Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH to 6FH 70H 71H 72H 73H 74H 75H 76H to 7AH 7BH 7CH 7DH 7EH 7FH * : Bit manipulation instruction cannot be used. ILR1 ILR2 ILR3 ILR4 PURC5 PURC0 PURC1 PURC2 PURC3 CNTR COMR Register name SMC12 SSD1 SIDR1/SODR1 SRC1 SMC21 SMC22 SSD2 SIDR2/SODR2 SRC2 EIC1 EIC2 EIE2 EIF2 PCR1 PCR2 PLBR Register Description UART/SIO serial mode control register 12 UART/SIO serial status and data register 1 UART/SIO serial data register 1 UART/SIO serial rate control register 1 UART serial mode control register 21 UART serial mode control register 22 UART serial status and data register 2 UART serial data register 2 UART serial rate control register 2 External interrupt 1 control register 1 External interrupt 1 control register 2 External interrupt 2 enable register External interrupt 2 flag register PWC control register 1 PWC control register 2 PWC reload buffer register (Reserved) PWM timer control register PWM timer compare register (Reserved) Port 0 pull up resistor control register Port 1 pull up resistor control register Port 2 pull up resistor control register Port 3 pull up resistor control register (Reserved) Port 5 pull up resistor control register (Reserved) Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 (Reserved) Read/Write R/W R R/W * R/W R/W R/W R R/W * R/W R/W R/W R/W R/W R/W R/W R/W R/W W* R/W R/W R/W R/W R/W W* W* W* W* Initial value 00000000B 00001---B XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00001---B XXXXXXXXB XXXXXXXXB 00000000B 00000000B ---00000B -------0B 0-0--000B 00000000B XXXXXXXXB 0-00000000B XXXXXXXXB 11111111B 11111111B 11111111B -1111111B ---1111B 11111111B 11111111B 11111111B 11111111B 23 MB89470 Series • Read/write access symbols R/W : Readable and writable R : Read-only W : Write-only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. : Unused bit. M : The initial value of this bit is determined by mask option. 24 MB89470 Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Power supply voltage Input voltage Output voltage “L” level maximum output current Symbol VCC AVCC VI VO IOL Value Min VSS − 0.3 VSS − 0.3 VSS − 0.3   Max VSS + 6.0 VCC + 0.3 VCC + 0.3 15 Unit V V V mA Average value (operating current × operating rate) P00 to P07, P10 to P17, P20 to P27, P50 to P54, RST Average value (operating current × operating rate) P30 to P36 Remarks AVCC must not exceed VCC IOLAV1 “L” level average output current IOLAV2 “L” level total maximum output current “L” level total average output current “H” level maximum output current “H” level average output current “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature ΣIOL ΣIOLAV IOH IOHAV ΣIOH ΣIOHAV PD TA Tstg 4 mA         −40 −55 12 mA 100 40 −15 −2 −50 −20 300 +85 +150 mA mA mA mA mA mA mW °C °C Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 25 MB89470 Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Symbol Value Min 2.2* 3.5* 2.7* 1.5 Operating temperature TA −40 Max 5.5 5.5 5.5 5.5 +85 Unit V V V V °C Remarks Operation assurance range Operation assurance range Operation assurance range Retains the RAM state in stop mode MB89475 MB89P475 MB89PV470 Power supply voltage VCC AVCC * : These values depend on the operating conditions and the analog assurance range. See “Operating Voltage vs. Main Clock Operating Frequency” and “5. A/D Converter Electrical Characteristics.” 26 MB89470 Series Operating Voltage (V) 5.5 5.0 4.5 4.0 3.5 3.0 2.7 2.2 2.0 Analog accuracy assurance range : VCC = AVCC = 4.5 V to 5.5 V Main clock operating Freq. (MHz) 1.0 4.0 Note : 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 12.5 0.33 0.32 Min execution time (inst. cycle) (µs) 2.0 1.33 1.0 0.8 0.66 0.57 0.50 0.44 0.4 0.36 This area is not assured for MB89P475. This area is not assured for MB89PV470 and MB89P475. Operating Voltage vs. Main Clock Operating Frequency “Operating Voltage vs. Main Clock Operating Frequency” indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH. Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 27 MB89470 Series 3. DC Characteristics (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Pin Condition Value Min Typ Max Unit Remarks Parameter Symbol VIH “H” level input voltage VIHS P00 to P07, P10 to P17, P20 to P27, P40 to P42, P50 to P54 RST, MODE, EC1, EC2, SCK1, SI1, SCK2, SI2, PWC, INT10 to INT13, INT20 to INT24 P00 to P07, P10 to P17, P20 to P27, P40 to P42, P50 to P54 RST, MODE, EC1, EC2, SCK1, SI1, SCK2, SI2, PWC, INT10 to INT13, INT20 to INT24  0.7 VCC  VCC + 0.3 V  0.8 VCC  VCC + 0.3 V VIL “L” level input voltage VILS  VSS − 0.3  0.3 VCC V  VSS − 0.3  0.2 VCC V Open-drain output pin application voltage “H” level output voltage VD P30 to P36  VSS − 0.3  VCC + 0.3 V VOH P00 to P07, P10 to P17, P20 to P27, P50 to P54 P00 to P07, P10 to P17, P20 to P27, P50 to P54, RST P30 to P36 P00 to P07, P10 to P17, P20 to P27, P50 to P54 IOH = −2.0 mA 4.0   V “L” level output voltage VOL1 IOL = 4.0 mA IOL = 12.0 mA 0.45 V < VI < VCC   −5    0.4 V VOL2 Input leakage current Open drain output leakage current 0.4 +5 V µA Without pull-up resistor ILI ILOD P30 to P36 0.45 V < VI < VCC −5  +5 µA (Continued) 28 MB89470 Series (Continued) (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pull-down resistance RDOWN MODE P00 to P07, P10 to P17, P20 to P27, P30 to P36, P50 to P54, RST Pin Condition VI = VCC Value Min 25 Typ 50 Max 100 Unit kΩ Remarks Except MB89P475 When pull-up resistor is selected (except RST) Pull-up resistance RPULL VI = 0.0 V 25 50 100 kΩ ICC1 FCH = 12.5 MHz tinst = 0.32 µs Main clock run mode FCH = 12.5 MHz tinst = 5.12 µs Main clock run mode FCH = 12.5 MHz tinst = 0.32 µs Main clock sleep mode FCH = 12.5 MHz tinst = 5.12 µs Main clock sleep mode FCL = 32.768 kHz Subclock mode FCL = 32.768 kHz Subclock sleep mode FCL = 32.768 kHz Watch mode Main clock stop mode Ta = +25 °C Subclock stop mode AVcc Other than VCC, VSS, AVCC, AVSS FCH = 12.5 MHz Ta = +25 °C f = 1 MHz  7 13 mA ICC2  1 3 mA ICCS1  2.5 5 mA ICCS2 VCC Power supply current ICCL  0.7 2 mA    37 350 85 785 µA µA µA MB89PV470 MB89475 MB89P475 ICCLS 11 30   1.4 5.6 15 21 µA µA MB89PV470 MB89475 MB89P475 ICCT ICCH 1    10 µA mA µA pF 29 A/D converting A/D stop IA IAH Input capacitance CIN 2.8 1 5 6 5 15 MB89470 Series 4. AC Characteristics (1) Reset Timing (VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter RST “L” pulse width Symbol tZLZH Condition  Value Min 48 tHCYL Max  Unit ns Remarks Notes : • tHCYL is the oscillation cycle (1/FC) to input to the X0 pin. • If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST). tZLZH RST 0.2 VCC 0.2 VCC (2) Power-on Reset (AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Power supply rising time Power supply cut-off time Symbol tR tOFF Condition  Value Min  1 Max 50  Unit ms ms Due to repeated operations Remarks Note : Make sure that power supply rises within the selected oscillation stabilization time. Rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR 3.5 V tOFF VCC 0.2 V 0.2 V 0.2 V 30 MB89470 Series (3) Clock Timing (AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Clock frequency Clock cycle time Symbol FCH FCL tHCYL tLCYL PWH PWL PWHL PWLL tCR tCF Pin X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0, X0A Value Min 1  80  20   Typ  32.768  30.5  15.2  Max 12.5  1000    10 Unit MHz kHz ns µs ns µs ns External clock Remarks Input clock pulse width Input clock rising/falling time X0 and X1 Timing and Conditions tHCYL PWH tCR tCF PWL X0 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 0.2 VCC Main Clock Conditions When a crystal or ceramic oscillator is used When an external clock is used X0 X1 FCH X0 X1 Open FCH C1 C2 31 MB89470 Series Subclock Timing and Conditions tLCYL 0.8 VCC 0.2 VCC PWHL tCF PWLL tCR X0A Subclock Conditions When a crystal or ceramic oscillator is used When an external clock is used When sub-clock is not used in dual clock product X0 A FCL X1A Rd X0A X1A Open FCL X0A X1A Open C0 C1 (4) Instruction Cycle Parameter Instruction cycle (minimum execution time) Symbol Value 4/FCH, 8/FCH, 16/FCH, 64/FCH tinst 2/FCL µs Unit µs Remarks (4/FCH) tinst = 0.32 µs when operating at FCH = 12.5 MHz tinst = 61.036 µs when operating at FCL = 32.768 kHz 32 MB89470 Series (5) Serial I/O Timing (VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Serial clock cycle time SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX SCK1, SCK2 SCK1, SO1, SCK2, SO2, SI1, SCK1, SI2, SCK2 SCK1, SI1, SCK2, SI2 SCK1, SCK2 SCK1, SO1, SCK2, SO2 SI1, SCK1, SI2, SCK2 SCK1, SI1, SCK2, SI2 External shift clock mode Internal shift clock mode Pin Condition Value Min 2 tinst* −200 1/2 tinst* 1/2 tinst* 1 tinst* 1 tinst* 0 1/2 tinst* 1/2 tinst* Max  +200     200   Unit µs ns ns ns µs µs ns ns ns * : For information on tinst, see “ (4) Instruction Cycle.” Internal Clock Operation tSCYC 2.4 V SCK 0.8 V tSLOV 0.8 V SO 2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC SI 0.8 VCC 0.2 VCC External Clock Operation tSLSH tSHSL 0.8 VCC 0.8 VCC SCK 0.2 VCC 0.2 VCC tSLOV SO 2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC SI 0.8 VCC 0.2 VCC 33 MB89470 Series (6) Peripheral Input Timing (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Peripheral input “H” pulse width 1 Peripheral input “L” pulse width 1 Symbol tILIH1 tIHIL1 Pin INT10 to INT13, INT20 to INT24, EC1, EC2, PWC Value Min 2 tinst* 2 tinst* Max   Unit µs µs Remarks * : For information on tinst, see “ (4) Instruction Cycle.” t IHIL1 t ILIH1 INT10 to INT13, INT20 to INT24, EC1, EC2, PWC 0.8 VCC 0.2 VCC 0.2 VCC 0.8 VCC 34 MB89470 Series 5. A/D Converter Electrical Characteristics (1) A/D Converter Electrical Characteristics (AVCC = VCC = 4.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage A/D mode conversion time Analog port input current Analog input voltage VOT VFST  IAIN VAIN AN0 to AN7   Symbol Pin Value Min     AVSS − 1.5 LSB AVCC − 4.5 LSB   AVSS Typ 10    AVSS + 0.5 LSB AVCC − 2.5 LSB    Max  ±4.0 ±2.5 ±1.9 AVSS + 2.5 LSB AVCC − 0.5 LSB 60 tinst* 10 AVCC Unit bit LSB LSB LSB V V µs µA V Remarks * : For information on tinst, see “ (4) Instruction Cycle” in “4. AC Characteristics”. (2) A/D Converter Glossary • Resolution Analog changes that are identifiable with the A/D converter When the number of bits is 10, analog voltage can be divided into 210 = 1024. • Linearity error (unit : LSB) The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics. • Differential linearity error (unit : LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value. • Total error (unit : LSB) The difference between theoretical and actual conversion values. 35 MB89470 Series Theoretical I/O characteristics 3FF 3FE 3FD Digital output 1.5 LSB Digital output VFST 3FF 3FE 3FD Total error Actual conversion value {1 LSB × N + VOT} 004 003 002 001 0.5 LSB AVSS Analog input AVCC VOT 1 LSB 004 003 002 001 AVSS Analog input VNT Actual conversion value Theoretical value AVCC 1 LSB = VFST − VOT 1022 (V) Total error = VNT − {1 LSB × N + 0.5 LSB} 1 LSB Full-scale transition error Theoretical value Zero transition error 004 Actual conversion value 003 Digital output Digital output 3FE 3FF Actual conversion value VFST (Actual measurement) 3FD Actual conversion value VOT (Actual measurement) 3FC 002 Actual conversion value 001 AVSS Analog input Analog input AVCC (Continued) 36 MB89470 Series (Continued) Linearity error 3FF 3FE 3FD Digital output VFST (Actual measurement) Digital output N Actual conversion value {1 LSB × N + VOT} Differential linearity error Theoretical value N+1 Actual conversion value V (N + 1) T VNT 004 003 002 Actual conversion value Theoretical value N−1 VNT Actual conversion value 001 VOT (Actual measurement) AVSS Analog input AVCC N−2 AVSS AVCC Analog input Linearity error = VNT − {1 LSB × N + VOT} 1 LSB Differential linearity error = V (N + 1) T − VNT 1 LSB −1 37 MB89470 Series (3) Notes on Using A/D Converter • Input impedance of the analog input pins The A/D converter used for the MB89470 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for 16 instruction cycles after activation A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low. Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 µF for the analog input pin. Analog Input Circuit Model Analog input pin Comparator If the analog input impedance is higher than to 10 kΩ, it is recommended to connect an external capacitor of approx. 0.1 µF. R C Sample hold circuit Close for 16 instruction cycles after activating A/D conversion. Analog channel selector Sample hold circuit R : analog input equivalent resistance C : analog input equivalent capacitance MB89475 MB89PV470 2.2 kΩ 45 pF MB89P475 2.6 kΩ 28 pF 38 MB89470 Series s EXAMPLE CHARACTERISTICS • “L” level output voltage VOL1 − IOL (MB89475) 0.8 VOL2 − IO2 (MB89475) VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VCC = 6.0 V 0.4 VCC = 3.0 V Ta = + 25 °C 0.6 Ta = + 25 °C 0.3 VOL1 (V) VOL2 (V) 0.4 0.2 VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VCC = 6.0 V 0.2 0.1 0.0 0 2 4 6 8 10 0.0 0 2 4 6 8 10 12 14 16 IOL1 (mA) IOL2 (mA) • “H” level output voltage ( VCC − VOH ) − IOH (MB89475) 1.4 1.2 VCC = 3.5 V Ta = + 25 °C VCC = 3.0 V VCC − VOH (V) 1.0 0.8 0.6 0.4 0.2 0.0 0 −2 −4 −6 −8 VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VCC = 6.0 V −10 IOH (mA) • “H” level input voltage/“L” level input voltage CMOS Input (MB89475) 4.0 3.5 Ta = + 25 C 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1 2 3 4 5 6 7 4.0 CMOS hysteresis Input (MB89475) 3.5 Ta = + 25 C 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1 2 3 4 5 6 7 VIN (V) VIN (V) VIHS VILS VCC (V) VCC (V) VIHS : Threshold when input voltage in hysteresis characteristics is set to “H” level. VILS : Threshold when input voltage in hysteresis characteristics is set to “L” level. 39 MB89470 Series • Power supply current (External clock) ICC1 − VCC (MB89475) 10.0 1.4 ICC2 − VCC (MB89475) FCH = 12.5 MHz ICC1 (mA) Ta = + 25 °C 8.0 Ta = + 25 °C 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1 2 3 4 5 FCH = 12.5 MHz FCH = 10.0 MHz FCH = 8.0 MHz FCH = 4.0 MHz FCH = 2.0 MHz FCH = 1.0 MHz 6 7 ICC1 (mA) FCH = 10.0 MHz FCH = 8.0 MHz FCH = 4.0 MHz 6.0 4.0 2.0 0.0 1 2 3 4 5 FCH = 2.0 MHz FCH = 1.0 MHz 6 7 VCC (V) VCC (V) ICCS1 − VCC (MB89475) 3.5 3.0 ICCS2 − VCC (MB89475) 1.0 Ta = + 25 °C FCH = 12.5 MHz FCH = 10.0 MHz FCH = 8.0 MHz ICC2 (mA) 0.8 0.6 0.4 Ta = + 25 °C FCH = 12.5 MHz FCH = 10.0 MHz FCH = 8.0 MHz ICC1 (mA) 2.5 2.0 1.5 1.0 0.5 0.0 1 2 3 4 5 FCH = 4.0 MHz FCH = 2.0 MHz FCH = 1.0 MHz 6 7 FCH = 4.0 MHz 0.2 0.0 1 2 3 4 5 6 7 FCH = 2.0 MHz FCH = 1.0 MHz VCC (V) VCC (V) (Continued) 40 MB89470 Series (Continued) ICCL − VCC (MB89475) 60 50 ICCLS − VCC (MB89475) 16 14 12 Ta = + 25 °C FCH = 32.768 MHz ICCLS (µA) Ta = + 25 °C FCH = 32.768 MHz ICCL (µA) 40 30 20 10 0 1 2 3 4 5 6 7 10 8 6 4 2 0 1 2 3 4 5 6 7 VCC (V) VCC (V) ICCT − VCC (MB89475) 2.8 2.4 2.0 Ta = + 25 °C ICCT (µA) 1.6 1.2 0.8 0.4 0.0 1 2 3 FCH = 32.768 MHz 4 5 6 7 VCC (V) 41 MB89470 Series • Pull-up resistance RPULL − VCC (MB89475) 320 280 RPULL (kΩ) 240 200 160 120 80 40 0 1 2 3 4 5 6 7 Ta = + 25 °C VCC (V) 42 MB89470 Series s MASK OPTIONS Part number No. Specifying procedure Selection of clock mode • Single clock mode • Dual clock mode MB89475 Specify when ordering mask Selectable MB89P475 Setting not possible 101/102 : Single clock 201/202 : Dual clock MB89PV470 Setting not possible 101 : Single clock 201 : Dual clock 1 2 Selection of oscillation stabilization time (OSC) Selectable • The initial value of the oscillation OSC stabilization time for the main 1 : 214/FCH clock can be set by selecting the 2 : 217/FCH values of the WTM1 and WTM0 3 : 218/FCH bits on the right. Selection of power-on stabilization time • Nil • 217/FCH Fixed to oscillation stabilization time of 218/FCH Fixed to oscillation stabilization time of 218/FCH 3 Selectable Fixed to power-on stabilization time of Fixed to nil 217/FCH s ORDERING INFORMATION Part number MB89475PFM MB89P475-101PFM MB89P475-102PFM MB89P475-201PFM MB89P475-202PFM MB89475PFV MB89P475-101PFV MB89P475-102PFV MB89P475-201PFV MB89P475-202PFV MB89475P-SH MB89P475-101P-SH MB89P475-102P-SH MB89P475-201P-SH MB89P475-202P-SH MB89PV470-101CF MB89PV470-201CF Package Remarks 48-pin Plastic QFP (FPT-48P-M13) 101 : Single clock, without content protection 102 : Single clock, with content protection 201 : Dual clock, without content protection 202 : Dual clock, with content protection 48-pin Plastic LQFP (FPT-48P-M05) 48-pin Plastic SH-DIP (DIP-48P-M01) 48-pin Ceramic MQFP (MQP-48C-P01) 43 MB89470 Series s PACKAGE DIMENSIONS 48-pin Plastic SH-DIP (DIP-48P-M01) 43.69 –0.30 1.720 –.012 +0.20 +.008 INDEX-1 13.80±0.25 (.543±.010) INDEX-2 5.25(.207) MAX 3.00(.118) MIN +0.50 +.020 0.51(.020)MIN 0.25±0.05 (.010±.002) 1.00 –0 .039 –0 0.45±0.10 (.018±.004) 15.24(.600) TYP 15°MAX 1.778±0.18 (.070±.007) 1.778(.070) MAX 40.894(1.610)REF C 1994 FUJITSU LIMITED D48002S-3C-3 Dimensions in mm (inches) Note : The values in parentheses are reference values. (Continued) 44 MB89470 Series 48-pin Plastic LQFP (FPT-48P-M05) 9.00±0.20(.354±.008)SQ *7.00 –0.10 (.276 –.004 )SQ 36 25 +0.40 +.016 0.145±0.055 (.006±.002) 37 24 0.08(.003) INDEX Details of "A" part 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) 48 13 "A" 0˚~8˚ LEAD No. 0.50(.020) 1 12 0.10±0.10 (.004±.004) (Stand off) 0.20±0.05 (.008±.002) 0.08(.003) M 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) C 2002 FUJITSU LIMITED F48013S-c-5-9 Dimensions in mm (inches) Note : The values in parentheses are reference values. (Continued) 45 MB89470 Series 48-pin Plastic QFP (FPT-48P-M13) 13.10±0.40(.516±.016)SQ Note 1) *: These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. * 10.00±0.20(.394±.008)SQ 36 25 0.17±0.06 (.007±.002) 37 24 Details of "A" part 0.10(.004) 1.95 –0.20 .077 –.008 +0.40 +.016 (Mounting height) INDEX 0~8˚ 48 13 0.25(.010) 1 12 "A" 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.20 –0.20 +0.10 +.004 .008 –.008 (Stand off) 0.80(.031) 0.32±0.05 (.013±.002) 0.20(.008) M C 2003 FUJITSU LIMITED F48023S-c-3-4 Dimensions in mm (inches) Note : The values in parentheses are reference values. (Continued) 46 MB89470 Series (Continued) 48-pin Ceramic MQFP (MQP-48C-P01) 17.20(.677)TYP 15.00±0.25 (.591±.010) 14.82±0.35 (.583±.014) 1.50(.059)TYP 1.00(.040)TYP 8.80(.346)REF 0.80±0.22 (.0315±.0087) PIN No.1 INDEX PIN No.1 INDEX 1.02±0.13 (.040±.005) 10.92 –0.0 +.005 .430 –0 +0.13 7.14(.281) 8.71(.343) TYP TYP PAD No.1 INDEX 0.30(.012)TYP 4.50(.177)TYP 1.10 –0.25 +.018 .043 –.010 +0.45 0.40±0.08 (.016±.003) 0.60(.024)TYP 8.50(.335)MAX 0.15±0.05 (.006±.002) C 1994 FUJITSU LIMITED M48001SC-4-2 Dimensions in mm (inches) Note : The values in parentheses are reference values. 47 MB89470 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0303 © FUJITSU LIMITED Printed in Japan