FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12559-1E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89480/MB89480L Series
MB89485/485L/P485/P485L/PV480
s DESCRIPTION
The MB89480 series has been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit single-chip microcontrollers. In addition to a compact instruction set, the microcontroller contains a variety of peripheral functions such as 21bit timebase timer, watch prescaler, PWC timer, PWM timer, 8/16-bit timer/counter, 6-bit PPG, LCD controller/ driver, external interrupt 1 (edge), external interrupt 2 (level), 10-bit A/D converter, UART/SIO, buzzer, watchdog timer reset. The MB89480 series is designed suitable for LCD remote controller as well as in a wide range of applications for consumer product. *: F2MC stands for FUJITSU Flexible Microcontroller.
s FEATURES
• Package used LQFP package and SH-DIP package for MB89P485/P485L, MB89485/485L MDIP package and MQFP package for MB89PV480 • High speed operating capability at low voltage • Minimum execution time: 0.32 µs at 12.5 MHz
(Continued)
s PACKAGES
64-pin Plastic SH-DIP 64-pin Plastic LQFP 64-pin Ceramic MDIP 64-pin Ceramic MQFP
(DIP-64P-M01)
(FPT-64P-M09)
(MDP-64C-P02)
(MQP-64C-P01)
MB89480/480L Series
(Continued) • F2MC-8L family CPU core
Instruction set optimized for controllers Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc.
• Six timers PWC timer (also usable as an interval timer) PWM timer 8/16-bit timer/counter x 2 21-bit timebase timer Watch prescaler • Programmable pulse generator 6-bit PPG with program-selectable pulse width and period • External interrupt Edge detection (selectable edge) : 4 channels Low level interrupt (wake-up function) : 8 channels • A/D converter (4 channels) 10-bit successive approximation type • UART/SIO Synchronous/asynchronous data transfer capability • LCD controller/driver Max 31 segments output x 4 commons Booster for LCD driving (selected by mask option) • Buzzer 7 frequencies are selectable by software • Low-power consumption mode Stop mode (oscillation stops so as to minimize the current consumption.) Sleep mode (CPU stops so as to reduce the current consumption to approx. 1/3 of normal.) Watch mode (everything except the watch prescaler stops so as to reduce the power comsumption to an extremely low level.) Sub-clock mode • Watchdog timer reset • I/O ports: Max 42 channels
2
MB89480/480L Series
s PRODUCT LINEUP
Part number Parameter Classification ROM size RAM size MB89485L MB89485 MB89P485L MB89P485 MB89PV480 Piggy-back 32K x 8-bit (external ROM)*1 1K × 8-bit : 136 : 8 bits : 1 to 3 bytes : 1, 8, 16 bits : 0.32 µs at 12.5 MHz : 2.88 µs at 12.5 MHz : 11 pins : 28 pins : 2 pins : 1 pin : 42 pins
Mass production products (mask ROM product) 16K x 8-bit (internal ROM)
OTP 16K x 8-bit (internal PROM with read protection) *2
512 x 8-bit Number of instructions Instruction bit length Instruction length Data bit length Minimum execution time Minimum interrupt processing time I/O ports (CMOS) N-channel open drain I/O ports Output ports (N-channel open drain) Input port Total
CPU functions
Ports
21-bit timebase timer Watchdog timer
Interrupt period (0.66 ms, 2.6 ms, 21.0 ms, 335.5 ms) at 12.5 MHz. Reset period (167.8 ms to 335.5 ms) at 12.5 MHz. 1 channel. 8-bit one-shot timer operation (supports underflow output, operating clock period: 1, 4, 32 tinst, external). 8-bit reload timer operation (supports square wave output, operating clock period: 1, 4, 32 tinst, external). 8-bit pulse width measurement operation (supports continuous measurement, H width, L width, rising edge to rising edge, falling edge to falling edge measurement and both edge measurement). 8-bit reload timer operation (supports square wave output, operating clock period: 1, 4, 32 tinst, external). 8-bit resolution PWM operation. Can generate square pulse with programmable period.
Pulse width count timer
PWM timer 6- bit programmable pulse generator
Can be operated either as a 2-channel 8-bit timer/counter (timer 11 and timer 12, each with its 8/16-bit timer/counter own independent operating clock cycle), or as one 16-bit timer/counter. 11, 12 In timer 11 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capability. Can be operated either as a 2-channel 8-bit timer/counter (timer 21 and timer 22, each with its 8/16-bit timer/counter own independent operating clock cycle), or as one 16-bit timer/counter. 21, 22 In timer 21 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capability. External interrupt 4 independent channels (selectable edge, interrupt vector, request flag). 8 channels (low level interrupt).
(Continued)
3
MB89480/480L Series
(Continued)
Part number Parameter A/D converter MB89485L MB89485 MB89P485L MB89P485 MB89PV480
10-bit resolution × 4 channels. A/D conversion function (conversion time: 60 tinst ). Supports repeated activation by internal clock. Common output Segment output : 4 (Max) : 31 (Max) (selected resistor ladder) : 26 (Max) (selected booster) :4 : 31 × 4 bits : selected by mask option
LCD controller/driver
Bias power supply pins LCD display RAM size Dividing resistor/booster
UART/SIO Buzzer output Standby mode Process Operating voltage
Synchronous/asynchronous data transfer capability. (Max baud rate: 97.656 Kbps at 12.5 MHz). (7 and 8 bits with parity bit; 8 and 9 bits without parity bit). 7 frequencies are selectable by software. Sleep mode, stop mode, watch mode, sub-clock mode. CMOS 2.2 V to 3.6 V 2.2 V to 5.5 V 2.7 V to 3.6 V 3.5 V to 5.5 V 2.7 V to 5.5 V
*1 : Use MBM27C256A as the external ROM. *2 : Read protection feature is selected by part number, detail please refer to MASK OPTIONS. Note : 1 tinst = one instruction cycle (execution time) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock.
s PACKAGE AND CORRESPONDING PRODUCTS
Part number Package DIP-64P-M01 FPT-64P-M09 MDP-64C-P02 MQP-64C-P01 O : Availabe X : Not available MB89485/485L O O X X MB89P485/P485L O O X X MB89PV480 X X O O
4
MB89480/480L Series
s DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following point: • The stack area is set at the upper limit of the RAM.
2. Current Consumption
• For the MB89PV480, the current consumed by the EPROM mounted in the piggy-back socket is needed to be included. • When operating at low speed, the current consumed by the one-time PROM product is greater than that for the mask ROM product. However, the current consumption is roughly the same in sleep and stop mode. • For more information, see “s ELECTRICAL CHARACTERISTICS”.
3. Oscillation Stabilization Time after Power-on Reset
• • • • For MB89PV480, MB89P485L and MB89485L, there is no power-on stabilization time after power-on reset. For MB89P485, there is power-on stabilization time after power-on reset. For MB89485, the power-on stabilization time can be selected. For more information, please refer to “s MASK OPTION”.
5
MB89480/480L Series
s PIN ASSIGNMENT
(TOP VIEW)
COM0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 P40/SEG8 P41/SEG9 P42/SEG10 P43/SEG11 P44/SEG12 P45/SEG13 P46/SEG14 P47/SEG15 P50/SEG16 P51/SEG17 P52/SEG18 P53/SEG19 P54/SEG20 P55/SEG21 P56/SEG22 P57 P10/SEG23/INT10 P11/SEG24/INT11 P12/SEG25/INT12 P13/SEG26/INT13 X0A X1A C *2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
*3 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS 65 66 67 68 69 70 71 72 73 74 75 76 77 78 92 91 90 89 88 87 86 85 84 83 82 81 80 79 VCC A14 A13 A8 A9 A11 OE A10 CE O8 O7 O6 O5 O4
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Vcc COM1 P30/COM2 P31/COM3 V3 P27/V2/EC1 P26/V1/TO1 V0/SEG0 P25/C0/EC2 *1 P24/C1/TO2 *1 P23/SI P22/SO P21/SCK P20/PWM P00/INT20 P01/INT21 P02/INT22 P03/INT23 *1 P04/INT24 *1 P05/INT25/PWC P06/INT26/PPG P07/INT27/BUZ AVss AVcc P17/SEG30/AN3 *1 P16/SEG29/AN2 *1 P15/SEG28/AN1 *1 P14/SEG27/AN0 *1 RST MODE X1 X0
(DIP-64P-M01) (MDP-64C-P02)
*1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively. Segment output of P17/SEG30/AN3 - P14/SEG27/AN0 will be disabled. *2: For product other than MB89P485, pin 31 is NC pin. *3: Pin assignment on package top. Pin no. Pin symbol Pin no. Pin symbol Pin no. Pin symbol Pin no. Pin symbol
65 66 67 68 69 70 71 72
A15 A12 A7 A6 A5 A4 A3 A2
73 74 75 76 77 78 79 80
A1 A0 O1 O2 O3 VSS O4 O5
81 82 83 84 85 86 87 88
O6 O7 O8 CE A10 OE A11 A9
89 90 91 92
A8 A13 A14 Vcc
N.C.: As connected internally, do not use.
(Continued)
6
MB89480/480L Series
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM0 Vcc COM1 P30/COM2 P31/COM3 V3 P27/V2/EC1 P26/V1/TO1 V0/SEG0
P40/SEG8 P41/SEG9 P42/SEG10 P43/SEG11 P44/SEG12 P45/SEG13 P46/SEG14 P47/SEG15 P50/SEG16 P51/SEG17 P52/SEG18 P53/SEG19 P54/SEG20 P55/SEG21 P56/SEG22 P57
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P25/C0/EC2 *1 P24/C1/TO2 *1 P23/SI P22/SO P21/SCK P20/PWM P00/INT20 P01/INT21 P02/INT22 P03/INT23 *1 P04/INT24 *1 P05/INT25/PWC P06/INT26/PPG P07/INT27/BUZ AVss AVcc
*1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively. Segment output of P17/SEG30/AN3 - P14/SEG27/AN0 will be disabled. *2: For product other than MB89P485, pin 23 is NC pin.
P10/SEG23/INT10 P11/SEG24/INT11 P12/SEG25/INT12 P13/SEG26/INT13 X0A X1A *2 C Vss X0 X1 MODE RST *1 P14/SEG27/AN0 1 P15/SEG28/AN1 * *1 P16/SEG29/AN2 *1 P17/SEG30/AN3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
(FPT-64P-M09)
(Continued)
7
MB89480/480L Series
(Continued)
SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM0 Vcc COM1 P30/COM2 P31/COM3 V3 P27/V2/EC1 64 63 62 61 60 59 58 57 56 55 54 53 52 SEG7 P40/SEG8 P41/SEG9 P42/SEG10 P43/SEG11 P44/SEG12 P45/SEG13 P46/SEG14 P47/SEG15 P50/SEG16 P51/SEG17 P52/SEG18 P53/SEG19 P54/SEG20 P55/SEG21 P56/SEG22 P57 P10/SEG23/INT10 P11/SEG24/INT11
(TOP VIEW)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
85 86 87 88 89 90 91 92 93
77 76 75 74 73 72 71 70 69
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P26/V1/TO1 V0/SEG0 P25/C0/EC2 *1 P24/C1/TO2 *1 P23/SI P22/SO P21/SCK P20/PWM P00/INT20 P01/INT21 P02/INT22 P03/INT23 *1 P04/INT24 *1 P05/INT25/PWC P06/INT26/PPG P07/INT27/BUZ AVss AVcc P17/SEG30/AN3 *1
*1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively. Segment output of P17/SEG30/AN3 - P14/SEG27/AN0 will be disabled. *2: Pin 24 is NC pin. Pin assignment on package top Pin no. 65 66 67 68 69 70 71 72 Pin symbol N.C. VPP A12 A7 A6 A5 A4 A3 Pin no. 73 74 75 76 77 78 79 80 Pin Pin Pin no. symbol symbol A2 A1 A0 N.C. O1 O2 O3 VSS 81 82 83 84 85 86 87 88 N.C. O4 O5 O6 O7 O8 CE A10 Pin no. 89 90 91 92 93 94 95 96 Pin symbol OE N.C. A11 A9 A8 A13 A14 VCC
N.C.: As connected internally, do not use.
8
P12/SEG25/INT12 P13/SEG26/INT13 X0A X1A *2 C Vss X0 X1 MODE RST *1 P14/SEG27/AN0 *1 P15/SEG28/AN1 *1 P16/SEG29/AN2
20 21 22 23 24 25 26 27 28 29 30 31 32
(MQP-64C-P01)
94 95 96 65 66 67 68
84 83 82 81 80 79 78
MB89480/480L Series
s PIN DESCRIPTION
Pin number SH-DIP*1 MQFP*2 MDIP*4 33 34 29 30 35 26 27 22 23 28 QFP*3 25 26 21 22 27 Pin name X0 X1 X0A X1A MODE A A I/O circuit type Function Connection pins for a crystal or other oscillator. An external clock can be connected to X0. In this case, leave X1 open. Connection pins for a crystal or other oscillator. An external clock can be connected to X0A. In this case, leave X1A open. Input pin for setting the memory access mode. Connect directly to VSS. Reset I/O pin. The pin is an N-ch open-drain type with pullup resistor and a hysteresis input. The pin outputs an “L” level when an internal reset request is present. Inputting an “L” level initializes internal circuits. General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input. General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input, and shared with 8/16-bit timer/counter 21, 22 input when booster is selected. General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input, and shared with 8/16-bit timer/counter 21, 22 output when booster is selected. General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input, and PWC input. General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input, and 6-bit PPG output. General-purpose CMOS I/O port. A hysteresis input. The pin is shared with external interrupt 2 input and buzzer output. General-purpose N-ch open-drain I/O port. A hysteresis input. The pin is shared with external interrupt 1 input and LCD segment output.
B
36
29
28
RST
C
50 to 48 43 to 41 42 to 40
P00/INT20 to P02/INT22
D
47
40
39
P03/INT23
D
46
39
38
P04/INT24
D
45
38
37
P05/INT25/ PWC
D
44
37
36
P06/INT26/ PPG
D
43
36
35
P07/INT27/ BUZ
D
P10/SEG23/ 25 to 28 18 to 21 17 to 20 INT10 to P13/ SEG26/INT13
F/K
(Continued)
9
MB89480/480L Series
Pin number SH-DIP*1 MQFP*2 MDIP*4 QFP*3 Pin name
I/O circuit type
Function General-purpose N-ch open-drain I/O port. An analog input. The pin is shared with A/D converter input and LCD segment output. LCD segment output will be disabled when booster is selected. General-purpose CMOS I/O port. The pin is shared with PWM output. General-purpose CMOS I/O port. The pin is shared with UART/SIO clock I/O. General-purpose CMOS I/O port. The pin is shared with UART/SIO data output. General-purpose CMOS I/O port. The pin is shared with UART/SIO data input. General-purpose CMOS I/O port. The pin is shared with 8/16-bit timer 21, 22 output (it is redirected to P04/INT24 when booster is selected), and as a capacitor connecting pin when booster is selected. General-purpose CMOS I/O port. A hysteresis input. The pin is shared with 8/16-bit timer 21, 22 input (it is redirected to P03/INT23 when booster is selected), and as a capacitor connecting pin when booster is selected. General-purpose CMOS I/O port. The pin is shared with 8/16-bit timer 11, 12 output, and LCD power driving pin. General-purpose CMOS I/O port. A hysteresis input. The pin is shared with 8/16-bit timer 11, 12 input, and LCD power driving pin. General-purpose N-ch open-drain output port. The pin is shared with the LCD common output. General-purpose N-ch open-drain output port. The pin is shared with the LCD common output. General-purpose N-ch open-drain I/O port. The pin is shared with LCD segment output. General-purpose N-ch open-drain I/O port. The pin is shared with LCD segment output. General-purpose CMOS input port.
37 to 40 30 to 33 29 to 32
P14/SEG27/ AN0 to P17/ SEG30/AN3
G/K
51 52 53 54
44 45 46 47
43 44 45 46
P20/PWM P21/SCK P22/SO P23/SI
E E E D
55
48
47
P24/C1/TO2
H
56
49
48
P25/C0/EC2
F
58
51
50
P26/V1/TO1
H
59
52
51
P27/V2/EC1
F
62 61 9 to 16
55 54 2 to 9
54 53 1 to 8
P30/COM2 P31/COM3 P40/SEG8 to P47/SEG15 P50/SEG16 to P56/SEG22 P57
I/K I/K H/K H/K J
17 to 23 10 to 16 9 to 15 24 17 16
(Continued)
10
MB89480/480L Series
(Continued) Pin number
SH-DIP*1 MQFP*2 MDIP*4 2 to 8 1, 63 60 57 59 to 64, 1 58, 56 53 50 QFP*3 58 to 64 57, 55 52 49 Pin name SEG1 to SEG7 COM0 to COM1 V3 V0/SEG0
I/O circuit type K K — —/K
Function
LCD segment output-only pins. LCD common output-only pins. LCD driving power supply pin. LCD driving power supply pin when booster is selected. LCD segment output when booster is not selected. When MB89P485 is used, connect an external 0.1 µF capacitor between this pin and the ground. N.C. pin when MB89485/485L, MB89P485L or MB89PV480 is used. Power supply pin (+3 V or +5 V). Power supply pin (GND). A/D converter power supply pin. A/D converter power supply pin. Use at the same voltage level as VSS.
31
24
23
C
—
64 32 41 42
57 25 34 35
56 24 33 34
VCC VSS AVCC AVSS
— — — —
*1: DIP-64P-M01 *2: MQP-64C-P01 *3: FPT-64P-M09 *4: MDP-64C-P02
11
MB89480/480L Series
s External EPROM Socket (MB89PV480 only)
Pin number MDIP*1 91 90 66 87 85 88 89 67 68 69 70 71 72 73 74 83 82 81 80 79 77 76 75 65 76 81 90 65 78 84 86 92 MQFP*2 95 94 67 91 88 92 93 68 69 70 71 72 73 74 75 86 85 84 83 82 79 78 77 65 76 81 90 66 80 87 89 96 Pin name A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O8 O7 O6 O5 O4 O3 O2 O1 I/O Function
O
Address output pins.
I
Data input pins.
N.C.
—
Internally connected pins. Always leave open.
VPP VSS CE OE VCC
O O O O O
“H” level output pin. Power supply pin (GND). Chip enable pin for the EPROM. Outputs “H” in standby mode. Output enable pin for the EPROM. Always outputs “L”. Power supply pin for the EPROM.
*1: MDP-64C-P02 *2: MQP-64C-P01
12
MB89480/480L Series
s I/O CIRCUIT TYPE
Type
X1 (X1A) N-ch P-ch X0 (X0A) P-ch N-ch N-ch
Circuit
Remarks • Main/Sub-clock circuit • Oscillation feedback resistance is approx. 500 kΩ for main clock circuit and 5 MΩ for sub-clock circuit.
A
Stop mode control signal
B
R
• Hysteresis input • The pull-down resistor (not available in MB89P485/P485L) Approx. 50 kΩ • The pull-up resistor (P-channel) Approx. 50 kΩ • Hysteresis input
R P-ch
C
N-ch
R P-ch P-ch
pull-up resistor register
• • • •
D
N-ch
CMOS output CMOS input Hysteresis input Selectable pull-up resistor Approx. 50 kΩ
port resource
R P-ch P-ch
pull-up resistor register
• CMOS output • CMOS input • Selectable pull-up resistor Approx. 50 kΩ
E
N-ch
port
(Continued)
13
MB89480/480L Series
(Continued)
Type Circuit Remarks • N-ch open-drain output • CMOS input • Hysteresis input F
N-ch
port resources
• N-ch open-drain output • CMOS input • Analog input G
N-ch
port analog input
• N-ch open-drain output • CMOS input H
N-ch
port
• N-ch open-drain output I
N-ch
• CMOS input J
port
• LCD segment output
P-ch N-ch
K
P-ch N-ch
14
MB89480/480L Series
s HANDLING DEVICES
1. Preventing Latch-up
Latch-up may occur on CMOS IC if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in s ELECTRICAL CHARACTERISTICS is applied between VCC and VSS. When latch-up occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/DConverter
Connect to be AVCC = VCC and AVSS = VSS even if the A/D converter is not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up from stop mode.
7. Notes on noise in the External Reset Pin (RST)
If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST).
15
MB89480/480L Series
s PROGRAMMING OTPROM IN MB89P485/P485L WITH SERIAL PROGRAMMER
1. Programming the OTPROM with Serial Programmer
• All OTP products can be programmed with serial programmer.
2. Programming the OTPROM
• To program the OTPROM using FUJITSU MCU programmer MB91919-001. Inquiry : Fujitsu Microelectronics Asia Pte Ltd. :TEL (65)-2810770 FAX (65)-2810220
3. Programming Adapter for OTPROM
• To program the OTPROM using FUJITSU MCU programmer MB91919-001, use the programming adapter listed below. Package Compatible socket adapter DIP-64P-M01 FPT-64P-M09 MB91919-812 MB91919-813
Inquiry : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65)-2810770 FAX (65)-2810220
4. OTPROM Content Protection
For product with OTPROM content protection feature (MB89P485/P485L-103, MB89P485/P485L-104), OTPROM content can be read using serial programmer if the OTPROM content protection mechanism is not activated. One predefined area of the OTPROM (FFFCH) is assigned to be used for preventing the read access of OTPROM content. If the protection code "00H" is written in this address (FFFCH), the OTPROM content cannot be read by any serial programmer. Note: The program written into the OTPROM cannot be verified once the OTPROM protection code is written ("00H" in FFFCH). It is advised to write the OTPROM protection code at last.
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times.
16
MB89480/480L Series
s PROGRAMMING OTPROM IN MB89P485/P485L WITH PARALLEL PROGRAMMER
1. Programming OTPROM with Parallel Programmer
• Only products without protection feature (i.e. MB89P485/P485L-101 and MB89P485/P485L-102) can be programmed with parallel programmer. Product with protection feature (i.e. MB89P485/P485L-103 and MB89P485/P485L-104) cannot be programmed with parallel programmer.
2. ROM Writer Adapters and Recommended ROM Writers
• The following shows ROM writer adapters and recommended ROM writers. Ando Electric Co., Ltd. (Parallel programmer) Package name Applicable adapter model DIP-64P-M01 FPT-64P-M09 ROM2-64SD-32DP-8LA2 ROM2-64QF2-32DP-8LA3 Recommended writer AF9708* AF9709* AF9723*
* : For the programmer and the version of the programmer, contact the Flash Support Group, Inc. Fujitsu Microelectronics Asia Pte Ltd. (Serial programmer) Package name Applicable adapter model DIP-64P-M01 FPT-64P-M09 MB91919-604 MB91919-605 Recommended writer MB91919-001
Inquiries : Fujitsu Microelectronics Asia Pte Ltd. : TEL (65)-2810770 Sunhayato Corp. : TEL 81-(3)-3986-7791 : FAX 81-(3)-3971-0535 E-mail : adapter@sunhayato.co.jp Flash Support Group, Inc : FAX 81-(53)-428-8377 E-mail : support@j-fsg.co.jp
3. Writing Data to the OTPROM using Writer from Minato Electronics Co., Ltd.
(1) Set the OTPROM writer for the CU50-OTP (device code: cdB6DC). (2) Load the program data to the OTPROM writer. (3) Write data using the OTPROM writer.
4. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times.
17
MB89480/480L Series
s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20TVM
2. Programming Socket Adapter
To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package Adapter socket part number LCC-32 (Rectangle) Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3986-0403 ROM-32LC-28DP-S
3. Memory Space
Memory space in each mode is shown in the diagram below.
Address Normal operating mode 0000H I/O 0080H RAM 0480H Not available 8000H
Corresponding addresses on the EPROM programmer
0000H
PROM 32KB
EPROM 32KB
FFFFH
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256. (2) Load program data into the EPROM programmer at 0000H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer.
18
MB89480/480L Series
s BLOCK DIAGRAM
X0 X1
Main clock oscillator Clock controller
CMOS I/O port Buzzer output 6-bit PPG Port 0 8-bit PWC timer External interrupt 2 (level)
8 P07/INT27/BUZ
X0A X1A
Sub-clock oscillator Reset circuit (Watchdog timer) 21-bit timebase timer Watch prescaler CMOS I/O port *4 Internal data bus
P06/INT26/PPG
P05/INT25/PWC P04/INT24 *1 P03/INT23 *1 P02/INT22 to P00/INT20 AVcc AVss
RST
10-bit A/D converter
4
P20/PWM P21/SCK P22/SO P23/SI
8-bit PWM timer
N-ch open-drain I/O port
4
4
UART/SIO Port 2 *4 8/16-bit timer/counter 21,22 8/16-bit timer/counter 11,12
2 Booster 2
P14/SEG27/AN0 to P17/SEG30/AN3
*1 *1
P24/C1/TO2 *1 P25/C0/EC2 *1 P26/V1/TO1 P27/V2/EC1
Port 1
External interrupt 1 (edge)
4
P10/SEG23/INT10 to P13/SEG26/INT13
8
7 SEG1 to SEG7 2 COM0 to COM1
Port 3
2
LCD controller/driver
P30/COM2 P31/COM3
V3 V0/SEG0 *3
N-ch open-drain output port
RAM
32 × 4-bit display RAM (16 bytes)
16
Port 4 and Port 5 *4
P57 3 4 4 4 P56/SEG22 to P54/SEG20 P53/SEG19 to P50/SEG16 P47/SEG15 to P44/SEG12 P43/SEG11 to P40/SEG8
F2MC-8L CPU N-ch open-drain I/O port
ROM Other pins Vcc, Vss, MODE, C *2
*1: If booster is selected, EC2 and TO2 will be redirected to P03/INT23 and P04/INT24 respectively. Segment output of P14/SEG27/AN0 to P17/SEG30/AN3 will be disabled. *2: For product other than MB89P485, C pin is NC pin. *3: If booster is selected, it serves as V0. If booster is not selected, it serves as SEG0. *4: P20 to P23 are CMOS I/O ports. P24 to P27 are N-ch open-drain I/O ports. P57 is input-only port.
19
MB89480/480L Series
s CPU CORE
1. Memory Space
The microcontrollers of the MB89480 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89480 series is structured as illustrated below. Memory Space
MB89485/485L 0000H I/O 0080H RAM 0100H 0200H 0280H
Generalpurpose registers
MB89P485/P485L 0000H I/O 0080H RAM 0100H 0200H 0280H 0480H
Generalpurpose registers
MB89PV480 0000H I/O 0080H RAM 0100H 0200H
Generalpurpose registers
Vacant
Vacant
Vacant
8000H C000H FFC0H FFFFH
ROM
C000H FFC0H FFFFH
ROM
FFC0H FFFFH
External ROM (32KB)
Vector table (reset, interrupt, vector call instruction)
20
MB89480/480L Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following registers are provided: Program counter (PC) Accumulator (A) : A 16-bit register for indicating instruction storage positions. : A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T) : A 16-bit register for performing arithmetic operations with the accumulator. When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX) Extra pointer (EP) Stack pointer (SP) Program status (PS) : A 16-bit register for index modification. : A 16-bit pointer for indicating a memory address. : A 16-bit register for indicating a stack area. : A 16-bit register for storing a register pointer, a condition code.
16 bits PC A T IX EP SP PS : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status Initial value FFFDH Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, 0 = 11 Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 3 N 2 Z 1 V 0 C
Vacancy Vacancy Vacancy
IL1, 0
RP
CCR
21
MB89480/480L Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below.
Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP Lower OP codes b1 ↓ b0 ↓
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag I-flag IL1, 0 : Set to "1" when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Clear to "0" otherwise. This flag is for decimal adjustment instructions. : Interrupt is allowed when this flag is set to "1". Interrupt is prohibited when the flag is set to "0". Clear to "0" when reset. : Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL0 0 1 0 1 Interrupt level 1 2 3 Low = no interrupt Priority High
IL1 0 0 1 1
N-flag Z-flag V-flag C-flag
: Set to "1" if the MSB is set to "1" as the result of an arithmetic operation. Clear to "0" otherwise. : Set to "1" when an arithmetic operation results in "0". Clear to "0" otherwise. : Set to "1" if a signed numeric value overflows because of an arithmetic calculation. Clear to "0" if the overflow does not occur. : Set to "1" when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Clear to "0" otherwise. Set to the shift-out value in the case of a shift instruction.
22
MB89480/480L Series
The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers. Up to a total of 32 banks can be used on the MB89480 series. The bank currently in use is indicated by the register bank pointer (RP).
Register Bank Configuration
This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area
23
MB89480/480L Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H to 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H to 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H ADC1 ADC2 ADDH ADDL ADEN PCR1 PCR2 PLBR A/D control register 1 A/D control register 2 A/D data register (Upper byte) A/D data register (Lower byte) A/D input enable register PWC control register 1 PWC control register 2 PWC reload buffer register SMC1 SMC2 SRC SSD SIDR/SODR EIC1 EIC2 EIE2 EIF2 PDR5 Port 5 data register (Reserved) UART/SIO mode control register 1 UART/SIO mode control register 2 UART/SIO rate control register UART/SIO status/data register UART/SIO data register External interrupt 1 control register 1 External interrupt 1 control register 2 External interrupt 2 enable register External interrupt 2 flag register (Reserved) R/W R/W R R R/W R/W R/W R/W -0000000B -0000001B ------XXB XXXXXXXXB 1111----B 0-0--000B 00000000B XXXXXXXXB R/W R/W R/W R R/W R/W R/W R/W R/W 00000000B 00000000B XXXXXXXXB 00001---B XXXXXXXXB 00000000B 00000000B 00000000B -------0B PDR4 Port 4 data register (Reserved) R/W X1111111B RSFR Reset flag register (Reserved) R/W 11111111B DDR2 SYCC STBC WDTC TBTC WPCR PDR3 Register name PDR0 DDR0 PDR1 DDR1 PDR2 Register description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register Port 2 data register (Reserved) Port 2 data direction register System clock control register Standby control register Watchdog timer control register Timebase timer control register Watch prescaler control register Port 3 data register (Reserved) R XXXX----B R/W R/W R/W W* R/W R/W R/W 00000000B X-1MM100B 00010XXXB 0---XXXXB 00---000B 00--0000B ------11B Read/Write R/W W* R/W W* R/W Initial value XXXXXXXXB 00000000B XXXXXXXXB 00000000B 00000000B
(Continued)
24
MB89480/480L Series
(Continued) Address
34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H to 5DH 5EH 5FH 60H to 6FH 70H 71H 72H 73H to 7AH 7BH 7CH 7DH 7EH 7FH * : Bit manipulation instruction cannot be used. • Read/write access symbols R/W : Readable and writable R : Read-only W : Write-only • Initial value symbols 0 1 X M : The initial value of this bit is “0”. : The initial value of this bit is “1”. : The initial value of this bit is undefined. : Unused bit. : The initial value of this bit is determined by mask option. ILR1 ILR2 ILR3 ILR4 PURC2 LCR1 LCR2 VRAM PURC0
Register name CNTR COMR T22CR T21CR T22DR T21DR T12CR T11CR T12DR T11DR PPGC1 PPGC2 BUZR
Register description PWM timer control register PWM timer compare register Timer 22 control register Timer 21 control register Timer 22 data register Timer 21 data register Timer 12 control register Timer 11 control register Timer 12 data register Timer 11 data register PPG control register 1 PPG control register 2 Buzzer control register (Reserved) LCD controller control register 1 LCD controller control register 2 LCD data RAM Port 0 pull up resistor control register (Reserved) Port 2 pull up resistor control register (Reserved) Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 (Reserved)
Read/Write R/W W* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W* W* W* W*
Initial value 0-000000B XXXXXXXXB 000000X0B 000000X0B XXXXXXXXB XXXXXXXXB 000000X0B 000000X0B XXXXXXXXB XXXXXXXXB 00000000B 0-000000B -----000B 00010000B -0000000B XXXXXXXXB 11111111B ----1111B 11111111B 11111111B 11111111B 11111111B
25
MB89480/480L Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V) Parameter Symbol VCC AVCC VCC AVCC LCD power supply voltage Input voltage Output voltage Maximum clamp current Total maximum clamp current “L” level maximum output current “L” level average output current “L” level total maximum output current “L” level total average output current “H” level maximum output current “H” level average output current “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature V0 to V3 VI VO ICLAMP ∑ |ICLAMP| IOL IOLAV ∑IOL ∑IOLAV IOH IOHAV ∑IOH ∑IOHAV PD TA Tstg Value Min VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 – 2.0 –40 –55 Max VSS + 6.0 VSS + 4.0 VSS + 6.0 VCC + 0.3 VCC + 0.3 + 2.0 20 15 4 100 40 –15 –4 –50 –20 300 +85 +150 Unit Remarks MB89PV480, MB89P485, MB89485 AVCC must not exceed VCC MB89P485L, MB89485L AVCC must not exceed VCC P00 to P07, P10 to P17, P20 to P27, P40 to P47, P50 to P57 P00 to P07, P10 to P17, P20 to P27, P30 to P31, P40 to P47, P50 to P56 * * Average value (operating current × operating rate)
V V V V V mA mA mA mA mA mA mA mA mA mA mW °C °C
Power supply voltage
Average value (operating current × operating rate) Average value (operating current × operating rate)
Average value (operating current × operating rate)
Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. * : • Applicable to pins: P00 to P07, P20 to P23, AN0 to AN3 • Use within recommended operating conditions. • Use at DC voltage (current). • The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. 26
MB89480/480L Series
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the Vcc pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on result. • Care must be taken not to leave the +B input pin open. • Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannnot accept +B signal input. • Sample recommended circuits :
Input/Output Equivalent circuits Protective diode
VCC
Limiting resistance B input (0 V to 16 V)
P-ch
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V) Parameter Symbol Value Min 2.2* 3.5* 2.7* Power supply voltage VCC AVCC Max 5.5 5.5 5.5 Unit V V V Remarks Operation assurance range Operation assurance range Operation assurance range Retains the RAM state in stop mode Operation assurance range Retains the RAM state in stop mode MB89485 MB89P485 MB89PV480 MB89485, MB89P485, MB89PV480 MB89485L, MB89P485L
1.5
5.5
V
2.2* 1.5 LCD power supply voltage Operating temperature V0 to V3 TA Vss –40
3.6 3.6 Vcc +85
V V V °C
27
MB89480/480L Series
* : These values depend on the operating conditions and the analog assurance range. See Figure 1, 2, 3 and “5. A/D Converter Electrical Characteristics.”
Operating voltage (V)
5.5 5.0 4.5 Analog accuracy assurance range : Vcc = AVcc =4.5V~5.5V
4.0 3.5 3.0 2.7 2.2 2.0
Main clock operating freq. (MHz) 1.0 4.0 2.0 2.0 3.0 1.33 4.0 1.0 5.0 0.8 6.0 0.66 7.0 0.57 8.0 0.50 9.0 0.44 10.0 0.4 11.0 12.0 12.5 0.36 0.33 0.32 Min execution time (inst. cycle) (µs)
Note : The shaded area is not assured for MB89P485
Figure 1 Operating Voltage vs. Main Clock Operating Frequency (MB89P485/485)
Operating voltage (V) 3.6 3.0 2.7 2.2 2.0 Analog accuracy assurance range : Vcc = AVcc = 2.7V~3.6V
Main clock operating freq. (MHz) 1.0 4.0 2.0 2.0 3.0 1.33 4.0 1.0 5.0 0.8 6.0 0.66 7.0 0.57 8.0 0.50 9.0 0.44 10.0 0.4 11.0 12.0 12.5 0.36 0.33 0.32 Min execution time (inst. cycle) (µs)
Note : The shaded area is not assured for MB89P485L
Figure 2 Operating Voltage vs. Main Clock Operating Frequency (MB89P485L/485L)
28
MB89480/480L Series
Operating voltage (V)
5.5 5.0 4.5 Analog accuracy assurance range : Vcc = AVcc = 4.5V~5.5V
4.0 3.5 3.0 2.7
Main clock operating Freq. (MHz) 1.0 4.0 2.0 2.0 3.0 1.33 4.0 1.0 5.0 0.8 6.0 0.66 7.0 0.57 8.0 0.50 9.0 0.44 10.0 0.4 11.0 12.0 12.5 0.36 0.33 0.32 Min execution time (inst. cycle) (µs)
Figure 3 Operating Voltage vs. Main Clock Operating Frequency (MB89PV480) Figure 1, 2 and 3 indicate the operating frequency of the external oscillator at an instruction cycle of 4/FCH. Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
29
MB89480/480L Series
3. DC Characteristics
(AVCC = VCC = 5.0 V for MB89PV480, MB89P485, MB89485, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) AVCC = VCC = 3.0 V for MB89P485L, MB89485L, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Parameter Symbol Pin Condition Unit Remarks Min Typ Max P00 to P07, P10 to P17, P20 to P27, P40 to P47, P50 to P57 RST, MODE, EC1, EC2, PWC, SCK, SI, INT10 to INT13, INT20 to INT27 P00 to P07, P10 to P17, P20 to P27, P40 to P47, P50 to P57 RST, MODE, EC1, EC2, PWC, SCK, SI, INT10 to INT13, INT20 to INT27 P10 to P17, P24 to P27, P30 to P31, P40 to P47, P50 to P56
VIH “H” level input voltage VIHS
—
0.7 VCC
—
VCC + 0.3
V
—
0.8 VCC
—
VCC + 0.3
V
VIL “L” level input voltage VILS
—
VSS − 0.3
—
0.3 VCC
V
—
VSS − 0.3
—
0.2 VCC
V
Open-drain output pin application voltage
VCC + 0.3 — VSS − 0.3 — V3 V
Product without booster Product with booster MB89PV480, MB89P485, MB89485 MB89P485L, MB89485L
VD
“H” level output voltage
VOH
P00 to P07, P20 to P23
4.0 IOH = –2.0 mA 2.2
—
—
V
—
—
V
“L” level output voltage
P00 to P07, P10 to P17, P20 to P27, P30 to P31, P40 to P47, P50 to P56, RST VOL P00 to P07, P20 to P23, RST P10 to P17, P24 to P27, P30 to P31, P40 to P47, P50 to P56
— IOL = 4.0 mA
—
0.4
V
MB89PV480, MB89P485, MB89485
—
—
0.4
V
MB89P485L, MB89485L
IOL = 2.0 mA
—
—
0.4
V
MB89P485L, MB89485L
(Continued)
30
MB89480/480L Series
(Continued) (AVCC = VCC = 5.0 V for MB89PV480, MB89P485, MB89485, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) AVCC = VCC = 3.0 V for MB89P485L, MB89485L, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Parameter Symbol Pin Condition Unit Remarks Min Typ Max
Input leakage current P00 to P07, P10 to P17, P20 to P27, P40 to P47, P50 to P57 P10 to P17, P24 to P27, P30 to P31, P40 to P47, P50 to P56 MODE Without pull-up resistor
ILI
0.45 V < VI < VCC
−5
—
+5
µA
Open-drain output leakage current Pull-down resistance
ILOD
0.45 V < VI < VCC
−5
—
+5
µA
RDOWN
VI = VCC
25
50
100
kΩ
Except MB89P485, MB89P485L When pull-up resistor is selected (except RST) MB89485 MB89485L MB89P485 MB89P485L MB89485 MB89485L MB89P485 MB89P485L MB89485 MB89485L MB89P485 MB89P485L MB89485 MB89485L MB89P485 MB89P485L MB89485 MB89485L MB89P485 MB89P485L
Pull-up resistance
RPULL
P00 to P07, P20 to P23, RST
VI = 0.0 V
25
50
100
kΩ
ICC1
FCH = 10 MHz, tinst = 0.4 µs, Main clock run mode FCH = 10 MHz, tinst = 6.4 µs, Main clock run mode FCH = 10 MHz, tinst = 0.4 µs, Main clock sleep mode FCH = 10 MHz, tinst = 6.4 µs, Main clock sleep mode FCL = 32.768 kHz, TA = +250C, Sub-clock run mode
— — — — — — — — — — — — — — — — — — — —
6 3 5 4 0.9 0.4 0.9 0.5 2 1 2.5 1.2 0.7 0.3 0.9 0.4 40 22 400 25
13 7 10 8 3 1.5 3 2 5 2.5 5 2.5 2 1 2 1 85 50 800 50 µA mA mA mA mA
ICC2
Power supply current
ICCS1
VCC
ICCS2
ICCL
(Continued)
31
MB89480/480L Series
(AVCC = VCC = 5.0 V for MB89PV480, MB89P485, MB89485, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) AVCC = VCC = 3.0 V for MB89P485L, MB89485L, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Parameter Symbol Pin Condition Unit Remarks Min Typ Max — ICCLS FCL = 32.768 kHz, TA = +250C, Sub-clock sleep mode — — — — ICCT VCC TA = +25 C, Watch mode, Main clock stop mode
0
15 7 12 7 2 1 5 1 1 0.8 3 0.8 1.3 1 1.3 1 1 0.8 1 0.8
30 15 30 15 10 5 15 5 5 4 10 4 6 3 6 3 5 4 5 4 µA mA µA µA µA
MB89485 MB89485L MB89P485 MB89P485L MB89485 MB89485L MB89P485 MB89P485L MB89485 MB89485L MB89P485 MB89P485L MB89485 MB89485L MB89P485 MB89P485L MB89485 MB89485L MB89P485 MB89P485L MB89P485L, MB89485L
— — — —
Power supply current
ICCH
TA = +250C, Sub-clock stop mode
— — — — — — — — — — —
IA AVcc IAH
A/D conversion active
TA = +250C, A/D conversion stop
Common output impedance
V1 to V3 = +3.0 V RVCOM COM0 to COM3 — V1 to V3 = +5.0 V — 2.5 kΩ
MB89PV480, MB89P485, MB89485 MB89P485L, MB89485L
Segment output impedance LCD divided resistance
V1 to V3 = +3.0 V RVSEG SEG0 to SEG30 — V1 to V3 = +5.0 V — 15 kΩ
MB89PV480, MB89P485, MB89485
RLCD
—
Between VCC and VSS
300
500
750
kΩ
(Continued)
32
MB89480/480L Series
(Continued) (AVCC = VCC = 5.0 V for MB89PV480, MB89P485, MB89485, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) AVCC = VCC = 3.0 V for MB89P485L, MB89485L, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Parameter Symbol Pin Condition Unit Remarks Min Typ Max
LCD controller/ driver leakage current Booster for LCD driving output voltage Reference input voltage for LCD driving Reference voltage input impedance V0 to V3, COM0 to COM3, SEG0 to SEG30 V3 V2
ILCDL
—
—
—
±1
µA
VV3 VV2
V1 = 1.5 V V1 = 1.5 V
4.3 2.9
4.5 3.0
4.7 3.1
V V Products with booster only
VV1
V1
IIN = 0.0 µA
1.4
1.5
1.7
V
RRIN
V1 Other than VCC, VSS, AVCC, AVSS
—
8.5
9.8
11
kΩ
Input CIN capacitance
f = 1 MHz
—
5
15
pF
33
MB89480/480L Series
4. AC Characteristics
(1) Reset Timing (AVCC = VCC = 5.0 V for MB89PV480, MB89P485, MB89485, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) AVCC = VCC = 3.0 V for MB89P485L, MB89485L, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Symbol Condition Unit Remarks Parameter Min Max RST “L” pulse width tZLZH — 48 tHCYL — ns
Note : tHCYL is the oscillation cycle (1/FCH) to input to the X0 pin. The MCU operation is not guaranteed when the "L" pulse width is shorter than tZLZH.
tZLZH RST
0.2 VCC
0.2 VCC
(2) Power-on Reset Value Min — 1 Max 50 —
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol tR tOFF Condition — Unit ms ms Due to repeated operations Remarks
Parameter Power supply rising time Power supply cut-off time
Note : Make sure that power supply rises within the selected oscillation stabilization time. Rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR Vth 0.2 V
tOFF
VCC
0.2 V
0.2 V
Vth = 3.5 V for MB89PV480, MB89P485 and MB89485 Vth = 1.8 V for MB89P485L and MB89485L
34
MB89480/480L Series
(3) Clock Timing
Parameter Clock frequency Clock cycle time
Symbol FCH FCL tHCYL tLCYL PWH PWL PWHL PWLL tCR tCF
Pin X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0, X0A
Min 1 — 80 — 20 — —
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Unit Remarks Typ Max — 32.768 — 30.5 — 15.2 — 12.5 — 1000 — — — 10 MHz kHz ns µs ns µs ns External clock
Input clock pulse width
Input clock rising/falling time
X0 and X1 Timing and Conditions
tHCYL PWH tCR 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC tCF PWL
Main Clock Conditions
When a crystal or ceramic reasonator is used When an external clock is used
X0
X1 FCH C1 C2
X0
X1 Open
FCH
35
MB89480/480L Series
Sub-clock Timing and Conditions
tLCYL 0.8 VCC 0.2 VCC PWHL PWLL tCF tCR
X0A
Sub-clock Conditions
When a crystal or ceramic oscillator is used
When an external clock is used
When subclock is not used
X0A FCL
X1A Rd
X0A
X1A Open FCL
X0A
X1A
Open
C0
C1
(4) Instruction Cycle Parameter Instruction cycle (minimum execution time) Symbol Value 4/FCH, 8/FCH, 16/FCH, 64/FCH tinst 2/FCL µs Unit µs Remarks (4/FCH)tinst = 0.32 µs when operating at FCH = 12.5 MHz tinst = 61.036 µs when operating at FCL = 32.768 kHz
36
MB89480/480L Series
(5) Serial I/O Timing (AVCC = VCC = 5.0 V for MB89PV480, MB89P485, MB89485, AVCC = VCC = 3.0 V for MB89P485L, MB89485L AVSS = VSS= 0.0 V, TA = –40°C to +85°C) Value Symbol Pin Condition Unit Min Max tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX SCK SCK, SO SI, SCK SCK, SI SCK SCK, SO SI, SCK SCK, SI External shift clock mode Internal shift clock mode 2 tinst* –200 1/2 tinst* 1/2 tinst* 1 tinst* 1 tinst* 0 1/2 tinst* 1/2 tinst* — 200 — — — — 200 — — µs ns µs µs µs µs ns µs µs
Parameter Serial clock cycle time SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time
* : For information on tinst, see “(4) Instruction Cycle.”
37
MB89480/480L Series
Internal Clock Operation
tSCYC SCK 0.8 V tSLOV SO 2.4 V 0.8 V tIVSH SI 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC 2.4 V 0.8 V
External Clock Operation
tSLSH SCK 0.8 VCC 0.2 VCC tSLOV SO 2.4 V 0.8 V tIVSH SI 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC 0.2 VCC 0.8 VCC tSHSL
38
MB89480/480L Series
(6) Peripheral Input Timing (AVCC = VCC = 5.0 V for MB89PV480, MB89P485, MB89485 AVCC = VCC = 3.0 V for MB89P485L, MB89485L AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Pin Unit Remarks Min Max INT10 to INT13, INT20 to INT27, EC1, EC2, PWC 2 tinst* 2 tinst* — — µs µs
Parameter Peripheral input “H” pulse width 1 Peripheral input “L” pulse width 1
Symbol tILIH1 tIHIL1
* : For information on tinst, see “(4) Instruction Cycle.”
t IHIL1
t ILIH1
INT10 to 13, INT20 to INT27, EC1, EC2, PWC
0.8 VCC 0.2 VCC 0.2 VCC
0.8 VCC
39
MB89480/480L Series
5. A/D Converter Electrical Characteristics
(1) A/D Converter Electrical Characteristics ( AVCC = VCC = 4.5 V to 5.5 V for MB89PV480, MB89P485, MB89485, AVCC = VCC = 2.7 V to 3.6 V for MB89P485L, MB89485L, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Parameter Symbol Pin Unit Remarks Min Typ Max Resolution Total error Linearity error Differential linearity error — Zero transition voltage Full-scale transition voltage A/D mode conversion time Analog port input current Analog input voltage VOT VFST — IAIN VAIN AN0 to AN3 — — — — — AVSS – 1.5 LSB AVCC – 4.5 LSB — — AVSS 10 — — — AVSS + 0.5 LSB AVCC – 2.5 LSB — — — — ±4.0 ±2.5 ±1.9 AVSS + 2.5 LSB AVCC - 0.5 LSB 60 tinst* 10 AVCC bit LSB LSB LSB mV mV µs µA V
* : For information on tinst, see "(4) Instruction Cycle" in "4. AC Characteristics". (2) A/D Converter Glossary • Resolution Analog changes that are identifiable with the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. • Linearity error (unit: LSB) The deviation of the straight line connecting the zero transition point ("00 0000 0000" ↔ "00 0000 0001") with the full-scale transition point ("11 1111 1111" ↔ "11 1111 1110") from actual conversion characteristics. • Differential linearity error (unit: LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value. • Total error (unit: LSB) The difference between theoretical and actual conversion values.
40
MB89480/480L Series
Theoretical I/O characteristics 3FF 3FE 3FD 1.5 LSB VFST 3FF 3FE 3FD
Total error
Actual conversion value
{1 LSB × N + VOT}
Digital output
004 003 002 001 0.5 LSB AVSS Analog input AVCC
Digital output
004 003
VNT Actual conversion value Theoretical value
VOT 1 LSB
002 001 AVSS
AVCC Analog input
1 LSB =
VFST – VOT 1022
(V)
Total error = VNT – {1 LSB × N + 0.5 LSB} 1 LSB
Full-scale transition error
Zero transition error 004 Actual conversion value 003 3FF
Theoretical value
Actual conversion value
Digital output
Digital output
3FE VFST (Actual measurement) Actual conversion value 3FC AVCC
002 Actual conversion value 001
3FD
VOT (Actual measurement) AVSS Analog input
Analog input
Linearity error 3FF 3FE 3FD Actual conversion value {1 LSB × N + VOT} VFST (Actual measurement) N+1
Differential linearity error
Theoretical value
Actual conversion value
V(N + 1)T
Digital output
Digital output
N
VNT
004 003 002 001 AVSS Analog input Theoretical value
N–1 Actual conversion value
VNT Actual conversion value
N–2 AVCC Analog input
VOT (Actual measurement) AVCC AVSS
Linearity error =
VNT – {1 LSB × N + VOT} 1 LSB
Differential linearity error =
V(N + 1)T – VNT 1 LSB
–1
41
MB89480/480L Series
(3) Notes on Using A/D Converter • Input impedance of the analog input pins The A/D converter used for the MB89480 series contains a sample and hold circuit as illustrated below to fetch analog input voltage into the sample and hold capacitor for 16 instruction cycles after activation A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low. Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 µF for the analog input pin. Analog Input Circuit Model
Analog input pin If the analog input impedance is higher than 10 kΩ, it is recommended to connect an external capacitor of approx. 0.1 µF. Comparator R C Sample hold circuit
Close for 16 instruction cycles after activating A/D conversion. Analog channel selector
R: analog input equivalent resistance C: analog input equivalent capacitance
MB89485 MB89PV480 2.2 kΩ 45 pF
MB89485L 2.8 kΩ 46 pF
MB89P485 2.6 kΩ 28 pF
MB89P485L 7.1 kΩ 48.3 pF
42
MB89480/480L Series
s EXAMPLE CHARACTERISTICS
(1) "L" level output voltage
VOL [V]
0.8
VOL vs. IOL (MB89485)
VCC 3.0 V 3.5 V 4.0 V 4.5 V 5.0 V 5.5 V 6.0 V
1.2 1.0 0.8 0.6 0.4
VOL [V] TA
VOL vs. IOL (MB89485L)
VCC 25 C VCC 2.0 V VCC VCC VCC 3.0 V 3.5 V 4.0 V 2.5 V
TA
0.6
25 C VCC VCC VCC VCC VCC VCC
0.4
0.2 0.2
IOL [mA]
0.0 0 2 4 6 8 10
0.0 0 2 4 6 8
IOL [mA]
10
(2) "H" level output voltage
VCC-VOH vs. IOH (MB89485)
2.0
VCC-VOH vs. IOH (MB89485L)
VCC 3.5 V
2.0
VCC-VOH [V] TA 25 C
VCC
3.0 V
VCC-VOH [V] TA 25 C
VCC
2.0 V
VCC
2.5 V
1.6
1.6
VCC
1.2
4.0 V 4.5 V 5.0 V 5.5 V 6.0 V
1.2
VCC VCC VCC VCC
VCC VCC VCC
3.0 V 3.5 V 4.0 V
0.8
0.8
0.4
0.4
0.0 0 2 4 6 8
IOH [mA]
10
0.0 0 2 4 6 8
IOH [mA]
10
43
MB89480/480L Series
(3) "H" level input voltage/"L" level input voltage
CMOS input (MB89485)
VIN [V] 4.0 TA = +25 oC 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1 2 3 4 5 6 7 Vcc [V]
CMOS hysteresis input (MB89485)
VIN [V] 4.0 TA = +25oC 3.5 3.0 2.5 VILS 2.0 1.5 1.0 0.5 0.0 1 2 3 4 5 6 7 Vcc [V] VIHS
VIHS : Threshold when input voltage in hysteresis characteristics is set to “H” level. VILS : Threshold when input voltage in hysteresis characteristics is set to “L” level.
44
MB89480/480L Series
(4) Power supply current (External clock)
ICC1 vs. VCC (MB89485)
ICC1 [mA]
10.0
ICC2 vs. VCC (MB89485)
ICC2 [mA]
1.6
TA
8.0
25 C
FCH FCH FCH
12.5 MHz
1.4
TA
25 C
FCH FCH FCH
12.5 MHz 10.0 MHz 8.0 MHz
10.0 MHz 8.0 MHz
1.2 1.0 0.8
6.0
4.0
FCH
2.0
4.0 MHz 2.0 MHz 1.0 MHz
7
0.6 0.4
FCH FCH FCH
4.0 MHz 2.0 MHz 1.0 MHz
FCH FCH
0.2 0.0
0.0 1 2 3 4 5 6
1
2
3
4
5
6
7
VCC [V]
VCC [V]
ICCS1 vs. VCC (MB89485)
ICCS1 [mA]
3.5
ICCS2 vs. VCC (MB89485)
ICCS2 [mA]
1.2
TA
3.0
25 C
FCH
12.5 MHz
1.0
TA
25 C
FCH FCH
12.5 MHz 10.0 MHz 8.0 MHz
FCH
2.5
10.0 MHz 8.0 MHz
0.8
FCH
2.0
FCH
0.6 1.5
FCH FCH 4.0 MHz 2.0 MHz 1.0 MHz
0.4
4.0 MHz 2.0 MHz 1.0 MHz
1.0 0.5
FCH FCH
FCH FCH
0.2
0.0 1 2 3 4 5 6 7
0.0
VCC [V]
1
2
3
4
5
6
7
VCC [V]
(Continued)
45
MB89480/480L Series
(Continued)
ICC1 vs. VCC (MB89485L)
7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 1 2 3 4 5
ICC2 vs. VCC (MB89485L)
1.0
ICC1 [mA] TA 25 C FCH FCH FCH 12.5 MHz
ICC2 [mA] TA 25 C FCH 12.5 MHz 10.0 MHz 8.0 MHz
0.8
10.0 MHz 8.0 MHz
0.6
FCH FCH
0.4
FCH FCH FCH
4.0 MHz
0.2
FCH FCH FCH
4.0 MHz 2.0 MHz 1.0 MHz
2.0 MHz 1.0 MHz
0.0
VCC [V]
1
2
3
4
5
VCC [V]
ICCS1 vs. VCC (MB89485L)
ICCS1 [mA]
2.4 0.7
ICCS2 vs. VCC (MB89485L)
ICCS2 [mA] TA 25 C FCH FCH FCH 12.5 MHz 10.0 MHz 8.0 MHz
TA
2.0 1.6 1.2 0.8 0.4 0.0 1
25 C FCH FCH FCH 12.5 MHz 10.0 MHz 8.0 MHz
0.4 0.3 0.6 0.5
FCH FCH FCH FCH
2 3 4
4.0 MHz 2.0 MHz 1.0 MHz
4.0 MHz 2.0 MHz 1.0 MHz
5
0.2 0.1 0.0
FCH FCH
VCC [V]
1
2
3
4
5
VCC [V]
46
MB89480/480L Series
(Continued)
ICCL vs. VCC (MB89485)
ICCL [ A]
60 2.8
ICCT vs. VCC (MB89485)
ICCT [ A] TA
2.4
TA
50 40
25 C
FCL
32.768 kHz
25 C FCL 32.768 kHz
2.0 1.6 30 1.2 20 10 0 1 2 3 4 5 6 7 0.8 0.4 0.0 1 2 3 4 5 6 7
VCC [V]
VCC [V]
ICCLS vs. VCC (MB89485)
ICCLS [ A]
16
TA
14 12 10 8 6 4 2 0 1 2
25 C FCL 32.768 kHz
3
4
5
6
7
VCC [V]
47
MB89480/480L Series
(5) Pull-up resistance
RPULL vs. VCC (MB89485)
RPULL [k ]
320 280 160 240 200 160 120 80 40 0 1 2 3 4 5 6 7 80 200
RPULL vs. VCC (MB89485L)
RPULL [k ]
120
TA TA TA
85 C 25 C 40 C VCC [V]
40
TA TA TA
85 C 25 C 40 C
0 1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VCC [V]
48
MB89480/480L Series
s MASK OPTIONS
Part number No. Specifying procedure Booster selection (KSV) • Internal resistor ladder • Booster Selection of OTPROM content protection feature • No protection feature • With protection feature Selection of oscillation stabilization time (OSC) 214/FCH (approx.1.3 ms) 217/FCH (approx.10.5 ms) 218/FCH (approx.21.0 ms) Selection of power-on stabilization time • Nil • 217/FCH MB89485 MB89485L MB89P485 MB89P485L Setting not possible MB89PV480 Setting not possible Specify when ordering mask Selectable
1
101/103 : Internal resistor 101 : Internal resistor ladder ladder 102/104: Booster 102: Booster 101/102 : No protection 103/104 : With protection
2
—
—
3
Selectable OSC
218/FCH (approx.21.0 ms)
218/FCH (approx.21.0 ms)
4
Selectable
Fixed to nil
217/FCH
Fixed to nil
Fixed to nil
49
MB89480/480L Series
s ORDERING INFORMATION
Part number MB89485PFM MB89P485-101PFM MB89P485-102PFM MB89P485-103PFM MB89P485-104PFM MB89485LPFM MB89P485L-101PFM MB89P485L-102PFM MB89P485L-103PFM MB89P485L-104PFM MB89485P-SH MB89P485-101P-SH MB89P485-102P-SH MB89P485-103P-SH MB89P485-104P-SH MB89485LP-SH MB89P485L-101P-SH MB89P485L-102P-SH MB89P485L-103P-SH MB89P485L-104P-SH MB89PV480-101C-SH MB89PV480-102C-SH MB89PV480-101CF MB89PV480-102CF Package Remarks
64-pin Plastic QFP (FPT-64P-M09)
64-pin Plastic SH-DIP (DIP-64P-M01)
101: With internal resistor ladder, without content protection 102: With booster, without content protection 103: With internal resistor ladder, with content protection 104: With booster, with content protection
64-pin Ceramic MDIP (MDP-64C-P02) 64-pin Ceramic MQFP (MQP-64C-P01)
50
MB89480/480L Series
s PACKAGE DIMENSIONS
64-pin Plastic SH-DIP (DIP-64P-M01)
58.00 –0.55 2.283 –.022
+0.22 +.009
Note: Pins width and pins thickness include plating thickness.
INDEX-1 17.00±0.25 (.669±.010) INDEX-2
4.95 –0.20 .195 –.008
+0.70 +.028
0.70 –0.19 .028 –.007
+0.50 +.020
3.30 –0.30 .130 –.012
+0.20 +.008 +0.40 +.016 –.008
0.27±0.10 (.011±.004) 1.378 –0.20 .0543 1.778(.0700) 0.47±0.10 (.019±.004) 0.25(.010)
M
19.05(.750) 0~15
1.00 –0 .039
+0.50 +.020 –.0
C
2001 FUJITSU LIMITED D64001S-c-4-5
Dimensions in mm (inches) Note : The values in parenthese are reference values.
(Continued)
51
MB89480/480L Series
64-pin Plastic LQFP (FPT-64P-M09)
14.00±0.20(.551±.008)SQ
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar remainder.
* 12.00±0.10(.472±.004)SQ
48 33
0.145±0.055 (.0057±.0022)
49
32
0.10(.004) Details of "A" part 1.50 –0.10 .059 –.004
+0.20 +.008
(Mounting height)
0.25(.010) INDEX 0~8˚
64 17
1
16
"A"
0.65(.026)
0.32±0.05 (.013±.002)
0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006)
0.10±0.10 (.004±.004) (Stand off)
0.13(.005)
M
C
2003 FUJITSU LIMITED F64018S-c-3-5
Dimensions in mm (inches) Note : The values in parentheses are reference values.
(Continued)
52
MB89480/480L Series
64-pin Ceramic MDIP (MDP-64C-P02)
0˚~9˚
56.90±0.64 (2.240±.025)
15.24(.600) TYP
18.75±0.30 (.738±.012)
19.05±0.30 (.750±.012)
INDEX AREA
2.54±0.25 (.100±.010) 33.02(1.300)REF
0.25±0.05 (.010±.002)
10.16(.400)MAX
1.27±0.25 (.050±.010)
1.778±0.25 (.070±.010)
0.46 –0.08 +.005 .018 –.003 55.12(2.170)REF
+0.13
0.90±0.13 (.035±.005)
3.43±0.38 (.135±.015)
C
1994 FUJITSU LIMITED M64002SC-1-4
Dimensions in mm (inches) Note : The values in parentheses are reference values.
(Continued)
53
MB89480/480L Series
(Continued) 64-pin Ceramic MQFP (MQP-64C-P01)
18.70(.736)TYP 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) 12.00(.472)TYP
+0.40 +.016 –.008
INDEX AREA
1.20 –0.20 .047
1.00±0.25 (.039±.010)
1.00±0.25 (.039±.010)
1.27±0.13 (.050±.005) 22.30±0.33 (.878±.013) 24.70(.972) TYP 0.30(.012) TYP 18.12±0.20 12.02(.473) (.713±.008) TYP 10.16(.400) 14.22(.560) TYP TYP
18.00(.709) TYP
1.27±0.13 (.050±.005)
0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP
0.40±0.10 (.016±.004)
0.40±0.10 (.016±.004)
1.20 –0.20 .047 –.008
+0.40 +.016
0.50(.020)TYP
10.82(.426) 0.15±0.05 MAX (.006±.002)
C
1994 FUJITSU LIMITED M64004SC-1-3
Dimensions in mm (inches) Note : The values in parentheses are referent value.
54
MB89480/480L Series
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
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