MB89P568PFV-102

FUJITSU SEMICONDUCTOR DATA SHEET 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89560H Series MB89567H/567HC/P568/PV560 s DESCRIPTION The MB89560H series has been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to a compact instruction set, the microcontroller contains a variety of peripheral functions such as I2C interface, timers, 2 ch PWM timers, 8/16-bit timer, 21bit timebase timer, 8 bit PWC timer , 17-bit Watch prescaler, Watch-dog timer, High speed UART, 8-bit SIO, UART/SIO, LCD controller/driver (optional booster), Two type Programmable Pulse Generators (PPG), an A/D converter, and external interrupt. *: F2MC stands for FUJITSU Flexible Microcontroller. s FEATURES • • • • • • • • • F2MC-8L family CPU core Low-voltage operation (when an A/D converter is not used) Low current consumption (applicable to the dual-clock system) Minimum execution time: 0.32 µs at 12.5 MHz I2C interface circuit LCD controller/driver : 24 segments x 4 commons (max. 96 pixels, duty LCD mode and Static LCD mode) LCD booster function (option) Wild register (max. 6 different address locations) 10-bit A/D converter: 8 channels (Continued) s PACKAGE 80-pin Plastic LQFP 80-pin Plastic QFP 80-pin Plastic LQFP 80-pin Ceramic MQFP (FPT-80P-M05) (FPT-80P-M06) (FPT-80P-M11) (MQP-80C-P01) FPT-80P-M05 FPT-80P-M06 FPT-80P-M11 MQP-80C-P01 MB89560H Series (Continued) • Three types of Serial Interface: High Speed UART (Transfer rate from 300 to 192000 bps /10 MHz main clock) 8-bit Serial I/O (SIO) UART/SIO • Two type of Programmable Pulse Generator(PPG) : 6-bit PPG and 12-bit PPG • Six types of timer 8 bit PWM 2 channels timers 8/16 bit timer/counter (8 bits x 2 channels or 16 bits x 1 channel) 21bit timebase timer 8 bit PWC timer operation Watch prescaler(17 bits) Watch-dog timer • I/O ports: max. 50 channels • External interrupt 1: 8 channels • External interrupt 2 (wake-up function): 4 channels • Low-power consumption modes (stop mode, sleep mode, and watch mode) • LQFP-80 and QFP-80 package • CMOS technology s PRODUCT LINEUP Part number Parameter Classification ROM size RAM size CPU functions MB89567H MB89567HC MB89P568 OTP 48 K × 8 bits (internal PROM) MB89PV560 Piggy-back 56 K × 8 bits (external ROM) 1K × 8 bits Mass production products (mask ROM products) 32 K × 8 bits (internal mask ROM) 1K × 8 bits Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Minimum interrupt processing time: General-purpose I/O ports (N-channel open drain) General-purpose I/O ports (CMOS) Total : 136 : 8 bits : 1 to 3 bytes : 1, 8, 16 bits : 0.4 µs/10 MHz : 3.6 µs/10 MHz : 20 pins (2 shared with I2C inputs, 16 shared with LCD, 2 shared with other resources) : 30 pins (shared with resources) : 50 pins Ports 21-bit timebase timer Watchdog timer Watch prescaler 8/16-bit timer/ counter 8-bit PWM 2 ch timer 21 bits Interrupt cycle: 211, 213, 216 or 220 tinst *5 Reset generate cycle: min. 220 tinst for main clock, min. 213 tinst for sub clock 17 bits Interrupt cycle: 0.50s, 1.00s, 2.00s, 4.00s/32.768 KHz for subclock Can be operated either as a 2-channel 8-bit timer/counter (Timer 1 and Timer 2, each with its own independent operating clock cycle), or as one 16-bit timer/counter In Timer 1 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capable 8-bit interval timer operation (square wave output capable, operating clock cycle: 1, 8, 16, 64 tinst) 8-bit resolution PWM operation (conversion cycle: 256 to 256 x 64 tinst) 8/16-bit timer/counter output for counter clock selectability 2 MB89560H Series Part number Parameter MB89567H MB89567HC MB89P568 MB89PV560 PWC timer 8-bit timer operation (count clock cycle: 1, 4, 32 tinst) 8-bit reload timer operation (toggle output possible, operating clock cycle: 1 - 32 tinst) 8-bit pulse width measurement (continuous measurement possible: High and Low widths, H to H, L to L, period & H at same time and High & rising to rising) 10-bit resolution × 8 channels A/D conversion function (conversion time: 60 tinst) Continuous activation by an 8/16-bit timer/counter output or a timebase timer output capable. Internal 6-bit counter Pulse width and cycle are program selectable Internal 12-bit counter Pulse width and cycle are program selectable Not Available 1 channel Use a 2-wire protocol to communicate with other device 10-bit A/D converter*2 6 bit PPG 12 bit PPG I2C interface*4 High speed UART Transfer data length: 4, 6, 7, 8 bits Transfer rate (300 to 192000 bps /10 MHz main clock) support sub-clock mode Transfer data length: 7, 8 bits for UART, 8 bits for SIO Transfer rate (1201 to 78125 bps / 10 MHz main clock) support sub-clock mode 8 bits, LSB first/MSB first selectability One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 2, 8, 32 tinst) Common output: 4 (max.) Segment output: 24 (max.) LCD driving power (bias) pins: 4 LCD display RAM size: 12 bytes (24 × 4 bits, max. 96 pixels) Duty LCD mode and Static LCD mode Booster for LCD driving: option Dividing resister for LCD driving: Built-in*1 Maximum of 6-byte data can be assigned in 6 different address. Used to replace any data in the ROM when specific address and data are assigned in Wild register. Wild register can be set up by using different communication methods through the device. 8 independent channels (interrupt vector, request flag, request output enable) Edge selectability (rising/falling) Used also for wake-up from stop/sleep mode. (edge detection is also permitted in stop mode.) 4 channels (“L” level interrupts, independent input enable). Used also for wake-up from stop/sleep mode. (Low-level detection is also permitted in stop mode.) Sleep mode, stop mode and clock mode CMOS 3.5 V to 5.5 V 3.5 V to 5.5 V 2.7 to 5.5 V 2.7 to 5.5 V*3 UART/SIO 8-bit serial I/O LCD Wild register External interrupt 1 (wake-up function) External interrupt 2 (wake-up function) Standby mode Process Operating voltage* * :Varies with conditions such as the operating frequency. (See “s Electrical Characteristics.”) *1 : When booster is used, the bias is reduced by 1/3. it can be selected by mask option. *2 : When the A/D converter is used, operating voltage must be 3.5V to 5.5V. *3 : Use MBM27C512-20 as the external ROM (operating voltage: 4.5 V to 5.5 V) *4 : I2C is complied to Intel Corp. System Management Bus Rev. 1.0 specification and to the Philips I2C specification. *5 : 1 tinst = one instruction cycle (execution time) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock if main clock mode is selected , or 1/2 of the subclock if subclock mode is selected 3 MB89560H Series s PACKAGE AND CORRESPONDING PRODUCTS Package FPT-80P-M05 FPT-80P-M06 FPT-80P-M11 MQP-80C-P01 MB89567H MB89567HC MB89P568-101 MB89P568-102 MB89PV560-101 MB89PV560-102 s DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the OTPROM (one-time PROM) products, verify its differences from the product that will actually be used. Take particular care on the following points: • The stack area, etc., is set at the upper limit of the RAM. 2. Current Consumption • For the MB89PV560, add the current consumed by the EPROM mounted in the piggy-back socket. • When operating at low speed, the current consumed by the one-time PROM product is greater than for the mask ROM product. However, the current consumption is roughly the same in sleep or stop mode. • (For more information, see “s Electrical Characteristics.”) 3. Mask Options The functions available as options and the method of specifying options differ between products. Before using options check “s Mask Options.” 4. Functionalities different between products in MB89560H series Functionalities MB89567H MB89567HC MB89P568 MB89PV560 Power-on reset wait time Wait time for external reset in stop/sub/clock mode or wait time for external interrupt trigger recover from main stop mode Port pin pullup resistors AD conversion time I2C noise cancelling circuit Regulator stab. time + Regulator recovery. time + Osc. stab. time Regulator stab. time + Osc. stab. time Osc. stab. time Regulator recovery time + Osc. stab. time Osc. stab. time Selectable by software. 60 tINST * — Always available independent of ICCR:DMBP bit selection. Not available. 33 tINST * Not available when ICCR:DMBP bit is asserted. Note: For more information on tINST see “s Electrical Characteristics (4) Instruction cycles" * : Instruction cycle 4 MB89560H Series s PIN ASSIGNMENT (Top view) SEG07 P50/SEG08 P51/SEG09 P52/SEG10 P53/SEG11 P54/SEG12 P55/SEG13 P56/SEG14 P57/SEG15 P60/SEG16 P61/SEG17 P62/SEG18 Vss P63/SEG19 P64/SEG20 P65/SEG21 P64/SEG22 P67/SEG23 AVR AVcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 SEG00 COM3 COM2 COM1 COM0 V3 V2 V1 V0 C0 C1 P47/PWC P46/UI/SI1 P45/UO/SO1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P44/UCK/SCK1 P43/PWM2/PPG2 P42/PWM1/EC1 P41/HCK/TO12 P40/WTO/TO11 P31/SDA P30/SCL Vcc P27/INT23 P26/INT22 P25/INT21 P24/INT20 P23/PPG1 P22/SCK P21/SO P20/SI X1 X0 MODA X1A P07/AN7 P06/AN6 P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AVss P17/INT17 P16/INT16 P15/INT15 P14/INT14 P13/INT13 P12/INT12 P11/INT11 C P10/INT10 RST X0A (FPT-80P-M05) (FPT-80P-M11) 5 MB89560H Series (Top view) SEG04 SEG03 SEG02 SEG01 SEG00 COM3 COM2 COM1 COM0 V3 V2 V1 V0 C0 C1 P47/PWC SEG05 SEG06 SEG07 P50/SEG08 P51/SEG09 P52/SEG10 P53/SEG11 P54/SEG12 P55/SEG13 P56/SEG14 P57/SEG15 P60/SEG16 P61/SEG17 P62/SEG18 Vss P63/SEG19 P64/SEG20 P65/SEG21 P66/SEG22 P67/SEG23 AVR AVcc P07/AN7 P06/AN6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P46/UI/SI1 P45/UO/SO1 P44/UCK/SCK1 P43/PWM/PPG2 P42/PWM1/EC1 P41/HCK/TO12 P40/WTO/TO11 P31/SDA P30/SCL Vcc P27/INT23 P26/INT22 P25/INT21 P24/INT20 P23/PPG1 P22/SCK P21/SO P20/SI X1 X0 MODA X1A X0A RST 6 P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AVss P17/INT17 P16/INT16 P15/INT15 P14/INT14 P13/INT13 P12/INT12 P11/INT11 C P10/INT10 FPT-80P-M06 MB89560H Series (Top view) SEG04 SEG03 SEG02 SEG01 SEG00 COM3 COM2 COM1 COM0 V3 V2 V1 V0 C0 C1 P47/PWC SEG05 SEG06 SEG07 P50/SEG08 P51/SEG09 P52/SEG10 P53/SEG11 P54/SEG12 P55/SEG13 P56/SEG14 P57/SEG15 P60/SEG16 P61/SEG17 P62/SEG18 Vss P63/SEG19 P64/SEG20 P65/SEG21 P66/SEG22 P67/SEG23 AVR AVcc P07/AN7 P06/AN6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 *1 101 102 103 104 105 106 107 108 109 93 92 91 90 89 88 87 86 85 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P46/UI/SI1 P45/UO/SO1 P44/UCK/SCK1 P43/PWM/PPG2 P42/PWM1/EC1 P41/HCK/TO12 P40/WTO/TO11 P31/SDA P30/SCL Vcc P27/INT23 P26/INT22 P25/INT21 P24/INT20 P23/PPG1 P22/SCK P21/SO P20/SI X1 X0 MODA X1A X0A RST *1 :Pin assignment on package top (MB89PV560 only) Pin no. 81 82 83 84 85 86 87 88 Pin name N.C. A15 A12 AD7 AD6 AD5 AD4 AD3 Pin no. 89 90 91 92 93 94 95 96 P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AVss P17/INT17 P16/INT16 P15/INT15 P14/INT14 P13/INT13 P12/INT12 P11/INT11 C P10/INT10 (MQP-80C-P01) Pin name AD2 AD1 AD0 N.C. O1 O2 O3 VSS 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin no. 97 98 99 100 101 102 103 104 110 111 112 81 82 83 84 100 99 98 97 96 95 94 Pin name N.C. 04 O5 O6 07 O8 CE A10 Pin no. 105 106 107 108 109 110 111 112 Pin name OE N.C. A11 A9 A8 A13 A14 VCC N.C.: Internally connected. Do not use. 7 MB89560H Series s PIN DESCRIPTION Pin no. LQFP*1 LQFP*2 43 44 MQFP*3 QFP*4 45 46 Pin name I/O circuit type Function X0 A X1 Crystal or other resonator connector pins for the main clock. The external clock can be connected to X0. When this is done, be sure to leave X1 open. CR oscillation selectability in model with a mask ROM only. Memory access mode setting pins. Connect directly to VSS. Hysteresis input type. Reset I/O pin This pin is a CMOS output type with a pull-up resistor, and a hysteresis input type. “L” is output from this pin by an internal reset request (optional). The internal circuit is initialized by the input of “L”. General-purpose CMOS I/O ports Also serve as an external interrupt 2 input (wake-up function). External interrupt 2 input is hysteresis input. Selectable pull-up resistor. General-purpose CMOS I/O ports Also serve as input for external interrupt 1 input. External interrupt 1 input is hysteresis input. Selectable pull-up resistor. General-purpose CMOS I/O ports Also serve as the clock I/O for the High-speed UART and Serial IO. The peripheral is a hysteresis input type. Selectable pull-up resistor. General-purpose CMOS I/O ports Also serves as the data output for the High-speed UART and Serial I/O. The peripheral is a hysteresis input type. Selectable pull-up resistor. N-ch open drain general-purpose I/O ports Also serves as the data input for the High-speed UART and Serial I/O. The peripheral is a hysteresis input type. N-ch open drain general-purpose I/O port Also serve as the external clock input for PWC. The peripheral is a hysteresis input. General-purpose CMOS I/O port Also serves as an 8/16-bit timer/counter output and PWC output. 42 44 MODA C 39 41 RST D 49 to 52 51 to 54 P24/INT20 to P27/INT23 E 30 to 36 ,38 32 to 38,40 P10/INT10 to P17/INT17 E 60 62 P44/UCK/ SCK1 E 61 63 P45/UO/SO1 F 62 64 P46/UI/SI1 G 63 65 P47/PWC G 56 58 P40/WTO/ TO11 F (Continued) *1: FPT-80P-M05 *2: FPT-80P-M11 *3: MQP-80C-P01 *4: FPT-80P-M06 8 MB89560H Series (Continued) Pin no. LQFP*1 LQFP*2 57 MQFP*3 QFP*4 59 Pin name I/O circuit type Function General-purpose CMOS I/O port Also serves as an 8/16-bit timer/counter output. and half of main clock output Selectable pull-up resistor. General-purpose CMOS I/O port Also serves as the data input for the serial I/O. The peripheral is a hysteresis input type. Selectable pull-up resistor. General-purpose CMOS I/O port Also serves as the data output for the serial I/O. Selectable pull-up resistor. General-purpose CMOS I/O port Also serves as the clock I/O for the serial I/O. The peripheral is a hysteresis input type. Selectable pull-up resistor. General-purpose CMOS I/O port Also serves as the 6 bit programmable pulse generator. Selectable pull-up resistor. N-ch open-drain general-purpose I/O port Data I/O pin for I2C interface N-ch open-drain general-purpose I/O port Data I/O pin for I2C interface Function as capacitor connection pin in the products with a booster. Function as capacitor connection pin in the products with a booster. General-purpose CMOS I/O port Also serves PWM wave output for the 8-bit PWM timer 1 and as 12 bit programmable pulse generator output. Selectable pull-up resistor. General-purpose CMOS I/O port Also serves as the PWM wave output and external clock for the 8/16 bit timer counter. Selectable pull-up resistor. General-purpose CMOS I/O ports Also serve as the analog input for the A/D converter. Selectable pull-up resistor. N-ch open-drain general-purpose output ports Also serve as an LCD controller/driver segment output. N-ch open-drain general-purpose output ports Also serve as an LCD controller/driver segment output. P41/HCK/ TO12 F 45 47 P20/SI E 46 48 P21/SO F 47 49 P22/SCK E 48 54 55 65 64 50 56 57 67 66 P23/PPG1 P30/SCL P31/SDA C0 C1 P43/PWM2/ PPG2 F G G — — 59 61 F 58 60 P42/PWM1/ EC1 P00/AN0 to P07/AN7 P60/SEG16 to P67/SEG23 P50/SEG8 to P57/SEG15 E 21 to 28 10 to 12 14 to 18 2 to 9 23 to 30 12 to 14 16 to 20 4 to 11 J H/I H/I (Continued) *1: FPT-80P-M05 *2: FPT-80P-M11 *3: MQP-80C-P01 *4: FPT-80P-M06 9 MB89560H Series (Continued) Pin no. LQFP*1 LQFP*2 74 to 80, 1 MQFP*3 QFP*4 1 to 3 76 to 80 Pin name I/O circuit type Function SEG0 to SEG7 COM0 to COM3 V0 to V3 X0A I LCD controller/driver segment output-only pins 70 to 73 72 to 75 I LCD controller/driver common output-only pins 68 to 71 42 43 55 39 15 22 21 31 70 to 73 44 45 57 41 17 24 23 33 — LCD driving power supply pins. Crystal or other resonator connector pins for the subclock (Subclock: 32.768 kHz) The external clock can be connected to X0A. When this is done, Be sure to leave X1A open. Power supply pin Capacitor connection pin *5 Power supply (GND) pin A/D converter power supply pin A/D converter reference voltage input pin A/D converter power supply pin Use this pin at the same voltage as VSS. B X1A Vcc C Vss AVcc AVR AVss — — — — — — *1: FPT-80P-M05 *2: FPT-80P-M11 *3: MQP-80C-P01 *4: FPT-80P-M06 *5: When MB89PV560-101 or MB89PV560-102 is used, this pin will become a NC pin without internal connection. When MB89P568-101 or MB89P568-102 is used, this pin will be select a regulator stabilization delay time. If 5V used in MB89P568-101 or MB89P568-102, this pin must be connected to Vss. If 3V used in MB89P568-101 or MB89P568-102, this pin must be connected to Vcc. If MB89567H or MB89567HC is used, 0.1µF capacitor should connect to this pin. 10 MB89560H Series s PIN DESCRIPTION FOR EXTERNAL EPROM SOCKET (MB89PV560 ONLY) Pin no. 82 83 84 85 86 87 88 89 90 91 93 94 95 96 98 99 100 101 102 103 104 105 107 108 109 110 111 112 81 92 97 106 Pin name A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 Vss O4 O5 O6 O7 O8 CE A10 OE/Vpp A11 A9 A8 A13 A14 Vcc I/O Function O Address output pins I O Data input pins Power supply (GND) pin I Data input pins O O O ROM chip enable pin Outputs “H” during standby. Address output pin ROM output enable pin Outputs “L” at all times. O Address output pins O O O EPROM power supply pin Internally connected pins Be sure to leave them open. N.C. — 11 MB89560H Series s I/O CIRCUIT TYPE Type Circuit Remarks X1 N-ch P-ch A X0 P-ch N-ch N-ch Main clock (main clock crystal oscillator) • At an oscillation feedback resistor of approximately 1 MΩ/5.0 V • CR oscillation is selectable (mask products only) X1A N-ch P-ch B X0A P-ch N-ch N-ch Subclock (subclock crystal oscillator) • At an oscillation feedback resistor of approximately 4.5 MΩ/5.0 V C • Hysteresis input R P-ch • CMOS output D N-ch • Hysteresis input • At an output pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V R P-ch P-ch Pull up resistor register E N-ch Port Peripheral • CMOS output • CMOS input • The peripheral is a hysteresis input type. • Selectable pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V (Continued) 12 MB89560H Series (Continued) Type R P-ch P-ch Circuit Remarks Pull up resistor register F N-ch Port • CMOS output • CMOS input • Selectable pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V N-ch G Port Peripheral • N-ch open-drain input/output • CMOS input • The peripheral is a hysteresis input type. H N-ch Port • N-ch open-drain output • CMOS input P-ch N-ch I P-ch N-ch • LCD controller/driver common/segment output R P-ch P-ch Pull up resistor register J N-ch ADEN Port Analog input • General CMOS I/O • Analog input (A/D converter) • Selectable pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V • Pull-up resistors must be disabled when used as an analog input). 13 MB89560H Series s HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in “s Electrical Characteristics” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AV CC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up from stop mode. 14 MB89560H Series s PROGRAMMING TO THE EPROM ON THE MB89P568 The MB89P568 is an OTPROM version of the MB89567H and MB89567HC. 1. Features • 48-Kbyte PROM on chip • Equivalency to the MBM271001A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in EPROM mode is diagrammed below. Normal operation 0000H 0080H I/O RAM 0480H Not available 4000H EPROM mode (Corresponding addresses on the EPROM programmer 4000H Program area (PROM) FFFFH Program area (PROM) FFFFH 3. Programming to the EPROM In EPROM mode, the MB89P568 functions equivalent to the MBM27C1001A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. • Programming procedure (1) Set the EPROM programmer to the MBM27C1001A. (2) Load program data into the EPROM programmer at 4000H to FFFFH (3) Program with the EPROM programmer. 15 MB89560H Series 4. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure. Program, verify Aging +150°C, 48 Hrs. Data verification Assembly 5. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 6. EPROM Programmer Socket Adapter Package FPT-80P-M05 FPT-80P-M06 FPT-80P-M11 Compatible socket adapter ROM-80SQF-32DP-8LA ROM-80QF-32DP-8LA2 ROM-80SQF-32DP-8LA Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 16 MB89560H Series s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C512-20TV 2. Programming Socket Adaptor To program to the PROM using an EPROM programmer, use the socket adaptor (manufacturer: Sun Hayato Co., Ltd.) listed below. Package Adaptor socket part number LCC-32 (Rectangle) ROM-32LC-28DP-YG Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-5396-9106 3. Memory Space Normal operation 0000H I/O 0080H RAM 0480H Not available 2000H 2000H (Corresponding addresses on the EPROM programmer) Program area (PROM) Program area (PROM) FFFFH FFFFH 4. Programming to EPROM (1) Set the EPROM programmer to the MBM27C512. (2) Load program data into the EPROM programmer at 2000H to FFFFH. (3) Program to 2000H to FFFFH with the EPROM programmer. 17 MB89560H Series s BLOCK DIAGRAM Main clock X0 X1 I2C*2 Oscillator N-ch open drain I/O port SIO High-speed UART 12 bit PPG Watch prescaler Reset circuit (Watchdog timer) 21-bit Time-base timer PWC *4 8-bit timer/counter 1 (Timer 1) Port 3 P30/SCL P31/SDA Clock controller Subclock X0A X1A Low-power oscillator (32.768 kHz) P40/WTO/TO11 P41/HCK*1/TO12 P42/PWM1/EC1 P43/PWM2/PPG2 RST Port 4 P44/UCK/SCK1 P45/UO/SO1 P10/INT10 to P17/INT17 Port 1 8 8 External interrupt 1 CMOS I/O port Internal data bus *4 8-bit timer/counter 2 (Timer 2) 8-bit PWM timer 2 8-bit PWM timer 1 CMOS I/O port (P46 and P47 are N-ch Open-diran I/O Type) N-ch open-drain I/O port Port 5 & Port 6 8 4 4 4 4 8 4 4 P46/UI/SI1 P47/PWC 6 bit PPG P24/INT20 to P27/INT23 P23/PPG1 P20/SI P21/SO P22/SCK 4 4 External interrupt 2 (wake-up function) UART/SIO CMOS I/O port LCD controller/ driver 8 P60/SEG16 to P63/SEG19 P64/SEG20 to P67/SEG23 P50/SEG8 to P53/SEG11 P54/SEG12 to P57/SEG15 SEG0 to SEG7 COM0 to COM3 V0 to V3 C0*3 C1*3 Option *1: Output of Main clock/2. *2 : I2C is not available in MB89567 and MB89567H. *3 : Selected by mask option *4 : Can be used as a 16-bit timer/counter by connecting Timer 1 output to Timer 2 input. Port 2 1K Byte RAM Display RAM (12 bytes) F2MC-8L CPU Booster Wild register CMOS I/O port 8 8 48K Byte ROM Other pins MODA, C, VCC, VSS 10-bit A/D converter P00/AN0 to P07/AN7 AVCC AVSS AVR Port 0 18 MB89560H Series s CPU CORE 1. Memory Space The microcontrollers of the MB89560H series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located the lowest address. The data area is provided immediately above the I/ O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89560H series is structured as illustrated below. Memory Space MB89PV560-101,102 0000H I/O 0080H RAM 0100H Registers MB89P568-101,102 0000H I/O 0080H RAM 0100H Registers 0000H 0080H MB89567H, MB89567HC I/O RAM 0100H Registers 0200H 0480H 0492H 2000H *2 Access prohibited 0200H 0480H 0492H *2 Access prohibited 0200H 0480H 0492H *2 4000H 8000H External*1 ROM FFC0H FFFFH FFC0H FFFFH External*1 ROM Access prohibited ROM FFC0H FFFFH *1: MB89P568-101,102 has OTP ROM inside *2 : Wild register setting registers 19 MB89560H Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following registers are provided: Program counter (PC): Accumulator (A): A 16-bit register for indicating specifies instruction storage positions. A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS): A 16-bit register for index modification A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area A 16-bit register for storing a register pointer, a condition code 16 bits PC A T IX EP SP PS : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status Initial value FFFDH Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, 0 = 11 Other bits are undefined. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) 15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 3 N 2 Z 1 V 0 C Vacancy Vacancy Vacancy IL1, 0 RP CCR 20 MB89560H Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area RP Lower OP codes b1 ↓ b0 ↓ “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: IL1, 0: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 IL0 0 1 0 1 Interrupt level 1 2 3 Low = no interrupt High-low High N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: V-flag: Set when an arithmetic operation results in 0. Cleared otherwise. Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. 21 MB89560H Series The following general-purpose registers are provided: General-purpose registers: An 8-bit resister for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers. Up to a total of 32 banks can be used on MB89567H and MB89567HC. The bank currently in use is indicated by the register bank pointer (RP). Register Bank Configuration This address = 0100H + 8 ´ (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks (MB89567H/567HC) Memory area 22 MB89560H Series s I/O MAP Address 00H 01H 02H 03H 04H - 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H - 19H 1AH 1BH 1CH 1DH 1EH - 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H SMC11 SRC1 SSD1 SMC12 CNTR1 CNTR2 CNTR3 COMR1 COMR2 PCR1 PCR2 RLBR SMC21 SMC22 T2CR T2DR T1CR T1DR Timer2 data register Timer1 control register Timer1 data register (Vacancy) UART1 mode control register 1 UART1 mode data register UART1 status/data register UART1 mode control register 2 PWM control register 1 PWM control register 2 PWM control register 3 PWM compare register 1 PWM compare register 2 PWC pulse width control register 1 PWC pulse width control register 2 PWC reload buffer register UART2/SIO mode control register UART2/SIO mode control register 2 R/W R/W R/W R/W R/W R/W R/W R/W W W R/W R/W R/W R/W R/W 00000000B XX011000B 00100X1XB XXXXXXXXB XX100001B 00000000B 000X0000B X000XXXXB XXXXXXXXB XXXXXXXXB 000XX000B 00000000B XXXXXXXXB 00000000B 00000000B PDR6 SYCC STBC WDTC TBTC WPCR PDR2 DDR2 PDR3 PDR4 DDR4 PDR5 Register name PDR0 DDR0 PDR1 DDR1 Register Description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register (Vacancy) System clock control register Standby control register Watchdog timer control register Timebase timer control register Watch prescaler control register Port 2 data register Port 2 data direction register Port 3 data register Port 4 data register Port 4 direction register Port 5 data register (Vacancy) Port 6 data register (Vacancy) Timer2 control register R/W R/W R/W R/W X000XXX0B XXXXXXXXB X000XXX0B XXXXXXXXB R/W 00000000B R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W XXXMM100B 00010XXXB 0XXXXXXXB 00XXX000B 00XX0000B XXXXXXXXB 00000000B XXXXXX11B XXXXXXXXB 00000000B 00000000B Read/Write R/W W R/W W Initial value XXXXXXXXB 00000000B XXXXXXXXB 00000000B SIDR1/SODR1 UART1 data register (Continued) 23 MB89560H Series (Continued) Address 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH - 3EH 3FH 40H 41H 42H 43H - 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H - 6FH 70H 71H 72H 73H 74H 75H 76H VRAM SMR SDR PURR0 PURR1 PURR2 PURR4 Display RAM Serial I/O mode register Serial I/O data register Pull-up resister register 0 Pull-up resister register 1 Pull-up resister register 2 Pull-up resister register 4 (Vacancy) IBSR IBCR ICCR IADR IDAR EIE2 EIF2 RCR1 RCR2 CKR LCR1 LCR2 LCR3 LDR1 2 2 Register name SSD2 SRC2 ADC1 ADC2 ADDL ADDH RCR21 RCR23 RCR22 RCR24 EIC1 EIC2 EIC3 EIC4 Register Description UART2/SIO status/data register UART2/SIO rate control register A/D control register 1 A/D control register 2 A/D data register L A/D data register H PPG control register 1(PPG2) PPG control register 2(PPG2) PPG control register 3(PPG2) PPG control register 4(PPG2) (Vacancy) External interrupt 1 control register 1 External interrupt 1 control register 2 External interrupt 1 control register 3 External interrupt 1 control register 4 (Vacancy) I C bus status register I C bus control register I2C clock control register I2C address register I C data register External interrupt 2 enable register External interrupt 2 flag register PPG control register 1(PPG1) PPG control register 2(PPG1) Clock Output control register LCD controller/driver control register 1 LCD controller/driver control register 1 LCD controller/driver control register 1 LCD data register 1 (Vacancy) 2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00001XXXB XXXXXXXXB XXXXXXXXB X00000X0B X0000001B XXXXXXXXB XXXXXXXXB 00000000B 0X000000B XX000000B XX000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 000XXXXXB XXXXXXXXB XXXXXXXXB XXXX0000B XXXXXXX0B 00000000B 0X000000B 00000000B 00010000B 00000000B XX000000B XXXXXXXXB XXXXXXXXB 00000000B XXXXXXXXB 11111111B 11111111B 11111111B XX111111B SIDR2/SODR2 UART2/SIO data register (Continued) 24 MB89560H Series (Continued) Address 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH ILR1 ILR2 ILR3 ILR4 ITR Register name WREN WROR ADEN Register Description Wild register enable register Wild register data test register A/D port input enable register (Vacancy) Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 Interrupt test register W W W W Access Prohibited 11111111B 11111111B 11111111B 11111111B 11111111B Read/Write R/W R/W R/W Initial value XX000000B XX000000B 11111111B s EXTEND I/O MAP Address 480H 481H 482H 483H 484H 485H 486H 487H 488H 489H 48AH 48BH 48CH 48DH 48EH 48FH 490H 491H Register name WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 WRARH3 WRARL3 WRDR3 WRARH4 WRARL4 WRDR4 WRARH5 WRARL5 WRDR5 WRARH6 WRARL6 WRDR6 Register description Wild register high-byte address register1 Wild register low-byte address register1 Wild register data register1 Wild register high-byte address register2 Wild register low-byte address register2 Wild register data register2 Wild register high-byte address register3 Wild register low-byte address register3 Wild register data register3 Wild register high-byte address register4 Wild register low-byte address register4 Wild register data register4 Wild register high-byte address register5 Wild register low-byte address register5 Wild register data register5 Wild register high-byte address register6 Wild register low-byte address register6 Wild register data register6 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB q Read/write access symbols R/W: Readable and writable R: Read-only W: Write-only q Initial value symbols 0: The initial value of this bit is “0”. 1: The initial value of this bit is “1”. X: The initial value of this bit is undefined. M: The initial value of this bit is determined by mask option. Note:Do not use vacancies. 25 MB89560H Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol VCC AVCC AVR VPP VI VO IOL IOLAV ∑IOL ∑IOLAV IOH IOHAV ∑IOH ∑IOHAV PD TA Tstg Value Min. VSS – 0.3 VSS – 0.3 VSS – 0.6 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3          –40 –55 Max. VSS + 6.0 VSS + 6.0 VSS +13.0 VCC + 0.3 VSS + 6.0 VCC + 0.3 VSS + 6.0 15 4 100 40 –15 –4 –50 –20 300 +85 +150 Unit V V V V V V V mA mA mA mA mA mA mA mA mW °C °C Remarks MB89567H, MB89567HC, MB89P568 and MB89PV560 Only for the MB89P568 For pins other than P30 and P31 For P30 and P31 For pins other than P30 and P31 For P30 and P31 Average value (operating current × operating rate) Power supply voltage Program voltage Input voltage Output voltage “H” level maximum output current “L” level average output current “L” level total maximum output current “L” level total average output current “H” level maximum output current “H” level average output current “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) * : Use AVCC and VCC set at the same voltage. Take care so that AVR and AVCC + 0.3V does not exceed VCC, such as when power is turned on. Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 26 MB89560H Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Symbol Value Min. 3.5* Max. 5.5* 5.5 5.5* 5.5 AVCC +85 Unit V V V V V °C Remarks For MB89567H and MB89567HC Retains the RAM state in stop mode for MB89567H and MB89567HC For MB89PV560 and MB89P568 Retains the RAM state in stop mode for MB89PV560 and MB89P568 Power supply voltage VCC AVCC 3.0 2.7* 1.5 A/D converter reference input voltage Operating temperature AVR TA 3.5 –40 * : These values depend on the operating conditions and the analog assurance range. See Figure 1, Figure 2, Figure 3 and “5. A/D Converter Electrical Characteristics.” : MB89P568, MB89PV560 Operating Voltage (V) : MB89567H, MB89P567HC A/D Converter accuracy assurance range : Vcc = AVcc =3.5V~5.5V 5.5 5.0 4.0 3.5 3.0 2.7 Operation assurance range 2.0 Main clock operating Freq. (MHz) 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 12.0 11.0 12.5 Min execution time (inst. cycle) (µs) 4.0 2.0 0.8 0.4 0.32 Figure 1 Operating Voltage vs. Main Clock Operating Frequency 27 MB89560H Series 3. DC Characteristics (AVCC = VCC = 5.0V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Condition Unit Remarks Min. Typ. Max. Parameter Symbol Pin P00 to P07, P10 to P17, P20 to P27, P30 to P37 P40 to P45 RST, MODA INT10 to INT17, INT20 to INT23, SI,SCK,EC1,UCK, SCK1,UI,SI1,PWC VIH — 0.7 VCC — VCC + 0.3 V “H” level input voltage VIHS — 0.8 VCC — VCC + 0.3 V VIHSMB SDL, SDA VIHI2C P00 to P07, P10 to P17, P20 to P27, P40 to P45 RST, MODA INT10 to INT17, INT20 to INT23, SI,SCK,EC1,UCK, SCK1,UI,SI1,PWC — — VSS +1.4 0.7 VCC — — VSS + 5.5 VCC + 0.3 V V SMB input buffer selected I2C input buffer selected VIL — VSS − 0.3 — 0.3 VCC V “L” level input voltage VILS — VSS − 0.3 — 0.2 VCC V VILSMB SCL, SDA VILI2C Open-drain output pin application voltage P60 to P67 P50 to P57 P46, P47 P30, P31 P00 to P07, P10 to P17, P40 to P45 P20 to P27 P00 to P07, P10 to P17, P30 to P31, P40 to P47, P50 to P57, P60 to P67, RST P20 to P27 — — VSS - 0.3 VSS − 0.3 — — VSS + 0.6 0.3 VCC V V SMB input buffer selected I2C input buffer selected VD — VSS − 0.3 — VCC + 0.3 V “H” level output voltage IOH = –2.0 mA 4.0 IOH = –15.0 mA — — V VOH “L” level output voltage IOL = 4.0 mA — — 0.4 V VOL IOL = 15.0 mA (Continued) 28 MB89560H Series (Continued) Parameter Symbol Pin (AVCC = VCC = 5.0V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Condition FCH = 10.0 MHz VCC = 5.0 V tinst*3 = 0.4 µs Main clock run mode FCH = 10.0 MHz VCC = 5.0 V tinst*3 = 6.4 µs Main clock run mode FCH = 10.0 MHz VCC = 5.0 V tinst*3 = 0.4 µs Main clock sleep mode FCH = 10.0 MHz VCC = 5.0 V tinst*3 = 6.4 µs Main clock sleep mode FCL = 32.768 kHz VCC = 5.0 Subclock mode FCL = 32.768 kHz VCC = 5.0 V Subclock sleep mode FCL = 32.768 kHz VCC = 3.0 V • Watch mode • Main clock stop mode TA = +25°C • Subclock stop mode FCH = 10.0 MHz, Value Min. — — Typ. 15 6 5 1.5 5 2 1.5 1 3 20 30 15 Max. 20 Unit Remarks MB89PV560 MB89P568 ICC1 mA 10 8.5 mA 3 7 mA 4 3 mA 2 7 50 50 µA 30 mA µA MB89567H MB89567HC MB89PV560 MB89P568 MB89567H MB89567HC MB89PV560 MB89P568 MB89567H MB89567HC MB89PV560 MB89P568 MB89567H MB89567HC MB89PV560 MB89P568 MB89567H MB89567HC MB89PV560 MB89P568 MB89567H MB89567HC — — ICC2 — — — — — — — — ICCS1 ICCS2 VCC ‘ Power supply current ICCL ICCLS ICCT — 5 15 µA ICCH — 3 10 µA when A/D conversion is activated when A/D conversion is stopped IA AVCC IAH — 4 6 mA FCH = 10.0 MHz, TA = +25°C, — 1 5 µA (Continued) 29 MB89560H Series (Continued) (AVCC = VCC = 5.0V, , AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin P00 to P07, P10 to P17, P20 to P27, P40 to P45, P50 to P57, P60 to P67 MODA Condition Value Min. Typ. Max. Unit Remarks Input leakage current -5 0.0V < VI < VCC -10 — +5 µA ILI Without pull-up Resister — +10 µA Open-drain output ILIOD leakage current P30, P32 P46, P47 P00 to P07, P10 to P17, P20 to P27, P30 to P31, P40 to P45, RST — COM0 to 3 0.0V < VI < Vss + 5.5V — — +5 µA Pull-up resistance RPULL VI = 0.0 V 25 50 100 kΩ When pullup resistor selected except RST LCD divided resistance RLCD Between VCC and VSS 300 — 500 — — 750 2.5 15 kΩ kΩ kΩ µA COM0 to COM3 RVCOM output impedance SEG0 to 23 output RVSEG impedance LCD controller/ driver leakage current Input capacitance ILCDL V1 to V3 = 5.0V SEG0 to 23 V0 to V3, COM0 to 3 SEG0 to 23 — — — — +1 CIN Other than AVCC, AVSS, VCC, f = 1 MHz and VSS — 10 — pF 30 MB89560H Series 4. AC Characteristics (1) Reset Timing (VCC = 5.0V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter RST “L” pulse width Symbol tZLZH Condition — Value Min. 48 tHCYL* Max. — Unit ns Remarks * : tHCYL is the oscillation cycle (1/FC) to input to the X0 pin. tZLZH RST 0.2 VCC 0.2 VCC (2) Power-on Reset (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Power supply rising time Power supply cut-off time Symbol tR tOFF Condition — Value Min. 0.5 1 Max. 50 — Unit ms ms Remarks Due to repeated operations Note: Make sure that power supply rises within the selected oscillation stabilization time. For example, when the main clock is operating at 10 MHz (FCH) and the oscillation stabilization time select option has been set to 218/FCH, the oscillation stabilization delay time is 26.2 ms. Therefore, the maximum value of power supply rising time is about 26.2 ms. Rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR 3.5 V 0.2 V tOFF VCC 0.2 V 0.2 V 31 MB89560H Series (3) Clock Timing (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Clock frequency Clock cycle time Symbol FCH FCL tHCYL tLCYL PWH PWL PWH PWL tCR tCF Pin X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0 Value Min. 1 — 80 — 20 — — Typ. — 32.768 — 30.5 — 15.2 — Max. 12.5 — 1000 — — — 10 Unit MHz kHz ns µs ns µs ns Remarks Main clock Subclock Main clock Subclock External clock External clock External clock Input clock pulse width Input clock rising/falling time X0 and X1 Timing and Conditions tHCYL PWH tCR 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC tCF PWL Main Clock Conditions When a crystal or ceramic reasonator is used When an external clock is used X0 X1 FCH C1 C2 X0 X1 Open FCH 32 MB89560H Series X0A and X1A Timing and Conditions tLCYL PWLH tCR 0.8 VCC X0A 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC tCF PWLL Subclock Conditions When a crystal or ceramic reasonator is used When an external clock is used X0A X1A FCL X0A X1A Open FCL C1 C2 (4) Instruction Cycle Parameter Instruction cycle (minimum execution time) Symbol Value 4/FCH, 8/FCH, 16/FCH, 64/FCH tinst 2/FCL µs Unit µs Remarks tinst = 0.32µs when operating at FCH = 12.5 MHz (4/FCH) tinst = 61.036 µs when operating at FCL = 32.768 kHz 33 MB89560H Series (5) Serial I/O Timing (Vcc = 5.0V, AVSS = VSS= 0.0 V, TA = –40°C to +85°C) Parameter Serial clock cycle time SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin SCK, SCK1, UCK SCK, SO, SCK1, SO1, UCK, UO SI, SCK, SI1, SCK1, UI, UCK SCK, SI, SCK1, SI1, UCK, UI SCK, SCK1, UCK SCK, SO, SCK1, SO1, UCK, UO SI, SCK, SI1, SCK1, UI, UCK SCK, SI, SCK1, SI1, UCK, UI Condition Value Min. 2 tinst* Max. — 200 — — — — 200 — — Unit µs ns ns ns µs µs ns ns ns Remarks Internal shift clock mode –200 200 200 1 tinst* 1 tinst* External shift clock mode 0 200 200 * : For information on tinst, see “(4) Instruction Cycle.” Internal Shift Clock Mode tSCYC SCK SCK1 UCK 2.4 V 0.8 V tSLOV SO SO1 UO 2.4 V 0.8 V tIVSH SI SI1 U1 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC 0.8 V External Shift Clock Mode tSLSH SCK SCK1 UCK 0.8 VCC 0.2 VCC tSLOV SO SO1 UO 2.4 V 0.8 V tIVSH SI SI1 UI 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC 0.2 VCC tSHSL 0.8 VCC 34 MB89560H Series (6) Peripheral Input Timing (Vcc = 5.0V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin INT10 to INT17, INT20 to INT23, EC, PWC Condition Value Min. 2 tinst* Max. — — Unit Remarks µs µs Peripheral input “H” pulse width 1 tILIH1 Peripheral input “L” pulse width 1 tIHIL1 — 2 tinst* * : For information on tinst, see “(4) Instruction Cycle.” t IHIL1 t ILIH1 INT10 to 17, INT20 to INT23 EC, PWC 0.2 VCC 0.8 VCC 0.2 VCC 0.8 VCC 35 MB89560H Series (7) I2C timing (Vcc = 5.0V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SCL SDA SDA SCL SCL SDA SDA Condition Value Min. 1/4tINST x m x n - 20 1/4tINST x (m x n + 8) - 20 1/4tINST x 6 + 40 1/4tINST x 6 + 40 1/4tINST x (m x n + 8) - 20 1/4tINST x 4 + 40 1/4tINST x m x n - 20 1/4tINST x (m x n + 8) - 20 1/4tINST x 4 - 20 1/4tINST x 4 - 20 1/4tINST x 6 + 40 1/4 tINST x 2 + 40 40 0 Max. 1/4tINST x m x n + 20 1/4tINST x (m x n + 8) + 20 — — 1/4tINST x (m x n + 8) + 20 — 1/4tINST x m x n + 20 1/4tINST x (m x n + 8) + 20 1/4tINST x 4 + 20 — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks master mode master mode Start condition output tSTA Stop condition output tSTO Start condition detect tSTA Stop condition detect tSTO Re-start condition output Re-start condition detect SCL output LOW width SCL output HIGH width SDA output delay SDA output setup time after interrupt SCL input LOW pulse width SCL input HIGH pulse width SDA hold time tSTASU tSTASU tLOW tHIGH tDO tDOSU tLOW tHIGH master mode master mode master mode SDA input setup time tSU tHO • For information in tINST, see "(4) Instruction Cycle". • m is defined in the ICCR CS4 and CS3 (bit 4 to bit 3) • n is defined in the ICCR CS2 to CS0 (bit 2 to bit 0) Data transmit (master/slave) tDO tDO tSU tHO tDOSU SDA tSTASU tSTA tLOW tHO ACK SCL 1 9 Data receive (master/slave) tSU tHO tDO tDO tDOSU SDA tHIGH tLOW ACK tSTO SCL 6 7 8 9 36 MB89560H Series 5. A/D Converter Electrical Characteristics (1) For MB89567H A/D Converter (AVcc=3.5~5.5V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Resolution Total error Non-linearity error Differential linearity error Symbol Pin Condition Min. — — — — — AVR=AVCC AVR 3.5 LSB AVR – 6.5 LSB — Value Typ. — — — — AVR + 0.5 LSB AVR – 1.5 LSB — 60 tinst*1 16 tinst*1 — — — 400 — Max. 10 ±5.0 ±2.5 ±1.9 AVR + 4.5 LSB AVR + 1.5 LSB 4 — — 10 AVR AVCC — 5 Unit bit LSB Remarks — LSB 1LSB = AVR/1024 LSB mV mV LSB 1LSB = AVR/1024 µs Zero transition voltage VOT Full-scale transition voltage Interchannel disparity A/D mode conversion time *3 A/D Sampling time Analog port input current Analog input voltage Reference voltage Reference voltage supply current IR IRH IAIN VAIN — — VFST — — — AN0 to AN7 — — AVss AVss+3.5 AVR A/D is Activated A/D is Stopped — — µA V V µA µA *2 * : 1 For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” * : 2 When A/D conversion is not in operation, and the CPU is in STOP mode. * : 3 Included sampling time 37 MB89560H Series (2) For MB89P568 A/D Converter (AVcc=3.5~5.5V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Resolution Total error Non-linearity error Differential linearity error Symbol Pin Condition Min. — — — — — AVR=AVCC AVR 1.5 LSB AVR – 3.5 LSB — Value Typ. — — — — AVR + 0.5 LSB AVR – 1.5 LSB — 60 tinst*1 16 tinst*1 — — — 400 — Max. 10 ±3.0 ±2.5 ±1.9 AVR + 2.5 LSB AVR + 1.5 LSB 4 — — 10 AVR AVCC — 5 Unit bit LSB Remarks — LSB 1LSB = AVR/1024 LSB mV mV LSB 1LSB = AVR/1024 µs Zero transition voltage VOT Full-scale transition voltage Interchannel disparity A/D mode conversion time *3 A/D Sampling time Analog port input current Analog input voltage Reference voltage Reference voltage supply current IR IRH IAIN VAIN — — VFST — — — AN0 to AN7 — — AVss AVss+3.5 AVR A/D is Activated A/D is Stopped — — µA V V µA µA *2 * : 1 For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” * : 2 When A/D conversion is not in operation, and the CPU is in STOP mode. * : 3 Included sampling time *: 38 MB89560H Series (3) Precautions • The smaller the | AVR–AVSS |, the greater the error would become relatively. • The output impedance of the external circuit for the analog input must satisfy the following conditions: Output impedance of the external circuit < Approx. 10 kΩ • If the output impedance of the external circuit is too high, an analog voltage sampling time might be insufficient (sampling time = 6 µs at 10MHz oscillation.) Analog Input Circuit Model Analog input pin Comparator If the analog input impedance is higher than 10 kW, it is recommended to connect an external capacitor of approx. 0.1 mF. . R = 6 kW . Close for 8 instruction cycles after activating A/D conversion. Analog channel selector Sample hold circuit . C = 33 pF . (4) A/D Converter Glossary • Resolution Analog changes that are identifiable with the A/D converter. • Linearity error The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics • Differential linearity error The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value • Total error (unit: LSB) The difference between theoretical and actual conversion values caused by the zero transition error, full-scale transition error, linearity error, quantization error, and noise Theoretical I/O characteristics 3FF 3FE 3FD 1.5 LSB VFST 3FF 3FE 3FD Total error Actual conversion value {1 LSB × N + 0.5 LSB} Digital output 004 003 002 001 0.5 LSB AVSS Analog input AVR Digital output 004 003 VNT Actual conversion value Theoretical value VOT 1 LSB 002 001 AVSS AVR Analog input 1 LSB = VFST – VOT 1022 (V) Digital output N total error = VNT – {1 LSB × N + 0.5 LSB} 1 LSB (Continued) 39 MB89560H Series (Continued) Zero transition error 004 Actual conversion value 003 Digital output Digital output 3FE VFST (Actual measurement) Actual conversion value 3FC AVR Analog input Analog input 3FF Actual conversion value Full-scale transition error Theoretical value 002 Actual conversion value 001 3FD VOT (Actual measurement) AVSS Linearity error 3FF 3FE 3FD Digital output VFST (Actual measurement) Digital output N Actual conversion value {1 LSB × N + VOT} N+1 Differential linearity error Theoretical value Actual conversion value V(N + 1)T VNT 004 003 002 001 AVSS Analog input Theoretical value N–1 Actual conversion value VNT Actual conversion value N–2 AVR Analog input VOT (Actual measurement) AVR AVSS Digital output N linearity error = VNT – {1 LSB × N + VOT} 1 LSB Digital output N differential linearity error = V(N + 1)T – VNT 1 LSB –1 40 MB89560H Series s INSTRUCTIONS Execution instructions can be divided into the following four groups: • • • • Transfer Arithmetic operation Branch Others Table 1 lists symbols used for notation of instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Instruction Symbols Meaning (Continued) 41 MB89560H Series (Continued) Symbol EP PC SP PS dr CCR RP Ri × (×) (( × )) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Meaning Columns indicate the following: Mnemonic: ~: #: Operation: TL, TH, AH: Assembler notation of an instruction Number of instructions Number of bytes Operation of an instruction A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: • “–” indicates no change. • dH is the 8 upper bits of operation description data. • AL and AH must become the contents of AL and AH immediately before the instruction is executed. • 00 becomes 00. N, Z, V, C: OP code: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ← This indicates 48, 49, ... 4F. 42 MB89560H Series Table 2 Mnemonic MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC ~ 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 # 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 Transfer Instructions (48 instructions) Operation (dir) ← (A) ( (IX) +off ) ← (A) (ext) ← (A) ( (EP) ) ← (A) (Ri) ← (A) (A) ← d8 (A) ← (dir) (A) ← ( (IX) +off) (A) ← (ext) (A) ← ( (A) ) (A) ← ( (EP) ) (A) ← (Ri) (dir) ← d8 ( (IX) +off ) ← d8 ( (EP) ) ← d8 (Ri) ← d8 (dir) ← (AH),(dir + 1) ← (AL) ( (IX) +off) ← (AH), ( (IX) +off + 1) ← (AL) (ext) ← (AH), (ext + 1) ← (AL) ( (EP) ) ← (AH),( (EP) + 1) ← (AL) (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir + 1) (AH) ← ( (IX) +off), (AL) ← ( (IX) +off + 1) (AH) ← (ext), (AL) ← (ext + 1) (AH) ← ( (A) ), (AL) ← ( (A) ) + 1) (AH) ← ( (EP) ), (AL) ← ( (EP) + 1) (A) ← (EP) (EP) ← d16 (IX) ← (A) (A) ← (IX) (SP) ← (A) (A) ← (SP) ( (A) ) ← (T) ( (A) ) ← (TH),( (A) + 1) ← (TL) (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ↔ (AL) (dir): b ← 1 (dir): b ← 0 (AL) ↔ (TL) (A) ↔ (T) (A) ↔ (EP) (A) ↔ (IX) (A) ↔ (SP) (A) ← (PC) TL – – – – – AL AL AL AL AL AL AL – – – – – – – – – AL AL AL AL AL AL – – – – – – – – – – – – – – – AL AL – – – – TH – – – – – – – – – – – – – – – – – – – – – AH AH AH AH AH AH – – – – – – – – – – – – – – – – AH – – – – AH – – – – – – – – – – – – – – – – – – – – – dH dH dH dH dH dH dH – – dH – dH – – – dH – – AL – – – dH dH dH dH dH NZVC –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++++ –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– OP code 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 D4 D7 E3 E4 C5 C6 C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0 Notes: • During byte transfer to A, T ← A is restricted to low bytes. • Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F 2MC-8 family) 43 MB89560H Series Table 3 Mnemonic ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir ~ 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 # 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation (A) ← (A) + (Ri) + C (A) ← (A) + d8 + C (A) ← (A) + (dir) + C (A) ← (A) + ( (IX) +off) + C (A) ← (A) + ( (EP) ) + C (A) ← (A) + (T) + C (AL) ← (AL) + (TL) + C (A) ← (A) − (Ri) − C (A) ← (A) − d8 − C (A) ← (A) − (dir) − C (A) ← (A) − ( (IX) +off) − C (A) ← (A) − ( (EP) ) − C (A) ← (T) − (A) − C (AL) ← (TL) − (AL) − C (Ri) ← (Ri) + 1 (EP) ← (EP) + 1 (IX) ← (IX) + 1 (A) ← (A) + 1 (Ri) ← (Ri) − 1 (EP) ← (EP) − 1 (IX) ← (IX) − 1 (A) ← (A) − 1 (A) ← (AL) × (TL) (A) ← (T) / (AL),MOD → (T) (A) ← (A) ∧ (T) (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL) − (AL) (T) − (A) → C→A C ← A← (A) − d8 (A) − (dir) (A) − ( (EP) ) (A) − ( (IX) +off) (A) − (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ( (EP) ) (A) ← (AL) ∀ ( (IX) +off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) TL – – – – – – – – – – – – – – – – – – – – – – – dL – – – – – – – – – – – – – – – – – – – – – – – TH – – – – – – – – – – – – – – – – – – – – – – – 00 – – – – – – – – – – – – – – – – – – – – – – – AH – – – – – dH – – – – – – dH – – – – dH – – – dH dH 00 dH dH dH – – – – – – – – – – – – – – – – – – – – NZVC ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++– –––– –––– ++–– +++– –––– –––– ++–– –––– –––– ++R– ++R– ++R– ++++ ++++ ++–+ ++–+ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– OP code 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 (Continued) 44 MB89560H Series (Continued) Mnemonic AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP ~ 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 # 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) ← (AL) ∧ ( (EP) ) (A) ← (AL) ∧ ( (IX) +off) (A) ← (AL) ∧ (Ri) (A) ← (AL) ∨ (TL) (A) ← (AL) ∨ d8 (A) ← (AL) ∨ (dir) (A) ← (AL) ∨ ( (EP) ) (A) ← (AL) ∨ ( (IX) +off) (A) ← (AL) ∨ (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ← (SP) + 1 (SP) ← (SP) – 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 # 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 TL – – – – – – – – – – – – – – – TH – – – – – – – – – – – – – – – AH – – – – – – – – – – – – – – – NZVC ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++++ ++++ ++++ ++++ –––– –––– OP code 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 Branch Instructions (17 instructions) Operation TL – – – – – – – – – – – – – – – – – TH – – – – – – – – – – – – – – – – – AH – – – – – – – – – – – – – – dH – – NZVC –––– –––– –––– –––– –––– –––– –––– –––– –+–– –+–– –––– –––– –––– –––– –––– –––– Restore OP code FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 If Z = 1 then PC ← PC + rel If Z = 0 then PC ← PC + rel If C = 1 then PC ← PC + rel If C = 0 then PC ← PC + rel If N = 1 then PC ← PC + rel If N = 0 then PC ← PC + rel If V ∀ N = 1 then PC ← PC + rel If V ∀ N = 0 then PC ← PC + reI If (dir: b) = 0 then PC ← PC + rel If (dir: b) = 1 then PC ← PC + rel (PC) ← (A) (PC) ← ext Vector call Subroutine call (PC) ← (A),(A) ← (PC) + 1 Return from subrountine Return form interrupt Table 5 Other Instructions (9 instructions) Operation TL – – – – – – – – – TH – – – – – – – – – AH – dH – – – – – – – NZVC –––– –––– –––– –––– –––– –––R –––S –––– –––– OP code 40 50 41 51 00 81 91 80 90 Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI ~ 4 4 4 4 1 1 1 1 1 # 1 1 1 1 1 1 1 1 1 45 46 3 RETI PUSHW POPW MOV MOVW CLRI A A A,ext A,PS SETC SETI CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC 4 5 6 7 8 9 A B C D E F CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP SUBC A A, T A A A XCH XOR AND OR MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX L H 0 1 2 0 NOP SWAP RET 1 MULU DIVU A A JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A 2 ROLC CMP ADDC A A A s INSTRUCTION MAP 3 A DAS RORC CMPW A XOR AND OR DAA A,#d8 A,#d8 A,#d8 A ADDCW SUBCW XCHW XORW ANDW ORW A A A, T A A MOVW MOVW CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC MB89560H Series 4 MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 5 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP SUBC A,@IX +d CMP @EP,#d 8 MOV @IX +d,A AND XOR @A,IX A,@IX +d +d OR A,@IX +d MOVW XCHW MOVW CLRB BBC MOVW CMP MOV A,IX @IX IX,#d16 dir: 6 dir: 6,rel A,@IX @IX @IX +d,A +d +d,#d8 +d,#d8 CLRB BBC MOVW MOVW MOVW XCHW dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP 6 MOV A,@IX +d CMP A,@IX +d ADDC A,@IX +d 7 MOV CMP ADDC SUBC MOV XOR AND OR MOV A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d 8 8 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 R7 R6 R5 R4 R3 R2 R1 R0 CALLV BNC #0 rel CALLV BC #1 CALLV BP #2 CALLV BN #3 CALLV BNZ #4 CALLV BZ #5 9 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel rel A MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel rel B MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel rel C MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel rel D MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel rel CALLV BGE #6 rel CALLV BLT #7 E MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel F MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel rel MB89560H Series s MASK OPTION Model NO. Specification method MB89567H MB89567HC Specify when ordering mask. MB89P568 Setting unavailable. MB89PV560 Setting unavailable. 1 Main clock oscillation stabilization delay time initial value* selection (FCH = 10 MHz) Selectable • 01: 212/FCH (Approx. 0.41 ms) • 10: 216/FCH (Approx. 6.55 ms) • 11: 218/FCH (Approx. 26.2 ms) 218/FCH (Approx. 26.2 ms) 218/FCH (approx. 26.2ms) 2 LCD driving power supply • On-chip voltage booster • Internal voltage divider (external divider resistors can be used) Internal voltage booster Selectable by version number -101 Internal voltage divider -102 On-chip voltage booster 47 MB89560H Series s ORDERING INFORMATION Part number MB89567HPFV MB89567HCPFV MB89P568PFV-101 MB89567HPFV MB89567HCPFV MB89P568PFV-102 MB89567HPF MB89567HCPF MB89P568PF-101 MB89567HPF MB89567HCPF MB89P568PF-102 MB89567HPFM MB89567HCPFM MB89P568PFM-101 MB89567HPFM MB89567HCPFM MB89P568PFM-102 MB89PV560CF-101 80-pin Ceramic MQFP (MQP-80C-P01) Package Remarks Without Booster Resistor divider 80-pin Plastic LQFP (FPT-80P-M05) With Booster 80-pin Plastic QFP (FPT-80P-M06) Without Booster Resistor divider With Booster 80-pin Plastic LQFP (FPT-80P-M11) Without Booster Resistor divider With Booster Without Booster Resistor divider With Booster MB89PV560CF-102 48 MB89560H Series s PACKAGE DIMENSIONS 80-pin Plastic LQFP (FPT-80P-M05) 14.00±0.20(.551±.008)SQ 60 12.00±0.10(.472±.004)SQ 1.50 –0.10 +.008 .059 –.004 41 +0.20 (Mounting height) 61 40 9.50 (.374) REF INDEX 80 21 13.00 (.512) NOM LEAD No. 1 20 "A" 0.127 –0.02 +.002 .005 –.001 +0.05 Details of "A" part 0.50±0.08 (.0197±.0031) 0.18 –0.03 +.003 .007 –.001 +0.08 0.10±0.10 (STAND OFF) (.004±.004) 0.50±0.20(.020±.008) 0.10(.004) 0 10˚ C 1994 FUJITSU LIMITED F80008S-2C-4 Dimension in mm (inches) 80-pin Plastic QFP (FPT-80P-M06) 23.90±0.40(.941±.016) 64 65 20.00±0.20(.787±.008) 41 40 3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF) 14.00±0.20 (.551±.008) INDEX 80 25 17.90±0.40 (.705±.016) 12.00(.472) REF 16.30±0.40 (.642±.016) "A" LEAD No. 1 24 0.80(.0315)TYP 0.35±0.10 (.014±.004) 0.16(.006) M 0.15±0.05(.006±.002) Details of "A" part 0.25(.010) "B" 0.10(.004) 18.40(.724)REF 22.30±0.40(.878±.016) 0.30(.012) 0.18(.007)MAX 0.58(.023)MAX Details of "B" part 0 10˚ 0.80±0.20 (.031±.008) C 1994 FUJITSU LIMITED F80010S-3C-2 Dimension in mm (inches) 49 MB89560H Series 80-pin Plastic LQFP (FPT-80P-M11) +0.20 16.00±0.20(.630±.008)SQ 60 14.00±0.10(.551±.004)SQ 41 1.50 0.10 +.008 .059 .004 (Mounting height) 61 40 12.35 (.486) REF 15.00 (.591) NOM 1 PIN INDEX 80 21 LEAD No. 1 20 "A" 0.30±0.10 (.012±.004) 0.13(.005) M Details of "A" part 0.127 .005 +0.05 0.02 +.002 .001 0.65(.0256)TYP 0.10±0.10 (STAND OFF) (.004±.004) 0.10(.004) 0 10˚ 0.50±0.20 (.020±.008) C 1995 FUJITSU LIMITED F80016S-1C-3 Deminsion in mm (inches) 80-pin Ceramic MQFP (MQP-80C-P01) 18.70(.736)TYP 12.00(.472)TYP 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) 1.50(.059)TYP 1.00(.040)TYP 4.50(.177) TYP 1.20 –0.20 +.016 .047 –.008 +0.40 INDEX AREA 0.80±0.25 (.0315±.010) 0.80±0.25 (.0315±.010) 1.27±0.13 (.050±.005) 22.30±0.33 (.878±.013) 24.70(.972) TYP 0.30(.012) TYP 18.12±0.20 12.02(.473) (.713±.008) TYP 10.16(.400) 14.22(.560) TYP TYP INDEX AREA 18.40(.724) REF INDEX 6.00(.236) TYP 0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP 0.40±0.10 (.016±.004) 1.50(.059) TYP 1.00(.040) TYP 1.27±0.13 (.050±.005) 0.40±0.10 (.016±.004) 1.20 –0.20 +.016 .047 –.008 +0.40 0.15±0.05 8.70(.343) (.006±.002) MAX C 1994 FUJITSU LIMITED M80001SC-4-2 Dimension in mm (inches) 50 MB89560H Series MEMO 51 MB89560H Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 1250 East Arques Avenue Sunnyvale, CA 94088-3470, USA Tel: (408) 737-5600 Fax: (408) 737-5999 Mon. - Fri.: 7 am - 5 pm (PST) Toll Free: (800) 866-8608 http://www.fma.fujitsu.com/ All Rights Reserved. Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. The information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support. http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9806 © FUJITSU LIMITED Printed in Japan 52