MB89P657APFV-106

FUJITSU SEMICONDUCTOR DATA SHEET DS07-12530-2E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89650AR Series MB89653AR/655AR/656AR/657AR/P657A MB89PV650A s DESCRIPTION The MB89650AR series has been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as dualclock control system, five operating speed control stages, timers, PWM timers, a serial interface, an A/D converter, external interrupts, an LCD controller/driver, and a watch prescaler. *: F2MC stands for FUJITSU Flexible Microcontroller. s FEATURES • • • • • • • F2MC-8L family CPU core Dual-clock control system Maximum memory space: 64 Kbytes Minimum execution time: 0.4 µs/10 MHz Interrupt processing time: 3.6 µs/10 MHz I/O ports: Max 64 channels 21-bit time-base counter (Continued) s PACKAGE 100-pin Plastic LQFP 100-pin Plastic QFP 100-pin Ceramic MQFP (FPT-100P-M05) (FPT-100P-M06) (MQP-100C-P02) MB89650AR Series (Continued) • 8-bit PWM timers: 2 channels (A maximum of 4 channels can be used for output.) • 8/16-bit timer/counter: 4 channels (16 bits × 2 channels) • 8-bit serial I/O: 1 channel • 8-bit A/D converter: 8 channels • External interrupt 1 Four independent channels with edge detection function • External interrupt 2 (wake-up function) Twelve “L” level-interrupt channels • Watch prescaler • LCD controller/driver: 16 to 32 segments × 2 to 4 commons • Power-on reset function • Low-power consumption modes (subclock mode, watch mode, sleep mode, and stop mode) • LQFP-100 and QFP-100 packages s PRODUCT LINEUP Part number MB89653AR MB89655AR Parameter MB89656AR MB89657AR MB89P657A MB89PV650A Classification Mass production products (mask ROM products) Piggyback/ evaluation One-time product (for PROM product evaluation and development) 32 K × 8 bits (internal PROM, programming with generalpurpose EPROM programmer) 1 K × 8 bits ROM size 8 K × 8 bits (internal mask ROM) 16 K × 8 bits (internal mask ROM) 24 K × 8 bits (internal mask ROM) 32 K × 8 bits (internal mask ROM) 32 K × 8 bits (external ROM) RAM size LCD display RAM 256 × 8 bits 512 × 8 bits 768 × 8 bits 16 × 8 bits CPU functions Number of instructions Instruction bit length Instruction length Data bit length Minimum execution time Interrupt processing time Input ports Output ports I/O ports Total : : : : : : : : : : 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.4 µs/10 MHz to 6.4 µs/10 MHz, 61.0 µs/32.768 kHz 3.6 µs/10 MHz to 57.6 µs/10 MHz, 549.3 µs/32.768 kHz 8 (All also serve as peripherals.) 8 (All also serve as peripherals.) 48 (All also serve as peripherals.) 64 Ports 8-bit timer 1, 8-bit timer 2 8-bit timer operation (toggled output capable, operating clock cycle: 0.8 to 12.8 µs) 16-bit timer operation (toggled output capable, operating clock cycle: 0.8 to 12.8 µs) 2 output channels are enabled when operating as an 8-bit timer. (Continued) 2 MB89650AR Series (Continued) Part number Parameter MB89653AR MB89655AR MB89656AR MB89657AR MB89P657A MB89PV650A 8-bit timer 3, 8-bit timer 4 Clock timer 8-bit PWM timer 1, 8-bit PWM timer 2 8-bit timer operation (toggled output capable, operating clock cycle: 0.8 to 12.8 µs) 16-bit timer operation (toggled output capable, operating clock cycle: 0.8 to 12.8 µs) 2 output channels are enabled when operating as an 8-bit timer. 21 bits × 1 (in main clock mode)/15 bits × 1 (at 32.768 kHz) 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs to 3.3 ms) 8-bit resolution PWM operation (conversion cycle: 102 µs to 839 ms) Both 8-bit PWM timer 1 and 8-bit PWM timer 2 can output 2 channels. 8 bits LSB first/MSB first selectability One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs) 8-bit resolution × 8 channels A/D conversion mode (conversion time: 18 µs) Sense mode (conversion time: 5 µs) Continuous activation by an internal timer capable Reference voltage input 4 independent channels (edge selection) Rising edge/falling edge selectability Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.) “L” level interrupt × 12 channels Subclock mode, sleep mode, watch mode, and stop mode CMOS 2.2 V to 6.0 V  2.7 V to 6.0 V MBM27C256A20TVM 8-bit serial I/O 8-bit A/D converter External interrupt 1 External interrupt 2 (wake-up function) Standby mode Process Operating voltage* EPROM for use * : Varies with conditions such as the operating frequency. (See section “s Electrical Characteristics”.) In the case of the MB89PV650A, the voltage varies with the restrictions of the EPROM for use. s PACKAGE AND CORRESPONDING PRODUCTS MB89653AR MB89655AR MB89656AR MB89657AR MB89P657A Package MB89PV650A FPT-100P-M05 FPT-100P-M06 MQP-100C-P02 : Available × : Not available × × × Note : For more information about each package, see section “s Package Dimensions”. 3 MB89650AR Series s DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: • On the MB89653AR, the upper half of the register bank cannot be used. • On the MB89P657A, the program area starts from address 8006H but on the MB89PV650A and MB89657AR starts from 8000H. (On the MB89P657A, addresses 8000H to 8005H comprise the option setting area, option settings can be read by reading these addresses. On the MB89PV650A and MB89657A, addresses 8000H to 8005H could also be used as a program ROM. However, do not use these addresses in order to maintain compatibility of the MB89P657A.) • The stack area, etc., is set at the upper limit of the RAM. 2. Current Consumption • In the case of the MB89PV650A, add the current consumed by the EPROM which is connected to the top socket. • When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same. (For more information, see sections “s Electrical Characteristics” and “s Example Characteristics.”) 3. Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “s Mask Options.” Take particular care on the following points: • A pull-up resistor cannot be set for P70 to P75 on the MB89P657A. On this product, a pull-up resistor must be selected in a group of four bits for P14 to P17, P40 to P43, and P44 to P47. • A pull-up resistor is not selectable for P30 to P37 and P40 to P47 if they are used as LCD pins. • Options are fixed on the MB89PV650A. 4. Differences between the MB89650A and MB89650AR Series • Electrical specifications/electrical characteristics Electrical specifications of the MB89650AR series are the same with that of the MB89650A series. Electrical characteristics of both series are much the same. • Oscillation circuit type In the MB89650A series, the circuit type of using an external clock differs from that of using a crystal or ceramic resonator as follows. Circuit type of the MB89650AR series is a circuit type in using external clock even when crystal or ceramic resonator is selected. • Memory access area and other specifications of both the MB89650A and MB89650AR series are the same. 4 MB89650AR Series • I/O circuit type Type X1 Circuit Remarks • Crystal or ceramic oscillation type (main clock) MB89PV650A and MB89P657A, external clock input selection versions of MB89653A/655A/656A/657A At an oscillation feedback resistor of approximately 1 MΩ/5.0 V • MB89653AR/655AR/656AR/657AR X0 A X1 Standby control signal X0 • Crystal or ceramic oscillation type (main clock) Crystal or ceramic oscillation selection versions of MB89653A/655A/656A/657A At an oscillation feedback resistor of approximately 1 MΩ/5.0 V Standby control signal s CORRESPONDENCE BETWEEN THE MB89650A AND MB89650AR SERIES • The MB89650AR series is the reduction version of the MB89650A series. • The MB89650A and MB89650AR series consist of the following products: MB89650A series MB89650AR series MB89653A MB89653AR MB89655A MB89655AR MB89656A MB89656AR MB89657A MB89P657A MB89657AR MB89PV650A 5 MB89650AR Series s PIN ASSIGNMENT (Top view) X0A X1A VCC P75 P74 P73 P72/BUZ P71/EC2 P70/EC1 AVR AVCC P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 AVSS P57/TO22 P56/TO21/HCLK P55/TO12 P54/TO11/LCLK P53/PWM22 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MOD0 MOD1 X0 X1 VSS RST P00/INT20 P01/INT21 P02/INT22 P03/INT23 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P10/INT10 P11/INT11 P12/INT12 P13/INT13 P14/INT28 P15/INT29 P16/INT2A P17/INT2B P20 P21 P22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P52/PWM21 P51/PWM12 P50/PWM11 COM3/P81 COM2/P80 COM1 COM0 V0 V1 V2 V3 P83 P82 SEG00 SEG01 SEG02 SEG03 SEG04 SEG05 VSS SEG06 SEG07 SEG08 SEG09 SEG10 P24/SI P25/SO P26/SCK P30/SEG31 P31/SEG30 P32/SEG29 P33/SEG28 P34/SEG27 P35/SEG26 P36/SEG25 P37/SEG24 P40/SEG23 P41/SEG22 P42/SEG21 P43/SEG20 P44/SEG19 P45/SEG18 P46/SEG17 P47/SEG16 SEG15 SEG14 VCC SEG13 SEG12 SEG11 (FPT-100P-M05) (Continued) 6 MB89650AR Series (Top view) P75 P74 P73 P72/BUZ P71/EC2 P70/EC1 AVR AVCC P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 AVSS P57/TO22 P56/TO21/HCLK P55/TO12 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VCC X1A X0A MOD0 MOD1 X0 X1 VSS RST P00/INT20 P01/INT21 P02/INT22 P03/INT23 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P10/INT10 P11/INT11 P12/INT12 P13/INT13 P14/INT28 P15/INT29 P16/INT2A P17/INT2B P20 P21 P22 P24/SI P25/SO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P54/TO11/LCLK P53/PWM22 P52/PWM21 P51/PWM12 P50/PWM11 COM3/P81 COM2/P80 COM1 COM0 V0 V1 V2 V3 P83 P82 SEG00 SEG01 SEG02 SEG03 SEG04 SEG05 VSS SEG06 SEG07 SEG08 SEG09 SEG10 SEG11 SEG12 SEG13 P26/SCK P30/SEG31 P31/SEG30 P32/SEG29 P33/SEG28 P34/SEG27 P35/SEG26 P36/SEG25 P37/SEG24 P40/SEG23 P41/SEG22 P42/SEG21 P43/SEG20 P44/SEG19 P45/SEG18 P46/SEG17 P47/SEG16 SEG15 SEG14 VCC (FPT-100P-M06) (Continued) 7 MB89650AR Series (Continued) (Top view) X0A X1A VCC P75 P74 P73 P72/BUZ P71/EC2 P70/EC1 AVR AVCC P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2 P61/AN1 P60/AN0 AVSS P57/TO22 P56/TO21/HCLK P55/TO12 P54/TO11/LCLK P53/PWM22 MOD0 MOD1 X0 X1 VSS RST P00/INT20 P01/INT21 P02/INT22 P03/INT23 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P10/INT10 P11/INT11 P12/INT12 P13/INT13 P14/INT28 P15/INT29 P16/INT2A P17/INT2B P20 P21 P22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 O8 CE A10 N.C. OE N.C. A11 A9 121 122 123 124 125 126 127 128 129 130 131 132 101 102 103 104 112 111 110 109 108 107 106 105 A0 A1 A2 N.C. N.C. A3 A4 A5 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P52/PWM21 P51/PWM12 P50/PWM11 COM3/P81 COM2/P80 COM1 COM0 V0 V1 V2 V3 P83 P82 SEG00 SEG01 SEG02 SEG03 SEG04 SEG05 VSS SEG06 SEG07 SEG08 SEG09 SEG10 VSS O7 O6 O5 O4 O3 O2 114 A7 120 119 118 117 116 115 A13 A14 A12 VCC VPP • Pin assignment on package top (MB89PV650A only) Pin no. 101 102 103 104 105 106 107 108 Pin name VPP A12 A7 A6 A5 A4 A3 N.C. Pin no. 109 110 111 112 113 114 115 116 Pin name N.C. A2 A1 A0 O1 O2 O3 VSS Pin no. 117 118 119 120 121 122 123 124 Pin name O4 O5 O6 O7 O8 CE A10 N.C. Pin no. 125 126 127 128 129 130 131 132 Pin name OE N.C. A11 A9 A8 A13 A14 VCC N.C.:Internally connected. Do not use. 8 P24/SI P25/SO P26/SCK P30/SEG31 P31/SEG30 P32/SEG29 P33/SEG28 P34/SEG27 P35/SEG26 P36/SEG25 P37/SEG24 P40/SEG23 P41/SEG22 P42/SEG21 P43/SEG20 P44/SEG19 P45/SEG18 P46/SEG17 P47/SEG16 SEG15 SEG14 VCC SEG13 SEG12 SEG11 (MQP-100C-P02) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A8 A6 113 O1 MB89650AR Series s PIN DESCRIPTION Pin no. QFP* 4 5 6 7 8 9 1 MQFP*2 LQFP*3 1 2 3 4 5 6 Pin name MOD0 MOD1 X0 X1 VSS RST Circuit type Function Operating mode selection pins Connect to VSS (GND) when using. Main clock crystal oscillator pins (Max 10 MHz) Power supply (GND) pin Reset input pin General-purpose I/O ports Also serve as an external interrupt 2 input (wake-up function). External interrupt 2 input (INT20 to INT27) is hysteresis input while port input (P00 to P07) is CMOS input. General-purpose I/O ports Also serve as an external interrupt 1 input. External interrupt 1 input (INT10 to INT13) is hysteresis input while port input (P10 to P13) is CMOS input. General-purpose I/O ports Also serve as an external interrupt 2 input (wake-up function). External interrupt 2 input (INT28 to INT2B) is hysteresis input while port input (P14 to P17) is CMOS input. General-purpose I/O ports General-purpose I/O ports The output type can be switched between N-ch opendrain and CMOS. These ports also serve as an 8-bit serial I/O. The P26/SCK pin is a CMOS input type when it functions as the port input (P26) while the pin is a hysteresis input type when it functions as the serial clock input (SCK). General-purpose I/O ports Also serve as an LCD controller/driver segment output. LCD controller/driver segment output pins J A  J 10 to 17 7 to 14 P00/INT20 to P07/INT27 F 18 to 21 15 to 18 P10/INT10 to P13/INT13 F 22 to 25 19 to 22 P14/INT28 to P15/INT2B F 26 to 28 23 to 25 P20 to P22 C 29, 30, 31 26, 27, 28 P24/SI, P25/SO, P26/SCK F 32 to 47 48, 49 29 to 44 45, 46 P36/SEG31 to P47/SEG26 SEG15, SEG14 H I *1 : FPT-100P-M06 *2 : FPT-100P-M05 *3 : MQP-100C-P02 (Continued) 9 MB89650AR Series (Continued) Pin no. QFP*1 50 51 to 58 59 60 to 65 66, 67 68 to 71 72, 73 74, 75 76 to 79 80, 81, 82, 83 84 85 to 92 93 94 95, 96 97, 98 to 100 1 2 3 MQFP*2 LQFP*3 47 48 to 55 56 57 to 62 63, 64 65 to 68 69, 70 71, 72 73 to 76 77, 78, 79, 80 81 82 to 89 90 91 92, 93 94, 95 to 97 98 99 100 VCC SEG13 to SEG06 VSS SEG05 to SEG00 P82, P83 V3 to V0 COM0, COM1 COM2/P80, COM3/P81 P50/PWM11 to P53/PWM22 P54/TO11/LCLK, P55/TO12, P56/TO21/HCLK, P57/TO22 AVSS P60/AN0 to P67/AN7 AVCC AVR P70/EC1, P71/EC2 P72/BUZ, P73 to P75 VCC X1A X0A Pin name Circuit type  I  I C  I H G Power supply pin Function LCD controller/driver segment output pins Power supply (GND) pin LCD controller/driver segment output pins General-purpose I/O ports LCD driving power supply pins LCD controller/driver common output pins General-purpose I/O ports Also serve as an LCD controller/driver common output. General-purpose output ports Also serve as an 8-bit PWM timer. General-purpose output ports Also serve as an 8/16-bit timer. P54 and P56 also serve as a 32.768 kHz oscillation output/10 MHz divide-by-two output. A/D converter power supply (GND) pin General-purpose input ports Also serve as an analog input. A/D converter power supply pin A/D converter reference voltage input pin General-purpose N-ch open-drain I/O ports Also serve as an 8/16-bit timer to input hysteresis. General-purpose N-ch open-drain I/O ports P72 also serves as a buzzer output. Power supply pin Subclock crystal oscillator pins (32.768 kHz) G  E   K D  B *1 : FPT-100P-M06 *2 : FPT-100P-M05 *3 : MQP-100C-P02 10 MB89650AR Series • External EPROM pins (MB89PV650A only) Pin no. 101 102 103 104 105 106 107 110 111 112 113 114 115 116 117 118 119 120 121 122 123 125 127 128 129 130 131 132 108 109 124 126 Pin name VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS O4 O5 O6 O7 O8 CE A10 OE A11 A9 A8 A13 A14 VCC I/O O “H” level output pin Function O Address output pins I O Data input pins Power supply (GND) pin I Data input pins O O O ROM chip enable pin Outputs “H” during standby. Address output pin ROM output enable pin Outputs “L” at all times. Address output pins Address output pin Address output pin EPROM power supply pin Internally connected pins Be sure to leave them open. O O O O N.C. — 11 MB89650AR Series s I/O CIRCUIT TYPE Type X1 Circuit Remarks • Crystal or ceramic oscillation type (main clock) At an oscillation feedback resistor of approximately 1 MΩ/5.0 V X0 A Standby control signal X1A X0A • Crystal or ceramic oscillation type (subclock) MB89PV650A, MB89P657A At an oscillation feedback resistor of approximately 4.5 MΩ/5.0 V B X1A Standby control signal X0A • Crystal or ceramic oscillation type (subclock) MB89653AR/655AR/656AR/657AR At an oscillation feedback resistor of approximately 4.5 MΩ/5.0 V Standby control signal • CMOS I/O R P-ch P-ch C N-ch • Pull-up resistor optional (except P82 and P83) • N-ch open-drain I/O • CMOS input R P-ch D N-ch • Pull-up resistor optional • A/D converter input • CMOS input P-ch Ain N-ch R E • Pull-up resistor optional (Continued) 12 MB89650AR Series (Continued) Type R P-ch P-ch Circuit Remarks • CMOS I/O (when selected as general-purpose ports) P24 to P26 outputs can be switched between CMOS and N-ch open-drain. • When toggled as hysteresis input peripherals. However, SI input excluded. F N-ch • Pull-up resistor optional • CMOS output P-ch G N-ch P-ch R N-ch P-ch N-ch • LCD controller/driver output • CMOS I/O H P-ch N-ch • Pull-up resistor optional P-ch • LCD controller/driver output I N-ch P-ch N-ch J • Hysteresis input • N-ch open-drain output R P-ch K N-ch • Pull-up resistor optional 13 MB89650AR Series s HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “s Electrical Characteristics” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode. 14 MB89650AR Series s PROGRAMMING TO THE EPROM ON THE MB89P657A The MB89P657A is an OTPROM version of the MB89650A series. 1. Features • 32-Kbyte PROM on chip • Options can be set using the EPROM programmer. • Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in each mode such as 32-Kbyte PROM, option area is diagrammed below. Address 0000 H I/O 0080 H RAM 0480 H Not available 8000 H Not available 8006 H 0006 H 0000 H Option area Single chip EPROM mode (Corresponding addresses on the EPROM programmer) PROM 32 KB EPROM 32 KB FFFFH 7FFFH 3. Programming to the EPROM In EPROM mode, the MB89P657A functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. When the operating ROM area for a single chip is 32 Kbytes (8006H to FFFFH) the PROM can be programmed as follows: • Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0006H to 7FFFH (note that addresses 8006H to FFFFH while operating as a single chip assign to 0006H to 7FFFH in EPROM mode). Load option data into addresses 0000H to 0005H of the EPROM programmer. (For information about each corresponding option, see “7. Setting OTPROM Options.”) (3) Program to 0000H to 7FFFH with the EPROM programmer. 15 MB89650AR Series 4. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program. Program, verify +150 °C, 48h Aging Data verification Assembly 5. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 6. EPROM Programmer Socket Adapter Package FPT-100P-M05 FPT-100P-M06 Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 Note : Connect the ROM-100SQF-28DP-8L jumper pin to VSS when using. Depending on the EPROM programmer, inserting a capacitor of about 0.1 µF between VPP and VSS or VCC and VSS can stabilize programming operations. Compatible socket adapter ROM-100SQF-28DP-8L ROM-100QF-28DP-8L2 16 MB89650AR Series 7. Setting OTPROM Options The programming procedure is the same as that for the PROM. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map: • OTPROM option bit map Bit 7 Bit 6 Vacancy 0000H Readable and writable P07 Pull-up 0001H 1: No 0: Yes P37 Pull-up 0002H 1: No 0: Yes P67 Pull-up 0003H 1: No 0: Yes P47 to P44 Pull-up 0004H 1: No 0: Yes Vacancy 0005H Readable and writable Vacancy Readable and writable P06 Pull-up 1: No 0: Yes P36 Pull-up 1: No 0: Yes P66 Pull-up 1: No 0: Yes P43 to P40 Pull-up 1: No 0: Yes Vacancy Readable and writable Bit 5 Vacancy Readable and writable P05 Pull-up 1: No 0: Yes P35 Pull-up 1: No 0: Yes P65 Pull-up 1: No 0: Yes P26 Pull-up 1: No 0: Yes Vacancy Readable and writable Bit 4 Vacancy Readable and writable P04 Pull-up 1: No 0: Yes P34 Pull-up 1: No 0: Yes P64 Pull-up 1: No 0: Yes P25 Pull-up 1: No 0: Yes P17 to P14 Pull-up 1: No 0: Yes Bit 3 Vacancy Readable and writable P03 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes P63 Pull-up 1: No 0: Yes P24 Pull-up 1: No 0: Yes P13 Pull-up 1: No 0: Yes Bit 2 P81 Pull-up 1: No 0: Yes P02 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P62 Pull-up 1: No 0: Yes P22 Pull-up 1: No 0: Yes P12 Pull-up 1: No 0: Yes Bit 1 P80 Pull-up 1: No 0: Yes P01 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes P61 Pull-up 1: No 0: Yes P21 Pull-up 1: No 0: Yes P11 Pull-up 1: No 0: Yes Bit 0 Single/dualclock system 1: Dual clock 2: Single clock P00 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes P60 Pull-up 1: No 0: Yes P20 Pull-up 1: No 0: Yes P10 Pull-up 1: No 0: Yes Notes : • Set each bit to 1 to erase. • Do not write 0 to the vacant bit. The read value of the vacant bit is 1, unless 0 is written to it. 17 MB89650AR Series s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C256A-20TVM 2. Programming Socket Adapter To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package Adapter socket part number LCC-32(Rectangle) LCC-32(Square) Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 ROM-32LC-28DP-YG ROM-32LC-28DP-S 3. Memory Space Memory space in each mode, such as 32-Kbyte PROM, option area is diagrammed below. Address 0000 H I/O 0080 H RAM 0480 H Not available 8000 H Not available 8006 H 0006 H 0000 H Option area Single chip Corresponding addresses on the EPROM programmer PROM 32 KB EPROM 32 KB FFFFH 7FFFH 4. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0006H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer. 18 MB89650AR Series s BLOCK DIAGRAM Time-base timer Output port P50/PWM11 P51/PWM12 P52/PWM21 P53/PWM22 X0 X1 Main clock oscillator 8-bit PWM timer 1 Clock controller 8-bit PWM timer 2 X0A X1A Subclock oscillator (32.768 kHz) 8-bit timer/ counter 4 P57/TO22 RST Internal bus Reset circuit P30/SEG31 to P37/SEG24 P40/SEG23 to P47/SEG16 SEG00 to SEG15 COM0, COM1 COM2/P80, COM3/P81 8 I/O port 8-bit timer/ counter 3 P56/TO21 /HCLK P71/EC2 8 16 2 2 32 8-bit timer/ counter 2 P55/TO12 2 2 LCD controller/driver 8-bit timer/ counter 1 P54/TO11 /LCLK P70/EC1 V0 to V3 4 Buzzer output 3 2 P72/BUZ P73 to P75 P82, P83 P24/SI P25/SO P26/SCK LCD display RAM (16 × 8 bits) 8-bit serial I/O 8 8 4 RAM External interrupt 2 (wake-up function) 4 P00/INT20 to P07/INT27 P14/INT28 to P17/INT2B P10/INT10 to P13/INT13 P20 to P22 F2MC-8L CPU 4 External interrupt 1 4 3 ROM I/O port Other pins MOD × 2, VCC × 2 VSS × 2 AVCC, AVSS, AVR 8-bit A/D converter 8 8 P60/AN0 to P67/AN7 Input port 19 MB89650AR Series s CPU CORE 1. Memory Space The microcontrollers of the MB89650AR series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89650AR series is structured as illustrated below. Memory Space MB89PV650A MB89P657A I/O 0080H 0100H 01FFH RAM 1 KB Register MB89653AR 0000H I/O 0080H 0100H 0180H 01FFH 0280H RAM 256 B Register MB89655AR 0000H I/O 0080H 0100H RAM 512 B Register MB89656AR 0000H I/O 0080H 0100H 01FFH 0380H RAM 768 B Register MB89657AR 0000H I/O 0080H 0100H 01FFH RAM 1 KB Register 0000H 0480H 0480H Not available 8006H Not available Not available Not available 8006H A000H Not available External ROM* 32 KB E000H FFFFH FFFFH ROM 8 KB C000H ROM 24 KB ROM 32 KB FFFFH ROM 16 KB FFFFH FFFFH *: This is an internal PROM on the MB89P657A. Since addresses 8000H to 8005H for the MB89P657A comprise an option area, do not use this area for the MB89PV650A. 20 MB89650AR Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): Accumulator (A): Temporary accumulator (T): Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS): A 16-bit register for indicating instruction storage positions A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register for index modification A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area A 16-bit register for storing a register pointer, a condition code 16 bits PC A T IX EP SP PS : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status Initial value FFFDH Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, 0 = 11 Other bits are undefined. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) Structure of the Program Status Register 15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 3 N 2 Z 1 V 0 C Vacancy Vacancy Vacancy IL1, 0 RP CCR 21 MB89650AR Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area Lower OP codes b1 ↓ b0 ↓ RP “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 IL0 0 1 0 1 Interrupt level 1 2 3 Low = no interrupt High-low High N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise. V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. 22 MB89650AR Series The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 16 banks can be used on the MB89653AR (RAM 256 × 8 bits). The bank currently in use is indicated by the register bank pointer (RP). Note:The number of register banks that can be used varies with the RAM size. Up to a total of 32 banks can be used on other than the MB89653AR. Register Bank Configuration This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 16 banks Memory area 23 MB89650AR Series s I/O MAP Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH (W) (R) (R/W) (R/W) (R/W) (W) ICR6 PDR6 PDR7 CHG2 CNTR1 COMP1 (R/W) PDR5 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) SCC SMC WDTC TBTC WCR PDR3 DDR3 PDR4 DDR4 T4CR T3CR T4DR T3DR Read/write (R/W) (W) (R/W) (W) (R/W) (R/W) Register name PDR0 DDR0 PDR1 DDR1 PDR2 DDR2 Register description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register Port 2 data register Port 2 data direction register Vacancy System clock control register System mode control register Watchdog time control register Time-base timer control register Watch prescaler control register Port 3 data register Port 3 data direction register Port 4 data register Port 4 data direction register Timer 4 control register Timer 3 control register Timer 4 data register Timer 3 data register Vacancy Vacancy Port 5 data register Vacancy Vacancy Vacancy Port 6 input control register Port 6 data register Port 7 data register Port 2 switching register PWM 0/1 control register PWM 0/1 compare register (Continued) 24 MB89650AR Series (Continued) Address 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H to 5FH 60H to 6FH 70H 71H 72H 73H 74H to 7BH 7CH 7DH 7EH 7FH Note : Do not use vacancies. (W) (W) (W) ILR1 ILR2 ILR3 (R/W) (R/W) (R/W) (R/W) (W) VRAM LCR1 LCR2 PDR8 DDR8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ADC1 ADC2 ADCD EIE1 EIF1 EIE2 EIF2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) T2CR T1CR T2DR T1DR SMR SDR Read/write (R/W) (W) Register name CNTR2 COMP2 Register description PWM 2/3 control register PWM 2/3 compare register Vacancy Vacancy Timer 2 control register Timer 1 control register Timer 2 data register Timer 1 data register Serial mode register Serial data register Vacancy Vacancy Vacancy A/D converter control register 1 A/D converter control register 2 A/D converter data register External interrupt 1 enable register External interrupt 1 flag register External interrupt 2 enable register External interrupt 2 flag register Vacancy Display data RAM LCD controller/driver control register 1 LCD controller/driver control register 2 Port 8 data register Port 8 data direction register Vacancy Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Vacancy 25 MB89650AR Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Power supply voltage A/D converter reference input voltage LCD power supply voltage Input voltage Output voltage Symbol VCC AVCC AVR V0 to V3 VI VI2 VO VO2 Value Min VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3          –40 –55 Max VSS + 7.0 VSS + 7.0 VSS + 7.0 VCC + 0.3 VSS + 7.0 VCC + 0.3 VSS + 7.0 20 4 100 40 –20 –4 –50 –20 300 +85 +150 Unit V *1 V V V V V V mA mA mA mA mA mA mA mA mW °C °C Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) V0 to V3 must not exceed VCC. Except P70 to P75*2 P70 to P75 Except P70 to P75*2 P70 to P75 Remarks “L” level maximum output current IOL “L” level average output current “L” level total maximum output current “L” level total average output current “H” level maximum output current IOLAV ∑IOL ∑IOLAV IOH “H” level average output current IOHAV “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature ∑IOH ∑IOHAV PD TA Tstg *1 : Use AVCC and VCC set at the same voltage. Take care so that AVR does not exceed AVCC + 0.3 V and AVCC does not exceed VCC, such as when power is turned on. *2 : VI and VO must not exceed VCC + 0.3 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 26 MB89650AR Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Symbol Value Min 2.2* Power supply voltage VCC AVCC 2.7* 1.5 A/D converter reference input voltage LCD power supply voltage Operating temperature AVR V0 to V3 TA 0.0 VSS –40 Max 6.0* 6.0* 6.0 AVCC VCC +85 Unit V V V V V °C LCD power supply range (The optimum value is dependent on the LCD element in use.) Remarks Normal operation assurance range* MB89653AR/655AR/656AR/657AR Normal operation assurance range* MB89PV650A/P657A Retains the RAM state in stop mode * : These values vary with the operating frequency, instruction cycle, and analog assurance range. See “Operating Voltage vs. Main Clock Operating Frequency” and “5. A/D Converter Electrical Characteristics.” 6 Analog accuracy assured in the AVCC = 3.5 V to 6.0 V range 5 Operation assurance range Operating voltage (V) 4 3 2 1 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 Main clock operating frequency (at an instruction cycle of 4/FCH) (MHz) 4.0 2.0 0.8 Minimum execution time (instruction cycle) (ms) 0.4 Note: The shaded area is assured only for the MB89653A/655A/656A/657A. Operating Voltage vs. Main Clock Operating Frequency ”Operating Voltage vs. Main Clock Operating Frequency” indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH. Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. 27 MB89650AR Series WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 28 MB89650AR Series 3. DC Characteristics Parameter Symbol VIH1 Pin P20 to P26, P30 to P37, P40 to P47, P60 to P67, P80 to P83 P72 to P75 P00 to P07, P10 to P17, RST, MOD0, MOD1, P26 (at SC input) P70, P71 P20 to P26, P30 to P37, P40 to P47, P60 to P67, P72 to P75, P80 to P83 P00 to P07, P10 to P17, P26 (at SC input), P70, P71, RST, MOD0, MOD1 P24 to P26 (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Condition  Value Min 0.7 VCC Typ  Max VCC + 0.3 Unit Remarks V Without pull-up resistor VIH2 “H” level input voltage VIHS  0.7 VCC  VSS + 6.0 V  0.8 VCC  VCC + 0.3 V Without pull-up resistor VIHS2  0.8 VCC  VSS + 6.0 V VIL “L” level input voltage VIS  VSS − 0.3  0.3 VCC V — VSS − 0.3  0.2 VCC V Open-drain output pin application voltage “H” level output voltage “L” level output voltage VD — VSS − 0.3 VSS − 0.3   VSS + 0.3 V N-ch open-drain VD2 P70 to P75  VSS + 6.0 V VOH P00 to P07, P10 to P17, P20 to P26, P30 to P37, IOH = –2.0 mA P40 to P47, P50 to P57, P80 to P83 P00 to P07, P10 to P17, P20 to P26, P30 to P37, IOL = 4.0 mA P40 to P47, P50 to P57, P70 to P75, P80 to P83 P00 to P07, P10 to P17, P20 to P26, P30 to P37, P40 to P47, P60 to P67, 0.0 V < VI < VCC P70 to P75, P80 to P83, MOD0, MOD1, RST P00 to P07, P10 to P17, P20 to P26, P30 to P37, VI = 0.0 V P40 to P47, P60 to P67, P70 to P75, P80 to P81 4.0   V VOL   0.4 V Input leakage current (Hi-z output ILI leakage current) Pull-up resistance RPULL   ±5 Without µA pull-up resistor 25 50 100 kΩ With pull-up resistor (Continued) 29 MB89650AR Series (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol ICC1 Pin Condition FCH = 10 MHz VCC = 5.0 V tinst*2 = 0.4 µs FCH = 10 MHz VCC = 3.0 V tinst*2 = 6.4 µs FCH = 10 MHz VCC = 5.0 V tinst*2 = 0.4 µs FCH = 10 MHz VCC = 3.0 V tinst*2 = 6.4 µs Value Min — Typ 12 Max 20 Unit Remarks mA MB89653AR/ 655AR/656AR/ 657AR/ PV650A MB89P657A ICC2 — — 1.0 1.5 3 2 2.5 7 mA mA mA Sleep mode ICCS1 — ICCS2 — 0.5 1.5 mA MB89653AR/ 655AR/656AR/ 657AR/ PV650A MB89P657A VCC ICCL Power supply current*1 FCL = 32.768 kHz, VCC = 3.0 V Subclock mode FCL = 32.768 kHz, VCC = 3.0 V Subclock sleep mode FCL = 32.768 kHz, VCC = 3.0 V • Watch mode • Main clock stop mode at dual- clock system TA = +25°C • Subclock stop mode • Main clock stop mode at single- clock system FCH = 10 MHz, when A/D conversion is activated FCH = 10 MHz, TA = +25°C, when A/D conversion is stopped — — 50 500 15 100 700 50 µA µA µA ICCLS — ICCT — 3 15 µA ICCH — — 1 µA IA AVCC IAH — 1.5 3 mA — — 1 µA (Continued) 30 MB89650AR Series (Continued) Symbol RLCD (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Pin Condition Between VCC and V0 at VCC = 5.0 V Value Min 300  V1 to V3 = 5.0 V SEG0 to SEG31 V0 to V3, COM0 to 3, SEG0 to SEG31 Other than AVCC, AVSS, VCC, and VSS  f = 1 MHz   —   10 15 ±1  kΩ µA pF Typ 500  Max 750 Unit Remarks Parameter LCD divided resistance  COM0 to COM03 kΩ kΩ COM0 to COM3 RVCOM output impedance SEG0 to SEG31 RVSEG output impedance LCD controller/ driver leakage current ILCDL 2.5 Input capacitance CIN *1 : The power supply current is measured at the external clock. *2 : For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” Note : For pins which serve as the LCD and ports (P30 to P37, P40 to P47, and P80 to P81), see the port parameter when these pins are used as ports and the LCD parameter when they are used as LCD pins. 31 MB89650AR Series 4. AC Characteristics (1) Reset Timing (VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol tZLZH Condition — Value Min 48 tHCYL Max — Unit ns Remarks Parameter RST “L” pulse width tZLZH RST 0.2 VCC 0.2 VCC (2) Power-on Reset Value Min — 1 Max 50 — (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol tR tOFF Condition — Unit ms ms Remarks Power-on reset function only Due to repeated operations Parameter Power supply rising time Power supply cut-off time Note : Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR 2.0 V 0.2 V tOFF 0.2 V 0.2 V VCC 32 MB89650AR Series (3) Clock Timing (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol FCH FCL tHCYL tLCYL PWH PWL PWLH PWLL tCR tCF Pin X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0 — Condition Value Min 1 — 100 — 20 — — Typ — 32.768 — 30.5 — 15.2 — Max 10 — 1000 — — — 10 Unit MHz kHz ns µs ns µs ns External clock External clock External clock Remarks Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time X0 and X1 Timing and Conditions tHCYL PWH tCR 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC tCF PWL Main Clock Conditions When a crystal or ceramic resonator is used When an external clock is used X0 X1 X0 X1 Open 33 MB89650AR Series X0A and X1A Timing and Conditions tLCYL PWLH tCR 0.8 VCC X0A 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC tCF PWLL Subclock Conditions When a crystal or ceramic resonator is used When an external clock is used X0A X1A X0A X1A Open (4) Instruction Cycle Parameter Instruction cycle (minimum execution time) Symbol Value (typical) 4/FCH, 8/FCH, 16/FCH, 64/FCH tinst 2/FCL µs Unit µs Remarks (4/FCH) tinst = 0.4 µs when operating at FCH = 10 MHz tinst = 61.036 µs when operating at FCL = 32.768 kHz Note : When operating at 10 MHz, the cycle varies with the set execution time. 34 MB89650AR Series (5) Serial I/O Timing (VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C) Parameter Serial clock cycle time SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin SCK SCK, SO SI, SCK SCK, SI SCK SCK, SO SI, SCK SCK, SI External shift clock mode Internal shift clock mode Condition Value Min 2 tinst* –200 1/2 tinst* 1/2 tinst* 1 tinst* 1 tinst* 0 1/2 tinst* 1/2 tinst* Max — 200 — — — — 200 — — Unit µs ns µs µs µs µs ns µs µs Remarks * : For information on tinst, see “(4) Instruction Cycle.” Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V t SLOV 2.4 V 0.8 V tIVSH SI 0.7 VCC 0.3 VCC tSHIX 0.7 VCC 0.3 VCC 0.8 V SO External Shift Clock Mode tSLSH SCK 0.8 VCC 0.2 VCC 0.2 VCC tSLOV SO 2.4 V 0.8 V tIVSH SI 0.7 VCC 0.3 VCC tSHIX 0.7 VCC 0.3 VCC tSHSL 0.8 VCC 35 MB89650AR Series (6) Peripheral Input Timing (VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol tILIH1 tIHIL1 tILIH2 tIHIL2 Pin INT10 to INT13, EC1, EC2 INT20 to INT2B Value Min 1 tinst* 1 tinst* 2 tinst* 2 tinst* Max — — — — Unit µs µs µs µs Remarks Parameter Peripheral input “H” pulse width 1 Peripheral input “L” pulse width 1 Peripheral input “H” pulse width 2 Peripheral input “L” pulse width 2 * : For information on tinst, see “(4) Instruction Cycle.” tIHIL1 INT10 to INT13, EC1, EC2 0.2 VCC 0.8 VCC 0.2 VCC tILIH1 0.8 VCC tIHIL2 INT20 to INT2B 0.8 VCC 0.2 VCC 0.2 VCC tILIH2 0.8 VCC 36 MB89650AR Series 5. A/D Converter Electrical Characteristics Symbol (AVCC = VCC = +3.5 V to +6.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Condition — Value Min — — — — Typ — — — — Max 8 ±1.5 ±1.0 ±0.9 Unit Remarks bit LSB LSB LSB mV mV LSB µs µs µA V V µA Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Interchannel disparity A/D mode conversion time Sense mode conversion time Analog port input current Analog input voltage Reference voltage Pin — VOT — VFST AVR = AVCC AVSS – 1.0 LSB AVSS + 0.5 LSB AVSS + 2.0 LSB AVR – 3.0 LSB AVR – 1.5 LSB AVR 0.5 — — 10 AVR AVCC  — — — — — IAIN — — IR AVR = 5.0V, when A/D conversion is activated AVR = 5.0V, when A/D conversion is stopped — 44 tinst* 12 tinst* — — — 100 AN0 to AN7 — 0.0 0.0 — Reference voltage supply current IRH AVR — — 1 µA * : For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” 37 MB89650AR Series (1) A/D Glossary • Resolution Analog changes that are identifiable with the A/D converter. When the number of bits is 8, analog voltage can be divided into 28 = 256. • Linearity error (unit: LSB) The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics • Differential linearity error (unit: LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value • Total error (unit: LSB) The difference between theoretical and actual conversion values Digital output 1111 1111 1111 • 1110 • • • • • • • • • • • • • • • • • • • Theoretical conversion value Actual conversion value (1 LSB × N + VOT) AVR 256 VNT – (1 LSB × N + VOT) 1 LSB V( N + 1 ) T – VNT – 1 1 LSB VNT – (1 LSB × N + 1 LSB) 1 LSB 1 LSB = Linearity error = Differential linearity error = Total error = 0010 0001 0000 VOT VNT V(N + 1)T VFST Analog input Linearity error 0000 0000 0000 38 MB89650AR Series (2) Precautions • Input impedance of the analog input pins The A/D converter used for the MB89650AR series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low (below 10 kΩ). Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 µF for the analog input pin. Analog Input Equivalent Circuit Sample hold circuit . C = 33 pF . Analog input pin Comparator If the analog input impedance is higher than 10 kΩ, it is recommended to connect an external capacitor of approx. 0.1 µF. . R = 6 kΩ . Close for 8 instruction cycles after activating A/D conversion. Analog channel selector • Error The smaller the | AVR – AVSS |, the greater the error would become relatively. 39 MB89650AR Series s EXAMPLE CHARACTERISTICS (1) “L” Level Output Voltage (2) “H” Level Output Voltage VOL (V) 0.5 VOL vs. IOL TA = +25°C VCC = 2.5 V VCC – VOH (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 VCC – VOH vs. IOH TA = +25°C VCC = 2.5 V VCC = 3.0 V 0.4 0.3 0.2 0.1 0.0 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V VCC = 3.0 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 IOH (mA) (3) “H” Level Input Voltage/“L” Level Input Voltage (CMOS Input) VIN vs. VCC TA = +25°C (4) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input) VIN vs.VCC TA = +25°C VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 VIHS VILS 3 4 5 6 7 VCC (V) 3 4 5 6 7 VCC (V) VIHS: Threshold when input voltage in hysteresis characteristics is set to “H” level VILS: Threshold when input voltage in hysteresis characteristics is set to “L” level 40 MB89650AR Series (5) Power Supply Current (External Clock) ICC (mA) 16 14 12 10 8 6 4 2 0 2.0 2.5 ICC1 vs. VCC, ICC2 vs. VCC FCH = 10 MHz TA = +25°C Divide by 4 (ICC1) ICCS (mA) 5.0 4.5 4.0 3.5 Divide by 8 Divide by 16 Divide by 64 (ICC2) 3.0 2.5 2.0 1.5 1.0 0.5 0 2.0 2.5 ICCS1 vs. VCC, ICCS2 vs. VCC F CH = 1 0 MHz TA = +25°C Divide by 4 (ICCS1) Divide by 8 Divide by 16 Divide by 64 (ICCS2) 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) ICCL (µA) 200 180 160 140 120 100 80 60 40 20 0 2.0 2.5 3.0 3.5 ICCL vs. VCC TA = +25°C ICCLS (µA) 50 45 40 35 30 25 20 15 10 5 ICCLS vs. VCC TA = +25°C 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) (Continued) 41 MB89650AR Series (Continued) ICCT (µA) 20 18 16 14 12 10 8 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) ICCT vs. VCC TA = +25°C ICCH (µA) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2.0 2.5 3.0 3.5 ICCH vs. VCC TA = +25°C 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V) IA (µA) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2.0 2.5 3.0 3.5 IA vs. AVCC FCH = 10 MHz TA = +25°C IR (µA) 200 180 160 140 120 100 80 60 40 20 IR vs. AVR TA = +25°C 4.0 4.5 5.0 5.5 6.0 6.5 AVCC (V) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 AVR (V) (6) Pull-up Resistance RPULL (kΩ) 1000 RPULL vs. VCC TA = +25°C 100 10 1 2 3 4 5 6 VCC (V) 42 MB89650AR Series s MASK OPTIONS Part number No. Specifying procedure Pull-up resistors P00 to P07, P10 to P17, P20 to P22, P24 to P26, P30 to P37, P40 to P47, P60 to P67, P70 to P75, P80 to P81 Power-on reset selection With power-on reset Without power-on reset Selection of the oscillation stabilization time initial value Crystal oscillator: 218/FCH (Approx. 26.2 ms*1) Ceramic oscillator: 213/FCH (Approx. 26.2 ms*1) Selection either single- or dual-clock system Single clock Dual clock Selection of a built-in booster*2 Without booster With booster (Segment output switching) 16 segments: Selection of P30 to P37 and P40 to P47 20 segments: Selection of P30 to P37 and P40 to P43 24 segments: Selection of P30 to P37 28 segments: Selection of P30 to P33 32 segments: No port selection MB89653AR MB89655AR MB89656AR MB89657AR Specify when ordering masking MB89P657A MB89PV650A Set with EPROM programmer Setting not possible 1 Can be set per pin. (Select in a group of four bits for P14 to P17, P40 Fixed to without Specify by pin to P43, and P40 to P47.) pull-up resistor (P75 to P70 are available only for without a pull-up resistor.) Selectable With power-on reset Fixed to with power-on reset 2 3 Selectable 218/FC H (Approx. 26.2 ms*1) Fixed to 218/FCH (Approx. 26.2 ms*1) 4 Selectable Setting possible Can be selected from the following six options: -101: Without booster Fixed to dual-clock system 5 Selectable -102: 16 segments -103: 20 segments -104: 24 segments -105: 28 segments -106: 32 segments Fixed to without booster *1 : The value at FCH = 10 MHz *2 : On microcontrollers with a built-in booster, only 1/3 bias can be used. The 1/2 duty cannot be used. Note : Reset is input asynchronized with the internal clock whether with or without power-on reset. 43 MB89650AR Series s ORDERING INFORMATION Part number MB89653APFV MB89655APFV MB89656APFV MB89657APFV MB89P657APFV-101 MB89P657APFV-102 MB89P657APFV-103 MB89P657APFV-104 MB89P657APFV-105 MB89P657APFV-106 MB89653APF MB89655APF MB89656APF MB89657APF MB89P657APF-101 MB89P657APF-102 MB89P657APF-103 MB89P657APF-104 MB89P657APF-105 MB89P657APF-106 MB89PV650ACF Package Remarks 100-pin Plastic LQFP (FPT-100P-M05) 100-pin Plastic QFP (FPT-100P-M06) 100-pin Ceramic MQFP (MQP-100C-P02) 44 MB89650AR Series s PACKAGE DIMENSIONS 100-pin plastic LQFP (FPT-100P-M05) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 16.00±0.20(.630±.008)SQ * 14.00±0.10(.551±.004)SQ 75 51 76 50 0.08(.003) Details of "A" part INDEX 1.50 –0.10 .059 –.004 (Mounting height) 26 +0.20 +.008 100 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) 0˚~8˚ "A" 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 1 25 0.50(.020) 0.20±0.05 (.008±.002) 0.08(.003) M 0.145±0.055 (.0057±.0022) C 2003 FUJITSU LIMITED F100007S-c-4-6 Dimensions in mm (inches) . Note : The values in parentheses are reference values. (Continued) 45 MB89650AR Series 100-pin plastic QFP (FPT-100P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 80 51 81 50 0.10(.004) 17.90±0.40 (.705±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 100 31 1 30 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8˚ 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off) 0.65(.026) 0.32±0.05 (.013±.002) 0.13(.005) M "A" C 2002 FUJITSU LIMITED F100008S-c-5-5 Dimensions in mm (inches) . Note : The values in parentheses are reference values. (Continued) 46 MB89650AR Series (Continued) 100-pin Ceramic MQFP (MQP-100C-P02) 15.00±0.25 SQ (.591±.010) 14.82±0.35 SQ (.583±.014) 0.50±0.15 (.0197±.0060) 0.18±0.05 (.007±.002) PIN No.1 INDEX 0.30(.012) TYP 1.02±0.13 (.040±.005) 10.92(.430) TYP 7.14(.281) TYP 12.00(.472) 17.20(.667) TYP TYP 4.50(.177)SQ TYP 10.92(.430) TYP PAD No.1 INDEX 1.10 –0.25 .043 –.010 +0.45 +.018 12.00(.472)TYP 17.20(.667)TYP 9.94(.392)MAX 0.15±0.05 (.006±.002) C 1994 FUJITSU LIMITED M100002SC-2-2 Dimensions in mm (inches) . Note : The values in parentheses are reference values. 47 MB89650AR Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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