MB89P825

FUJITSU SEMICONDUCTOR DATA SHEET DS07-12513-6E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89820 Series MB89821/823R/825/P825/PV820 s DESCRIPTION MB89820 series is a line of single-chip microcontrollers using the F2MC-8L* CPU core which can operate at low voltage but at high speed. In addition to an LCD controller/driver allowing 200-pixel display the microcontrollers contain a variety of peripheral functions such as timers, a UART, a serial interface, and an external interrupt. The configuration of the MB89820 series is therefore best suited to control of LCD display panels. * : F2MC stands for FUJITSU Flexible Microcontroller. s FEATURES • Minimum execution time : 0.8 µs/5 MHz (VCC = +5.0 V) • F2MC-8L family CPU core Multiplication and division instructions Instruction set optimized for controllers 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc. • LCD controller/driver Max 50 segments × 4 commons Divided resistor for LCD power supply (Continued) s PACKAGES 80 Pin Plastic QFP 80 Pin Plastic MQFP (FTP-80P-M11) (MQP-80C-P01) MB89820 Series (Continued) • Three types of timers 8-bit PWM timer (also usable as a reload timer) 8-bit pulse width count timer (also usable as a reload timer) 20-bit time-base timer • Two serial interfaces 8-bit synchronous serial interface (Switchable transfer direction allows communication with various equipment.) UART (5-, 7-, 8-bit transfer capable) • External interrupt : 2 channels Capable of wake-up from low-power consumption modes (with an edge detection function) • Low-power consumption modes Stop mode (Oscillation stops to minimize the current consumption.) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.) s PRODUCT LINEUP Part number Parameter MB89821 MB89823R MB89825 MB89P825 MB89PV820 Piggyback/ evaluation product for evaluation and development 32 K × 8 bits (external ROM) Classification Mass production product (mask ROM products) ROM size 4 K × 8 bits (internal mask ROM) 8 K × 8 bits (internal mask ROM) 16 K × 8 bits (internal mask ROM) One-time PROM product 16 K × 8 bits (internal PROM, programming with generalpurpose EPROM programmer) RAM size CPU functions 128 × 8 bits Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: I/O ports (N-ch open-drain): I/O ports (N-ch open-drain): I/O ports (CMOS): Input ports: Total: 256 × 8 bits 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.8 µs/5 MHz (VCC = 5.0 V) 7.2 µs/5 MHz (VCC = 5.0 V) 1024 × 8 bits Ports 16 (All also serve as segment pins.)*1 6 6 (5 ports also serve as peripheral I/O.) 4 (1 port also serves as an external interrupt input.) 32 (Max) 8-bit PWM timer 8-bit reload timer operation (toggled output capable) 8-bit resolution PWM operation Operating clock (pulse width count timer output: 0.8 µs, 12.8 µs, 51.2 µs/5 MHz) 8-bit reload timer operation 8-bit pulse width count operation (continuous measurement capable “H” width, “L” width, or single-cycle measurement capable) Operating clock (0.8 µs, 3.2 µs, 25.6 µs/5 MHz) 8-bit pulse width count timer (Continued) 2 MB89820 Series (Continued) Part number MB89821 Parameter MB89823R MB89825 MB89P825 MB89PV820 8-bit serial I/O 8 bits One clock selectable from four transfer clocks (one external shift clock, three internal shift clock, three internal shift clocks: 1.6 µs, 6.4 µs, 25.6 µs/5 MHz) LSB first/MSB first selectability 5-, 7-, 8-bit transfer capable Internal baud-rate generator (Max 78125 bps/5 MHz) Common output: 4 Segment output: 50 (Max) Operating mode: 1/2 bias, 1/2 duty; 1/3 bias, 1/3 duty; 1/3 bias, 1/4 duty LCD display RAM size: 50 × 4 bits Dividing resistor for LCD driving: Built-in (An external resistor selectable) 2 channels (edge selectable) (1 channel also serves as a pulse width count timer input) Sleep mode, stop mode CMOS 2.2 V*3 to 6.0 V 2.7 V to 6.0 V MBM27C256A20TV (LCC package) UART LCD controller/ driver External interrupt Standby mode Process Operating voltage*2 EPROM for use *1: The function is selected by the mask option. *2: Varies with conditions such as the operating frequency. (See section “s Electrical Characteristics.”) *3: The operation at less than 2.2 V is assured separately. Please contact FUJITSU LIMITED. s PACKAGE AND CORRESPONDING PRODUCTS Package FPT-80P-M11 MQP-80C-P01 : Available × × : Not available MB89821 MB89823R MB89825 MB89P825 MB89PV820 × Note: For more information about each package, see section “s Package Dimensions.” 3 MB89820 Series s DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: • On the MB89821, the register bank address upper than 0140H cannot be used. On the MB89823R, MB89825 and MB89P825, each register bank addresses upper than 0180H can be used. • On the MB89P825, addresses BFF0H to BFF6H comprise the option setting area, option settings can be read by reading these addresses. • The stack area, etc., is set at the upper limit of the RAM. 2. Current Consumption • In the case of the MB89PV820, add the current consumed by the EPROM which is connected to the top socket. • However, the current consumption in sleep/stop modes is the same. (For more information, see section “ s E lectrical Characteristics.” 3. Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “s Mask Options.” Take particular care on the following point : Options are fixed on the MB89PV820. 4 s PIN ASSIGNMENT VSS X1 X0 RST MOD1 MOD0 P45/SCK P44/SO P43/SI P42/PWC/INT1 P41/PWM P40 P33 P32 P31 P30/INT0 P25 P24 P23 P22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (Top view) (FPT-80P-M11) P21 P20 VCC P17/SEG49 P16/SEG48 P15/SEG47 P14/SEG46 P13/SEG45 P12/SEG44 P11/SEG43 A10/SEG42 P07/SEG41 P06/SEG40 P05/SEG39 P04/SEG38 P03/SEG37 P02/SEG36 P01/SEG35 P00/SEG34 SEG33 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 V1 V2 V3 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 MB89820 Series 5 MB89820 Series (Top view) SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 V3 V2 V1 X1 X0 VSS RST MOD1 MOD0 P45/SCK P44/SO P43/SI P42/PWC/INT1 P41/PWM P40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 101 102 103 104 105 106 107 108 109 93 92 91 90 89 88 87 86 85 Each pin inside the dashed line is for the MB89PV820 only. SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 VCC SEG30 SEG31 SEG32 SEG33 P00/SEG34 P01/SEG35 P02/SEG36 P03/SEG37 P04/SEG38 P05/SEG39 P06/SEG40 P07/SEG41 P10/SEG42 P11/SEG43 • Pin assignment on package top (MB89PV820 only) Pin no. 81 82 83 84 85 86 87 88 Pin name N.C. VPP A12 A7 A6 A5 A4 A3 Pin no. 89 90 91 92 93 94 95 96 Pin name A2 A1 A0 N.C. O1 O2 O3 VSS Pin no. 97 98 99 100 101 102 103 104 Pin name N.C. O4 O5 O6 O7 O8 CE A10 Pin no. 105 106 107 108 109 110 111 112 Pin name OE N.C. A11 A9 A8 A13 A14 VCC N.C.: Internally connected. Do not use. 6 P33 P32 P31 P30/INT0 P25 P24 P23 P22 P21 P20 P17/SEG49 P16/SEG48 P15/SEG47 P14/SEG46 P13/SEG45 P12/SEG44 (MQP-80C-P01) 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 110 111 112 81 82 83 84 100 99 98 97 96 95 94 MB89820 Series s PIN DESCRIPTION Pin no. QFP*1 3 2 6 5 4 MQFP*2 14 13 18 17 16 X0 X1 MOD0 MOD1 RST C B Operating mode selection pins Connect directly to VSS. Reset I/O pin This pin is an N-ch open-drain type with a pull-up resistor, and a hysteresis input type. “L” is output from this pin by an internal reset source (optional function). The internal circuit is initialized by the input of “L”. General-purpose N-ch open-drain I/O ports Also serve as an LCD controller/driver segment output. The port and segment output are switched by mask option in 8-bit unit. General-purpose N-ch open-drain I/O ports Also serve as an LCD controller/driver segment output. The port and segment output are switched by mask option in 4 to 1-bit unit. General-purpose N-ch open-drain I/O ports A pull-up resistor option is provided. General-purpose input port The input is hysteresis input. Also serves as an external interrupt input (INT0). A pull-up resistor option is provided. General-purpose input ports These pins are a hysteresis input type. A pull-up resistor option is provided. General-purpose I/O port A pull-up resistor option is provided. General-purpose I/O port A pull-up resistor option is provided. Also serves as an 8-bit PWM timer toggle output (PWM). General-purpose I/O port A pull-up resistor option is provided. Also serves as an 8-bit pulse width count timer input (PWC) and an external interrupt input (INT1). The PWC and INT1 input is hysteresis input. General-purpose I/O port A pull-up resistor option is provided. Also serves as an 8-bit serial I/O and a UART data input (SI). The SI input is hysteresis input. Pin name Circuit type A Function Clock crystal oscillator pins 39 to 32 50 to 43 P00/SEG34 to P07/SEG41 D 31 to 24 42 to 35 P10/SEG42 to P17/SEG49 D 22 to 17 16 34 to 29 P20 to P25 28 P30/INT0 F H 15 to 13 27 to 25 P31 to P33 H 12 11 24 23 P40 P41/PWM E E 10 22 P42/PWC/INT1 E 9 21 P43/SI E *1: FPT-80P-M11 *2: MQP-80C-P01 (Continued) 7 MB89820 Series (Continued) Pin no. QFP*1 8 MQFP*2 20 Pin name P44/SO Circuit type E Function General-purpose I/O port A pull-up resistor option is provided. Also serves as a serial I/O and a UART data output (SO). General-purpose I/O port A pull-up resistor option is provided. Also serves as a serial I/O and a UART clock I/O (SCK). The SCK input is hysteresis input. LCD controller/driver segment output pins 7 19 P45/SCK E 73 to 40 5 to 1, SEG0 to 80 to 56, SEG33 54 to 51 9 to 6 COM0 to COM3 VCC VSS G 77 to 74 80 to 78 23 1 G — — — LCD controller/driver common output pins LCD driving power supply pins Power supply pin Power supply (GND) pin 12 to 10 V1 to V3 55 15 *1: FPT-80P-M11 *2: MQP-80C-P01 8 MB89820 Series • External EPROM pins (MB89PV820 only) Pin no. 82 83 84 85 86 87 88 89 90 91 93 94 95 96 98 99 100 101 102 103 104 105 107 108 109 110 111 112 81 92 97 106 Pin name VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS O4 O5 O6 O7 O8 CE A10 OE A11 A9 A8 A13 A14 VCC N.C. I/O O O “H” level output pin Address output pins Function I Data input pins O I Power supply (GND) pin Data input pins O O O O ROM chip enable pin Outputs “H” during standby. Address output pin ROM output enable pin Outputs “L” at all times. Address output pins O O O — EPROM power supply pin Internally connected pins Be sure to leave them open. 9 MB89820 Series s I/O CIRCUIT TYPE Type A X1 Circuit Remarks • Crystal oscillator circuit • At an oscillation feedback resistor of approximately 1 MΩ/5.0 V X0 Standby control signal B C R P-ch • At an output pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V • Hysteresis input N-ch D P-ch N-ch P-ch N-ch • N-ch open-drain output • CMOS input N-ch Port • Segment output optional • CMOS output • CMOS input • Hysteresis input (peripheral input) E R P-ch P-ch N-ch Peripheral Port • Pull-up resistor optional (Continued) 10 MB89820 Series (Continued) Type F R P-ch Circuit Remarks • N-ch open-drain output • CMOS input N-ch • Pull-up resistor optional G P-ch N-ch P-ch N-ch • LCD controller/driver H R • Hysteresis input • Pull-up resistor optional 11 MB89820 Series s HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “s Electrical Characteristics” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode. 7. Note to Noise In the External Reset Pin (RST) If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST) . 12 MB89820 Series s PROGRAMMING TO THE EPROM ON THE MB89P825 The MB89P825 is an OTPROM (one-time PROM) version for the MB89820 series. 1. Features • 16-Kbyte PROM on chip • Options can be set using the EPROM programmer. • Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in EPROM mode is diagrammed below. Address 0000H I/O 0080H RAM 0180H Single chip EPROM mode (Corresponding addresses on EPROM programmer) Not available 8000H Not available BFF0H Option area BFF6H Not available C000H PROM 16 KB FFFFH 0000H Vacancy (Read value FFH) 3FF0H Option area 3FF6H Vacancy (Read value FFH) 4000H EPROM 16 KB 7FFFH 3. Programming to the EPROM In EPROM mode, the MB89P825 functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. • Programming procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 4000H to 7FFFH (note that addresses C000H to FFFFH while operating as a single chip assign to 4000H to 7FFFH in EPROM mode). Load option data into addresses 3FF0H to 3FF5H of the EPROM programmer. (For information about each corresponding option, see “7. OTPROM Option Bit Map.” (3) Program with the EPROM programmer. 13 MB89820 Series 4. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product for a product with a blanked OTPROM microcomputer program. Program, verify Aging +150 ˚C, 48 h Data verification Assembly 5. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 6. EPROM Programmer Socket Adapter Package FPT-80P-M11 Compatible socket adapter ROM-80QF2-28DP-8L3 Inquiry: Sunhayato Corp. : TEL : +81-3-3984-7791 FAX : +81-3-3971-0535 E-mail : adapter@sunhayato.co.jp 14 MB89820 Series 7. OTPROM Option Bit Map Bit 7 Vacancy 3FF0H Readable Bit 6 Vacancy Readable Bit 5 Vacancy Readable Bit 4 Vacancy Readable Bit 3 Vacancy Readable Bit 2 Reset pin output 1: Yes 0: No Vacancy Readable Vacancy Readable P22 Pull-up 1: No 0: Yes P42 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes Bit 1 Oscillation stabilization time 1: 218/FC 0: 214/FC Vacancy Readable Vacancy Readable P21 Pull-up 1: No 0: Yes P41 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes Bit 0 Power-on reset 1: Yes 0: No Vacancy Readable Vacancy Readable P20 Pull-up 1: No 0: Yes P40 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes Vacancy 3FF1H Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable Vacancy Readable P25 Pull-up 1: No 0: Yes P45 Pull-up 1: No 0: Yes Vacancy Readable Vacancy Readable Vacancy Readable P24 Pull-up 1: No 0: Yes P44 Pull-up 1: No 0: Yes Vacancy Readable Vacancy Readable Vacancy Readable P23 Pull-up 1: No 0: Yes P43 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes Readable Vacancy 3FF2H Readable Vacancy 3FF3H Readable Vacancy 3FF4H Readable Vacancy 3FF5H Readable Notes: • Set each bit to 1 to erase. • Do not write 0 to the vacant bit. The read value of the vacant bit is 1, unless 0 is written to it. 15 MB89820 Series s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C256A-20TV 2. Programming Socket Adapter To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sunhayato Corp.) listed below. Package LCC-32 (Rectangle) Adapter socket part number ROM-32LC-28DP-YG Inquiry: Sunhayato Corp. : TEL : +81-3-3984-7791 FAX : +81-3-3971-0535 E-mail : adapter@sunhayato.co.jp 3. Memory Space Memory space in each mode, such as 32 Kbyte PROM, option area is diagrammed below. Address 0000H Single chip I/O Corresponding addresses in EPROM programmer 0080H RAM 0480H Not available 8000H 0000H PROM 32 KB EPROM 32 KB FFFFH 7FFFH 4. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0000H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer. 16 MB89820 Series s BLOCK DIAGRAM X0 X1 20-bit time-base timer Oscillator Clock controller 8-bit PWM timer P41/PWM 8-bit pulse width timer/ counter Port 2 N-ch open-drain I/O port 8-bit serial I/O Noise cancellation Port 4 RST Reset circuit (WDT) Internal bus External interrupt P42/PWC/INT1 6 P20 to P25 P45/SCK P44/SO P43/SI P30/INT0 External interrupt UART 3 P31 to P33 Port 3 I/O port CMOS I/O port P40 RAM N-ch open-drain I/O port Port 0 and port 1 8 P00/SEG34 to P07/SEG41 8 P10/SEG42 to P17/SEG49 LCD controller/driver 34 SEG0 to SEG33 16 F2MC-8L CPU ROM Other pins MOD0, MOD1, VCC, VSS 4 3 COM0 to COM3 V1 to V3 17 MB89820 Series s CPU CORE 1. Memory Space The microcontrollers of the MB89820 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89820 series is structured as illustrated below. Memory Space MB89821 MB89823 MB89825 MB89P825 MB89PV820 0000 H I/O 0080 H Vacancy 00C0 H 0100 H 0140 H Register RAM 192 B 0000 H 0080 H I/O 0000 H 0080 H I/O 0000 H 0080 H RAM 256 B I/O 0000 H 0080 H I/O 0100 H 0180 H Register RAM 256 B 0100 H 0180 H Register 0100 H 0180 H Register RAM 256 B 0100 H Register 0200 H RAM 1 KB 0480 H Unused Unused Unused Unused Unused 8000 H C000 H E000 H F000 H ROM 4 KB FFFFH FFFFH ROM 8 KB ROM 16 KB C000 H External ROM 32 KB PROM 16 KB FFFFH FFFFH FFFFH 18 MB89820 Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): Accumulator (A): Temporary accumulator (T): Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS): A 16-bit register for indicating instruction storage positions A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register for index modification A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area A 16-bit register for storing a register pointer, a condition code Initial value : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFDH Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, IL0 = 11 Other bits are undefined. 16 bits PC A T IX EP SP PS The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) Structure of the Program Status Register 15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 3 N 2 Z 1 V 0 C Vacancy Vacancy Vacancy IL1, 0 RP CCR 19 MB89820 Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area RP Lower OP codes b1 ↓ b0 ↓ "0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag : Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag : Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. IL1, 0 : Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 IL0 0 1 0 1 Interrupt level 1 2 3 Low = no interrupt High-low High N-flag : Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag : Set when an arithmetic operation results in 0. Cleared otherwise. V-flag : Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag : Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. 20 MB89820 Series The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 16 banks can be used on the MB89823R/825 (RAM 256 × 8 bits). The bank currently in use is indicated by the register bank pointer (RP). NoteThe number of register banks that can be used varies with the RAM size. MB89821 MB89823R MB89825 MB89P825 MB89PV820 0100H to 013FH 0100H to 017FH 0100H to 017FH 0100H to 017FH 0100H to 01FFH 8 banks 16 banks 16 banks 16 banks 32 banks Register Bank Configuration This address = 0100 H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 16 banks Memory area 21 MB89820 Series s I/O MAP Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH (R/W) (R/W) SMR SDR (R/W) (W) (R/W) (R/W) (R/W) (R/W) CNTR COMR PCR1 PCR2 RLBR NCCR (R/W) (W) PDR4 DDR4 (R) PDR3 (R/W) (R/W) (R/W) STBC WDTC TBCR (R/W) PDR2 (R/W) PDR1 Read/write (R/W) Register name PDR0 Vacancy Port 1 data register Vacancy Port 2 data register Vacancy Vacancy Vacancy Standby control register Watchdog timer control register Time-base timer control register Vacancy Port 3 data register Vacancy Port 4 data register Port 4 data direction register Vacancy Vacancy PWM timer control register PWM timer compare register PWC pulse width control register 1 PWC pulse width control register 2 PWC reload buffer register PWC noise cancellation control register Vacancy Vacancy Vacancy Vacancy Serial mode register Serial data register Vacancy Vacancy Register description Port 0 data register (Continued) 22 MB89820 Series (Continued) Address 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H to 5FH 60H to 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH Note: Do not use vacancies. (W) (W) (W) ILR1 ILR2 ILR3 (R/W) (R/W) (R/W) VRAM LCR1 SEGR (R/W) EIC1 Read/write (R/W) (R/W) (R/W) (R/W) (R/W) Register name SMC1 SRC SSD SIDR/SODR SMC2 Register description UART serial mode control register 1 UART serial rate control register UART serial status/data register UART serial data register UART serial mode control register 2 Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy External interrupt 1 control register Vacancy Display data RAM LCD controller/driver control register Segment output selection register Vacancy Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Vacancy 23 MB89820 Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = 0.0 V) Parameter Power supply voltage LCD power supply voltage Symbol VCC V3 Value Min VSS – 0.3 VSS – 0.3 VSS – 0.3 Max VSS + 7.0 VSS + 7.0 VCC + 0.3 Unit V V V3 pin VI1 must not exceed VSS + 7.0 V. Except P00 to P07 and P10 to P17 for the MB89P825/PV820, and P20 to P25 without a pull-up resistor P00 to P07 and P10 to P17 (when selected as ports) for the MB89821/ 823R/825, and P20 to P25 without a pull-up resistor P00 to P07 and P10 to P17 for the MB89P825/PV820 VO1 must not exceed VSS + 7.0 V. Except P00 to P07 and P10 to P17 for the MB89P825/PV820, and P20 to P25 without a pull-up resistor P00 to P07 and P10 to P17 (when selected as ports) for the MB89821/ 823R/825, and P20 to P25 without a pull-up resistor P00 to P07 and P10 to P17 for the MB89P825/PV820 Except power supply pins Average value (operating current × operating rate) Except power supply pins Except power supply pins Average value (operating current × operating rate) Except power supply pins Remarks VI1 V Input voltage VI2 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS + 7.0 V3 + 0.3 VCC + 0.3 V VI3 V VO1 V Output voltage VO2 VSS – 0.3 VSS – 0.3 — — — — — — — –40 –55 VSS + 7.0 V3 + 0.3 10 4 40 –5 –2 –10 300 +85 +150 V VO3 “L” level output current “L” level average output current Total “L” level output current “H” level output current “H” level average output current Total “H” level output current Power consumption Operating temperature Storage temperature IOL IOLAV ΣIOL IOH IOHAV ΣIOH PD TA Tstg V mA mA mA mA mA mA mW °C °C WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 24 MB89820 Series 2. Recommended Operating Conditions (VSS = 0.0 V) Parameter Power supply voltage Symbol VCC Value Min 2.2* 1.5 VSS –40 Max 6.0* 6.0 6.0 +85 Unit V V V °C Remarks Normal operation assurance range* Retains the RAM state in stop mode V3 pin LCD power supply range. The optimum value is dependent on the element in use. LCD power supply voltage Operating temperature V3 TA *: The minimum operating power supply voltage varies with the operating frequency. 6 5 Operation assurance range Operating voltage (V) 4 3 2 1 1 2 3 4 5 Clock operating frequency (MHz) 4.0 2.0 1.3 1.0 0.8 Minimum execution time (instruction cycle) (µs) Note: The shaded area is assured only for the MB89821/823R/825. Figure 1 Operating Voltage vs. Clock Operating Frequency Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FC. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 25 MB89820 Series 3. DC Characteristics Symbol (VCC = V3 = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C) Value Unit Remarks Min Typ Max VCC + 0.3*1 Parameter Pin P00 to P07, P10 to P17, P20 to P25, P30 to P33, P40 to P45 RST, MOD0, MOD1, INT0, SCK, SI, PWC/INT1 P00 to P07, P10 to P17, P22 to P25, P30 to P33, P40 to P45 RST, MOD0, MOD1, INT0, SCK, SI, PWC/INT1 Condition VIH “H” level input voltage VIHS — 0.7 VCC*1 — V — 0.8 VCC — VCC + 0.3 V VIL “L” level input voltage VILS — VCC – 0.3 — 0.3 VCC*1 V — VSS – 0.3 — 0.2 VCC V P00 to P07 and P10 to P17 (when selected as ports) for the MB89821/ 823R/825, and P20 to P25 without pullup resistor Open-drain output pin application voltage “H” level output voltage “L” level output voltage VD P20 to P25, P00 to P07, P10 to P17 — VSS – 0.3 — VCC + 6.0 V VOH P40 to P45 P00 to P07, P10 to P17, P20 to P25, P40 to P45 RST MOD0, MOD1, P30 to P33, P40 to P45 IOH = –2 mA 2.4 — — V VOL1 VOL2 IOL = 1.8 mA IOL = 4 mA — — — — — — 0.4 0.4 ±5 V V µA Without pull-up resistor for the MB89821/823R/825 Without pull-up resistor for the MB89P825/PV820 Without pull-up resistor for the MB89821/823R/825 Without pull-up resistor for the MB89P825/PV820 ILI1 Input leakage current (Hi-Z output leakage current) ILI2 MOD0, MOD1, 0.0 V < VI < VCC P00 to P07, P10 to P17, P30 to P33, P40 to P45 P00 to P07, P10 to P17, P20 to P25 P20 to P25 — — ±5 µA — 0.0 V < VI < 6.0 V — — ±1 ±1 µA µA — (Continued) 26 MB89820 Series (Continued) (VCC =V3 = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C) Value Unit Remarks Min Typ Max 25 50 100 kΩ kΩ kΩ kΩ With pull-up resistor Parameter Pull-up resistance Symbol Pin P20 to P25, P30 to P33, P40 to P45, RST COM0 to COM3 SEG0 to SEG49 — V1 to V3, COM0 to COM3, SEG0 to SEG49 Condition RPULL V1 = 0.0 V V1 to V3 = +5.0 V V1 to V3 = +5.0 V Between V3 and VSS Common output RVCOM impedance Segment output RVSEG impedance LCD divided resistance LCD leakage current RLCD — — 30 — — 60 2.5 15 120 ILCDL — — — ±1 µA ICC FC = 5 MHz tinst*3 = 0.8 µs — — 3.5 4.0 5.0 6.5 MB89821, MB89823R, mA MB89825, MB89PV820 mA MB89P825 MB89821, MB89823R, mA MB89825, MB89PV820, MB89P825 µA µA pF MB89821, MB89823R, MB89825 MB89PV820, MB89P825 Power supply current*2 ICCS VCC FC = 5 MHz tinst*3 = 0.8 µs Sleep mode — 1.1 1.7 ICCH TA = +25°C Stop mode Other than VCC and VSS — — 0.1 0.1 5 1 10 15 Input capacitance CIN f = 1 MHz — *1: The input voltage to P00 to P07 and P10 to P17 for the MB89P825/PV820 must not exceed the LCD power supply voltage (V3 pin voltage). *2: The measurement condition of power supply current is as follows: the external clock, open output pins and the external LCD dividing resistor. In the case of the MB89PV820, the current consumed by the connected EPROM and ICE is not included. *3: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” 27 MB89820 Series 4. AC Characteristics (1) Reset Timing (VCC = +5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C) Value Condition Unit Remarks Min Max — 48 tXCYL — ns Parameter RST “L” pulse width Symbol t ZLZH Notes : • tXCYL is the main clock oscillator period. • If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST) . tZLZH RST 0.2 VCC 0.2 VCC (2) Power-on Reset (VSS = 0.0 V, TA = –40°C to +85°C) Parameter Power supply rising time Power supply cut-off time Symbol tR — tOFF 1 — ms Condition Value Min — Max 50 Unit ms Remarks Power-on reset function only Due to repeated operations Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. 2.0 V VCC 0.2 V 0.2 V tOFF 0.2 V tR 28 MB89820 Series (3) Clock Timing (VSS = 0.0 V, TA = –40°C to +85°C) Parameter Clock frequency Clock cycle time Input clock duty ratio* Input clock rising/ falling time Symbol FC tXCYL duty tCR tCF X0 X0, X1 — Pin Condition Value Min 1 200 30 — Typ — — — — Max 5 1000 70 10 Unit MHz ns % ns Crystal or ceramic resonator External clock External clock Remarks *: duty = PWH/tHCYL, PWL/tHCYL X0 and X1 Timing and Conditions tXCYL PWH tCR 0.8 VCC 0.8 VCC tCF PWL X0 0.2 VCC 0.2 VCC 0.2 VCC Clock Conditions When a crystal or ceramic resonator is used When an external clock in use X0 X1 FC X0 X1 Open FC C0 C1 (4) Instruction Cycle Parameter Instruction cycle (minimum execution time) Symbol tinst Value (typical) 4/FC Unit µs Remarks tinst = 0.8 µs when operating at FC = 5 MHz 29 MB89820 Series (5) Serial I/O Timing (VCC = +5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Serial clock cycle time SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin SCK SCK, SO Internal shift clock SI, SCK mode SCK, SI SCK External SCK, SO shift clock mode SI, SCK SCK, SI Condition Value Min 2 tinst* –200 0.5 tinst* 0.5 tinst* 1 tinst* 1 tinst* 0 0.5 tinst* 0.5 tinst* Max — 200 — — — — 200 — — Unit µs ns µs µs µs µs ns µs µs Remarks *: For information on tinst, see “(4) Instruction Cycle.” (6) UART Timing (VCC = +5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Serial clock cycle time SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin SCK SCK, SO Internal shift clock SI, SCK mode SCK, SI SCK External SCK, SO shift clock mode SI, SCK SCK, SI Condition Value Min 2 tinst* –200 0.5 tinst* 0.5 tinst* 1 tinst* 1 tinst* 0 0.5 tinst* 0.5 tinst* Max — 200 — — — — 200 — — Unit µs ns µs µs µs µs ns µs µs Remarks *: For information on tinst, see “(4) Instruction Cycle.” 30 MB89820 Series Internal Shift Clock Mode tSCYC SCK 0.8 V 2.4 V 0.8 V tSLOV SO 2.4 V 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC SI 0.2 VCC External Shift Clock Mode tSLSH tSHSL 0.8 VCC 0.8 VCC SCK 0.2 VCC 0.2 VCC tSLOV SO 2.4 V 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC SI 0.2 VCC 31 MB89820 Series (7) Peripheral Input Timing (VCC = +5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Peripheral input “H” pulse width Peripheral input “L” pulse width Symbol tILIH tIHIL Pin Condition Value Min 2 tinst* — 2 tinst* — µs Max — Unit µs Remarks PWC/INT1 INT0 *: For information on tinst, see “(4) Instruction Cycle.” tILIH 0.8 VCC tIHIL 0.8 VCC PWC/INT1 INT0 0.2 VCC 0.2 VCC 32 MB89820 Series s EXAMPLE CHARACTERISTICS (1) “L” Level Output Voltage (2) “H” Level Output Voltage VOL1 (V) 0.6 TA = +25°C 0.5 0.4 0.3 0.2 0.1 0 VOL vs. IOL VCC = 2.5 V VCC = 3.0 V VCC = 2.0 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V VCC – VOH vs. IOH VCC = 2.5 V VCC – VOH (V) VCC = 2.0 V VCC = 3.0 V 1.0 TA = +25°C 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) 0 0 –1 –2 –3 –4 –5 IOH (mA) (3) “H” Level Input Voltage/“L” Level Input Voltage (CMOS Input) (4) “H” level Input Voltage/“L” Level Input Voltage (CMOS Hysteresis Input) VIN vs. VCC VIN vs. VCC VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1 2 3 4 5 6 7 VCC (V) TA = +25°C VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1 2 3 4 TA = +25°C VIHS VILS 5 6 7 VCC (V) VIHS: Threshold when input voltage in hysteresis characteristics is set to “H” level VILS: Threshold when input voltage in hysteresis characteristics is set to “L” level 33 MB89820 Series (5) Power Supply Current (External Clock) ICC vs. V CC ICC(mA) 5.0 4.5 FC = 5 MHz 4.0 FC = 4.2 MHz 3.5 3.0 2.5 2.0 1.5 FC = 1 MHz 1.0 0.5 0 1 2 3 4 5 6 7 VCC (V) 0.2 0.1 0 1 2 3 4 5 6 7 VCC (V) FC = 3 MHz TA = +25 °C ICCS (mA) 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 FC = 1 MHz FC = 4.2 MHz FC = 3 MHz ICCS vs. VCC TA = +25 °C FC = 5 MHz (6) Pull-up Resistance RPULL (kΩ) 1,000 500 RPULL vs. VCC TA = +25 °C 100 50 10 1 2 3 4 5 6 7 VCC (V) 34 MB89820 Series s MASK OPTIONS Part number No. Specifying procedure Pull-up resistors P20 to P25, P30 to P33, P40 to P45 Power-on reset With power-on reset Without power-on reset Oscillation stabilization time selection (FC = 5 MHz)*1 Approx. 218/FC (Approx. 52.4 ms) Approx. 214/FC (Approx. 3.28 ms) Reset pin output With reset output Without reset output Segment output switching 50 segments: No port selection 49 segments: Selection of P17 48 segments: Selection of P17 to P16 46 segments: Selection of P17 to P14 42 segments: Selection of P17 to P10 34 segments: Selection of P17 to P10 and P07 to P00 MB89821/823R/825 Specify when ordering masking Selectable by pin Selectable MB89P825 Set with EPROM programmer Can be set per pin Can be set MB89PV820 Setting not possible (Fixed) Without pull-up resistor With power-on reset Oscillation stabilization time Approx. 218/FC (Approx. 52.4 ms) With reset output 1 2 3 Selectable Can be set 4 Selectable Can be set 5 Selectable*2 Can be set*3 Can be set*3 *1: The oscillation settling time is generated by dividing the oscillation clock frequency. Since the oscillation period is not stable immediately after oscillation has been started, therefore, the oscillation settling time in the above list should be regarded as a reference. *2: Port selection must be same setting of the segment output selection register of LCD controller. *3: Note that, when ports are set, the input voltage value for the port pins are different from those for mask ROM products. Ports are set by the register setting of the segment output selection register of LCD controller. s ORDERING INFORMATION Part number MB89821PFM MB89823RPFM MB89825PFM MB89P825PFM MB89PV820CF Package 80-pin Plastic QFP (FPT-80P-M11) 80-pin Ceramic MQFP (MQP-80C-P01) Remarks 35 MB89820 Series s PACKAGE DIMENSIONS 80-pin Plastic QFP (FPT-80P-M11) 16.00±0.20(.630±.008)SQ Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. * 14.00±0.10(.551±.004)SQ 60 41 0.145±0.055 (.006±.002) 61 40 0.10(.004) Details of "A" part 1.50 –0.10 .059 –.004 (Mounting height) 0.25(.010) INDEX 0~8˚ 21 +0.20 +.008 80 1 20 "A" 0.13(.005) M 0.65(.026) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) (Stand off) 0.32±0.05 (.013±.002) C 2003 FUJITSU LIMITED F80016S-c-3-6 Dimensions in mm (inches) . Note : The values in parentheses are reference values. (Continued) 36 MB89820 Series (Continued) 80-pin Ceramic MQFP (MQP-80C-P01) 18.70(.736)TYP 12.00(.472)TYP 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) 1.50(.059)TYP 1.00(.040)TYP 4.50(.177) TYP 1.20 –0.20 .047 +0.40 +.016 –.008 INDEX AREA 0.80±0.25 (.0315±.010) 0.80±0.25 (.0315±.010) 1.27±0.13 (.050±.005) 22.30±0.33 (.878±.013) 24.70(.972) TYP 0.30(.012) TYP 18.12±0.20 12.02(.473) (.713±.008) TYP 10.16(.400) 14.22(.560) TYP TYP INDEX AREA 18.40(.724) REF INDEX 6.00(.236) TYP 0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP 0.40±0.10 (.016±.004) 1.50(.059) TYP 1.00(.040) TYP 1.27±0.13 (.050±.005) 0.40±0.10 (.016±.004) 1.20 –0.20 .047 –.008 +0.40 +.016 0.15±0.05 8.70(.343) (.006±.002) MAX C 1994 FUJITSU LIMITED M80001SC-4-2 Dimensions in mm (inches) . Note : The values in parentheses are reference values. 37 MB89820 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0405 © FUJITSU LIMITED Printed in Japan