MB89P945PF

FUJITSU SEMICONDUCTOR DATA SHEET DS07-12536-5E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89940 Series MB89943/945/P945/PV940 s DESCRIPTION The MB89940 series is specially designed for automotive instrumentation applications. It features a combination of two PWM pulse generators and four high-drive-current outputs for controlling a stepping motor. It also contains two analog inputs, two PWM pulse generators and 10-digit LCD controller/driver for various sensor/indicator devices. The MB89940 series is manufactured with high performance CMOS technologies and packaged in a 48-pin QFP . s FEATURES • • • • • • • • • • • • • • • 8-bit core CPU: 4 MHz system clock (8 MHz external, 500 ns instruction cycle) 21-bit timebase timer Watchdog timer Clock generator/controller 16-bit interval timer Two PWM pulse generators with four high-drive-current outputs Two-channel 8-bit A/D converter Three external interrupt Low supply voltage reset External voltage monitor interrupt Two more PWM pulse generators for controlling indicator devices 4-common 17-segment LCD driver/controller Package: 48-pin plastic QFP 48-pin ceramic MQFP , 5.0 V single power supply (VPP required for MB89P945) On-chip voltage regulator for internal 3.0 V power supply (MB89943, MB89945) s PACKAGES 48-pin Plastic QFP 48-pin Ceramic MQFP (FPT-48P-M16) (MQP-48C-P01) MB89940 Series s PRODUCT LINEUP Part number Item Classification ROM size RAM size CPU functions MB89943 MB89945 MB89P945 One-time PROM 16 K × 8 bits (internal ROM) MB89PV940 Piggyback 32 K × 8 bits (external on piggyback) 1 K × 8 bits Mass-produced products (mask ROM products) 8 K × 8 bits 16 K × 8 bits (internal mask ROM) (internal mask ROM) 512 × 8 bits The number of instructions: 136 Instruction cycle: 0.5 µs*1@8 MHz Interrupt response time: 4.0 µs*1@8 MHz Multiply instruction time: 19 instruction cycles Divide instruction time: 21 instruction cycles Direct addressing memory-to/from-register data transfer: 7 instruction cycles Output: Input/Output: 5-bit N-ch open-drain Two 8-bit CMOS schmitt I/Os and 8-bit CMOS I/Os Ports Timebase timer 8-bit/16-bit timer Watchdog Reset Stepping motor controller 8-bit PWM timers External interrupt A/D converter 21 bits Interrupt interval: 1 ms, 4.1 ms, 32.8 ms or 524.3 ms Can be used as two 8-bit timers or one 16-bit timer Operation clock: 1 µs, 16 µs, 256 µs or external *1 Reset interval: Approx. 524 ms to 1049 ms Two 8-bit PWM pulse generators Synchronized 4-channel high current output Operation clock: 250 ns, 500 ns, 1 µs or 4 µs*1 Two 8-bit PWM timers 3 channels, selective positive edge or negative edge trigger 8-bit resolution, two-channel input A/D conversion time : (MB89943/945 : 26 µs*1/8 MHz oscillation, MB89P945/MB89PV940 : 22 µs*1/8MHz oscillation) 4-common and 17-segment outputs Number of outputs programmable Autonomous reset when low supply voltage Reset voltage: 3.3 V, 3.6 V, 4.0 V Interrupts when voltage at external pin is lower than the reference voltage Stop mode and sleep mode 3.5 V to 5.5 V CMOS MBM27C256A-20TVM LCD controller Low supply voltage reset External voltage monitor interrupt Standby modes Operating voltage*2 Process External EPROM *1: Execution times and clock cycle times are dependent on the use of MCU. *2: Varies with conditions such as the operating frequency. (See section “s Electrical Characteristics.”) In the case of the MB89PV940, the voltage varies with the restrictions of the EPROM for use. 2 MB89940 Series s PACKAGE AND CORRESPONDING PRODUCTS Package FPT-48P-M16 MQP-48C-P01 : Available ×: Not available × MB89943 MB89945 MB89P945 MB89PV940 × Note: For more information about each package, see section “s Package Dimensions.” s DIFFERENCES AMONG PRODUCTS 1. Memory Size Prior to evaluating/developing the software for the MB89940 series, please check the differences between the product types. • RAM/ROM configurations are dependent on the product type. • If the bottom address of the stack is set to the upper limit of the RAM address, it should be relocated when changing the product type. 2. Power Dissipation • For the piggyback product, add the power dissipation of the EEPROM on the piggyback. • The power dissipation differs between the product types. 3. Technology The mask ROM product is fabricated with a 0.5 µm CMOS technology whereas the other products with 0.8 µm CMOS technology. Also the mask ROM product contains the on-chip voltage regulator for the internal 3.0 power supply. For details, refer to MB89940 Series Hardware Manual. 4. Mask Option Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “s Mask Options.” • No options are available for the piggyback product. • The power-on reset and reset output options are always activated with the mask ROM product. • Pull-up option must not be specified with the pins used as LCD outputs. 3 MB89940 Series s PIN ASSIGNMENT (Top view) MODE VINT P40/PW P37/FUELI P36/TEMPI AVSS DVSS P35/PWM2M P34/PWM2P P33/PWM1M P32/PWM1P P31/TEMPO AVCC RST P41/COM0 P42/COM1 X0 X1 VCC P43/COM2 P44/COM3 P27/INT2 P26/INT1 P25/INT0 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P24/V3 P23/TO/V2 P22/EC/V1 P21/V0 P20/SEG16 P17/SEG15 VSS P16/SEG14 P15/SEG13 P14/SEG12 P13/SEG11 P12/SEG10 13 14 15 16 17 18 19 20 21 22 23 24 DVCC P30/FUELO P00/SEG00 P01/SEG01 P02/SEG02 P03/SEG03 P04/SEG04 P05/SEG05 P06/SEG06 P07/SEG07 P10/SEG08 P11/SEG09 (FPT-48P-M16) (Continued) 4 MB89940 Series (Continued) (Top view) MODE VINT P40/PW P37/FUELI P36/TEMPI AVSS DVSS P35/PWM2M P34/PWM2P P33/PWM1M P32/PWM1P P31/TEMPO AVCC RST P41/COM0 P42/COM1 X0 X1 VCC P43/COM2 P44/COM3 P27/INT2 P26/INT1 P25/INT0 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 69 70 71 72 73 74 75 76 77 78 79 80 49 50 51 52 60 59 58 57 56 55 54 53 • Pin assignment on package top (MB89PV940 only) Pin no. 49 50 51 52 53 54 55 56 Pin name A15 A12 A7 A6 A5 A4 A3 N.C. Pin no. 57 58 59 60 61 62 63 64 Pin name N.C. A2 A1 A0 O1 O2 O3 VSS Pin no. 65 66 67 68 69 70 71 72 Pin name O4 O5 O6 O7 O8 CE A10 N.C. Pin no. 73 74 75 76 77 78 79 80 Pin name OE N.C. A11 A9 A8 A13 A14 VCC N.C.: Internally connected. Do not use. 5 P24/V3 P23/TO/V2 P22/EC/V1 P21/V0 P20/SEG16 P17/SEG15 VSS P16/SEG14 P15/SEG13 P14/SEG12 P13/SEG11 P12/SEG10 13 14 15 16 17 18 19 20 21 22 23 24 DVCC P30/FUELO P00/SEG00 P01/SEG01 P02/SEG02 P03/SEG03 P04/SEG04 P05/SEG05 P06/SEG06 P07/SEG07 P10/SEG08 P11/SEG09 (MQP-48C-P01) 68 67 66 65 64 63 62 61 MB89940 Series s PIN DESCRIPTION Pin no. QFP* 5 6 48 1 MQFP*2 5 6 48 X0 X1 Pin name Circuit type A Function Pin for connecting the crystal resonator. X0 and X1 can be directly connected to a crystal oscillator. When the oscillation clock is provided to X0 externally, X1 should be left open. The mode input is used for entering the MPU into the test mode. In user applications, MODE is connected to VSS. Applying a reset pulse to this pin forces the MPU to enter the initial state. RST is active low and drives low state when an internal reset occurs. Reset pulses of the duration less than the minimum pulse width may cause the MCU to enter undefined states. These pins have two functions. Their functions can be switched between Port 0 and LCD segment signal outputs by setting the internal registers of the LCD controller. These pins have two functions. Their functions can be switched between Port 1 and LCD segment signal outputs by setting the internal registers of the LCD controller. This pin can be used as the bit 0 of Port 2 or an LCD segment signal output by setting the internal register of the LCD controller. This pin is the bit 1 of Port 2. This pin can also be used for an external LCD bias voltage input. This pin can be used as the bit 2 of Port 2 or the external clock input for the interval timer. This pin can also be used for an external LCD bias voltage input. This pin can be used as the bit 3 of Port 2 or the output for the interval timer. Its function can be switched by setting the internal register of the interval timer. This pin can also be used for an external LCD bias voltage input. This pin can be used as the bit 4 of Port 2 or an external LCD bias voltage input. These pins are used for Port 2. They can also be used for external interrupt inputs. This pin can be used for the bit 0 of Port 3 or the output from PWM3. The function of this pin can be switched by setting the internal register of PWM3. MODE B 2 2 RST C 34 to 27 34 to 27 P00/SEG00 to P07/SEG07 H 26 to 20, 18 26 to 20, 18 P10/SEG08 to P17/SEG15 J 17 17 P20/SEG16 I 16 16 P21/V0 F 15 15 P22/EC/V1 F 14 14 P23/TO/V2 F 13 12, 11, 10 35 13 12, 11, 10 35 P24/V3 P25/INT0 to P27/INT2 P30/FUELO F E D *1: FPT-48P-M16 *2: MQP-48C-P01 6 (Continued) MB89940 Series (Continued) Pin no. 1 MQFP*2 QFP* 37 37 Pin name P31/TEMPO Circuit type G Function This pin can be used for the bit 1 of Port 3 or the output from PWM4. The function of this pin can be switched by setting the internal register of PWM4. This output has a high drive-current capability. These pins are the pair of high-current driver outputs for one of two motor coils. They can be also used for the bits 2 and 3 of Port 3 by setting the internal register of the stepper motor controller. These pins are the pair of high-current driver outputs for one of two motor coils. They can be also used for the bits 4 and 5 of Port 3 by setting the internal register of the stepper motor controller. This analog input is connected to channel 1 of the A/D converter. It can also be used for the bit 6 of Port 3 when this A/D input enable register bit is set to ‘0’. This analog input is connected to channel 0 of the A/D converter. It can also be used for the bit 7 of Port 3 when this A/D input enable register bit is set to ‘0’. This pin has two functions. When this pin is used as an open-drain output of Port 4, the external voltage monitor reset should be in the power down mode. When it is used as the PW input of external voltage monitor reset, the corresponding bit of the port data register should be set to ‘1’. These pins are the LCD common signal outputs. When LCD is not used, these pins can be also used for Port 4. An external capacitor should be connected to this pin for stabilizing the internal 3.0 V power supply. For MB89PV940 and MB89P945, this pin should be left open. VCC VSS The power supply pin for the analog circuit The same voltage should be applied as VCC. The power supply pin for the analog circuit The same voltage should be applied as VSS. The dedicated power supply pin for the high-current driver output The same voltage should be applied as VCC. The dedicated power supply pin for the high-current driver output The same voltage should be applied as VSS. 38, 39 38, 39 P32/PWM1P , P33/PWM1M G 40, 41 40, 41 P34/PWM2P , P35/PWM2M G 44 44 P36/TEMPI M 45 45 P37/FUELI M 46 46 P40/PW L 3, 4 8, 9 47 3, 4 8, 9 47 P41/COM0 to P44/COM3 VINT K — 7 19 1 43 36 7 19 1 43 36 VCC VSS AVCC AVSS DVCC — — — — — 42 42 DVSS — *1: FPT-48P-M16 *2: MQP-48C-P01 7 MB89940 Series • External EPROM pins (MB89PV940 only) Pin no. 49 50 51 52 53 54 55 58 59 60 61 62 63 65 66 67 68 69 70 71 73 75 76 77 78 79 80 64 56 57 72 74 Pin name A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 O4 O5 O6 O7 O8 CE A10 OE A11 A9 A8 A13 A14 VCC VSS N.C. I/O O Address output pins Function I Data input pins O O O O ROM chip enable pin Outputs “H” during standby. Address output pin ROM output enable pin Outputs “L” at all times. Address output pin O O — EPROM power supply pin Power supply (GND) pin Internally connected pins Be sure to leave them open. 8 MB89940 Series s I/O CIRCUIT TYPE Type A X1 Circuit Remarks • Oscillator I/O With feedback resistor of approx. 1 MΩ. X0 Standby control signal B R • Schmitt-trigger input (Pull-down resistance only for MB89943, MB89945) C R P-ch • Open-drain output with pull-up resistor (Approx. 50 kΩ). • Schmitt-trigger input • Hysteresis input N-ch D P-ch • CMOS I/O N-ch E R P-ch Mask Option N-ch • CMOS I/O (Schmitt trigger) • Pull-up resistor optional (Continued) 9 MB89940 Series (Continued) Type F R Mask Option Circuit Remarks • CMOS I/O (Schmitt trigger) • External bias input • Pull-up resistor optional P-ch N-ch Standby control signal P-ch N-ch G P-ch • CMOS I/O (High output current) N-ch H P-ch • CMOS I/O • LCD controller/driver output N-ch Standby control signal P-ch N-ch P-ch N-ch I R P-ch • • • • CMOS I/O LCD controller/driver output Pull-up resistor optional Hysteresis input N-ch Standby control signal P-ch N-ch P-ch N-ch (Continued) 10 MB89940 Series (Continued) Type J R Mask Option Circuit Remarks • CMOS I/O • LCD controller/driver output • Pull-up resistor optional (Except P11/SEG09, P10/SEG08) P-ch N-ch Standby control signal P-ch N-ch P-ch N-ch K N-ch • N-ch open-drain output • LCD controller/driver output P-ch N-ch P-ch N-ch L N-ch • N-ch open-drain output • Analog input M P-ch • CMOS I/O • Analog input N-ch Standby control signal 11 MB89940 Series s HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “s Electrical Characteristics” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. The VINT pin of MB89PV940 and MB89P945 is the only exception. 3. Treatment of Power Supply Pins on Microcontrollers with A/D Converter Connect to be AVCC = VCC and AVSS = VSS even if the A/D converter are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Note to Noise in the External Reset Pin (RST) If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST). 12 MB89940 Series s PROGRAMMING TO THE EPROM ON THE MB89P945 1. Programming MB89P945 Using the EPROM adapter (provided by Sun Hayato Co., Ltd.) and a standard EPROM programmer, user-defined data can be written into the OTPROM and option PROM. The EPROM programmer should be set to MB27C256A20TVM and electro-signature mode should not be used. When programming the data, the internal addresses are mapped as follows. 2. Memory Space Address 0000 H Single chip EPROM mode (Corresponding addresses on the EPROM programmer) 8000 H 0000 H 3FF0 H Option PROM C000 H One Time PROM 16 KB FFFFH 4000 H One Time PROM 16 KB 7FFFH 3. EPROM Programmer Socket Adapter Package FPT-48P-M16 Compatible socket adapter Sun Hayato Co., Ltd. ROM-48QF-28DP-8L3 Inquiry : Sun Hayato Co., Ltd.: FAX : +81-3-5396-9106 (Tokyo) 4. Screening MB89P945 It is recommended that high-temperature aging is performed on the MB89P945 prior to the assembly. Program, verify Aging +150 °C, 48 h Data verification Assembly 13 MB89940 Series 5. Setting OTPROM Options For MB89P945, mask options are described in the internal option PROM area. The table below shows the bit map of the option PROM. The option data can be written by a standard EPROM programmer. • OTPROM option bit map PROM Address Bit 7 Bit 6 Unused Bit 5 Unused Bit 4 Reserved Bit 3 Reset output 1: Active 0: Inactive P13 Pull-up 1: Inactive 0: Active P23 Pull-up 1: Inactive 0: Active Low volt. S1 bit Bit 2 Power-on reset 1: Active 0: Inactive P12 Pull-up 1: Inactive 0: Active P22 Pull-up 1: Inactive 0: Active Low volt. S0 bit Bit 1 Bit 0 3FF0H Unused Oscillation stabilization time 11: 218 TOSC 10: 217 TOSC 01: 214 TOSC Unused Unused 3FF1H P17 Pull-up 1: Inactive 0: Active 3FF2H P27 Pull-up 1: Inactive 0: Active 3FF3H Unused P16 Pull-up 1: Inactive 0: Active P26 Pull-up 1: Inactive 0: Active Unused P15 Pull-up 1: Inactive 0: Active P25 Pull-up 1: Inactive 0: Active Unused P14 Pull-up 1: Inactive 0: Active P24 Pull-up 1: Inactive 0: Active Low volt. PDX bit P21 Pull-up 1: Inactive 0: Active Low volt. LVE bit P20 Pull-up 1: Inactive 0: Active Low volt. 1: Register active 0: Option active Unused Unused Unused 3FF4H Unused 3FF5H Unused 3FF6H Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Notes: • Default values are all ‘1’. • TOSC: One oscillation clock cycle time • When the bit 0 of “3FF3H” is “0”, it activates the option setting for the Low Voltage Reset Control register. • When this option is activated, software setting in the register has no effect. 6. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 14 MB89940 Series s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C256A-20TVM 2. Programming Socket Adapter Package LCC-32(Rectangle) Compatible socket adapter Sun Hayato Co., Ltd. ROM-32LC-28DP-S Inquiry : Sun Hayato Co., Ltd.: FAX : +81-3-5396-9106 (Tokyo) 3. Memory Space The memory space of the piggyback EPROM is mapped onto the internal memory space as shown in the figure below. Address 0000 H Single chip Corresponding addresses on the EPROM programmer 8000 H 0000 H Piggy Back EPROM 32 KB FFFFH 7FFFH For EPROM devices suitable for MB89PV940, please consult Fujitsu. 4. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C256A-20TVM. (2) Load program data into the EPROM programmer at 0000H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer. 15 MB89940 Series s BLOCK DIAGRAM X0 X1 Oscillator Interrupt controller Clock controller Timebase timer Low supply voltage reset Internal bus Reset circuit RST P41/COM0 to P44/COM3 P10/SEG08 to P17/SEG15 P00/SEG00 to P07/SEG07 P20/SEG16 P21/V0 P22/EC/V1 P23/TO/V2 P24/V3 P25/INT0 to P27/INT2 MODE 4 Port 0, 1 and 4 8 8 LCD controller driver Port 4 External voltage monitor interrupt P40/PW 8-bit A/D converter P37/FUELI P36/TEMPI DVCC DVSS Interval timer 3 Stepper motor macro PWM1 PWM2 High-drive-current P32/PWM1P P33/PWM1M P34/PWM2P P35/PWM2M Port 2 RAM PWM3 F2MC-8L core CPU PWM4 P30/FUELO High-drive-current P31/TEMPO ROM Other pins VCC, VSS AVCC, AVSS VINT Port 3 16 MB89940 Series s CPU CORE 1. Memory Space The MB89940 Series has a memory space of 64 Kbytes. All peripheral registers, RAM and ROM areas are mapped onto the 0000H to FFFFH range. The peripheral registers address below 007FH and the RAM addresses the range 0080H to 027FH (0080H to 047FH for MB89PV940). A part of this RAM area is also assigned as the general-purpose registers. The ROM addresses above E000H for MB89943, or C000H for MB89945. The OneTime PROM addresses the range above C000H. The external ROM for the piggy sample addresses the range above 8000H. The reset vector, interrupt vectors and vectors for vector-call instructions are stored in the highest addresses of the memory space. Memory Space MB89943 0000 H Peripheral registers 007F H 0100 H Generalpurpose registers 512 B 007F H 0100 H RAM 0200 H 027F H 0000 H MB89945/P945 0000 H Peripheral registers 007F H Generalpurpose registers 512 B 0100 H RAM 0200 H MB89PV940 Peripheral registers Generalpurpose registers 1 KB RAM 0200 H 027F H 047F H 8000 H C000 H E000 H ROM 8 KB FFFFH FFFFH MB89945 : ROM MB89P945 : OTPROM 16 KB FFFFH External ROM 32 KB 17 MB89940 Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): Accumulator (A): Temporary accumulator (T): Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS): A 16-bit register for indicating instruction storage positions A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register for index modification A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area A 16-bit register for storing a register pointer, a condition code 16 bits PC A T IX EP SP PS : Program counter : Accumulator Initial value FFFDH Indeterminate : Temporary accumulator Indeterminate : Index register : Extra pointer : Stack pointer : Program status Indeterminate Indeterminate Indeterminate I-flag = 0, IL1, 0 = 11 The other bit values are indeterminate. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) Structure of the Program Status Register 15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 3 N 2 Z 1 V 0 C Vacancy Vacancy Vacancy IL1, 0 RP CCR 18 MB89940 Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area Lower OP codes b1 ↓ b0 ↓ RP “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag:Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag:Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared to ‘0’ at the reset. IL1, 0:Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 IL0 0 1 0 1 Interrupt level 1 2 3 Low High-low High N-flag:Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ otherwise. Z-flag:Set to ‘1’ when an arithmetic operation results in 0. Cleared to ‘0’ otherwise. V-flag:Set to ‘1’ if the complement on ‘2’ overflows as a result of an arithmetic operation. Cleared to ‘0’ if the overflow does not occur. C-flag:Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to ‘0’ otherwise. Set to ‘1’ to the shift-out value in the case of a shift instruction. 19 MB89940 Series The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 32 banks can be used on the MB89940 series. The bank currently in use is indicated by the register bank pointer (RP). Register Bank Configuration This address = 0100H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area 20 MB89940 Series s I/O MAP Address 00H 01H 02H 03H 04H to 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H to 17H 18H 19H 1AH 1BH 1CH to 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH (W) (R/W) (R/W) (R/W) (W) (R/W) COMP2 SELR1 SELR2 CNTR3 COMP3 CNTR4 (R/W) (R/W) (R/W) (R/W) (W) ADC1 ADC2 ADCD CNTR COMP1 (R/W) (R/W) (R/W) (R/W) T2CR T1CR T2DR T1DR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (W) (R/W) (R/W) SCC SMC WDTC TBTC LVRC PDR2 PDD2 PDR3 PDD3 PDR4 ADE Read/write (R/W) (W) (R/W) (W) Register name PDR0 PDD0 PDR1 PDD1 Register description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register Vacancy System clock control register Standby mode control register Watchdog timer control register Timebase timer control register Low voltage reset control Port 2 data register Port 2 data direction register Port 3 data register Port 3 data direction register Port 4 data register Port 3 A/D input enable register Vacancy Timer 2 control register Timer 1 control register Timer 2 data register Timer 1 data register Vacancy A/D converter control register 1 A/D converter control register 2 A/D converter data register PWM control register PWM1 compare register Vacancy PWM2 compare register PWM1 select register PWM2 select register PWM3 control register PWM3 compare register PWM4 control register (Continued) 21 MB89940 Series (Continued) Address 2CH 2DH 2EH 2FH 30H 31H to 5FH 60H to 68H 69H to 71H 72H 73H 74H to 7BH 7CH 7DH 7EH 7FH (W) (W) (W) ILR1 ILR2 ILR3 (R/W) (R/W) LCR1 LCR2 (R/W) VRAM Read/write (W) (R/W) (R/W) (R/W) (R/W) Register name COMP4 SELT PFC EIR1 EIR2 Register description PWM4 compare register Selector test register Power fail control register External interrupt control 1 register External interrupt control 2 register Vacancy Display data RAM Vacancy LCD controller/driver 1register LCD controller/driver 2 register Vacancy Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Vacancy 22 MB89940 Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = 0.0 V) Parameter Symbol VCC Rating Min VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 — — — — — — — — — — — — — — — — — –40 –55 Max VSS + 6.5 VSS + 6.5 VSS + 6.5 VCC + 0.3 DVCC + 0.3 VSS + 6.5 VCC + 0.3 VCC + 0.3 DVCC + 0.3 VSS + 6.5 VCC + 0.3 20 50 4 40 100 200 40 100 –20 –50 –4 –40 –50 –200 –20 –100 300 +85 +150 Unit V V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mW °C °C Remarks Power supply voltage AVCC DVCC VI1 VI2 Should not exceed VCC Should not exceed VCC Except P31 to P35 and P41 to P44 P31 to P35 P41 to P44 MB89PV940/945 P41 to P44 MB89943/945 Except P31 to P35 and P41 to P44 P31 to P35 P41 to P44 MB89PV940/945 P41 to P44 MB89943/945 Except P31 to P35 P31 to P35 Except P31 to P35 P31 to P35 Except P31 to P35 P31 to P35 Except P31 to P35 P31 to P35 Except P31 to P35 P31 to P35 Except P31 to P35 P31 to P35 Except P31 to P35 P31 to P35 Except P31 to P35 P31 to P35 Input voltage VI3 VI4 VO1 VO2 Output voltage VO3 VO4 “L” level maximum output current “L” level average output current “L” level total maximum output current “L” level total average output current “H” level maximum output current “H” level average output current “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature IOL IOLAV Σ IOL Σ IOLAV IOH IOHAV Σ IOH Σ IOHAV PD TA Tstg WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 23 MB89940 Series 2. Recommended Operating Conditions (AVCC = VCC = DVCC = 5.0 V, VSS = AVSS = DVSS = 0.0 V) Parameter Symbol VCC AVCC DVCC VCC AVCC DVCC CVINT TA Value Min 3.5 Typ — Max 5.5 Unit Remarks Operating supply voltage range V RAM data retention supply voltage range Smoothing capacitor Operating temperature range 3.0 0.1 –40 — — — 5.5 1.0 +85 V µF °C MB89943/MB89945 only* *: Use either a ceramic capacitor or a capacitor with similar frequency characteristics. The bypass capacitor of VCC pin should be greater than CVINT. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. VINT CVINT Figure1 VINT Pin Connection Diagram 24 MB89940 Series 6 5.5 Operating Voltage (V) 5 Operation assurance range 4 3.5 3 2 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 Oparating frequency (MHz) (At instruction cycle = 4/FCH) 4.0 2.0 0.8 0.5 0.4 Minimum execution time (Instruction cycle) (µs) Figure2 Operating voltage - Operating frequency 25 MB89940 Series 3. DC Characteristics (AVCC = VCC = DVCC = 5.0 V, VSS = AVSS = DVSS = 0.0 V) Parameter Symbol Pin name P00 to P07, P10 to P17, P30 to P37, P40 to P47 RST, MODE, P20 to P27 P00 to P07, P10 to P17, P30 to P37, P40 to P47 RST, MODE, P20 to P27 P40 P41 to P44 P41 to P44 Condition — — — — — — — Value Min 0.7 VCC 0.8 VCC VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 4.0 VCC − 0.5 — — Typ — — — — — — — — — Max VCC + 0.3 VCC + 0.3 0.3 VCC 0.2 VCC VCC + 0.3 VSS + 5.5 VCC + 0.3 — — Unit V V V V V V V V V Remarks “H” level input voltage VIH VIHS VIL VILS VD “L” level input voltage Open-drain output pin application voltage VD2 VD3 VOH MB89PV940/ 945 MB89943/ 945 “H” level output voltage P10 to P17, P20 to P27, IOH = –2.0 mA P30, P36, P37 P31 to P35 IOH = –30, VCC = DVCC VOH2 “L” level output voltage VOL VOL2 P10 to P17, P20 to P27, P30, P36, P37, P40 to IOL = 4.0 mA P44 P31 to P35 IOL = 30 mA, VSS = DVSS — — 0.4 0.5 V V µA Without pull-up option With pull-up option Input leakage current Pull-up resistance LCD internal bias voltage resister IIL1 MODE, P10 to P17, 0.0 V< VI < P20 to P27, P30 to P37, VCC, P40 to P44 VCC = DVCC RST, P12 to P17, P20 to P27 V0-V1, V1-V2, V2-V3 — –5 — +5 RPULL 25 50 100 kΩ RLCD — 50 100 200 kΩ (Continued) 26 MB89940 Series (Continued) (AVCC = VCC = DVCC = 5.0 V, VSS = AVSS = DVSS = 0.0 V) Parameter Symbol Pin name Condition FC = 8 MHz, tinst* = 0.5 µs, ICC = I(VCC) + I(DVCC) FC = 8 MHz, tinst* = 0.5 µs, ICCS = I(VCC) + I(DVCC) in Sleep mode In Stop mode, TA = 25°C, ICCH = I(VCC) + I(DVCC) Value Min — Typ 12 Max 20 Unit Remarks mA MB89PV940 MB89943, mA MB89945, MB89P945 ICC — 12 20 Power supply current ICCS VCC — 3 7 mA ICCH — 5 10 µA Input capacitance CIN — f = 1 MHz — 10 — pF *: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” 27 MB89940 Series ” 4. AC Characteristics (1) Reset Timing (AVSS = VSS = DVSS, TA = –40°C to +85°C) Parameter RST “L” pulse width Symbol tZLZH Condition — Value Min 48 tHCYL Max — Unit ns Remarks tHCYL: One oscillation clock cycle time tZLZH RST 0.8 VCC 0.2 VCC Notes: • If power-on reset option is not activated, the external reset signal must be kept asserted until the oscillation is stabilized. • If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST). (2) Power-on Profile (AVSS = VSS = DVSS, TA = –40°C to +85°C) Parameter Power supply voltage rising time Power supply voltage rising time Power-off minimum period tHCYL: One oscillation clock cycle time Symbol tR tR tOFF Condition — — — Value Min — — 1 Max 50 219 tHCYL — Unit ms ns ms Remarks MB89PV940, MB89P945 MB89943, MB89945 Note: Power supply voltage should reach the minimum operation voltage within the specified default duration of the oscillation stabilization time. tR 3.5 V 0.2 V tOFF 0.2 V 0.2 V VCC 28 MB89940 Series (3) Clock Timing (AVSS = VSS = DVSS, TA = –40°C to +85°C) Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time Symbol FC tCYC tWH tWL tCR tCF Condition Value Min 1 125 Max 8 1000 — 10 Unit MHz ns ns ns Remarks — 20 — X0 and X1 Timing and Conditions tCYC tWL tCR 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC tCF tWL Clock Conditions When a crystal or ceramic resonator is used When an external clock is used X0 X1 X0 X1 Open (4) Instruction Cycle Parameter Symbol Value (typical) 4/FC, 8/FC, 16/FC, 64/FC Unit µs Remarks (4/FC) tinst = 0.5 µs when operating at FC = 8 MHz Instruction cycle tinst (minimum execution time) Note : When operating at 8 MHz, the cycle varies with the set execution time. 29 MB89940 Series (5) Peripheral Input Timing (AVSS = VSS= DVSS, TA = –40°C to +85°C) Parameter Peripheral input “H” pulse width Peripheral input “L” pulse width Symbol tWH tWL Pin name INT0, INT1, INT2, EC INT0, INT1, INT2, EC Value Min 2 tinst* 2 tinst* Max — — Unit µs µs Remarks *: For information on tinst, see “(4) Instruction Cycle.” tWL 0.8 VCC INT0, INT1, INT2, EC 0.8 VCC 0.2 VCC tWL 0.2 VCC 30 MB89940 Series 5. A/D Converter Electrical Characteristics (AVSS = VSS = DVSS, TA = –40°C to +85°C) Parameter Resolution Total error Nonlinearity error Differential linearity error Zero transition voltage Symbol Pin name Condition Value Min — — Typ — — — — AVSS + 0.5 LSB AVSS + 1.0 LSB AVCC – 1.5 LSB — — — Max 8 ±1.5 ±1.0 ±0.9 AVSS + 2.0 LSB AVSS + 2.0 LSB AVCC Unit bit LSB LSB LSB V V Remarks — — — AVSS – 1.0 LSB AVSS – 1.0 LSB AVCC – 3.0 LSB — VOT — — MB89PV940/ MB89P945 MB89943/ MB89945 MB89943/ MB89945/ MB89PV940/ MB89P945 Full-scale transition VFST voltage Interchannel disparity A/D mode conversion time — V 0.5 44 tinst* 52 tinst* LSB µs µs MB89PV940/ MB89P945 MB89943/ MB89945 — — FC = 8 MHz, IA = I(AVCC) A/D in operation FC = 8 MHz, IAH = I(AVCC) A/D stopped — — IA Power supply current IAH Analog input current Analog input voltage range AVCC — 6 8 mA — 5 10 µA µA V IAIN — — 0 — — 10 AVCC *: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” 31 MB89940 Series 6. A/D Converter Glossary • Resolution Analog changes that are identifiable with the A/D converter When the number of bits is 8, analog voltage can be divided into 28 = 256. • Linearity error (unit: LSB) The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics • Differential linearity error (unit: LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value • Total error (unit: LSB) The difference between theoretical and actual conversion values Digital output 1111 1111 1111 • 1110 • • • • • • • • • • • • • • • • • • • Theoretical conversion value Actual conversion value (1 LSB × N + VOT) AVR 256 VNT – (1 LSB × N + VOT) 1 LSB V( N + 1 ) T – VNT – 1 1 LSB VNT – (1 LSB × N + 1 LSB) 1 LSB 1 LSB = Linearity error = Differential linearity error = Total error = 0010 0001 0000 VOT VNT V(N + 1)T VFST Analog input Linearity error 0000 0000 0000 32 MB89940 Series 7. Notes on Using A/D Converter • Input impedance of the analog input pins The A/D converter used for the MB89940 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low (below 10 kΩ). Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 µF for the analog input pin. Analog Input Equivalent Circuit Sample hold circuit . C = 33 pF . Analog input pin Comparator If the analog input impedance is higher than 10 kΩ, it is recommended to connect an external capacitor of approx. 0.1 µF. . R = 6 kΩ . Close for 8 instruction cycles after activating A/D conversion. Analog channel selector • Error The smaller the | AVCC – AVSS |, the greater the error would become relatively. 33 MB89940 Series 8. Low Supply Voltage Reset Electrical Characteristics Parameter Symbol VDL1 Reset voltage VDL2 VDL3 Hysteresis of reset voltage Delay time to reset Supply voltage slew rate VHYS tD dV/dt Value Min 3.0 3.3 3.7 0.1 — — Max 3.6 3.9 4.3 — 2.0 0.1 Unit V V V V µs V/µs Remarks When the voltage is dropping. Refer to the register definition. When the voltage is recovering. 9. External Voltage Monitor Interrupt Electrical Characteristics Parameter Reference voltage Delay time to interrupt Input slew rate Symbol VREF TD dV/dt Value Min 1.18 — — Max 1.38 2.0 0.1 Unit V µs V/µs Refer to the register definition. Remarks 34 MB89940 Series s MASK OPTIONS Part number No. Specifying procedure MB89943/MB89945 Specify when ordering masking Selectable per pin (P20 and P12 to P17 must be set to without pull-up resistor when they are used as LCD outputs.) Fixed to with power-on reset MB89P945 Set with EPROM Programmer MB89PV940 Setting not possible 1 Pull-up resistors P12 to P17, P20 to P27 Can be set per pin Fixed to without pull-up resistor 2 Power-on reset With power-on reset Without power-on reset Main clock oscillation stabilization time selection (when operating at 8 MHz) Approx. 218/FC (Approx. 32.8 ms) Approx. 217/FC (Approx. 16.4 ms) Approx. 214/FC (Approx. 2.0 ms) Reset pin output With reset output Without reset output Setting possible Fixed to with power-on reset Fixed to approx. 218/FC (Approx. 32.8 ms) Fixed to with reset output 3 Selectable Setting possible 4 Fixed to with reset output Setting possible s ORDERING INFORMATION Part number MB89943PF MB89945PF MB89P945PF MB89PV940CF Package 48-pin Plastic QFP (FPT-48P-M16) 48-pin Ceramic MQFP (MQP-48C-P01) Remarks 35 MB89940 Series s PACKAGE DIMENSION 48-pin Plastic QFP (FPT-48P-M16) 17.20±0.40(.677±.016)SQ 12.00 –0.10 .472 –.004 SQ 36 25 +0.30 +.012 Note : Pins width and pins thickness include plating thickness. 0.17±0.06 (.007±.002) Details of "A" part 37 24 2.40 –0.20 .094 –.008 0.15(.006) 0~8° +0.30 +.012 (Mouting height) INDEX 48 13 1.80±0.30 (.071±.012) "A" 1 12 0.25 –0.20 +0.10 +.004 .010 –.008 (Stand off) 0.80(.031) 0.32±0.05 (.013±.002) 0.20(.008) M C 2001 FUJITSU LIMITED F48026S-c-2-3 Dimensions in mm (inches) (Continued) 36 MB89940 Series (Continued) 48-pin Ceramic MQFP (MQP-48C-P01) 17.20(.677)TYP 15.00±0.25 (.591±.010) 14.82±0.35 (.583±.014) 1.50(.059)TYP 1.00(.040)TYP 8.80(.346)REF 0.80±0.22 (.0315±.0087) PIN No.1 INDEX PIN No.1 INDEX 1.02±0.13 (.040±.005) 10.92 –0.0 .430 –0 +0.13 +.005 7.14(.281) 8.71(.343) TYP TYP PAD No.1 INDEX 0.30(.012)TYP 4.50(.177)TYP 1.10 –0.25 .043 –.010 +0.45 +.018 0.40±0.08 (.016±.003) 0.60(.024)TYP 8.50(.335)MAX 0.15±0.05 (.006±.002) C 1994 FUJITSU LIMITED M48001SC-4-2 Dimensions in mm (inches) 37 MB89940 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0209 © FUJITSU LIMITED Printed in Japan