MB89PV190CF

FUJITSU SEMICONDUCTOR DATA SHEET DS07-12538-1E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89990 Series MB89997 s OUTLINE The MB89990 series microcontrollers contain various resources such as timers, external interrupts, and remotecontrol functions, as well as an F2MC*-8L CPU core for low-voltage and high-speed operations. These singlechip microcontrollers are suitable for small devices such as remote controllers incorporating compact packages. *: F2MC stands for FUJITSU Flexible Microcontroller. s FEATURES • Minimum execution time: 0.95 µs at 4.2 MHz (VCC = 2.7 V) • F2MC-8L family CPU core • Two timers 8/16-bit timer/counter 20-bit timebase counter (Continued) s PACKAGE 28-pin Plastic SOP 28-pin Plastic SH-DIP 48-pin Ceramic MQFP (FPT-28P-M17) (DIP-28P-M03) (MQP-48C-P01) MB89990 Series (Continued) • External interrupts Edge detection (Edge selection enabled): 3 channels Low-level interrupt (Wake-up function): 8 channels • Internal remote-control transmission frequency generator • Low-power consumption modes Stop mode (Almost no current consumption occurs because oscillation stops.) Sleep mode (The current consumption is about 1/3 of that during normal operation because the CPU stops.) • Packages SOP-28 and SH-DIP-28 s PRODUCT LINEUP Part number MB89997 Item Classification ROM size 32 K × 8 bits (internal mask ROM) RAM size CPU functions 128 × 8 bits The number of basic instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: I/O port (N channel open drain): I/O port (CMOS): Total: Mass-produced products (mask ROM products) One-time PROM product 16 K × 8 bits (internal PROM, to be programmed with generalpurpose EPROM programmer) 256 × 8 bits 136 8 bits 1 to 3 bytes 1, 8, and 16 bits 0.95 µs at 4.2 MHz 8.57 µs at 4.2 MHz 6 16 (13 serves as resources) 22 For development and evaluation 32 K × 8 bits (external ROM) MB89P195*1 MB89PV190*2 Ports 8/16-bit timer/ counter External interrupt 1 2 channels for 8-bit timer counter or for 16-bit event counter (operation clock: 1.9 µs, 30.4 µs, and 487.6 µs at 4.2 MHz, and external clock) 3 independent channels (edge selection, interrupt vector, and interrupt source flag) Rising edge/falling edge/both edge selectability Used for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.) 8 channels (low-level interrupt only) External interrupt 2 (Wake-up function) Remote-control transmission frequency generation The pulse width and cycle are software-programmable. (Continued) 2 MB89990 Series (Continued) Part number MB89997 Item Low-power consumption (standby mode) Process Power supply voltage*3 EPROM for use 2.2 V to 6.0 V Sleep mode and stop mode CMOS 2.7 V to 6.0 V MBM27C256A-20TVM MB89P195*1 MB89PV190*2 *1 : The MB89P195 microtroller is the one-time product for the MB89190 series which can be also be used for the MB89990 series. *2 : The MB89PV190 microtroller is the evaluation and development product for the MB89190 series which can be also be used for the MB89990 series. *3 : Varies with conditions such as operating frequencies (see “s Electrical Characteristics.”) s PACKAGE AND CORRESPONDING PRODUCTS Package DIP-28P-M03 FPT-28P-M17 MQP-48C-P01 : Available × × MB89997 MB89P195 × MB89PV190 × × * × : Not available * : A socket (manufacturer: Sun Hayato Co., Ltd.) for pin pitch conversion is available. 480F-28SOP-8L: (MQP-48C-P01) → for conversion to FPT-28P-M02 Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403 FAX: (81)-3-5396-9106 Note: For more information on each package, see “s Package Dimensions.” 3 MB89990 Series s DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback model, verify its difference from the model that will actually be used. Take particular care on the following points: • On the MB89997, addresses 0140H to 0180H cannot be used for register banks. • The stack area, etc., is set in the upper limit of the RAM. 2. Current Consumption • In the case of MB89PV190, add the current consumed by the EPROM which is connected to the top socket. • When operated at low speed, a model with an OTPROM (EPROM) will consume more current than a model with a mask ROM. However, current consumption in the sleep/stop mode in the same. (For more information, see “s Electrical Characteristics.”) 3. Mask Options Functions that can be selected as options and how to designate these options vary by model. Before using options check “s Mask Options.” Take particular care on the following points: • The power-on reset option is fixed as “enabled” for MB89P195. • Options are fixed on the MB89PV190. 4 MB89990 Series s PIN ASSIGNMENT (Top view) P04/INT24 P05/INT25 P06/INT26 P07/INT27 TEST RST X0 X1 VSS P37/RCO P36/INT12 P35/INT11 P34/TO/INT10 P33/EC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC P03/INT23 P02/INT22 P01/INT21 P00/INT20 P45 P44 P43 P42 P41 P40 P30 P31 P32 (FPT-28P-M17) (DIP-28P-M03) 5 MB89990 Series (Top view) P35/INT11 N. C. N. C. N. C. N. C. N. C. N. C. N. C. N. C. N. C. 38 48 47 46 45 44 43 42 41 40 39 68 67 66 65 64 63 62 61 37 N. C. V SS P34/TO/INT10 P33/EC P32/(SI) P31/(SO) P30/(SCK) P40/(AN0) P41/(AN1) P42/(AN2) P43/(AN3) P44/(AV SS) P45/(AVR) P00/INT20/(AN4) 1 2 3 4 5 6 7 8 9 10 11 36 35 N. C. N. C. P36/INT12 P37/(BZ)/RCO X1 X0 RST TEST P07/INT27 P06/INT26 P05/INT25 P04/INT24 69 70 71 72 73 74 75 76 Each pin inside the dashed line is for MB89PV190/PV190A units only. 60 59 58 57 56 55 54 53 34 33 32 31 30 29 28 27 26 77 78 79 80 49 50 51 12 13 14 52 25 23 P02/INT22/(AN6) 24 P03/INT23/(AN7) 15 16 17 18 19 20 21 N. C. P01/INT21/(AN5) N. C. N. C. N. C. N. C. N. C. N. C. (MQP-48C-P01) • Pin assignment on the package top (MB89PV190/PV190A only) Pin no. 49 50 51 52 53 54 55 56 Pin name VPP A12 A7 A6 A5 A4 A3 N.C. Pin no. 57 58 59 60 61 62 63 64 Pin name N.C. A2 A1 A0 O1 O2 O3 VSS Pin no. 65 66 67 68 69 70 71 72 Pin name O4 O5 O6 O7 O8 CE A10 N.C. Pin no. 73 74 75 76 77 78 79 80 Pin name OE N.C. A11 A9 A8 A13 A14 VCC N.C.: Internally connected. Do not use. Note: Parenthesized pin function is only for the MB89PV190A. 6 N. C. V CC 22 MB89990 Series s PIN DESCRIPTION Pin no. SOP*1, SH-DIP*2 7 8 5 6 MQFP*3 31 32 29 30 Pin name X0 X1 TEST RST B C Test input pin This pin is connected directly to VSS. Reset I/O pin This pin consists of an N-ch open-drain output with a pull-up resistor and hysteresis input. A low level is output from this pin by internal source. The internal circuit is initialized at the input of a low level. General-purpose I/O ports Also serve as external interrupt input pins. External interrupt input is hysteresis input type. General-purpose I/O ports Also serve as external interrupt input. External interrupt input is hysteresis input type. General-purpose I/O port Also serves as a serial I/O clock I/O. The serial I/O clock input is hysteresis input type with a built-in noise filter. General-purpose I/O port Also serves as a serial I/O data output pin. General-purpose I/O port Also serves as a serial I/O data input pin. The serial I/O data input is hysteresis input type with a built-in noise filter. General-purpose I/O port Also serves as an external clock input pin for the 8bit timer/counter. External clock input of the 8-bit timer/counter is hysteresis input type with a built-in noise filter. General-purpose I/O port Also serves as the overflow output and external interrupt input for the 8-bit timer/counter. External interrupt input is hysteresis input type with a built-in noise filter. General-purpose I/O port Also serve as external interrupt input pins. External interrupt input is hysteresis input type with a built-in noise filter. Circuit type A Function Clock oscillation pins 24, 25, 26, 27 1 to 4 12, 13, 23, 24 25 to 28 P00/INT20, P01/INT21, P02/INT22, P03/INT23 P04/INT24 to P07/INT27 P30 G D 17 5 D 16 15 4 3 P31 P32 E D 14 2 P33/EC D 13 1 P34/TO/INT10 D 12, 11 48, 34 P35/INT11, P36/INT12 D *1: FPT-28P-M17 *2: DIP-28P-M03 *3: MQP-48C-P01 (Continued) 7 MB89990 Series (Continued) Pin no. SOP*1, SH-DIP*2 10 18 to 21 23 22 28 9 MQFP*3 33 6 to 9 11 10 18 42 Pin name P37//RCO P40 to P43 P45 P44 VCC VSS Circuit type E F F F — — Function General-purpose I/O port Also serves as remote-control output pin. N-ch open-drain I/O ports N-ch open-drain type I/O port N-ch open-drain type I/O port Power supply pin Power supply (GND) pin *1: FPT-28P-M17 *2: DIP-28P-M03 *3: MQP-48C-P01 8 MB89990 Series • External EPROM pins (MB89PV190 only) Pin no. 49 79 78 50 75 71 76 77 51 52 53 54 55 58 59 60 61 62 63 65 66 67 68 69 70 73 80 64 VPP A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 O4 O5 O6 O7 O8 CE OE VCC VSS Pin name I/O O O “H” level output pin Address output pins Function I Data input pins O O O O ROM chip enable pin Outputs “H” during standby. ROM output enable pin Outputs “L” at all times. EPROM power pin Power supply (GND) pin 9 MB89990 Series s I/O CIRCUIT TYPE Type A X1 X0 Circuit Remarks • At an oscillation feedback registor of approximately 1 MΩ at 5.0 V Standby control signal • When crystal and ceramic oscillators are selected optionally X1 X0 Standby control signal • When CR oscillation is selected optionally B C R P-ch • Output pull-up resistor (P-ch): About 50 kΩ at 5.0 V • Hysteresis input N-ch • Pull-up resistor optional D R P-ch • CMOS output • CMOS input • Hysteresis input (resource input) P-ch N-ch • Pull-up resistor optional (Continued) 10 MB89990 Series (Continued) Type E R P-ch Circuit • CMOS output • CMOS input Remarks P-ch N-ch • Pull-up resistor optional F R P-ch • N-ch open-drain output • Analog input P-ch N-ch Analog input • Pull-up resistor optional (MB89990 series only) • • • • CMOS output CMOS input Hysteresis input (resource input) Analog input G R P-ch P-ch N-ch Analog input • Pull-up resistor optional (MB89990 series only) 11 MB89990 Series s HANDLING DEVICES 1. Preventing Latch-up Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input or output pins other than medium-to high-voltage pins or if higher than the voltage which shows on “ 1. Absolute Maximum Ratings” in “s Electrical Characteristics” is applied between VCC to VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to pull-up or pull-down resistor. 3. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 4. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 5. Precautions when Using an External Clock When an external clock is used, oscillation stabilization time is required even for power-on reset (option selection) and release from stop mode. 12 MB89990 Series s PROGRAMMING TO PROM ON THE MB89P195 The MB89P195 can program data in the internal PROM using a dedicated conversion adaptor and specified general-purpose EPROM programmer. 1. Memory Space Address in normal operation mode EPROM mode (Corresponding addresses on the EPROM programmer) 0000 H I/O 0080 H RAM 0180 H 8000 H Not available 0000 H Free area (Read value FF H) C000 H PROM 16 KB FFFF H 4000 H EPROM 16 KB 7FFF H 2. Specified ROM Programmer Manufacturer, Model Name, and Programming in ROM • Recommended ROM programmer Manufacturer ADVANTEST • Programming procedure (1) Load program data into the ROM programmer at addresses 4000H to 7FFFH. (Addresses 0C000H to 0FFFFH in the operation mode assign to 4000H to 7FFFH in ROM programmer. See the illustration above.) (2) Set the data at addresses 0000H to 3FFFH of the programmer ROM in the ROM programmer, to FFH. (3) To set up the successive-address write mode of the ROM programmer, press the DEVICE, PROG, SET, SELECT, E and SET keys in this order. Note: Program must be started at the address 0000H. For details, contact our Sales Division. Model R4945 13 MB89990 Series 3. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcontroller program. Program, verify Aging +150°C for 48 Hrs. Data verification Assembly 4. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature (one time PROM). For this reason, a programming yield of 100% cannot be assured at all times. 5. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer Part no. Package Compatible socket adapter Sun Hayato Co., Ltd. Minato Electronics Inc. Recommended programmer manufacturer and programmer name MODEL 1890A (ver. 2.2) + OU-910 (ver. 4.1) UNISITE (ver. 5.0 or later) Data I/O Co., Ltd. 3900 (ver. 2.8 or later) 2900 (ver. 3.8 or later) Inquiry: Sun Hayato Co., Ltd. : TEL: (81)-3-3986-0403 FAX: (81)-3-5396-9106 Minato Electronics Inc. : TEL: USA (1)-916-348-6066 JAPAN (81)-45-591-5611 Data I/O Co., Ltd. : TEL: USA/ASIA (1)-206-881-6444 EUROPE (49)-8-985-8580 Recommended MB89P195PF SOP-28 ROM-28SOP-28DP-8L Recommended 14 MB89990 Series s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C256A-20TVM 2. Programming Socket Adapter To program to the EPROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) below. Package LCC-32 (Rectangle) Adapter socket part number ROM-32LC-28DP-S Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403 FAX: (81)-3-5396-9106 3. Memory Space Address in normal operation mode 0000 H I/O 0080 H RAM 0180 H Not available 8000 H Address when writing to EPROM (Corresponding addresses on the EPROM programmer) 0000 H PROM 32 KB EPROM 32 KB FFFF H 7FFF H 4. Programming to the EPROM (1) Set the EPROM programmer to MBM27C256A. (2) Load program data into the EPROM programmer at 0006H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer. 15 MB89990 Series s BLOCK DIAGRAM X0 X1 Main oscillator circuit Remote-control carrier frequency P34/TO/INT10 Internal data bus Clock control 8-bit timer/counter Port 3 P33/EC RST Reset circuit (WDT) P30 to P32 8-bit timer/counter P35/INT11 External interrupt P36/INT12 CMOS I/O port P37/RCO Timebase timer RAM (128 × 8 bits) CMOS I/O port F2MC-8L CPU External interrupt (wake-up function) ROM (32K × 8 bits) Port 0 8 P00/INT20 to P07/INT27 The other pins TEST, VCC, VSS N-ch open drain I/O port Port 4 6 P40 to P45 16 MB89990 Series s CPU CORE 1. Memory Space The microcontrollers of MB89990 series offer 64 Kbytes of memory for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provide immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end of I/O area, that is, near the highest address. Provide the tables of interrupt reset vectors, and vector call instructions toward the highest address within the program area. The memory space of the MB89990 series is structured below: • Memory Space MB89997 0000H 0080H 00C0H I/O Reserved RAM 0100H 0000H 0080H MB89P195 I/O RAM 256 B Register 0200H 0280H 0200H 0280H 0100H 0000H 0080H MB89PV190 I/O RAM 256 B Register 128 B 0100H Register 0140H Not available Not available Not available 8000H ROM 32 KB C000H 8000H ROM ROM 16 KB 32 KB FFFFH 17 MB89990 Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): Accumulator (A): Temporary accumulator (T): A 16-bit-long register for indicating the instruction storage positions A 16-bit-long temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit-long register which performs arithmetic operations with the accumulator. When the instruction is an 18-bit data processing instruction, the lower byte is used. A 16-bit-long register for index modification A 16-bit-long pointer for indicating a memory address A 16-bit-long register for indicating a stack area A 16-bit-long register for storing a register pointer, a condition code Index register (IX): Extra pointer (EP) : Stack pointer (SP) : Program status (PS) : 16 bits PC A T IX EP SP PS : Program counter : Accumulator Initial value FFFDH Indeterminate : Temporary accumulator Indeterminate : Index register : Extra pointer : Stack pointer : Program status Indeterminate Indeterminate Indeterminate I-flag = 0, IL1, 0 = 11 The other bit values are indeterminate. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR) (see the diagram below). • Structure of the Program Status Register 15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 3 N 2 Z 1 V 0 C Vacancy Vacancy Vacancy IL1, 0 RP CCR 18 MB89990 Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. • Rule for Conversion of Actual Addresses of the General-purpose Register Area RP Lower OP codes b1 ↓ b0 ↓ “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to ‘0’ otherwise. This flag is for decimal adjustment instructions. I-flag: IL1, 0: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared to ‘0’ at the rest. Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 IL0 0 1 0 1 Interrupt level 1 2 3 High-low High Low N-flag: Set to ‘1’ if the MSB becomes 1 as the result of an arithmetic operation. Cleared to ‘0’ when the bit is cleared to ‘0’. Z-flag: V-flag: Set to ‘1’ when an arithmetic operation results in 0. Cleared otherwise. Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to ‘0’ if the overflow does not occur. C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to ‘0’ otherwise. Set the shift-out value in the case of a shift instruction. 19 MB89990 Series The following general-purpose registers are provided: General-purpose registers: An 8-bit-long register for storing data The general-purpose registers are 8 bits and located in register banks of the memory. One bank contains eight registers and up to a total of 16 banks can be used on the MB89957 (RAM 128 × 8 bits). The bank currently in use is indicated by the register bank pointer. (RP) Note: The number of register banks that can be used varies with the RAM size. • Register Bank Configuraiton This address = 0100 H + 8 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 16 banks (8 banks for the MB89957) Memory area 20 MB89990 Series s I/O MAP Address 00H 01H 02H to 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH to 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH to 22H 23H 24H 25H to 31H 32H 33H 34H to 7BH 7CH 7DH 7EH 7FH Note: Do not use vacancies. (W) (W) (W) ILR1 ILR2 ILR3 (R/W) (R/W) EIE2 EIF2 (R/W) (R/W) EIC1 EIC2 (R/W) (R/W) (R/W) (R/W) T2CR T1CR T2DR T1DR (R/W) (R/W) RCR1 RCR2 (R/W) (W) (R/W) PDR3 DDR3 PDR4 (R/W) (R/W) (R/W) STBC WDTC TBTC Read/write (R/W) (W) Register name PDR0 DDR0 Register description Port 0 data register Port 0 data direction register Vacancy Standby control register Watchdog timer control register Timebase timer control register Vacancy Port 3 data register Port 3 data direction register Port 4 data register Vacancy Remote-control register 1 Remote-control register 2 Vacancy Vacancy Timer 2 control register Timer 1 control register Timer 2 data register Timer 1 data register Vacancy External interrupt control register 1 External interrupt control register 2 Vacancy External interrupt 2 enable register External interrupt 2 flag register Vacancy Interrupt level register 1 Interrupt level register 2 Interrupt level register 3 Vacancy 21 MB89990 Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Rating (VSS = 0.0 V) Parameter Power supply voltage EPROM program voltage Input voltage Output voltage “L” level maximum output current Symbol VCC VPP VI VO IOL1 IOL2 IOLAV1 “L” level average output current IOLAV2 “L” level total average output current “L” level maximum total output current “H” level maximum output current ΣIOLAV ΣIOL IOH1 IOH2 IOHAV1 “H” level average output current IOHAV2 “H” level total average output current “H” level total maximum output current Power consumption Operating temperature Storage temperature ΣIOHAV ΣIOH PD TA Tstg     –40 –55 –4 –10 –30 200 +85 +150 mA mA mA mW °C °C       8 20 –100 –10 –20 –2 mA mA mA mA mA mA Except P33, P34, and P37 P33, P34, P37 Except P33, P34, and P37 Average value (operating current × operation rate) Except P33, P34, and P37 Average value (operating current × operation rate) Average value (operating current × operation rate) Value Min. VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3    Max. VSS + 7.0 VSS + 13.0 VCC + 0.3 VCC + 0.3 10 20 4 Unit V V V V mA mA mA Except P33 and P34 P33, P34 Except P33 and P34 Average value (operating current × operation rate) P33 and P34 Average value (operating current × operation rate) Average value (operating current × operation rate) Applicable to TEST pin of MB89P195. Remarks WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 22 MB89990 Series 2. Recommended Operating Conditions (VSS = 0.0 V) Parameter Symbol Value Min. 2.2* Power supply voltage VCC 2.7* 1.5 Operating temperature TA –40 Max. 6.0* 6.0* 6.0 +85 Unit V V V °C Remarks Normal operation assurance range* MB89997 Normal operation assurance range* MB89P195 Retains the RAM state in stop mode * : The guaranteed normal operation range varies depending on the operation frequency and the guaranteed analog operation range. See Figure 1. • Figure 1 Operating Voltage vs. Main Clock Operating Frequency 6 Operating voltage (V) 5 Operation assurance range 4 3 2 1 1 2 3 4 Main clock operation frequency (at an instruction cycle of 4/Fc) (MHz) 4.0 2.0 0.95 (µs) Minimum execution time (instruction cycle) (µs) Note: The shaded area is assured only for the MB89997. Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FC. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. 23 MB89990 Series 3. DC Characteristics (VCC = +5.0 V, VSS = 0.0 V, TA = –40°C to +85°C) Value Unit Remarks Min. Typ. Max. 0.7 VCC — VCC + 0.3 V Parameter Symbol Pin name P00 to P07, P30 to P37, TEST RST, INT10 to INT12, EC, INT20 to INT27 P00 to P03, P33 to P36, TEST RST, INT10 to INT12, EC, INT 20 to INT27 P40 to P44 P00 to P07, P30 to P32, P35, P36 P33, P34 P37 P00 to P07, P30 to P32, P35 to P37 RST P33, P34 P40 to P45 P00 to P07, P30 to P37, TEST P40 to P45 P00 to P07, P30 to P37, P40 to P45, RST Condition VIH “H” level input voltage VIHS — — 0.8 VCC — VCC + 0.3 V VIL “L” level input voltage VILS Open-drain output pin application voltage — VSS − 0.3 — 0.3 VCC V — VSS − 0.3 — 0.2 VCC V VD — VSS − 0.3 — VSS + 0.3 V VOH1 “H” level output voltage VOH2 VOH3 VOL1 “L” level output voltage VOL2 VOL3 VOL4 Input leakage current (Hi-z output leakage current) ILI1 IOH = –2.0 mA IOH = –4.0 mA IOH = –4.0 mA IOL = 4.0 mA IOL = 4.0 mA IOL = 12 mA IOL = 8 mA 0.45 V < VI < VCC 0.45 V < VI < VCC 4.0 4.0 4.0 — — — — — — — — — — — — — — — — 0.4 0.4 0.4 0.4 ±5 V V V V V V V µA Without pull-up resistor Without pull-up resistor Open-drain output leakage ILD1 current (Off state) Pull-up resistance RPULL — — ±5 µA VI = 0.0 V 25 50 100 kΩ (Continued) 24 MB89990 Series (Continued) Parameter Symbol Pin name Condition FC = 4.2 MHz (VCC = 5.0 V, VSS = 0.0 V, TA = –40°C to +85°C) Value Unit Remarks Min. Typ. Max. — — — — — 5 7 3 — 10 10 12 7 1 — mA MB89997 mA MB89P195 mA Sleep mode µA pF Stop mode ICC Power supply voltage* ICCS ICCH Input capacitance CIN VCC FC = 4.2 MHz TA = +25 °C Except AVR, f = 1 MHz AVSS, VCC, and VSS * : For the MB89PV190, the current consumption of a connected EPROM and ICE is not included. The mesurement condition of the power supply current are set as VCC = 5.0 V with an external clock. 4. AC Characteristics (1) Reset Timing (VCC = +5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C) Value Condition Unit Remarks Min. Max. — 16 tHCYL — ns Parameter RST “L” pulse width Symbol tZLZH Note: tXCYL is the oscillation period (1/FC) input to the X0 pin. t ZLZH RST 0.2 VCC 0.2 VCC 25 MB89990 Series (2) Power-on Reset (VSS = 0.0 V, TA = –40°C to +85°C) Parameter Power supply rising time Power supply cut-off time Symbol tR tOFF Condition — Value Min. — 1 Max. 50 — Unit ms ms Due to repeated operations Remarks Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR 2.0 V 0.2 V t OFF VCC 0.2 V 0.2 V 26 MB89990 Series (3) Clock Timing (VSS = 0.0 V, TA = –40°C to +85°C) Parameter Clock frequency Clock cycle time Input clock pulse width Input clock pulse risilng/falling time Symbol FC tXCYL PWH PWL tCR tCF Pin name X0, X1 X0, X1 X0 X0 Condition — — — — Value Min. 1 238 20 — Max. 4.2 1000 — 10 Unit MHz ns ns ns External clock External clock Remarks • Timings Conditions t XCYL PWH t CR 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC t CF PWL X0 0.2 VCC • Clock Configurations When a crystal or ceramic resonator is used When an external clock is used X0 X1 X0 X1 Open (4) Instruction Cycle (VSS = 0.0 V, TA = –40°C to +85°C) Parameter Instruction cycle (minimum execution time) Symbol tinst Value (typical) 4/FC Unit µs Remarks tinst = 0.95 µs when operating at FC = 4.2 MHz 27 MB89990 Series (5) Peripheral Input Timing (VCC = 5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C) Value Pin name Unit Remarks Min. Max. EC, INT10 to INT12, INT20 to INT27 2 tinst* 2 tinst* — — µs µs Parameter Peripheral input “H” pulse width 1 Peripheral input “L” pulse width 1 Symbol tILIH1 tIHIL1 * : For information on tinst, see “(4) Instruction Cycles.” • Peripheral Input Timing Diagram t IHIL t ILIH 0.8 VCC 0.2 VCC 0.2 VCC 0.8 VCC EC INT10 to INTR INT20 to INT27 (VCC = 5.0 V±10%, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Peripheral input “H” noise limit width Peripheral input “L” noise limit width Symbol tIHNC tILNC Pin name EC, INT10 to INT12 EC, INT10 to INT12, INT20 to INT27 Value Min. 7 7 Typ. 15 15 Max. 23 23 Unit ns ns Remarks • Peripheral Input Timing Diagram t ILNC t IHNC 0.8 VCC 0.8 VCC EC INT10 to INT12 0.2 VCC 0.2 VCC 28 MB89990 Series s EXAMPLE CHARACTERISTICS (1) “L” Level Output Voltage VOL1 vs. IOL VOL (V) 0.30 TA = +25°C 0.25 0.20 0.15 0.10 0.05 0.00 VCC = 2.5 V VCC = 3.0 V VCC = 2.0 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 0.5 0.4 0.3 0.2 0.1 0.0 VOL (V) 0.6 VOL2 vs. IOL VCC = 2.5 V VCC = 3.0 V VCC = 2.0 V TA = +25°C VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V 0 1 2 3 4 5 IOL (mA) 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) VOL3 vs. IOL VOL (V) 1.2 TA = +25°C 1.0 0.8 VCC = 3.0 V 0.6 0.4 0.2 0.0 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V VCC = 2.0 V VCC = 2.5 V 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) 29 MB89990 Series (2) “H” Level Output Voltage VOH1 vs. IOH VCC = 4.0 V VCC = 2.5 V VCC = 2.0 V VCC = 3.0 V VCC = 5.0 V VCC = 6.0 V VOH2 vs. IOH VCC - VOH (V) VCC = 3.0 V 3.0 TA = +25°C VCC = 2.5 V 2.5 2.0 1.5 1.0 0.5 0 –1 –2 –3 –4 –5 IOH (mA) 0.0 0 –4 –8 – 12 – 16 – 20 IOH (mA) VCC = 2.0 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V VCC - VOH (V) 0.6 TA = +25°C 0.5 0.4 0.3 0.2 0.1 0.0 VOH3 vs. IOH VCC - VOH (V) VCC = 2.0 V 1.2 TA = + 25°C 1.0 0.8 0.6 0.4 0.2 0.0 0 –2 –4 –6 –8 – 10 IOH (mA) VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V VCC = 2.5 V VCC = 3.0 V (3) “H” Level Input Voltage/“L” Level Input Voltage (CMOS Input) (4) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input) VIN (V) 5.0 4.5 VIN vs. VCC TA = +25°C VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 VIN vs. VCC TA= +25°C 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 3 4 5 6 7 VCC (V) VILS VIHS 3 4 5 6 7 VCC (V) VIHS: Threshold when input voltage in hysteresis characteristics is set to “H” level VILS: Threshold when input voltage in hysteresis characteristics is set to “L” level 30 MB89990 Series (5) Power Supply Current (External Clock) ICC (mA) 6 5 4 3 2 1 0 1 2 3 4 ICCH vs. VCC 5 6 7 VCC (V) ICCH (µA) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1 2 3 4 5 6 7 VCC (V) 0 1 2 3 4 5 6 7 AVR (V) 50 25 75 TA = +25°C IR (µA) 150 TA = +25°C 125 100 IR vs. AVR Fc = 1.0 MHz Fc = 4.2 MHz Fc = 3.0 MHz ICC vs. VCC TA = +25°C ICCS (mA) 1.50 1.25 1.00 0.75 0.50 0.25 0.00 1 2 3 4 5 6 7 VCC (V) ICCS vs. VCC TA = +25°C Fc = 4.2 MHz Fc = 3.0 MHz Fc = 1.0 MHz (3) Pull-up Resistance RPULL (kΩ) 1000 RPULL vs. VCC TA = +25°C 100 10 1 2 3 4 5 6 VCC (V) 31 MB89990 Series s INSTRUCTIONS Execution instructions can be divided into the following four groups: • • • • Transfer Arithmetic operation Branch Others Table 1 lists symbols used for notation for instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Instruction Symbols Meaning (Continued) 32 MB89990 Series (Continued) Symbol EP PC SP PS dr CCR RP Ri × (×) (( × )) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Meaning Columns indicate the following: Mnemonic: ~: #: Operation: TL, TH, AH: Assembler notation of an instruction The number of instructions The number of bytes Operation of an instruction A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: • “-” indicates no change. • dH is the 8 upper bits of operation description data. • AL and AH must become the contents of AL and AH prior to the instruction executed. • 00 becomes 00. N, Z, V, C: OP code: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ← This indicates 48, 49, ... 4F. 33 MB89990 Series Table 2 Mnemonic MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP ,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP ,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP ,A MOVW EP ,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP ,#d16 MOVW IX,A MOVW A,IX MOVW SP ,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP ,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC ~ 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 # 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 Transfer Instructions (48 instructions) Operation (dir) ← (A) ( (IX) +off ) ← (A) (ext) ← (A) ( (EP) ) ← (A) (Ri) ← (A) (A) ← d8 (A) ← (dir) (A) ← ( (IX) +off) (A) ← (ext) (A) ← ( (A) ) (A) ← ( (EP) ) (A) ← (Ri) (dir) ← d8 ( (IX) +off ) ← d8 ( (EP) ) ← d8 (Ri) ← d8 (dir) ← (AH),(dir + 1) ← (AL) ( (IX) +off) ← (AH), ( (IX) +off + 1) ← (AL) (ext) ← (AH), (ext + 1) ← (AL) ((EP)) ← (AH),( (EP) + 1) ← (AL) (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir + 1) (AH) ← ((IX) +off), (AL) ← ( (IX) +off + 1) (AH) ← (ext), (AL) ← (ext + 1) (AH) ← ( (A) ), (AL) ← ( (A) ) + 1) (A) ← (EP) (EP) ← d16 (IX) ← (A) (A) ← (IX) (SP) ← (A) (A) ← (SP) ( (A) ) ← (T) ( (A) ) ← (TH),( (A) + 1) ← (TL) (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ↔ (AL) (dir): b ← 1 (dir): b ← 0 (AL) ↔ (TL) (A) ↔ (T) (A) ↔ (EP) (A) ↔ (IX) (A) ↔ (SP) (A) ← (PC) (AH) ← ( (EP) ), (AL) ← ( (EP) + 1) TL – – – – – AL AL AL AL AL AL AL – – – – – – – – – AL AL AL AL AL AL – – – – – – – – – – – – – – – AL AL – – – – TH – – – – – – – – – – – – – – – – – – – – – AH AH AH AH AH AH – – – – – – – – – – – – – – – – AH – – – – AH – – – – – – – – – – – – – – – – – – – – – dH dH dH dH dH dH dH – – dH – dH – – – dH – – AL – – – dH dH dH dH dH NZVC –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++++ –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– OP code 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 D4 D7 E3 E4 C5 C6 C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0 Notes: • During byte transfer to A, T ← A is restricted to low bytes. • Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) 34 MB89990 Series Table 3 Mnemonic ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir ~ 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 Arithmetic Operation Instructions (62 instructions) # 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Operation (A) ← (A) + (Ri) + C (A) ← (A) + d8 + C (A) ← (A) + (dir) + C (A) ← (A) + ( (IX) +off) + C (A) ← (A) + ( (EP) ) + C (A) ← (A) + (T) + C (AL) ← (AL) + (TL) + C (A) ← (A) − (Ri) − C (A) ← (A) − d8 − C (A) ← (A) − (dir) − C (A) ← (A) − ( (IX) +off) − C (A) ← (A) − ( (EP) ) − C (A) ← (T) − (A) − C (AL) ← (TL) − (AL) − C (Ri) ← (Ri) + 1 (EP) ← (EP) + 1 (IX) ← (IX) + 1 (A) ← (A) + 1 (Ri) ← (Ri) − 1 (EP) ← (EP) − 1 (IX) ← (IX) − 1 (A) ← (A) − 1 (A) ← (AL) × (TL) (A) ← (T) / (AL),MOD → (T) (A) ← (A) ∧ (T) (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL) − (AL) (T) − (A) →C →A C←A← (A) −d8 (A) − (dir) (A) − ( (EP) ) (A) − ( (IX) +off) (A) − (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ( (EP) ) (A) ← (AL) ∀ ( (IX) +off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) TL – – – – – – – – – – – – – – – – – – – – – – – dL – – – – – – – – – – – – – – – – – – – – – – – TH – – – – – – – – – – – – – – – – – – – – – – – 00 – – – – – – – – – – – – – – – – – – – – – – – AH – – – – – dH – – – – – – dH – – – – dH – – – dH dH 00 dH dH dH – – – – – – – – – – – – – – – – – – – – NZVC ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++– –––– –––– ++–– +++– –––– –––– ++–– –––– –––– ++R– ++R– ++R– ++++ ++++ ++–+ ++–+ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– OP code 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 toDF D3 D2 D0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 (Continued) 35 MB89990 Series (Continued) Mnemonic AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP ,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP ~ 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 # 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 # 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 Operation (A) ← (AL) ∧ ( (EP) ) (A) ← (AL) ∧ ( (IX) +off) (A) ← (AL) ∧ (Ri) (A) ← (AL) ∨ (TL) (A) ← (AL) ∨ d8 (A) ← (AL) ∨ (dir) (A) ← (AL) ∨ ( (EP) ) (A) ← (AL) ∨ ( (IX) +off) (A) ← (AL) ∨ (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) +off) – d8 (Ri) – d8 (SP) ← (SP) + 1 (SP) ← (SP) – 1 TL – – – – – – – – – – – – – – – TH – – – – – – – – – – – – – – – AH – – – – – – – – – – – – – – – NZVC ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++++ ++++ ++++ ++++ –––– –––– OP code 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 Branch Instructions (17 instructions) Operation If Z = 1 then PC ← PC + rel If Z = 0 then PC ← PC + rel If C = 1 then PC ← PC + rel If C = 0 then PC ← PC + rel If N = 1 then PC ← PC + rel If N = 0 then PC ← PC + rel If V ∀ N= 1 then PC ← PC + rel If V ∀ N= 0 then PC ← PC + reI If (dir: b)= 0 then PC ← PC + rel If (dir: b)= 1 then PC ← PC + rel (PC) ← (A) (PC) ← ext Vector call Subroutine call (PC) ← (A),(A) ← (PC) + 1 Return from subrountine Return form interrupt TL – – – – – – – – – – – – – – – – – TH – – – – – – – – – – – – – – – – – AH – – – – – – – – – – – – – – dH – – NZVC –––– –––– –––– –––– –––– –––– –––– –––– –+–– –+–– –––– –––– –––– –––– –––– –––– Restore OP code FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 Table 5 Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI ~ 4 4 4 4 1 1 1 1 1 # 1 1 1 1 1 1 1 1 1 Other Instructions (9 instructions) Operation TL – – – – – – – – – TH – – – – – – – – – AH – dH – – – – – – – NZVC –––– –––– –––– –––– –––– –––R –––S –––– –––– OP code 40 50 41 51 00 81 91 80 90 36 L RETI SETC PUSHW POPW MOV MOVW CLRI A A A,ext A,PS CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP ,A A,SP SETI CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC H 3 4 5 6 7 8 9 A B C D E F 0 1 2 0 NOP SWAP RET 1 SUBC A A MULU DIVU A XCH XOR AND OR A, T A A A JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX 2 ROLC CMP ADDC A A A s INSTRUCTION MAP 3 XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS RORC CMPW ADDCW SUBCW XCHW XORW ANDW ORW MOVW MOVW CLRB BBC INCW DECW MOVW MOVW A A A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP ,A A,EP CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC 4 MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 5 SUBC MOV XOR AND OR MOV CMP MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP ,#d16 A,SP CLRB BBC MOVW MOVW MOVW XCHW dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX 6 MOV CMP ADDC A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A@,IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 7 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW ,#d8 @EP ,#d8 A,@EP A,@EP A,@EP A,@EP @EP ,A A,@EP A,@EP A,@EP @EP dir: 7 dir: 7,rel A,@EP @EP ,A EP ,#d16 A,EP 8 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel R0 R0 #0 rel rel rel rel 9 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel R1 R1 #1 A MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BP A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel R2 R2 #2 B MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BN A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel R3 R3 #3 C MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNZ A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel R4 R4 #4 rel rel D MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BZ A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel R5 R5 #5 E MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BGE A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel R6 R6 #6 rel MB89990 Series F MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BLT A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel R7 R7 #7 rel 37 MB89990 Series s MASK OPTION LIST Part number No. MB89997 Specify when ordering masking Selectable by pin –101*2 None MB89P195 Specify when ordering masking Selectable by pin –201*2 None MB89PV190 Fixed Not available Enabled Specifying procedure Port pull-up resistors P00 to P07 P30 to P37 P40 to P45 1 2 Power-on reset selection Power-on reset provided No power-on reset Selection of oscillation stabilization wait time (at 4.2 MHz)*1 218/FC (Approx. 62.4 ms) 216/FC (Approx. 15.6 ms) 212/FC (Approx. 0.98 ms) 22/FC (Approx. 0 ms) Selectable Enabled Enabled Enabled 3 Selectable Fixed to 216/FC Selectable Fixed to 216/FC Fixed to 216/FC 4 Reset pin output Reset output provided No reset output Oscillation type of clock 1 Crystal and ceramic oscillators 2 CR Selectable Enabled Selectable Enabled Output enabled 5 Selectable “1” only Selectable “1” only “1” only *1: The oscillation stabilization delay time is generated by dividing the original clock oscillation. The time described in this item should be used as a guideline since the oscillation cycle is unstable immediately after oscillation starts. “FC” indicates the original oscillation frequency. *2: –101 is provided respectively for the MB89P195 OTP versions as the standard product. 38 MB89990 Series s ORDERING INFORMATION Part number MB89997PF MB89P195PF-101 MB89997P-SH MB89PV190CF Package 28-pin Plastic SOP (FPT-28P-M17) 28-pin Plastic SH-DIP (DIP-28C-M03) 48-pin Ceramic MQFP (MQP-48C-P01) Remarks 39 MB89990 Series s PACKAGE DIMENSIONS 28-pin Plastic SOP (FPT-28P-M17) 28 17.75 –0.20 +.010 .699 –.008 +0.25 15 Details of "B" part Details of "A" part 0.35(.014) 11.80±0.30 (.465±.012) 8.60±0.20 (.339±.008) 0.15(.006) INDEX "A" 0.20(.008) 0.18(.007) MAX 0.68(.027) MAX 14 0.20(.008) 0.18(.007) MAX 0.68(.027) MAX 1 1.27(.050) TYP "B" 0.45±0.10 (.018±.004) 0.13(.005) M 0.15±0.05 (.006±.002) 2.80(.110)MAX (Mounting height) 0.10(.004) 16.51(.650) REF 0.80±0.20 (.031±.008) 10.20±0.30 (.402±.012) 0(0)MIN (STAND OFF) C 1994 FUJITSU LIMITED F28048S-1C-1 Dimensions in mm (inches) 28-pin Plastic SH-DIP (DIP-28P-M03) 26.00 –0.30 1.024 –.012 +.008 +0.20 INDEX-1 9.10±0.25 (.358±.010) INDEX-2 4.85(.191)MAX 0.51(.020)MIN 0.25±0.05 (.010±.002) 3.00(.118)MIN 0.45±0.10 (.018±.004) 1.00 –0 +0.50 +.020 .039 –0 1.778±0.18 (.070±.007) 1.778(.070) MAX 10.16(.400) TYP 15°MAX 23.114(.910)REF C 1994 FUJITSU LIMITED D28012S-3C-3 Dimensions in mm (inches) 40 MB89990 Series 48-pin Ceramic MQFP (MQP-48C-P01) 17.20(.677)TYP 15.00±0.25 (.591±.010) 14.82±0.35 (.583±.014) 1.50(.059)TYP 1.00(.040)TYP 8.80(.346)REF 0.80±0.22 (.0315±.0087) PIN No.1 INDEX PIN No.1 INDEX 1.02±0.13 (.040±.005) 10.92 –0.0 +.005 .430 –0 +0.13 7.14(.281) 8.71(.343) TYP TYP PAD No.1 INDEX 0.30(.012)TYP 4.50(.177)TYP 1.10 –0.25 +.018 .043 –.010 +0.45 0.40±0.08 (.016±.003) 0.60(.024)TYP 8.50(.335)MAX 0.15±0.05 (.006±.002) C 1994 FUJITSU LIMITED M48001SC-4-2 Dimensions in mm (inches) 41 MB89990 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F9710 © FUJITSU LIMITED Printed in Japan