MB89PV560-102

FUJITSU SEMICONDUCTOR DATA SHEET DS07-12555-1E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89560A Series MB89567A/567AC/P568/PV560 s DESCRIPTION The MB89560A series has been developed as a general-purpose version of the F2MC*1-8L family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to a compact instruction set, the microcontroller contains a variety of peripheral functions such as I2C interface*2, timers, 2 ch 8-bit PWM timers, 8/16-bit timer, 21-bit timebase timer, 8-bit PWC timer, 17-bit Watch prescaler, Watch-dog timer, High speed UART, 8-bit SIO, UART/SIO, LCD controller/driver (optional booster), Two type Programmable Pulse Generators (PPG), an A/D converter, and external interrupt. *1 : F2MC stands for FUJITSU Flexible Microcontroller. *2 : I2C of this product is complied to Intel Corp. System Management Bus Rev. 1.0 specification and to the Philips I2C specification. s FEATURES • • • • F2MC-8L family CPU core Low-voltage operation (when an A/D converter is not used) Low current consumption (applicable to the dual-clock system) Minimum execution time: 0.32 µs at 12.5 MHz /3.5 V to 5.5 V (Continued) s PACKAGES 80-pin Plastic LQFP 80-pin Plastic QFP 80-pin Plastic LQFP 80-pin Ceramic MQFP FPT-80P-M05 FPT-80P-M06 FPT-80P-M11 MQP-80C-P01 MB89560A Series (Continued) • I2C interface circuit • LCD controller/driver: 24 segments x 4 commons (Max 96 pixels, duty LCD mode and Static LCD mode) • LCD booster function (option) • Wild register (Max 6 different address locations) • 10-bit A/D converter: 8 channels • Three types of Serial Interface: High Speed UART (Transfer rate from 300 bps to 192000 bps /10 MHz main clock) 8-bit Serial I/O (SIO) UART/SIO • Two type of Programmable Pulse Generator(PPG): 6-bit PPG and 12-bit PPG • Six types of timer 8-bit PWM 2 channels timers 8/16-bit timer/counter (8 bits x 2 channels or 16 bits x 1 channel) 21-bit timebase timer 8-bit PWC timer operation 17-bit Watch prescaler Watch-dog timer • I/O ports: Max 50 channels • External interrupt 1: 8 channels • External interrupt 2 (wake-up function): 4 channels • Low-power consumption modes (stop mode, sleep mode, and watch mode) • LQFP-80 and QFP-80 package • CMOS technology 2 MB89560A Series s PRODUCT LINEUP Part number MB89567A Parameter Classification ROM size RAM size Mass production products (mask ROM products) 32 K x 8-bit (internal mask ROM) 1 K x 8-bit Number of instructions Instruction bit length Instruction length Data bit length Minimum execution time Minimum interrupt processing time : 136 : 8-bit : 1 to 3 bytes : 1-, 8-, 16-bit : 0.32 µs/12.5 MHz : 2.88 µs/12.5 MHz OTP 48 K x 8-bit (internal PROM) Piggy-back 56 K x 8-bit (external ROM) 1 K x 8-bit MB89567AC MB89P568 MB89PV560 CPU functions Ports General-purpose I/O ports (N-channel open drain): 20 pins (2 shared with I2C inputs, 16 shared with LCD, 2 shared with other resources) General-purpose I/O ports (CMOS) : 30 pins (shared with resources) Total : 50 pins 21-bit Interrupt cycle: (213, 215, 218 or 222)/FCH*7 Reset generate cycle: Min 221/FCH*7 for main clock, Min 214/FCL*7 for sub clock 17-bit Interrupt cycle: 31.25 ms, 0.25 s, 0.50 s, 1.00 s, 2.00 s, 4.00 s/32.768 kHz for subclock Can be operated either as a 2-channel 8-bit timer/counter (Timer 1 and Timer 2, each with its own independent operating clock cycle), or as one 16-bit timer/counter In Timer 1 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capable 8-bit interval timer operation (square wave output capable, operating clock cycle: 1 tinst, 8 tinst, 16 tinst, 64 tinst) 8-bit resolution PWM operation (conversion cycle: 128 x 1 tinst to 256 x 64 tinst) 8/16-bit timer/counter output for counter clock selectability 8-bit timer operation (count clock cycle: 1 tinst, 4 tinst, 32 tinst) 8-bit reload timer operation (toggle output possible, operating clock cycle: 1 to 32 tinst) 8-bit pulse width measurement (continuous measurement possible: H-width, L-width, rising edge to rising edge, falling edge to falling edge, and rising edge to falling edge) 10-bit resolution × 8 channels A/D conversion function (conversion time: 60 tinst) Continuous activation by an 8/16-bit timer/counter output or a timebase timer output capable. Internal 6-bit counter Pulse width and cycle are program selectable Internal 12-bit counter Pulse width and cycle are program selectable 21-bit timebase timer Watchdog timer Watch prescaler 8/16-bit timer/ counter 8-bit PWM 2 ch timer PWC timer 10-bit A/D converter *2 6-bit PPG 12-bit PPG (Continued) 3 MB89560A Series (Continued) Part number MB89567A Parameter I2C interface*4 Not Available 1 channel MB89567AC MB89P568 MB89PV560 Transfer data length: 4-, 6-, 7-, 8-bit High speed UART Transfer rate (300 bps to 192000 bps /9.216 MHz main clock) support sub-clock mode UART/SIO Transfer data length: 7-, 8-bit for UART, 8-bit for SIO Transfer rate (1201 bps to 78125 bps / 10 MHz main clock) support sub-clock mode 8-bit, LSB first/MSB first selectability Transfer clocks (one external shift clock, three internal shift clocks: 2 tinst, 8 tinst, 32 tinst) *5 Common output: 4 (Max) Segment output: 24 (Max) LCD driving power (bias) pins: 4 LCD display RAM size: 12 bytes (24 × 4 bits, Max 96 pixels) Duty LCD mode and Static LCD mode Booster for LCD driving: option*1 Dividing resistor for LCD driving: option Maximum of 6-byte data can be assigned in 6 different address. Used to replace any data in the ROM when specific address and data are assigned in Wild register. Wild register can be set up by using different communication methods through the device. 8 independent channels (interrupt vector, request flag, request output enable) Edge selectability (rising/falling) Used also for wake-up from stop/sleep mode. (edge detection is also permitted in stop mode.) 4 channels (“L” level interrupts, independent input enable). Used also for wake-up from stop/sleep mode. (Low-level detection is also permitted in stop mode.) Sub clock mode, sleep mode, stop mode and clock mode CMOS 2.2 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V*3 8-bit serial I/O LCD Wild register External interrupt 1 (wake-up function) External interrupt 2 (wake-up function) Standby mode Process Operating voltage *6 *1 : When booster is used, the bias is reduced by 1/3. It can be selected by mask option. *2 : Voltage varies with product. *3 : When external ROM is used, EPROM: MBM27C512-20 should be used, the operating voltage: 4.5 V to 5.5 V. *4 : I2C is complied to Intel Corp. System Management Bus Rev. 1.0 specification and to the Philips I2C specification. *5 : 1 tinst = one instruction cycle (execution time) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock if main clock mode is selected, or 1/2 of the subclock if subclock mode is selected. *6 : Varies with conditions such as the operating frequency. (See “sELECTRICAL CHARACTERISTICS.”) *7 : FCH : main clock source oscillation, FCL : sub clock source oscillation 4 MB89560A Series s PACKAGE AND CORRESPONDING PRODUCTS Package FPT-80P-M05 FPT-80P-M06 FPT-80P-M11 MQP-80C-P01 MB89567A MB89567AC MB89P568-101 MB89P568-102 MB89PV560-101 MB89PV560-102 s DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the OTPROM (one-time PROM) products, verify its differences from the product that will actually be used. Take particular care on the following points: • The stack area, etc., is set at the upper limit of the RAM. 2. Current Consumption • For the MB89PV560, add the current consumed by the EPROM mounted in the piggy-back socket. • When operating at low speed, the current consumed by the one-time PROM product is greater than that for the mask ROM product. However, the current consumption is roughly the same in sleep or stop mode. • For more information, see “s ELECTRICAL CHARACTERISTICS.” 3. Mask Options The functions available as options and the method of specifying options differ between products. Before using options check “s MASK OPTIONS.” 4. Wild register function The Wild Register can be used in the following address spaces. Device MB89PV560 MB89P568 MB89567A/567AC 4000H to FFFFH 4000H to FFFFH 8000H to FFFFH Address Space 5. P40, P41 It will take about 64 count clock of external oscillation to initialize P40 and P41 pins in MB89PV560/P568. Therefore, these ports will be unstable for a while during power-on. For MB89567A/567AC, these ports will be in High-Z during power-on. 5 MB89560A Series s PIN ASSIGNMENT (Top view) SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 SEG00 COM3 COM2 COM1 COM0 V3 V2 V1 V0 C0*2 C1*2 P47/PWC P46/UI/SI1 P45/UO/SO1 SEG07 P50/SEG08 P51/SEG09 P52/SEG10 P53/SEG11 P54/SEG12 P55/SEG13 P56/SEG14 P57/SEG15 P60/SEG16 P61/SEG17 P62/SEG18 Vss P63/SEG19 P64/SEG20 P65/SEG21 P66/SEG22 P67/SEG23 AVR AVcc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P44/UCK/SCK1 P43/PWM2/PPG2 P42/PWM1/EC1 P41/HCK*1/TO12 P40/WTO/TO11 P31/SDA P30/SCL Vcc P27/INT23 P26/INT22 P25/INT21 P24/INT20 P23/PPG1 P22/SCK P21/SO P20/SI X1 X0 MODA X1A *1: Main clock divided by two output *2: For built-in LCD booster only Note: For mask option of *2, please refer to “s MASK OPTIONS”. P07/AN7 P06/AN6 P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AVss P17/INT17 P16/INT16 P15/INT15 P14/INT14 P13/INT13 P12/INT12 P11/INT11 C P10/INT10 RST X0A (FPT-80P-M05) (FPT-80P-M11) (Continued) 6 MB89560A Series (Top view) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 SEG04 SEG03 SEG02 SEG01 SEG00 COM3 COM2 COM1 COM0 V3 V2 V1 V0 C0*2 C1*2 P47/PWC SEG05 SEG06 SEG07 P50/SEG08 P51/SEG09 P52/SEG10 P53/SEG11 P54/SEG12 P55/SEG13 P56/SEG14 P57/SEG15 P60/SEG16 P61/SEG17 P62/SEG18 Vss P63/SEG19 P64/SEG20 P65/SEG21 P66/SEG22 P67/SEG23 AVR AVcc P07/AN7 P06/AN6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P46/UI/SI1 P45/UO/SO1 P44/UCK/SCK1 P43/PWM2/PPG2 P42/PWM1/EC1 P41/HCK*1/TO12 P40/WTO/TO11 P31/SDA P30/SCL Vcc P27/INT23 P26/INT22 P25/INT21 P24/INT20 P23/PPG1 P22/SCK P21/SO P20/SI X1 X0 MODA X1A X0A RST *1: Main clock divided by two output *2: For built-in LCD booster only Note: For mask option of *2, please refer to “s MASK OPTIONS”. P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AVss P17/INT17 P16/INT16 P15/INT15 P14/INT14 P13/INT13 P12/INT12 P11/INT11 C P10/INT10 (FPT-80P-M06) (Continued) 7 MB89560A Series (Continued) (Top view) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 SEG04 SEG03 SEG02 SEG01 SEG00 COM3 COM2 COM1 COM0 V3 V2 V1 V0 C0*2 C1*2 P47/PWC SEG05 SEG06 SEG07 P50/SEG08 P51/SEG09 P52/SEG10 P53/SEG11 P54/SEG12 P55/SEG13 P56/SEG14 P57/SEG15 P60/SEG16 P61/SEG17 P62/SEG18 Vss P63/SEG19 P64/SEG20 P65/SEG21 P66/SEG22 P67/SEG23 AVR AVcc P07/AN7 P06/AN6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 *3 100 99 98 97 96 95 94 101 102 103 104 105 106 107 108 109 93 92 91 90 89 88 87 86 85 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P46/UI/SI1 P45/UO/SO1 P44/UCK/SCK1 P43/PWM2/PPG2 P42/PWM1/EC1 P41/HCK*1/TO12 P40/WTO/TO11 P31/SDA P30/SCL Vcc P27/INT23 P26/INT22 P25/INT21 P24/INT20 P23/PPG1 P22/SCK P21/SO P20/SI X1 X0 MODA X1A X0A RST *1: Main clock divided by two output *2: For built-in LCD booster only *3: Pin assignment on package top (MB89PV560 only) Pin no. Pin Pin no. Pin Pin no. Pin 81 N.C. 89 AD2 97 N.C. 82 83 84 85 86 87 88 A15 A12 AD7 AD6 AD5 AD4 AD3 90 91 92 93 94 95 96 AD1 AD0 N.C. O1 O2 O3 VSS 98 99 100 101 102 103 104 04 O5 O6 07 O8 CE A10 P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AVss P17/INT17 P16/INT16 P15/INT15 P14/INT14 P13/INT13 P12/INT12 P11/INT11 C P10/INT10 (MQP-80C-P01) 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 110 111 112 81 82 83 84 Pin no. 105 106 107 108 109 110 111 112 Pin OE N.C. A11 A9 A8 A13 A14 VCC N.C.: Internally connected. Do not use. Note: For mask option of *2, please refer to “s MASK OPTIONS”. 8 MB89560A Series s PIN DESCRIPTION Pin no. LQFP*1 LQFP*2 43 44 42 MQFP*3 QFP*4 45 46 44 Pin name X0 X1 MODA A I/O circuit type Function Crystal or other resonator connector pins for the main clock. The external clock can be connected to X0. When this is done, be sure to leave X1 open. Memory access mode setting pins. Connect directly to VSS. Hysteresis input type. Reset I/O pin This pin is a CMOS output type with a pull-up resistor, and a hysteresis input type. “L” is output from this pin by an internal reset request (optional). The internal circuit is initialized by the input of “L”. General-purpose CMOS I/O ports Also serve as an external interrupt 2 input (wake-up function). External interrupt 2 input is hysteresis input. Selectable pull-up resistor. General-purpose CMOS I/O ports Also serve as input for external interrupt 1 input. External interrupt 1 input is hysteresis input. Selectable pull-up resistor. General-purpose CMOS I/O ports Also serve as the clock I/O for the High-speed UART and Serial I/O. The peripheral is a hysteresis input type. Selectable pull-up resistor. General-purpose CMOS I/O ports Also serves as the data output for the High-speed UART and Serial I/O. N-ch open drain general-purpose I/O ports Also serves as the data input for the High-speed UART and Serial I/O. The peripheral is a hysteresis input type. N-ch open drain general-purpose I/O port Also serve as the external clock input for PWC. The peripheral is a hysteresis input. General-purpose CMOS I/O port Also serves as an 8/16-bit timer/counter output and PWC output. C 39 41 RST D 49 to 52 51 to 54 P24/INT20 to P27/INT23 P10/INT10 to P17/INT17 E 30 to 36, 38 32 to 38, 40 E 60 62 P44/UCK/ SCK1 E 61 63 P45/UO/ SO1 P46/UI/SI1 F 62 64 G 63 56 65 58 P47/PWC P40/WTO/ TO11 G F (Continued) 9 MB89560A Series Pin no. LQFP*1 LQFP*2 MQFP*3 QFP*4 Pin name I/O circuit type Function General-purpose CMOS I/O port Also serves as an 8/16-bit timer/counter output. and half of main clock output Selectable pull-up resistor. General-purpose CMOS I/O port Also serves as the data input for the serial I/O. The peripheral is a hysteresis input type. Selectable pull-up resistor. General-purpose CMOS I/O port Also serves as the data output for the serial I/O. Selectable pull-up resistor. General-purpose CMOS I/O port Also serves as the clock I/O for the serial I/O. The peripheral is a hysteresis input type. Selectable pull-up resistor. General-purpose CMOS I/O port Also serves as the 6 bit PPG output pin. Selectable pull-up resistor. N-ch open-drain general-purpose I/O port Clock I/O pin for I2C interface N-ch open-drain general-purpose I/O port Data I/O pin for I2C interface Function as capacitor connection pin in the products with a booster. General-purpose CMOS I/O port Also serves PWM wave output for the 8-bit PWM timer 1 and as 12 bit programmable pulse generator output. Selectable pull-up resistor. General-purpose CMOS I/O port Also serves as the PWM wave output and external clock for the 8/16 bit timer counter. Selectable pull-up resistor. General-purpose CMOS I/O ports Also serve as the analog input for the A/D converter. Selectable pull-up resistor. 57 59 P41/HCK/ TO12 F 45 47 P20/SI E 46 48 P21/SO F 47 49 P22/SCK E 48 50 P23/PPG1 F 54 55 65 64 56 57 67 66 P30/SCL P31/SDA C0 C1 P43/ PWM2/ PPG2 P42/ PWM1/ EC1 P00/AN0 to P07/AN7 G G — 59 61 F 58 60 E 21 to 28 23 to 30 J (Continued) 10 MB89560A Series (Continued) Pin no. LQFP*1 LQFP*2 10 to 12 14 to 18 MQFP*3 QFP*4 12 to 14 16 to 20 Pin name P60/ SEG16 to P67/ SEG23 P50/SEG8 to P57/ SEG15 SEG0 to SEG7 COM0 to COM3 V0 to V3 X0A X1A Vcc C Vss AVcc AVR AVss I/O circuit type Function H N-ch open-drain general-purpose output ports Also serve as an LCD controller/driver segment output. 2 to 9 4 to 11 H N-ch open-drain general-purpose output ports Also serve as an LCD controller/driver segment output. 74 to 80, 1 1 to 3 76 to 80 72 to 75 I LCD controller/driver segment output-only pins 70 to 73 I LCD controller/driver common output-only pins 66 to 69 40 41 53 37 13 20 19 29 68 to 71 42 43 55 39 15 22 21 31 — LCD driving power supply pins. Crystal or other resonator connector pins for the subclock (Subclock: 32.768 kHz) Power supply pin Capacitor connection pin *5 Power supply (GND) pin A/D converter power supply pin A/D converter reference voltage input pin A/D converter power supply pin Use this pin at the same voltage as VSS. B — — — — — — *1: FPT-80P-M05 *2: FPT-80P-M11 *3: MQP-80C-P01 *4: FPT-80P-M06 *5: When MB89567A / MB89567AC / MB89PV560-101 / MB89PV560-102 is used, this pin will become NC pin without internal connection. There is no problem to leave pins open, to fix pins at VCC and to fix pins at VSS. When MB89P568-101 or MB89P568-102 is used, this pin must be connected to VSS. 11 MB89560A Series • For External EPROM Socket (MB89PV560 ONLY) Pin no. Pin name I/O 82 83 84 85 86 87 88 89 90 91 93 94 95 96 98 99 100 101 102 103 104 105 107 108 109 110 111 112 81 92 97 106 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 Vss O4 O5 O6 O7 O8 CE A10 OE/Vpp A11 A9 A8 A13 A14 Vcc Function O Address output pins I O Data input pins Power supply (GND) pin I Data input pins O O O ROM chip enable pin Outputs “H” during standby. Address output pin ROM output enable pin Outputs “L” at all times. O Address output pins O O O EPROM power supply pin Internally connected pins Be sure to leave them open. N.C. — 12 MB89560A Series s I/O CIRCUIT TYPE Type X1 Nch Pch Pch Nch Circuit Remarks Main clock (main clock crystal oscillator) • At an oscillation feedback resistor of approximately 1 MΩ/5.0 V A X0 Main clock control signal X1A Nch Pch Subclock (subclock crystal oscillator) • At an oscillation feedback resistor of approximately 4.5 MΩ/5.0 V B X0A Nch Sub clock control signal • Hysteresis input C • CMOS output • Hysteresis input • At an output pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V R Pch D Nch R Pch Pch Pull-up control register E Nch • CMOS output • CMOS input • The peripheral is a hysteresis input type. • Selectable pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V Port Peripheral (Continued) 13 MB89560A Series (Continued) Type R Circuit Pull-up resistor control register Pch Remarks • CMOS output • CMOS input • Selectable pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V Pch F Nch Port • N-ch open-drain input/output • CMOS input • The peripheral is a hysteresis input type. (P30,P31 are OR-type input for I2C) Nch G Port Peripheral Pch Nch Pch Nch • N-ch open-drain output • CMOS input • LCD controller/driver segment output H Nch Port • LCD controller/driver common/ segment output Pch Nch I Pch Nch R Pch Pch Pull-up control register J Nch ADEN • General CMOS I/O • Analog input (A/D converter) • Selectable pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V • Pull-up resistors must be disabled when used as an analog input. Port Analog input 14 MB89560A Series s HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in “s ELECTRICAL CHARACTERISTICS” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVCC = DVCC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 Hz to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up from stop mode. 7. Unused LCD dedicated pins When LCD dedicated pins are not in use, keep it open. 8. Ports shared with SEG pin When using port shared with SEG pin, be sure that the input voltage to port does not exceed the voltage of V3 (SEG driving voltage). This is particularly important to those devices with booster. When power-on or reset, SEG pin will output an initial value of “L”. 9. LCD not in use When LCD is not in use, connect the V3 pin to Vcc and keep other LCD dedicated pins open. 10. Wild Register function In MB89PV560, wild register function cannot be evaluated. To evaluate the wild register function, use MB89P568. 11. Programming operation on RAM Program operation debugging at RAM is not possible even when using MB89PV560. 12. Note to Noise in the External Reset Pin (RST) If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST) . 15 MB89560A Series s PROGRAMMING TO THE EPROM ON THE MB89P568 The MB89P568 is an OTPROM version of the MB89567A and MB89567AC. 1. Features • 48-Kbyte PROM on chip • Equivalency to the MBM27C1001 in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in EPROM mode is diagrammed below. Normal operation 0000 H EPROM mode (Corresponding addresses on the EPROM programmer) I/O 0080 H RAM 0480 H Not available 4000 H 4000 H Program area (PROM) FFFF H FFFF H Program area (PROM) 3. Programming to the EPROM In EPROM mode, the MB89P568 functions equivalent to the MBM27C1001. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. • Programming procedure (1) Set the EPROM programmer to the MBM27C1001. (2) Load program data into the EPROM programmer at 4000H to FFFFH (3) Program with the EPROM programmer. 16 MB89560A Series 4. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure. Program, verify Program, verify +100 °C, 48 h Read Assembly 5. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 6. EPROM Programmer Socket Adapter Package FPT-80P-M05 FPT-80P-M06 FPT-80P-M11 Compatible socket adapter ROM-80SQF-32DP-8LA ROM-80QF-32DP-8LA2 ROM-80QF2-32DP-8LA2 Inquiry: San Hayato Co., Ltd.: FAX +81-3-5396-9106 (Tokyo) 17 MB89560A Series s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C512-20TV 2. Programming Socket Adapter To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package Adapter socket part number LCC-32 (Rectangle) Inquiry: San Hayato Co., Ltd.: FAX +81-3-5396-9106 (Tokyo) ROM-32LC-28DP-YG 3. Memory Space Normal operation 0000 H EPROM mode (Corresponding addresses on the EPROM programmer) I/O 0080 H RAM 0480 H Not available 2000 H 2000 H Program area (PROM) Program area (PROM) FFFF H FFFF H 4. Programming to EPROM (1) Set the EPROM programmer to the MBM27C512. (2) Load program data into the EPROM programmer at 2000H to FFFFH. (3) Program to 2000H to FFFFH with the EPROM programmer. 18 MB89560A Series s BLOCK DIAGRAM Main clock X0 X1 I2C*2 Oscillator N-ch open drain I/O port SIO High-speed UART 12 bit PPG Watch prescaler Reset circuit (Watchdog timer) 21-bit Time-base timer PWC *4 8-bit timer/counter 1 (Timer 1) Internal data bus *4 8-bit timer/counter 2 (Timer 2) Port 3 P30/SCL P31/SDA Clock controller Subclock X0A X1A Low-power oscillator (32.768 kHz) P40/WTO/TO11 P41/HCK*1/TO12 P42/PWM1/EC1 P43/PWM2/PPG2 RST Port 4 P44/UCK/SCK1 P45/UO/SO1 P10/INT10 to P17/INT17 Port 1 8 8 External interrupt 1 CMOS I/O port 8-bit PWM timer 2 8-bit PWM timer 1 CMOS I/O port (P46 and P47 are N-ch Open-drain I/O Type) N-ch open-drain output port Port 5 & Port 6 8 4 4 4 4 P46/UI/SI1 P47/PWC 6 bit PPG P24/INT20 to P27/INT23 P23/PPG1 P20/SI P21/SO P22/SCK 4 4 External interrupt 2 (wake-up function) UART/SIO CMOS I/O port LCD controller/ driver 8 P60/SEG16 to P63/SEG19 P64/SEG20 to P67/SEG23 P50/SEG8 to P53/SEG11 P54/SEG12 to P57/SEG15 SEG0 to SEG7 COM0 to COM3 V0 to V3 C0*3 C1*3 Option *1: Output of Main clock/2. *2: I2C is not available in MB89567A. *3: Selected by mask option *4: Can be used as a 16-bit timer/counter by connecting Timer 1 output to Timer 2 input. *5: C pin becomes NC pin in MB89567A/AC/PV560 *6: 48 K byte ROM for MB89P568 Port 2 1K Byte RAM Display RAM (12 bytes) 8 4 4 F2MC-8L CPU Booster Wild register CMOS I/O port 8 8 32K*6 Byte ROM Other pins MODA, C,*5 VCC, VSS 10-bit A/D converter P00/AN0 to P07/AN7 AVCC AVSS AVR Port 0 19 MB89560A Series s CPU CORE 1. Memory Space The microcontrollers of the MB89560A series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located the lowest address. The data area is provided immediately above the I/ O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89560A series is structured as illustrated below. Memory space MB89567A, MB89567AC 0000 H MB89P568-101,102 0000 H MB89PV560-101,102 0000 H I/O 0080 H 0080 H I/O 0080 H I/O RAM 0100 H 0100 H RAM 0100 H RAM Register 0200 H 0480 H *2 Register 0200 H 0480 H *2 0492 H 0200 H 0480 H 0492 H Register *2 0492 H Access prohibited 4000 H 8000 H Access prohibited Access prohibited 2000 H ROM FFC0 H FFFF H FFC0 H FFFF H External*1 ROM FFC0 H FFFF H External*1 ROM Vector table (Reset • Interrupt • Vector call instruction) *1 : MB89P568-101,102 has OTP ROM inside. *2 : Wild register setting registers 20 MB89560A Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following registers are provided: Program counter (PC) Accumulator (A) : A 16-bit register for indicating specifies instruction storage positions. : A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX) : A 16-bit register for index modification Extra pointer (EP) : A 16-bit pointer for indicating a memory address Stack pointer (SP) : A 16-bit register for indicating a stack area Program status (PS) : A 16-bit register for storing a register pointer, a condition code 16 bits PC A Initial value : Program counter : Accumulator : Temporally accumulator FFFDH Undefined Undefined Undefined Undefined Undefined I Flag = 0, IL1, 0 = 11 other bits are undefined. IX EP SP PS : Indexing register : Extra pointer : Stuck pointer : Program status The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) • Structure of program status 15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 3 N 2 Z 1 V 0 C Va- VaVacancy cancy cancy IL1 IL0 RP CCR 21 MB89560A Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. • Rule for Conversion of Actual Addresses of the General-purpose Register Area Operation Code lower b1 b0 RP Upper "0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2 Generated address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag : Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag : Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. IL1, 0 : Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level High-low 0 0 1 1 0 1 0 1 1 2 3 Low = no interrupt High N-flag : Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag : Set when an arithmetic operation results in 0. Cleared otherwise. V-flag : Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag : Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. The following general-purpose registers are provided : General-purpose registers : An 8-bit resister for storing data 22 MB89560A Series The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers. Up to a total of 32 banks can be used. The bank currently in use is indicated by the register bank pointer (RP). • Register Bank Configuration This address = 0100H+8× (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 bank (MB89567A/567AC) Memory range 23 MB89560A Series s I/O MAP Address 00H 01H 02H 03H 04H to 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H to 19H 1AH 1BH 1CH 1DH 1EH to 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH SMC11 SRC1 SSD1 SIDR1/SODR1 SMC12 CNTR1 CNTR2 CNTR3 COMR1 COMR2 PCR1 T2CR T2DR T1CR T1DR Timer2 control register Timer2 data register Timer1 control register Timer1 data register (Vacancy) UART1 mode control register 1 UART1 mode data register UART1 status/data register UART1 data register UART1 mode control register 2 PWM control register 1 PWM control register 2 PWM control register 3 PWM compare register 1 PWM compare register 2 PWC pulse width control register 1 R/W R/W R/W R/W R/W R/W R/W R/W W W R/W 00000000B XX011000B 00100X1XB XXXXXXXXB XX100001B 00000000B 000X0000B X000XXXXB XXXXXXXXB XXXXXXXXB 000XX000B PDR6 Port 6 data register (Vacancy) R/W R/W R/W R/W X00000X0B XXXXXXXXB X00000X0B XXXXXXXXB SYCC STBC WDTC TBTC WPCR PDR2 DDR2 PDR3 PDR4 DDR4 PDR5 Register name PDR0 DDR0 PDR1 DDR1 Register Description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register (Vacancy) System clock control register Standby control register Watchdog timer control register Timebase timer control register Watch prescaler control register Port 2 data register Port 2 data direction register Port 3 data register Port 4 data register Port 4 direction register Port 5 data register (Vacancy) R/W 00000000B R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W XXXMM100B 00010XXXB 0XXXXXXXB 00XXX000B 00XX0000B XXXXXXXXB 00000000B XXXXXX11B XXXXXXXXB XX000000B 00000000B Read/Write R/W W R/W W Initial value XXXXXXXXB 00000000B XXXXXXXXB 00000000B (Continued) 24 MB89560A Series Address 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH to 3EH 3FH 40H 41H 42H 43H to 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH IBSR IBCR ICCR IADR IDAR EIE2 EIF2 RCR1 RCR2 CKR LCR1 LCR2 LCR3 LDR1 I2C bus status register I2C bus control register I C clock control register I C address register I2C data register External interrupt 2 enable register External interrupt 2 flag register PPG control register 1(PPG1) PPG control register 2(PPG1) Clock Output control register LCD controller/driver control register 1 LCD controller/driver control register 2 LCD controller/driver control register 3 LCD data register 1 2 2 Register name PCR2 RLBR SMC21 SMC22 SSD2 SIDR2/SODR2 SRC2 ADC1 ADC2 ADDL ADDH RCR21 RCR23 RCR22 RCR24 EIC1 EIC2 EIC3 EIC4 Register Description PWC pulse width control register 2 PWC reload buffer register UART2/SIO mode control register UART2/SIO mode control register 2 UART2/SIO status/data register UART2/SIO data register UART2/SIO rate control register A/D control register 1 A/D control register 2 A/D data register L A/D data register H PPG control register 1(PPG2) PPG control register 3(PPG2) PPG control register 2(PPG2) PPG control register 4(PPG2) (Vacancy) External interrupt 1 control register 1 External interrupt 1 control register 2 External interrupt 1 control register 3 External interrupt 1 control register 4 (Vacancy) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B XXXXXXXXB 00000000B 00000000B 00001XXXB XXXXXXXXB XXXXXXXXB X00000X0B X0000001B XXXXXXXXB XXXXXXXXB 00000000B 0X000000B XX000000B XX000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 000XXXXXB XXXXXXXXB XXXXXXXXB XXXX0000B XXXXXXX0B 00000000B 0X000000B 00000000B 00010000B 00000000B XX000000B XXXXXXXXB (Continued) 25 MB89560A Series (Continued) Address 5FH 60H to 6BH 6CH to 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH ILR1 ILR2 ILR3 ILR4 ITR WREN WROR ADEN SMR SDR PURR0 PURR1 PURR2 PURR4 Serial I/O data register Pull-up resistor register 0 Pull-up resistor register 1 Pull-up resistor register 2 Pull-up resistor register 4 (Vacancy) Wild register enable register Wild register data test register A/D port input enable register (Vacancy) Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 Interrupt test register W W W W Access Prohibited 11111111B 11111111B 11111111B 11111111B 11111111B R/W R/W R/W XX000000B XX000000B 11111111B VRAM Display RAM (Vacancy) Serial I/O mode register R/W R/W R/W R/W R/W R/W 00000000B XXXXXXXXB 11111111B 11111111B 11111111B XX111111B Register name Register Description (Vacancy) Read/Write R/W Initial value XXXXXXXXB Read/write access symbols R/W : Readable and writable R : Read-only W : Write-only Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. M : The initial value of this bit is determined by mask option. Note : Do not use vacancies. 26 MB89560A Series s WILD REGISTER I/O MAP Address 480H 481H 482H 483H 484H 485H 486H 487H 488H 489H 48AH 48BH 48CH 48DH 48EH 48FH 490H 491H Register name WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 WRARH3 WRARL3 WRDR3 WRARH4 WRARL4 WRDR4 WRARH5 WRARL5 WRDR5 WRARH6 WRARL6 WRDR6 Register description Wild register high-byte address register1 Wild register low-byte address register1 Wild register data register1 Wild register high-byte address register2 Wild register low-byte address register2 Wild register data register2 Wild register high-byte address register3 Wild register low-byte address register3 Wild register data register3 Wild register high-byte address register4 Wild register low-byte address register4 Wild register data register4 Wild register high-byte address register5 Wild register low-byte address register5 Wild register data register5 Wild register high-byte address register6 Wild register low-byte address register6 Wild register data register6 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Read/write access symbols R/W : Readable and writable R : Read-only W : Write-only Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. M : The initial value of this bit is determined by mask option. Note : Do not use vacancies. 27 MB89560A Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol VCC AVCC AVR LCD power voltage Program voltage V0 to V3 VPP Rating Min VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.6 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 “L” level maximum output current “L” level average output current “L” level total maximum output current “L” level total average output current IOL IOLAV ∑IOL ∑IOLAV     Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS +13.0 VCC + 0.3 VCC + 0.3 V3 VSS + 6.0 VCC + 0.3 VCC + 0.3 V3 VSS + 6.0 15 30 4 15 100 60 Unit V V V V V V V V V V V V mA mA mA mA mA mA *2 For pins other than P20 to P27, P30, P31, P46, P47, P50 to P57, P60 to P67 For P20 to P27 only For pins other than P20 to P27*2 For P20 to P27 only*2 Remarks MB89567A, MB89567AC, MB89P568 and MB89PV560*1 AVR must not exceed “AVcc + 0.3V”. V0 to V3 should not exceed Vcc Without booster Only for the MB89P568 For pins other than P30, P31, P46, P47, P50 to P57 and P60 to P67 P50 to P57, P60 to P67 Resister Ladder option P50 to P57, P60 to P67 LCD booster option For P30, P31, P46, P47 For pins other than P30, P31, P46, P47, P50 to P57 and P60 to P67 P50 to P57, P60 to P67 Resister Ladder option P50 to P57, P60 to P67 LCD booster option For P30, P31, P46, P47 For pins other than P20 to P27 For P20 to P27 only For pins other than P20 to P27*2 For P20 to P27 only*2 Power supply voltage Input voltage VI Output voltage VO “H” level maximum output current IOH  – 15 – 30 mA mA mA “H” level average output current IOHAV  –4 – 15 (Continued) 28 MB89560A Series (Continued) (AVSS = VSS = 0.0 V) Parameter “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature Symbol ∑IOH ∑IOHAV PD TA Tstg Rating Min    – 40 – 55 Max – 50 – 30 300 + 85 + 150 Unit mA mA mW °C °C *2 Remarks *1 : Use AVCC and VCC set at the same voltage. Take care so that AVR does not exceed AVCC + 0.3 V, such as when power is turned on. Take care so that AVCC does not exceed VCC, such as when power is turned on. *2 : Average value (operating current × operating rate) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 29 MB89560A Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Symbol Value Min 2.2* Max 5.5* 5.5 5.5* 5.5 Unit V V V V Remarks For MB89567A and MB89567AC Retains the RAM state in stop mode for MB89567A and MB89567AC For MB89PV560 and MB89P568 Retains the RAM state in stop mode for MB89PV560 and MB89P568 Liquid crystal power supply range : without booster (The best value is according to the specification of LCD used.) Power supply voltage VCC AVCC 1.5 2.7* 1.5 LCD power voltage V0 to V3 Vss VCC V A/D converter reference input voltage Operating temperature AVR TA 3.5 – 40 AVCC + 85 V °C * : These values depend on the operating conditions and the analog assurance range. See Figure “Operating Voltage vs. Main Clock Operating Frequency (MB89567A, MB89567AC) ”, “Operating Voltage vs. Main Clock Operating Frequency (MB89P568/MB89PV560) ” and “6. A/D Converter Electrical Characteristics.” 30 MB89560A Series “Operating Voltage vs. Main Clock Operating Frequency (MB89567A, MB89567AC) and “Operating Voltage vs. Main Clock Operating Frequency (MB89P568/MB89PV560) indicate the operating frequency of the external oscillator at an instruction cycle of 4/FCH Operating Voltage (V) A/D Converter accuracy assurance range: Vcc = AVcc =3.5 V to 5.5 V 5.5 5.0 Operation assurance range 4.0 3.5 3.0 2.7 2.2 2.0 Main clock operating Freq. (MHz) 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 12.5 Min execution time (inst. cycle) (µs) 4.0 2.0 0.8 0.4 0.32 Operating Voltage vs. Main Clock Operating Frequency (MB89567A, MB89567AC) 31 MB89560A Series Operating Voltage (V) A/D Converter accuracy assurance range: Vcc = AVcc = 3.5 V to 5.5 V 5.5 5.0 4.5 Operation assurance range 4.0 3.5 3.0 2.7 2.5 2.2 2.0 1.0 Operation assurance : TA = −10 °C to +55 °C (Only for MB89P568) 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 12.0 Main clock operating Freq. (MHz) 11.0 12.5 Min execution time (inst. cycle) (µs) 4.0 2.0 0.8 0.4 0.32 Operating Voltage vs. Main Clock Operating Frequency (MB89P568/MB89PV560) Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 32 MB89560A Series 3. DC Characteristics (power supply voltage : 5.0V) Parameter Symbol Pin P00 to P07, P10 to P17, P20 to P27, P30 to P31, P40 to P45, P50 to P57, P60 to P67 RST, MODA, INT10 to INT17, INT20 to INT23, SI,SCK,EC1,UCK, SCK1,UI,SI1,PWC (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C) Value Condition Unit Remarks Min Typ Max VIH — 0.7 VCC — VCC + 0.3 V CMOS “H” level input voltage VIHS — 0.8 VCC — VCC + 0.3 V Hysteresis VIHSMB SCL, SDA VIHI2C P00 to P07, P10 to P17, P20 to P27, P30 to P31, P40 to P45, P50 to P57, P60 to P67 RST, MODA, INT10 to INT17, INT20 to INT23, SI,SCK,EC1,UCK, SCK1,UI,SI1,PWC — — VSS +1.4 0.7 VCC — — VSS + 5.5 VSS + 5.5 V V SMB input buffer selected I2C input buffer selected VIL — VSS − 0.3 — 0.3 VCC V CMOS “L” level input voltage VILS — VSS − 0.3 — 0.2 VCC V Hysteresis VILSMB SCL, SDA VILI2C P60 to P67, P50 to P57 VD P60 to P67, P50 to P57 P46, P47, P30, P31 P00 to P07, P10 to P17, P40 to P45 P20 to P27  — — — — VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 4.0 4.0 — — — — — VSS + 0.6 0.3 VCC VCC + 0.3 V3 VSS + 5.5 V V V V V SMB input buffer selected I2C input buffer selected Resister Ladder option LCD booster option Open-drain output pin application voltage “H” level output voltage VOH IOH = –2.0 mA IOH = –15.0 mA — — — — V (Continued) 33 MB89560A Series (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C) Value Condition Unit Remarks Min Typ Max Parameter Symbol Pin P00 to P07, P10 to P17, P30, P31, P40 to P47, P50 to P57, P60 to P67, RST P20 to P27 P00 to P07, P10 to P17, P20 to P27, P40 to P45 “L” level output voltage VOL IOL = 4.0 mA — — 0.4 V IOL = 15.0 mA — −5 — — 0.4 +5 µA Without pull-up Resistor Resistor Ladder option LCD booster option MB89PV560 MB89P568 Resistor Ladder option LCD booster option Input leakage current (High-Z output leakage current) 0.0 V < VI < VCC −5 0.0 V < VI < V3 0.0 V < VI < VCC 0.0 V < VI < VCC 0.0 V < VI < V3 0.0 V < VI < Vss + 5.5 V −5 − 10 — — — — — — — — — +5 +5 +10 +5 +5 +5 µA µA µA µA µA µA ILI P50 to P57, P60 to P67 P50 to P57, P60 to P67 MODA P50 to P57, P60 to P67 Open-drain output leakage current ILIOD P50 to P57, P60 to P67 P30, P31, P46, P47 P00 to P07, P10 to P17, P20 to P27, P40 to P45, RST MODA Pull-up resistance Pull-down resistance RPULL VI = 0.0 V 25 50 100 kΩ When pull-up resistor selected except RST MB89567A/ MB89567AC MB89PV560 MB89P568 MB89567A MB89567AC MB89PV560 MB89P568 MB89567A MB89567AC MB89PV560 MB89P568 MB89567A MB89567AC (Continued) RMODA VI = 3.0 V FCH = 10 MHz, tinst*2 = 0.4 µs, Main clock run mode FCH = 10 MHz, tinst*2 = 6.4 µs, Main clock run mode FCH = 10 MHz, tinst*2 = 0.4 µs, Main clock sleep mode 50 — — — — — — 100 15 8 5 1 5 2.5 200 20 kΩ ICC1 mA 13 8.5 mA 3 7 mA 5 Power supply current *1 ICC2 VCC ICCS1 34 MB89560A Series (Continued) Parameter Symbol Pin (AVCC = VCC = 5.0 V, , AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C) Condition FCH = 10 MHz, tinst*2 = 6.4 µs, Sleep mode FCL = 32.768 kHz, Subclock mode, TA = +25 °C Value Min — — — — — — Typ 1.5 0.7 3 50 30 15 5 — 1.6 15 Max 3 Unit Remarks MB89PV560 MB89P568 MB89567A MB89567AC MB89PV560 MB89P568 MB89567A MB89567AC MB89PV560 MB89P568 MB89567A MB89567AC MB89PV560 MB89P568 MB89567A MB89567AC MB89PV560 MB89P568 MB89567A MB89567AC ICCS2 mA 2 7 85 50 µA 30 15 µA µA µA µA kΩ kΩ mA µA ICCL Power supply current *1 ICCLS VCC FCL = 32.768 kHz, Subclock sleep mode, TA = +25 °C FCL = 32.768 kHz, TA = +25 °C, Watch mode, Main clock stop mode TA = +25 °C, Subclock stop mode Between VCC and VSS ICCT Power supply current *1 LCD divided resistance COM0 to COM3 output impedance SEG0 to SEG23 output impedance LCD controller/ driver leakage current Input capacitance 3 — 1 300 — 500 — 10 10 750 5 ICCH VCC RLCD RVCOM — COM0 to COM3 V1 to V3 = 5.0 V RVSEG SEG0 to SEG23 V0 to V3, COM0 to COM3, SEG0 to SEG23 — — 15 kΩ ILCDL — −1 — 1 µA CIN Other than AVCC, AVSS, VCC, and f = 1 MHz VSS — 10 — pF *1 : The power supply current is measured at the external clock *2 : For information on tinst, see “5. AC Characteristics (4) Instruction Cycle.” Note : For LCD and port multiplex pin (P50 to P57, P60 to P67), please refer to LCD specification when the port is used, and refer to LCD specification when used as LCD pin. 35 MB89560A Series 4. DC Characteristics (power supply voltage : 3.0V) Parameter Symbol Pin P00 to P07, P10 to P17, P20 to P27, P30 to P31, P40 to P45, P50 to P57, P60 to P67 RST, MODA, INT10 to INT17, INT20 to INT23, SI,SCK,EC1,UCK, SCK1,UI,SI1,PWC (AVCC = VCC = 3.0V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C) Value Condition Unit Remarks Min Typ Max VIH — 0.7 VCC — VCC + 0.3 V CMOS “H” level input voltage VIHS — 0.8 VCC — VCC + 0.3 V Hysteresis VIHSMB SCL, SDA VIHI2C P00 to P07, P10 to P17, P20 to P27, P30 to P31, P40 to P45, P50 to P57, P60 to P67 RST, MODA, INT10 to INT17, INT20 to INT23, SI,SCK,EC1,UCK, SCK1,UI,SI1,PWC — — VSS +1.4 0.7 VCC — — VSS + 5.5 VSS + 5.5 V V SMB input buffer selected I2C input buffer selected VIL — VSS − 0.3 — 0.3 VCC V CMOS “L” level input voltage VILS — VSS − 0.3 — 0.2 VCC V Hysteresis VILSMB SCL, SDA VILI2C P60 to P67, P50 to P57 VD P60 to P67, P50 to P57 P46, P47, P30, P31 P00 to P07, P10 to P17, P40 to P45 P20 to P27 — — — — — VSS - 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 2.4 2.4 — — — — — VSS + 0.6 0.3 VCC VCC + 0.3 V3 VSS + 5.5 V V V V V SMB input buffer selected I2C input buffer selected Resistor Ladder option LCD booster option Open-drain output pin application voltage “H” level output voltage VOH IOH = –2.0 mA IOH = –10 mA — — — — V (Continued) 36 MB89560A Series (AVCC = VCC = 3.0V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C) Value Condition Unit Remarks Min Typ Max Parameter Symbol Pin P00 to P07, P10 to P17, P30, P31, P40 to P47, P50 to P57, P60 to P67, RST P20 to P27 P00 to P07, P10 to P17, P20 to P27, P40 to P45 “L” level output voltage VOL IOL = 4.0 mA — — 0.4 V IOL = 10 mA — — 0.4 +5 µA Without pull-up Resister Resister Ladder option LCD booster option MB89PV560 MB89P568 Resister Ladder option LCD booster option –5 0.0 V < VI < VCC –5 — Input leakage current (Hi-z output leakage current) ILI P50 to P57, P60 to P67 P50 to P57, P60 to P67 MODA P50 to P57, P60 to P67 0.0 V < VI < V3 0.0 V < VI < VCC — +5 +5 +10 µA µA µA µA µA µA –5 –10 — — 0.0 V < VI < VCC — — +5 Open-drain output leakage current ILIOD P50 to P57, P60 to P67 P30, P31, P46, P47 P00 to P07, P10 to P17, P20 to P27, P40 to P45, RST MODA 0.0 V < VI < V3 0.0 V < VI < Vss + 5.5 V — — — — +5 +5 Pull-up resistance RPULL VI = 0.0 V 50 100 200 kΩ When pull-up resistor selected except RST MB89567A MB89567AC MB89PV560 MB89P568 MB89567A MB89567AC MB89PV560 MB89P568 MB89567A MB89567AC Pull-down resistance RMODA VI = 5.0 V FCH = 10 MHz, tinst*2 = 0.4 µs, Main clock run mode 25 — — 50 6 4 1.5 0.4 100 10 kΩ ICC1 Power supply current *1 ICC2 VCC mA 9 3 mA 2 FCH = 10 MHz, tinst*2 = 6.4 µs, Main clock run mode — — (Continued) 37 MB89560A Series (Continued) Parameter Symbol Pin (AVCC = VCC = 3.0 V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C) Value Condition Unit Remarks Min Typ Max FCH = 10 MHz, tinst*2 = 0.4 µs, Main clock sleep mode FCH = 10 MHz, tinst*2 = 6.4 µs, Main clock sleep mode FCL = 32.768 kHz, Subclock mode, TA = +25 °C VCC ICCLS FCL = 32.768 kHz, Subclock sleep mode , TA = +25 °C FCL = 32.768 kHz, TA = +25 °C, Watch mode, Main clock stop mode TA = +25 °C, Subclock stop mode — COM0 to COM3 V1 to V3 = 3.0 V SEG0 to SEG23 V0 to V3, COM0 to COM3, SEG0 to SEG23 — — –1 — — 15 1 kΩ µA Between VCC and VSS — — — — — — — — 2 1 1 0.3 1 25 15 8 5 — 1 14 µA 4 mA 3 2 mA 1.5 3 60 30 µA 25 15 µA mA µA MB89PV560 MB89P568 MB89567A MB89567AC MB89PV560 MB89P568 MB89567A MB89567AC MB89PV560 MB89P568 MB89567A MB89567AC MB89PV560 MB89P568 MB89567A MB89567AC MB89PV560 MB89P568 MB89567A MB89567AC ICCS1 ICCS2 ICCL Power supply current *1 ICCT ICCH LCD divided resistance COM0 to COM3 output impedance — 300 — 1 500 — 5 750 5 µA kΩ kΩ RLCD RVCOM SEG0 to 23 output RVSEG impedance LCD controller/ driver leakage current Input capacitance ILCDL CIN Other than AVCC, AVSS, VCC, and f = 1 MHz VSS — 10 — pF *1 : The power supply current is measured at the external clock *2 : For information on tinst, see “5. AC Characteristics (4) Instruction Cycle.” Note : For LCD and port multiplex pin (P50 to P57, P60 to P67), please refer to LCD specification when the port is used, and refer to LCD specification when used as LCD pin. 38 MB89560A Series 5. AC Characteristics (1) Reset Timing (VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Value Condition Unit Remarks Min Max — 48 tHCYL — ns Parameter RST “L” pulse width Symbol tZLZH Notes : • tHCYL is the oscillation cycle (1/FCH) to input to the X0 pin. • If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST) . t ZLZH RST 0.2 V CC 0.2 V CC (2) Power-on Reset Value Min 0.5 1 (AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol tR tOFF Condition — Max 50 — Unit ms ms Due to repeated operations Remarks Parameter Power supply rising time Power supply cut-off time Note : Make sure that power supply rises within the selected oscillation stabilization time. For example, when the main clock is operating at 10 MHz (FCH) and the oscillation stabilization time select option has been set to 218/FCH, the oscillation stabilization delay time is 26.2 ms. Therefore, the maximum value of power supply rising time is about 26.2 ms. Rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR 2.0 V 0.2 V 0.2 V tOFF VCC 0.2 V 39 MB89560A Series (3) Clock Timing Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time Symbol FCH FCL tHCYL tLCYL PWH PWL tCR tCF Pin X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0 Min 1 — 80 — 20 — (AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C) Value Unit Remarks Typ Max — 32.768 — 30.5 — — 12.5 — 1000 — — 10 MHz Main clock kHz ns µs ns ns Subclock Main clock Subclock External clock External clock X0 and X1 Timing and Conditions tHCYL PWH tCR 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2VCC 0.8 VCC tCF PWL Main Clock Conditions When using a crystal oscillator or ceramic oscillator When using an external clock X0 X1 FCH C1 C2 X0 X1 Open FCH 40 MB89560A Series X0A and X1A Timing tLCYL 0.7 VCC X0A 0.3 VCC 0.7 VCC 0.3 VCC 0.3 VCC When using a crystal oscillator X0A X1A FCL C1 C2 Note : External clock is not available. (4) Instruction Cycle Parameter Instruction cycle (minimum execution time) Symbol Value (AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C) Unit µs µs Remarks tinst = 0.32 µs when operating at FCH = 12.5 MHz (4/FCH) tinst = 61.036 µs when operating at FCL = 32.768 kHz 4/FCH, 8/FCH, 16/FCH, 64/FCH tinst 2/FCL 41 MB89560A Series (5) Serial I/O Timing Parameter Serial clock cycle time SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SO time Valid SI → SCK ↑ SCK ↑ → valid SI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin (Vcc = 5.0V, AVSS = VSS= 0.0 V, TA = –40 °C to +85 °C) Value Condition Unit Remarks Min Max 2 tinst* –200 Internal shift clock mode 200 200 1 tinst* 1 tinst* External shift clock mode 0 200 200 — +200 — — — — 200 — — µs ns ns ns µs µs ns ns ns SCK, SCK1, UCK SCK, SO, SCK1, SO1, UCK, UO SI, SCK, SI1, SCK1, UI, UCK SCK, SI, SCK1, SI1, UCK, UI SCK, SCK1, UCK SCK, SO, SCK1, SO1, UCK, UO SI, SCK, SI1, SCK1, UI, UCK SCK, SI, SCK1, SI1, UCK, UI * : For information on tinst, see “(4) Instruction Cycle.” 42 MB89560A Series Internal Shift Clock Mode tSCYC SCK SCK1 UCK SO SO1 UO SI SI1 UI 0.8 VCC 0.2 VCC tSLOV 0.8 VCC 0.2 VCC tIVSH 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC 0.2 VCC External Shift Clock Mode tSLSH SCK SCK1 UCK 0.2 VCC SO SO1 UO SI SI1 UI 0.2 VCC tSLOV 0.8VCC 0.2 VCC tIVSH 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC 0.8 VCC tSHSL 0.8 VCC (6) Peripheral Input Timing Parameter Peripheral input “H” pulse width 1 Peripheral input “L” pulse width 1 Symbol tILIH1 tIHIL1 (Vcc = 5.0V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C) Value Pin Condition Unit Remarks Min Max INT10 to INT17, INT20 to INT23, EC, PWC 2 tinst* — 2 tinst* — — µs µs * : For information on tinst, see “(4) Instruction Cycle.” tIHIL1 tILIH1 INT10 INT17, INT20 INT23, EC,PWC 0.2 VCC 0.8 VCC 0.2 VCC 0.8 VCC 43 MB89560A Series (7) I2C timing Parameter Start condition output Stop condition output Start condition detect Stop condition detect Re-start condition output Re-start condition detect SCL output LOW width SCL output HIGH width SDA output delay SDA output setup time after interrupt SCL input LOW pulse width SCL input HIGH pulse width SDA input setup time SDA hold time Symbol tSTA tSTO tSTA tSTO tSTASU tSTASU tLOW tHIGH tDO tDOSU tLOW tHIGH tSU tHO Pin SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SCL SDA SDA SCL SCL SDA SDA Condition — — — — — — — — — — — — — — (Vcc = 5.0 V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C) Value Unit Remarks Min Max 1/4 tinst*1 × M*2 x N*3 - 20 1/4 tinst × M*2 x N*3 + 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns *4 Master mode Master mode Master mode Master mode Master mode 1/4 tinst × 1/4 tinst × (M*2 × N*3 + 8) - 20 (M*2 × N*3 + 8) + 20 1/4 tinst × 6 + 40 1/4 tinst × 6 + 40 — — 1/4 tinst × 1/4 tinst × (M*2 × N*3 + 8) - 20 (M*2 × N*3 + 8) + 20 1/4 tinst × 4 + 40 1/4 tinst × M*2 × N*3 - 20 — 1/4 tinst × M*2 × N*3 + 20 1/4 tinst × 1/4 tinst × (M*2 × N*3 + 8) - 20 (M*2 × N*3 + 8) + 20 1/4 tinst × 4 - 20 1/4 tinst × 4 - 20 1/4 tinst × 6 + 40 1/4 tinst × 2 + 40 40 0 1/4 tinst × 4 + 20 — — — — — *1 : For information in tinst, see " (4) Instruction Cycle". *2 : M is defined in the ICCR CS4 and CS3 (bit 4 to bit 3) . For details, please refer to the H/W manual register explanation. *3 : N is defined in the ICCR CS2 to CS0 (bit 2 to bit 0) . *4 : When the interrupt period is greater than SCL "L" width, SDA and SCL output (Standard) value is based on hypothesis when rising time is 0 ns. 44 MB89560A Series Data transmit (master/slave) tDO SDA tSTASU tSTA SCL tLOW tHO 1 9 tDO tSU tHO ACK tDOSU Data receive (master/slave) tSU SDA tHIGH SCL 6 7 tLOW 8 9 tHO tDO ACK tSTO tDO tDOSU 45 MB89560A Series 6. A/D Converter Electrical Characteristics (1) For MB89567A/AC A/D Converter (AVcc = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C) Value Condition Unit Remarks Min Typ Max — — — — — — VOT — VFST AVR=AVCC AVss – 1.5 LSB AVR – 3.5 LSB — — — — — IAIN VAIN AN0 to AN7 — AVss — — 10 AVR µA V when A/D mA conversion is activated when A/D µA conversion is stopped V µA µA *2 — — — — AVss + 0.5 LSB AVR – 1.5 LSB — 60 tinst*1 16 t * inst 1 Parameter Resolution Total error Non-linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Interchannel disparity A/D mode conversion time *3 A/D Sampling time Analog port input current Analog input voltage Symbol Pin 10 ±3.0 ±2.5 ±1.9 AVss + 2.5 LSB AVR + 1.5 LSB 4 — bit LSB LSB 1LSB = AVR/1024 LSB mV mV LSB 1LSB = AVR/1024 µs — IA Power supply current IAH Reference voltage Reference voltage supply current AVCC — — 4 6 TA = +25 °C — AVR A/D is Activated A/D is Stopped — 1 5 — IR IRH AVss+3.5 — — — 200 — AVCC — 5 *1 : For information on tinst, see “(4) Instruction Cycle” in “5. AC Characteristics.” *2 : When A/D conversion is not in operation, and the CPU is in STOP mode. *3 : Included sampling time 46 MB89560A Series (2) For MB89P568/PV560 A/D Converter Parameter Resolution Total error Non-linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Interchannel disparity A/D mode conversion time *3 A/D Sampling time Analog port input current Analog input voltage Symbol Pin (AVcc=3.5 V to 5.5 V, AVSS = VSS = 0.0 V, TA = –40 °C to +85 °C) Value Condition Unit Remarks Min Typ Max — — — — — — — — — AVss + 0.5 LSB AVR – 1.5 LSB — 60 tinst*1 16 t * — — 4 inst 1 10 ±3.0 ±2.5 ±1.9 AVss + 2.5 LSB AVR + 1.5 LSB 4 — — 10 AVR 6 bit LSB 1LSB = LSB AVR/1024 — LSB mV mV LSB 1LSB = AVR/1024 VOT — VFST AVR=AVCC AVss – 1.5 LSB AVR – 3.5 LSB — — — — — — AVss — AVCC — µs µA V when A/D mA conversion is activated when A/D µA conversion is stopped V µA µA *2 IAIN VAIN IA AN0 to AN7 Power supply current IAH Reference voltage Reference voltage supply current — IR IRH TA = +25 °C — AVR A/D is Activated A/D is Stopped — AVss + 3.5 — — 1 — 400 — 5 AVCC — 5 *1 : For information on tinst, see “(4) Instruction Cycle” in “5. AC Characteristics.” *2 : When A/D conversion is not in operation, and the CPU is in STOP mode. *3 : Included sampling time 47 MB89560A Series (3) A/D Converter Glossary • Resolution Analog changes that are identifiable with the A/D converter. • Linearity error The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics • Differential linearity error The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value • Total error (unit: LSB) The difference between theoretical and actual conversion values caused by the zero transition error, full-scale transition error, linearity error, quantization error, and noise Theoretical I/O characteristics 3FF 3FE 3FD 1.5 LSB VFST 3FF 3FE 3FD Total error Actual Conversion Characteristic {1 LSB × N + 0.5 LSB} Digital Output Digital Output 004 003 002 001 0.5 LSB AVSS AVR 004 003 002 001 AVSS VNT VOT 1 LSB Actual Conversion Characteristic Theoretical Conversion Characteristic AVR Analog Input VFST − VOT 1022 Analog Input VNT − {1 LSB × N + 0.5 LSB} 1 LSB 1 LSB = (V) Total error for digital output N = (Continued) 48 MB89560A Series (Continued) Zero transition error Full-scale transition error Theoretical Characteristic 3FF 004 Actual Conversion Characteristic Digital Output Actual Conversion Characteristics Digital Output 003 3FE 002 VFST 3FD 001 Actual Conversion Characteristic (actual measured value) Actual Conversion Characteristic VOT (actual measured value) AVSS 3FC AVR Linearity error Differential linearity error 3FF 3FE Actual Conversion Characteristic Digital Output {1 LSB × N + VOT} N+1 Digital Output Actual Conversion Characteristic 3FD V(N + 1)T VFST 004 003 002 001 VOT AVSS N (actual measured value) Actual Conversion Characteristic Theoretical Characteristic (actual measured value) AVR VNT N−1 VNT (actual measured value) N−2 Actual Conversion Characteristic AVR AVSS Analog Input Analog Input Linearity error in digital output N = VNT − {1 LSB × N + 0.5 LSB} 1 LSB Differential linearity error in digital output N = V(N + 1)T − VNT −1 1 LSB 49 MB89560A Series (4) Precautions • The smaller the | AVR–AVSS | is, the greater the error would become relatively. • The output impedance of the external circuit for the analog input must satisfy the following conditions : Output impedance of the external circuit < Approx. 10 kΩ • If the output impedance of the external circuit is too high, an analog voltage sampling time might be insufficient. Analog Input equivalent circuit Sample hold circuit * . C = 45 pF . Analog input pin Comparator If the analog input impedance is higher than 10 kΩ, it is recommended to connect an external capacitor of approx. 0.1 µF. . R = 2.2 kΩ . Close for 8 instruction cycles after starting A/D conversion. Analog channel selector * : The value of R and C at the sample hold circuit depends on the following. MB89567A/MB89567AC : R = 2.2 kΩ, C = 45 pF : : MB89P568/MB89PV560 : R = 1.4 kΩ, C = 64 pF : : 50 MB89560A Series s EXAMPLE CHARACTERISTICS (1) “L” Level Output Voltage VCC - VOL1 vs. IOL VCC = 4.0 V VCC = 5.0 V VCC = 2.5 V VCC = 3.0 V VCC = 3.5 V VCC = 4.5 V VCC = 5.5 V VCC = 6.0 V VCC = 6.5 V 1.0 0.9 0.8 VCC - VOL1 (V) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 2 4 6 8 10 IOL (mA) 12 14 16 18 20 (2) “H” Level Output Voltage VCC - VOH1 vs. IOH 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 -2 -4 IOH (mA) VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VCC = 6.0 V VCC = 6.5 V VCC - VOH1 (V) -6 -8 -10 51 MB89560A Series (3) “H” Level Input Voltage / “L” Level Input Voltage CMOS input 5.0 4.5 4.0 3.5 TA = + 25 °C Hysteresis input 5.0 4.5 4.0 3.5 VIN (V) TA = + 25 °C VIHS VIN (V) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1 2 3 4 VCC (V) 5 6 7 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1 2 3 4 VCC (V) 5 6 7 VILS VIHS : Threshold when input voltage in hysteresis characteristics is set to “H” level. VILS : Threshold when input voltage in hysteresis characteristics is set to “L” level. 52 MB89560A Series (4) Power Supply Current (External Clock) ICC1 vs. VCC (Mask ROM products) ICC2 vs. VCC (Mask ROM products) 15 TA = + 25 °C 12 ICC1 (mA) 1.2 TA = + 25 °C FCH = 12.5 MHz 1.0 0.8 FCH = 12.5 MHz FCH = 10.0 MHz 9 FCH = 10.0 MHz ICC2 (mA) 0.6 0.4 0.2 FCH = 1.0 MHz FCH = 4.2 MHz FCH = 3.0 MHz 6 FCH = 4.2 MHz 3 0 0 1 2 3 4 VCC (V) ICCS1 vs. VCC (Mask ROM products) 4.0 3.5 3.0 ICCS1 (mA) 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 3 4 5 TA = + 25 °C FCH = 3.0 MHz FCH = 1.0 MHz 0.0 5 6 7 0 1 2 3 4 VCC (V) 5 6 7 0.7 FCH = 12.5 MHz FCH = 10.0 MHz ICCS2 vs. VCC (Mask ROM products) TA = + 25 °C FCH = 12.5 MHz 0.6 0.5 ICCS2 (mA) FCH = 10.0 MHz 0.4 0.3 0.2 0.1 FCH = 3.0 MHz FCH = 1.0 MHz FCH = 4.2 MHz FCH = 4.2 MHz FCH = 3.0 MHz FCH = 1.0 MHz 0.0 6 7 VCC (V) 0 1 2 3 4 VCC (V) 5 6 7 ICCL vs. VCC (Mask ROM products) ICCT vs. VCC 4.0 3.6 3.2 2.8 ICCT (µA) (Mask ROM products) 100 TA = + 25 °C 80 ICCL (µA) TA = + 25 °C FCL = 32.768 kHz 60 FCL = 32.768 kHz 2.4 2.0 1.6 1.2 0.8 0.4 0.0 40 20 0 0 1 2 3 4 VCC (V) 5 6 7 0 1 2 3 4 VCC (V) 5 6 7 (Continued) 53 MB89560A Series (Continued) ICCLS vs. VCC (Mask ROM products) 22 20 18 16 14 12 10 8 6 4 2 0 0 TA = + 25 °C ICCLS (µA) 1 2 3 4 VCC (V) 5 6 7 IA VS. AVCC 4.0 3.5 3.0 2.5 IA (mA) IR vs. AVR 200 180 160 FCH = 10.0 MHz TA = + 25 °C IR (µA) 140 120 100 80 60 40 20 0 TA = + 25 °C 2.0 1.5 1.0 0.5 0.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 AVCC (V) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 AVR (V) (5) Pull-up Resistance Rpull vs.VCC 210 190 170 Rpull (kΩ) 150 130 110 90 70 50 30 10 2 3 4 5 VCC (V) 6 7 TA = + 93 °C TA = + 25 °C TA = − 40 °C 8 54 MB89560A Series s MASK OPTIONS Model No. Specification method MB89567A MB89567AC Specify when ordering mask. MB89P568 Setting unavailable. MB89PV560 Setting unavailable. 1 Main clock oscillation stabilization delay time initial value* selection (FCH = 10 MHz) • 01: 214/FCH (Approx. 1.6 ms) Selectable • 10: 217/FCH (Approx. 13.1 ms) • 11: 218/FCH (Approx. 26.2 ms) LCD driving power supply • On-chip voltage booster • Internal voltage divider (external divider resistors can be used) 218/FCH (Approx. 26.2 ms) 218/FCH (approx. 26.2 ms) 2 Selectable -101 Internal voltage divider -102 On-chip voltage booster -101 Internal voltage divider -102 On-chip voltage booster s ORDERING INFORMATION Part number MB89567APFV MB89567ACPFV MB89P568PFV-101 MB89567APFV MB89567ACPFV MB89P568PFV-102 MB89567APF MB89567ACPF MB89P568PF-101 MB89567APF MB89567ACPF MB89P568PF-102 MB89567APFM MB89567ACPFM MB89P568PFM-101 MB89567APFM MB89567ACPFM MB89P568PFM-102 MB89PV560CF-101 MB89PV560CF-102 Package Remarks Without Booster Resistor divider 80-pin Plastic LQFP (FPT-80P-M05) With Booster 80-pin Plastic QFP (FPT-80P-M06) Without Booster Resistor divider With Booster 80-pin Plastic LQFP (FPT-80P-M11) Without Booster Resistor divider With Booster Without Booster Resistor divider With Booster 80-pin Ceramic MQFP (MQP-80C-P01) 55 MB89560A Series s PACKAGE DIMENSIONS 80-pin plastic LQFP (FPT-80P-M05) 14.00±0.20(.551±.008)SQ 12.00±0.10(.472±.004)SQ 60 41 *Pins width and pins thickness include plating thickness. 0.145±0.055 (.006±.002) 61 40 0.08(.003) Details of "A" part 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) INDEX 80 21 0°~8° 0.10±0.10 (.004±.004) (Stand off) "A" LEAD No. 1 20 0.50(.020) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) 0.20±0.05 (.008±.002) 0.08(.003) M C 2000 FUJITSU LIMITED F80008S-c-3-7 Dimensions in mm (inches) (Continued) 56 MB89560A Series 80-pin plastic QFP (FPT-80P-M06) 23.90±0.40(.941±.016) 20.00±0.20(.787±.008) 64 41 *Pins width and pins thickness include plating thickness. 65 40 0.10(.004) 17.90±0.40 (.705±.016) 14.00±0.20 (.551±.008) INDEX Details of "A" part 80 25 0.25(.010) +0.30 3.05 –0.20 +.012 .120 –.008 (Mounting height) 1 24 0.80(.031) 0~8° M 0.37±0.05 (.015±.002) 0.20(.008) 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.30 –0.25 +0.10 +.004 "A" .012 –.010 (Stand off) C 2001 FUJITSU LIMITED F80010S-c-4-4 Dimensions in mm (inches) (Continued) 57 MB89560A Series 80-pin plastic LQFP (FPT-80P-M11) 16.00±0.20(.630±.008)SQ 14.00±0.10(.551±.004)SQ 60 41 *Pins width and pins thickness include plating thickness. 0.145±0.055 (.006±.002) 61 40 0.10(.004) Details of "A" part 1.50 –0.10 .059 –.004 (Mounting height) 0.25(.010) INDEX 0~8° 21 +0.20 +.008 80 1 20 "A" 0.13(.005) M 0.65(.026) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) (Stand off) 0.32±0.05 (.013±.002) C 2001 FUJITSU LIMITED F80016S-c-2-5 Dimensions in mm (inches) (Continued) 58 MB89560A Series (Continued) 80-pin ceramic (MQP-80C-P01) 18.70(.736)TYP 12.00(.472)TYP 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) 1.50(.059)TYP 1.00(.040)TYP 4.50(.177) TYP 1.20 –0.20 .047 –.008 +0.40 +.016 INDEX AREA 0.80±0.25 (.0315±.010) 0.80±0.25 (.0315±.010) 1.27±0.13 (.050±.005) 22.30±0.33 (.878±.013) 24.70(.972) TYP 0.30(.012) TYP 18.12±0.20 12.02(.473) (.713±.008) TYP 10.16(.400) 14.22(.560) TYP TYP INDEX AREA 18.40(.724) REF INDEX 6.00(.236) TYP 0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP 0.40±0.10 (.016±.004) 1.50(.059) TYP 1.00(.040) TYP 1.27±0.13 (.050±.005) 0.40±0.10 (.016±.004) 1.20 –0.20 .047 –.008 +0.40 +.016 0.15±0.05 8.70(.343) (.006±.002) MAX C 1994 FUJITSU LIMITED M80001SC-4-2 Dimensions in mm (inches) 59 MB89560A Series FUJITSU LIMITED All Rights Reserved. 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