MB89PV680CF

FUJITSU SEMICONDUCTOR DATA SHEET DS07-12525-2E 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89680 Series MB89689/P689/W689/PV680 s OUTLINE The MB89680 series is a line of single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as dual-clock control system, four operating speed control stages, timers, PWM timer, a serial interface, a UART, an A/D converter, and an external interrupt. s FEATURES • • • • • • • • • • • • • • • • • • F2MC-8L family CPU core Dual-clock control system Maximum memory space: 64 Kbytes Minimum execution time: 0.5 µs/8 MHz Interrupt processing time: 4.5 µs/8 MHz I/O ports: max. 85 channels 21-bit timebase counter 8-bit PWM timer 8/16-bit timer UART Serial I/O with 1-byte buffer 8-bit A/D converter Pulse width counter Modem signal output External interrupts: 16 channels Power-on reset function Low-power consumption modes (subclock mode, watch mode, sleep mode, and stop mode) CMOS technology s PACKAGE 100-pin Plastic QFP 100-pin Ceramic QFP 100-pin Ceramic MQFP (FPT-100P-M06) (FPT-100C-A02) (MQP-100C-P01) MB89680 Series s PRODUCT LINEUP Part number Item Classification MB89689 MB89P689 MB89W689 MB89PV680 Piggyback/ evaluation product (for development) 60 K × 8 bits (external ROM) Mass-produced One-time PROM product product (mask ROM product) 60 K × 8 bits (internal mask ROM) 60 K × 8 bits (internal PROM) EPROM product 60 K × 8 bits (internal EPROM) ROM size RAM size Instruction bit length Instruction length Data bit length Number of instructions Clock generator Minimum execution time Interrupt processing time Ports ( ) indicate dual function ports 2.0 K × 8 bits 8 bits 1 byte to 3 bytes 1, 8, 16 bits 136 Built-in 0.5 µs/8 MHz to 8 µs/8 MHz, 61 µs/32.768 kHz 4.5 µs/8 MHz to 72 µs/8 MHz, 562.5 µs/32.768 kHz Output ports (N-ch open-drain): Output ports (CMOS): I/O ports (N-ch open-drain): I/O ports (CMOS): Total: 8 bits × 1 channel 8 bits × 2 channels, or 16 bits × 1 channel With 1-byte buffer × 1 channel 8 bits × 8 channels Full-duplex double buffer Transfer data length: 6 bits to 8 bits 8 baud rates selectability, external clock available 5-bit noise reduction circuit Pulse edge detectable and selectable (rising, falling, and both edges) 1200-bps/2400-bps modem output 16 channels 21 bits 15 bits Watch mode, subclock mode, sleep mode, and stop mode CMOS 2.2 V to 6.0 V 2.7 V to 6.0 V MBM27C512-20TV 21 (8) 8 (0) 8 (6) 48 (29) 85 (43) 8-bit PWM timer 8/16-bit timer/counter 8-bit serial I/O 8-bit A/D converter UART Pulse width counter Software modem transmission circuit External interrupt Timebase timer Watch prescaler Standby mode Process Power supply voltage* EPROM for use * : Varies with conditions such as the operating frequency. (See section “s ELECTRICAL CHARACTERISTICS.”) 2 MB89680 Series s PACKAGE AND CORRESPONDING PRODUCTS Package FPT-100P-M06 FPT-100C-A02 MQP-100C-P01 : Available × × × MB89689 MB89P689 MB89W689 × MB89PV680 × × × : Not available Note: For more information about each package, see section “s Package Dimensions.” s DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the piggyback product, verify its differences from the product that will actually be used. 2. Current Consumption In the case of the MB89PV680, add the current consumed by the EPROM which is connected to the top socket. When operated at low speed, the product with an OTPROM or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same. 3. Mask Options Functions that can be selected as options and how to designate these options vary by the product. Before using options check section “s Mask Options.” Take particular care on the following points: • Options are fixed on the MB89PV680. 3 MB89680 Series s PIN ASSIGNMENT (Top view) PA7/INT3 PA6/INT2 PA5/INT1 PA4/INT0 PA3/INLB N.C. AVR (AVCC) VCC P57/AN07 P56/AN06 P55/AN05 P54/AN04 P53/AN03 P52/AN02 P51/AN01 P50/AN00 (AVSS) VSS PA2/INLA PA1/INL9 PA0/INL8 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 VCC X1A X0A MOD0 MOD1 X0 X1 VSS RST P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P97/INL7 P96/INL6 P95/INL5 P94/INL4 P93/INL3 P92/INL2 P91/INL1 P90/INL0 P87 P86 P85 P84 P83 P82 P81 P80 P77 P76 P75/BSO2 P74/BSI2 P73/BSK2 VSS P72/UO2 P71/UI2 P70/UCK2 P67/BSO1 P66/BSI1 P65/BSK1 P64 P63/MSKO 4 P25 P26 P27 P40 P41 P42 P43 P44 P30/PWM P31/BUZR P32/MSKI P33 P34 P35/UCK1 P36/UI1 P37/UO1 P60/TMO1 P61/TMO2 P62/TCLK VCC (FPT-100P-M06) (FPT-100C-A02) MB89680 Series (Top view) PA7/INT3 PA6/INT2 PA5/INT1 PA4/INT0 PA3/INLB N.C. AVR (AVCC) VCC P57/AN07 P56/AN06 P55/AN05 P54/AN04 P53/AN03 P52/AN02 P51/AN01 P50/AN00 (AVSS) VSS PA2/INLA PA1/INL9 PA0/INL8 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 VCC X1A X0A MOD0 MOD1 X0 X1 VSS RST P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 O7 O8 CE 01 N.C. A0 A1 A2 A3 A4 A5 A6 N.C. A15 A13 A14 A12 A10 OE N.C. A11 A9 A8 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P97/INL7 P96/INL6 P95/INL5 P94/INL4 P93/INL3 P92/INL2 P91/INL1 P90/INL0 P87 P86 P85 P84 P83 P82 P81 P80 P77 P76 P75/BSO2 P74/BSI2 P73/BSK2 VSS P72/UO2 P71/UI2 P70/UCK2 P67/BSO1 P66/BSI1 P65/BSK1 P64 P63/MSKO N.C. VSS O6 O5 O4 O3 V CC 132 • Pin assignment on package top (MB89PV680 only) Pin no. 101 102 103 104 105 106 107 108 Pin name N.C. A15 A12 A7 A6 A5 A4 A3 Pin no. 109 110 111 112 113 114 115 116 Pin name A2 A1 A0 N.C. O1 O2 O3 VSS Pin no. 117 118 119 120 121 122 123 124 Pin name N.C. O4 O5 O6 O7 O8 CE A10 Pin no. 125 126 127 128 129 130 131 132 Pin name OE N.C. A11 A9 A8 A13 A14 VCC N.C.: Internally connected. Do not use. 5 P25 P26 P27 P40 P41 P42 P43 P44 P30/PWM P31/BUZR P32/MSKI P33 P34 P35/UCK1 P36/UI1 P37/UO1 P60/TMO1 P61/TMO2 P62/TCLK VCC (MQP-100C-P01) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 101 A7 O2 MB89680 Series s PIN DESCRIPTION Pin no. QFP*1, MQFP*2 1 2 3 4 5 6 7 8 9 10 to 17 18 to 25 26 to 33 34 to 38 39 40 41 42, 43 44, 45, 46 47, 48, 49 50 51 52 53, 54, 55 Pin name VCC X1A X0A MOD0 MOD1 X0 X1 VSS RST P00 to P07 P10 to P17 P20 to P27 P40 to P44 P30/PWM P31/BUZR P32/MSKI P33, P34 P35/UCK1, P36/UI1, P37/UO1 P60/TMO1, P61/TMO2, P62/TCLK VCC P63/MSKO P64 P65/BSK1, P66/BSI1, P67/BSO1 — C D D F I E E E E E Power supply (GND) pin Reset input pin General-purpose I/O ports General-purpose I/O ports General-purpose output ports General-purpose output ports General-purpose I/O port Also serve as an 8-bit PWM. General-purpose I/O port Also serve as a buzzer output. General-purpose I/O port Also serve as a pulse width counter. General-purpose I/O ports General-purpose I/O ports Also serve as a UART I/O 1. General-purpose I/O ports Also serve as an 8/16-bit timer. Power supply pin General-purpose I/O port Also serve as a modem output. General-purpose I/O port General-purpose I/O ports Also serve as a serial I/O 1 with 1-byte buffer. A B Operating mode selection pins Connect to VSS (GND) when using. Main clock crystal oscillator pins (8 MHz) Circuit type — A Power supply pin Subclock crystal oscillator pins (32.768 kHz) Function E — E E E *1: FPT-100P-M06, FPT-100C-A02 *2: MQP-100C-P01 (Continued) 6 MB89680 Series (Continued) Pin no. QFP*1, MQFP*2 56, 57, 58 59 60, 61, 62 63, 64 65 to 72 73 to 80 81 to 83 84 85 to 92 93 94 95 96 to 100 Pin name P70/UCK2, P71/UI2, P72/UO2 VSS P73/BSK2, P74/BSI2, P75/BSO2 P76, P77 P80 to P87 P90/INL0 to P97/INL7 PA0/INL8 to PA2/INLA VSS (AVSS) P50/AN00 to P57/AN07 VCC (AVCC) AVR N.C. PA3/INLB, PA4/INT0 to PA7/INT3 Circuit type H Function General-purpose I/O ports Also serve as a UART I/O 2. Power supply (GND) pin General-purpose I/O ports Also serve as a serial I/O 2 with 1-byte buffer. General-purpose I/O ports General-purpose output ports General-purpose I/O ports External interrupt input is hysteresis input. General-purpose I/O ports External interrupt input is hysteresis input. (A/D converter) power supply (GND) pin General-purpose I/O ports Also serve as an analog input. (A/D converter) power supply pin A/D converter reference voltage input pin Internally connected pins Be sure to leave them open. General-purpose I/O ports External interrupt input is hysteresis input. — H H I E E — G — — — E *1: FPT-100P-M06, FPT-100C-A02 *2: MQP-100C-P01 7 MB89680 Series s I/O CIRCUIT TYPE Type A X1, X1A * Circuit Remarks • Main clock (A2) (At an oscillation feedback resistor of approximately 1 MΩ/5.0 V) • Subclock (A1) (At an oscillation feedback resistor of approximately 4.5 MΩ/5.0 V * The subclock circuit in the MB89PV680 contains no oscillation feedback resistor. X0, X0A Standby control signal B C R P-ch • At an output pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V • Hysteresis input N-ch D R P-ch P-ch • CMOS output • CMOS input • Pull-up resistor optional N-ch E R P-ch P-ch • CMOS output • Hysteresis input • Pull-up resistor optional N-ch (Continued) 8 MB89680 Series (Continued) Type F P-ch Circuit • CMOS output Remarks N-ch G P-ch • N-ch open-drain output • Analog input N-ch Analog input H R P-ch • N-ch open-drain output • Hysteresis input • Pull-up resistor optional N-ch I R P-ch • N-ch open-drain output • Pull-up resistor optional N-ch 9 MB89680 Series s HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in section “s Electrical Characteristics” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AV CC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 Hz to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode. 10 MB89680 Series s PROGRAMMING TO THE EPROM ON THE MB89P689/W689 The MB89P689/W689 is an OTPROM version of the MP89680 series. 1. Features • 60-Kbyte PROM on chip • Options can be set using the EPROM programmer. • Equivalent to the MBM27C1001 in EPROM mode (when programmed with the EPROM programmer) and supporting the 4-byte programming mode 2. Memory Space Memory space in each mode such as 60-Kbyte PROM, option area is diagrammed below. Address 00000H I/O 00080H RAM 2 KB 00880H Not available 00FE4H Option area 00FFCH 01000H PROM 60 KB 0FFFFH 0FFFFH 00FFCH 01000H PROM 60 KB 00FE4H Option area Not available Single chip EPROM mode (Corresponding addresses on the EPROM programmer) 00000H Not available 1FFFFH 3. Programming to the EPROM In EPROM mode, the MB89P689 functions equivalent to the MBM27C1001. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. When the operating ROM area for a single chip is 60 Kbytes (1000H to FFFFH) the PROM can be programmed as follows: • Programming procedure (1) Set the EPROM programmer to MBM27C1001. (2) Load program data into the EPROM programmer at 1000H to FFFFH. Load option data into addresses 0FE4H to 0FFCH of the EPROM programmer. (For information about each corresponding option, see “8. Setting PROM Options.”) (3) Program to 0FE4H to 0FFCH and 1000H to FFFFH with the EPROM programmer. 11 MB89680 Series 4. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program. Program, verify Aging +150°C, 48 Hrs. Data verification Assembly 5. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 6. MB89W689 Erasure In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an ultraviolet light source. A dosage of 10 W-seconds/cm2 is required to completely erase an internal EPROM. This dosage can be obtained by exposure to an ultraviolent lamp (wavelength of 2537 Angstroms (Å)) with intensity of 12000µW/cm2 for 15 to 21 minutes. The internal EPROM should be about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the internal EPROM and similar devices, will erase with light sources having wavelengths shorter than 4000 Å. Although erasure time will be much longer than with UV source at 2537 Å, nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package windows should be covered by an opaque label or substance. 12 MB89680 Series 7. EPROM Programmer Socket Adapter Part no. Package Compatible socket adapter Sun Hayato Co., Ltd. MB89P689PF QFP-100 ROM-100QF-32DP-8LA Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403 FAX: (81)-3-5396-9106 8. Setting PROM Options The programming procedure is the same as that for the program data. Options can be set by programming values at the addresses shown on the memory map. The relationship between bits and options is shown on the following bit map: • PROM option bit map Address Bit 7 Vacancy Bit 6 Vacancy Bit 5 Vacancy Bit 4 Bit 3 Reset output 1: Yes 0: No P03 Pull-up 1: No 0: Yes P13 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes P63 Pull-up 1: No 0: Yes P93 Pull-up 1: No 0: Yes PA3 Pull-up 1: No 0: Yes Bit 2 Power-on reset 1: Yes 0: No P02 Pull-up 1: No 0: Yes P12 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P62 Pull-up 1: No 0: Yes P92 Pull-up 1: No 0: Yes PA2 Pull-up 1: No 0: Yes Bit 1 Bit 0 00FE4H Single/dualclock system Readable Readable Readable 1: Dual clock and writable and writable and writable 2: Single clock Oscillation stabilization time 11 218/FCH 01 212/FCH P01 Pull-up 1: No 0: Yes P11 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes P61 Pull-up 1: No 0: Yes P91 Pull-up 1: No 0: Yes PA1 Pull-up 1: No 0: Yes 10 216/FCH 00 2 3/FCH P00 Pull-up 1: No 0: Yes P10 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes P60 Pull-up 1: No 0: Yes P90 Pull-up 1: No 0: Yes PA0 Pull-up 1: No 0: Yes P07 Pull-up 00FE8H 1: No 0: Yes P17 Pull-up 00FECH 1: No 0: Yes 00FF0H P06 Pull-up 1: No 0: Yes P16 Pull-up 1: No 0: Yes P36 Pull-up 1: No 0: Yes P66 Pull-up P05 Pull-up 1: No 0: Yes P15 Pull-up 1: No 0: Yes P35 Pull-up 1: No 0: Yes P65 Pull-up P04 Pull-up 1: No 0: Yes P14 Pull-up 1: No 0: Yes P34 Pull-up 1: No 0: Yes P37 Pull-up 1: No 0: Yes P67 Pull-up 00FF4H P64 Pull-up Readable Readable Readable 1: No and writable and writable and writable 0: Yes P97 Pull-up 1: No 0: Yes P96 Pull-up 1: No 0: Yes PA6 Pull-up 1: No 0: Yes P95 Pull-up 1: No 0: Yes PA5 Pull-up 1: No 0: Yes P94 Pull-up 1: No 0: Yes PA4 Pull-up 1: No 0: Yes 00FF8H PA7 Pull-up 00FFCH 1: No 0: Yes Notes: • Note that the option setting area addresses are at intervals of four addresses to support the 4-byte programming mode. • In three bytes between adjacent setup addresses, the value written to the preceding setup address is mirrored. Be sure to set the same data in the programmer. • Each bit is set to ‘1’ as the initialized value. 13 MB89680 Series s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C512-20TV 2. Programming Socket Adapter Package LCC-32 (Rectangle) Adapter socket part number ROM-32LC-28DP-YG Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403 FAX: (81)-3-5396-9106 3. Memory Space Address 0000H MB89PV680 I/O MBM27C512 0080H 0100H Register 0200H RAM 2 KB 0880H 1000H External ROM 60 KB FFFFH FFFFH 1000H EPROM 60 KB 4. Programming to the EPROM (1) Set the EPROM programmer to the MBM27C512. (2) Load program data into the EPROM programmer at 1000H to FFFFH. (3) Program to 1000H to FFFFH with the EPROM programmer. 14 MB89680 Series s BLOCK DIAGRAM CMOS I/O Timebase timer 8-bit PWM timer RST Port 3 Reset circuit (Watchdog) P30/PWM Buzzer output Modem timer P31/BUZR P32/MSKI P33 P34 P35/UCK1 P36/UI1 P37/UO1 X0 X1 Main clock oscillator (max 8 MHz) UART Clock controller X0A X1A 8 Subclock oscillator (32.768 kHz) N-ch open-drain output port 4 N-ch open-drain output 8-bit A/D converter CMOS I/O 8/16-bit timer 8 Port 5 5 P40 t o P44 P00 to P07 CMOS I/O port 0 Internal data bus P10 to P17 8 CMOS I/O port 1 Internal data bus 8 P50/AN00 t o P57/AN07 P20 to P27 8 CMOS I/O port 2 Modem output Port 6 P60/TMO1 P61/TMO2 P62/TCLK P63/MSKO P64 P65/BSK1 P66/BSI1 P67/BSO1 8-bit serial I/O with 1-byte buffer RAM Port 7 F2MC-8L CPU N-ch open-drain I/O ROM N-ch open-drain output port 8 8 P70/UCK2 P71/UI2 P72/UO2 P73/BSK2 P74/BSI2 P75/BSO2 P76 P77 P80 t o P87 Port 9 and port A CMOS I/O 12 8 4 4 Other pins VCC × 2, VSS × 2 MOD0, MOD1, N.C. AVCC, AVR, AVSS External interrupt 2 External interrupt 1 4 P90/INL0 t o P97/INL7 PA0/INL8 t o PA3/INLB PA4/INT0 t o PA7/INT3 15 MB89680 Series s CPU CORE 1. Memory Space The microcontrollers of the MB89680 series offer 64 Kbytes of memory for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end of I/O area, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89680 series is structured as illustrated below. • Memory space MB89689 0000H I/O 007FH 0080H 007FH 0080H 0000H MB89P689 MB89W689 MB89PV680 0000H I/O 007FH 0080H I/O 00FFH 0100H Register 01FFH 0200H 00FFH 0100H Register 01FFH 0200H 00FFH 0100H Register 01FFH 0200H RAM 2.0 KB RAM 2.0 KB RAM 2.0 KB 087FH 0880H Vacancy 0FFFH 1000H ROM 60 KB 087FH 0880H Vacancy 0FFFH 1000H ROM 60 KB 087FH 0880H Vacancy 0FFFH 1000H External ROM 60 KB FFFFH FFFFH FFFFH 16 MB89680 Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided: Program counter (PC): Accumulator (A): Temporary accumulator (T): Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS): A 16-bit register for indicating the instruction storage positions A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register for index modification A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area A 16-bit register for storing a register pointer, a condition code 16 bits PC A T IX EP SP PS : Program counter : Accumulator Initial value FFFDH Indeterminate : Temporary accumulator Indeterminate : Index register : Extra pointer : Stack pointer : Program status Indeterminate Indeterminate Indeterminate I-flag = 0, IL1, 0 = 11 The other bit values are indeterminate. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) • Structure of the program status register 15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 3 N 2 Z 1 V 0 C Vacancy Vacancy Vacancy IL1, 0 RP CCR 17 MB89680 Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. • Rule for conversion of actual addresses of the general-purpose register area RP Lower OP codes b1 ↓ b0 ↓ “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to ‘0’ otherwise. This flag is for decimal adjustment instructions. I-flag: IL1, 0: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared to ‘0’ at the reset. Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 IL0 0 1 0 1 Interrupt level 0 1 2 3 Low High-low High N-flag: Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ when the bit is cleared to ‘0’. Z-flag: V-flag: Set to ‘1’ when an arithmetic operation results in 0. Cleared to ‘0’ otherwise. Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to ‘0’ if the overflow does not occur. C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to ‘0’ otherwise. Set to the shift-out value in the case of a shift instruction. 18 MB89680 Series The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 32 banks can be used. The bank currently in use is indicated by the register bank pointer (RP). • Register bank configuration This address = 0100H + 2 × (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area 19 MB89680 Series s I/O MAP Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H (R/W) SBMR (R/W) (W) CNTR COMR (R/W) (R/W) (R/W) (R/W) PDR9 DDR9 PDRA DDRA (R/W) PDR8 (R/W) (R/W) (R/W) PDR6 DDR6 PDR7 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) SYCC SMC WDTC TBTC WPCR PDR3 DDR3 PDR4 BZCR PDR5 Read/write (R/W) (W) (R/W) (W) (R/W) Register name PDR0 DDR0 PDR1 DDR1 PDR2 Register description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register Port 2 data register (Vacancy) System clock control register Standby control register Watchdog timer control register Timebase timer control register Watch prescaler control register Port 3 data register Port 3 data direction register Port 4 data register Buzzer register Port 5 data register (Vacancy) Port 6 data register Port 6 data direction register Port 7 data register (Vacancy) Port 8 data register (Vacancy) Port 9 data register Port 9 data direction register Port A data register Port A data direction register (Vacancy) PWM control register PWM compare register (Vacancy) Serial mode register with 1 byte buffer (Continued) 20 MB89680 Series (Continued) Address 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH to 7BH 7CH 7DH 7EH 7FH Note: Do not use (vacancies). (W) (W) (W) ILR1 ILR2 ILR3 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R) (R) (R/W) (R/W) (R/W) (R) (W) (R/W) ADC1 ADC2 ADCD EIE1 EIF1 EIE2 EIF2 MDC1 MDC2 MLDH MLDL SMC SRC SSD SIDR SODR SSEL Read/write (R/W) (W) (R) (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Register name SBFR SBUFW SBUFR SBDR T2CR T1CR T2DR T1DR MODC MODA Register description Serial flag register with 1 byte buffer Serial buffer write register Serial buffer read register Serial data register with 1 byte buffer Timer 2 control register Timer 1 control register Timer 2 data register Timer 1 data register Modem output control register Modem output data register (Vacancy) A/D converter control 1 register A/D converter control 2 register A/D converter data register External interrupt 1 enable register External interrupt 1 flag register External interrupt 2 enable register External interrupt 2 flag register Modem timer control 1 register Modem timer control 2 register Modem timer “H” level data register Modem timer “L” level data register UART serial mode control register UART serial rate control register UART serial status and data register UART serial input data register UART serial output data register Serial I/O port switching register (Vacancy) Interrupt level 1 setting register Interrupt level 2 setting register Interrupt level 3 setting register (Vacancy) 21 MB89680 Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol VCC Power supply voltage AVCC AVR Input voltage Output voltage “L” level maximum output current “L” level average output current “L” level total maximum output current “L” level total average output current “H” level maximum output current “H” level average output current “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature VI VI VO IOL I OLAV ∑IOL ∑IOLAV IOH I OHAV ∑IOH ∑IOHAV PD TA Tstg Value Min. VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3          –40 –55 Max. VSS + 7.0 VSS + 7.0 VSS + 7.0 VCC + 0.3 VSS + 7.0 VCC + 0.3 20 10 120 40 –20 –10 –60 –20 200 +85 +150 Unit V V V V V V mA mA mA mA mA mA mA mA mW °C °C Peak value Average value (operating current × operating rate) Peak value Average value (operating current × operating rate) Peak value Average value (operating current × operating rate) Peak value Average value (operating current × operating rate) Set VCC = AVCC* AVR must not exceed “AVCC + 0.3 V”. Except P4, P7, P8 P4, P7, P8 Remarks * : Use AVCC and VCC set to the same voltage. Take care so that AVCC does not exceed VCC, such as when power is turned on. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 22 MB89680 Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Parameter Symbol VCC, AVCC Power supply voltage VCC, AVCC VCC, AVCC A/D converter reference input voltage Operating temperature AVR TA Value Min. 2.2* 2.7* 1.5 0.0 –40 Max. 6.0* 6.0* 6.0 AVCC +85 Unit V V V V °C Remarks Normal operation assurance range* (MB89689) Normal operation assurance range* (MB89P689/W689/PV680) Retains the RAM state in stop mode * : This values vary with the operating frequency. See Figure 1. Figure 1 Operating Voltage vs. Main Clock Operating Frequency 6 5 Operating voltage (V) Operation assurance range Analog accuracy assured in the AVCC = 3.5 V to 6.0 V range 4 3 2 1 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 Main clock operating frequency (MHz) (at an instruction cycle of 4/F CH) Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH. Since the operating voltage range is dependent of the instruction cycle, see minimum execution time if the operating speed is switched using a gear. 23 MB89680 Series WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. 24 MB89680 Series 3. DC Characteristics (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name P0, P1 P3, P6, P9, PA, RST, MOD0, MOD1, X0, X0A P7 P0, P1 P3, P6, P7, P9, PA, RST, MOD0, MOD1, X0, X0A P4, P7, P8 P5 P0 to P3, P6, P9, PA Condition Value Min. 0.7 VCC 0.8 VCC 0.8 VCC Typ. — — Max. VCC + 0.3 VCC + 0.3 VSS + 7.0 Unit V V V V V V V V V V µA Remarks VIH “H” level input voltage VIHS VIHS2 VIL “L” level input voltage VILS — VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 — — — — — — — — 0.3 VCC 0.2 VCC VSS + 7.0 VCC + 0.3 Open-drain output pin applied VD voltage “H” level output voltage “L” level output voltage Input leakage current (Hi-z output leakage current) VOH VOL1 VOL2 ILI IOH = –2.0 mA 2.4 — — — — 0.4 0.4 ±5 P0 to P4, P6 to P9, IOL = 4.0 mA PA RST P0 to P9, PA, MOD0, MOD1 IOL = 4.0 mA 0.45 V < VI < VCC FCH = 8 MHz VCC = 5.0 V Main clock opration Highest gear speed FCH = 8 MHz VCC = 5.0 V Main sleep mode Highest gear speed FCH = 32.768 kHz ICC VCC — 13 26 mA Power supply current ICCS1 VCC — 4 8 mA ICCS2 VCC VCC = 3.0 V Subclock sleep mode TA = +25°C Subclock stop mode — 25 50 µA ICCH1 VCC — — 1 µA (Continued) 25 MB89680 Series (Continued) (AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin name Condition TA = +85°C Subclock stop mode FCL = 32.768 kHz Value Min. — Typ. 1 Max. 10 Unit µA Remarks ICCH2 VCC ICSB Power supply current VCC VCC = 3.0 V Subclock operation VCC = 3.0 V Watch mode — 50 100 µA ICCT IA VCC AVCC — — — 1.5 15 3.5 µA When A/D mA conversion is activated µA pF When A/D conversion is stopped FCH = 8 MHz IAH Input capacitance CIN AVCC Other than AVCC, AVSS, VCC, and VSS f = 1 MHz — — 1 10 5 — 26 MB89680 Series 4. AC Characteristics (1) Reset Timing (VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter RST “L” pulse width RST “H” pulse width Symbol tZLZH tZHZL Condition — Value Min. 48 tXCYL* 24 tXCYL* Max. — — Unit ns ns Remarks * : tXCYL is the oscillation cycle input to the X0. tZLZH RST 0.2 VCC tZHZL 0.8 VCC 0.2 VCC 0.2 VCC (2) Specifications for Power-on Reset (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Power supply rising time Power supply cut-off time Symbol tR tOFF Condition — Value Min. — 1 Max. 50 — Unit ms ms Remarks Power-on reset function only Due to repeated operations Note: Make sure that power supply rises within the selected oscillation stabilization time selected. For example, when the main clock is operating at F CH = 8 MHz and the oscillation stabilization time is 212/FCH, the oscillation stabilization time is 0.5 ms. Therefore, the maximum value of power supply rising time is about 0.5 ms. When increasing the supply voltage during operation, voltage variation should be within twice the intended increment so that the voltage rises as smoothly as possible. tR 4.5 V tOFF VCC 0.2 V 0.2 V 0.2 V 27 MB89680 Series (3) Clock Timing (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol FCH Input clock frequency FCL tHCYL Clock cycle time tLCYL duty*1 duty1* tCR1 Input clock rising/falling time tCF1 tCR2 tCF2 *1: duty = PWH/tHCYL *2: duty1= PWHL/tHCYL 2 Pin name X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X1 X0 X0 X0A X0A Condition Value Min. 1 — 125 — Typ. — 32.768 Max. 8 — 1000 — 70 70 24 24 200 200 Unit MHz kHz ns µs % % ns ns ns ns Remarks Main clock Subclock Main clock Subclock — 30.5 — — — — — — — Input clock duty rate 30 30 — — — — External clock • Main clock timing conditions tHCYL 0.8 VCC X0 0.2 VCC PWH tCF PWL tCR 0.2 VCC 0.8 VCC 0.8 VCC • Main clock configurations When a crystal or ceramic resonator is used When an external clock is used X0 X1 X0 X1 Open FCH C0 C1 FCH 28 MB89680 Series • Subclock timing conditions tLCYL 0.8 VCC X0A 0.2 VCC PWHL tCF PWLL tCR 0.2 VCC 0.8 VCC 0.8 VCC • Subclock configurations When a crystal or ceramic resonator is used When an external clock is used X0A X1A X0A X1A Open FCL C0 C1 FCL (4) Instruction Cycle (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Minimum execution time (instruction cycle) Symbol tinst tinst Value (typical) 4/FCH, 8/FCH, 16/FCH, 64/FCH 2/FCL Unit µs µs Remarks (4/FCH) tinst = 0.5 µs when operating at FCH = 8 MHz tinst = 61.036 µs when operating at FCL = 32.768 kHz 29 MB89680 Series (5) Serial I/O Timing (AVCC = VCC = 5.0 V ±10%, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Serial clock cycle time BSK/UCK ↓ → BSO/UO time Valid BSI/UI → BSK/UCK ↑ BSK/UCK ↑ → valid BSI/UI hold time Serial clock “H” pulse width Serial clock “L” pulse width BSK/UCK ↓ → BSO/UO time Valid BSI/UI → BSK/UCK ↑ BSK/UCK ↑ → valid BSI/UI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name BSK/UCK BSK/UCK, BSO/UO BSI/UI, BSK/UCK BSK/UCK, BSI/UI BSK/UCK BSK/UCK BSK/UCK, BSO/UO BSI/UI, BSK/UCK BSK/UCK, BSI/UI External shift clock mode Condition Value Min. 2 tinst* –200 Internal shift clock mode 1/2 tinst* 1/2 tinst* 1 tinst* 1 tinst* 0 1/2 tinst* 1/2 tinst* Max. — 200 — — — — 200 — — Unit µs ns µs µs µs µs ns µs µs Remarks * : For information on tinst, see “(4) Instruction Cycle.” • Internal shift clock mode tSCYC BSK/UCK 2.4 V 0.8 V t SLOV 2.4 V 0.8 V tIVSH BSI/UI 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC 0.8 V BSO/UO • External shift clock mode tSLSH BSK/UCK 0.8 VCC 0.2 VCC 0.2 VCC tSLOV BSO/UO 2.4 V 0.8 V tIVSH BSI/UI 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC tSHSL 0.8 VCC 30 MB89680 Series (6) Peripheral Input Timing (AVCC = VCC = 5.0 V ±10%, VSS = 0.0 V, TA = –40°C to +85°C) Parameter Peripheral input “H” level pulse width Peripheral input “L” level pulse width Symbol tILIH tIHIL Pin INL0 to INLB, INT0 to INT3 INL20 to INLB, INT0 to INT3 Value Min. 2 tinst* 2 tinst* Max. — — Unit µs µs Remarks * : For information on tinst, see “(4) Instruction Cycle.” tIHIL INL0 to INLB INT0 to INT3 0.2 VCC 0.8 VCC 0.2 VCC tILIH 0.8 VCC 31 MB89680 Series 5. A/D Converter Electrical Characteristics (AVCC = VCC = 3.5 V to 6.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Interchannel disparity A/D mode conversion time Sense mode conversion time Analog port input current Analog input voltage Reference voltage Reference voltage supply current IR IRH Symbol Pin name — — — — — — — — — AN00 to AN07 AN00 to AN07 AVR AVR AVR Condition AVR = AVCC = 5.0 V Value Min. — — — — Typ. — — — — AVss +0.5 LSB AVR –1.5 LSB — 44 12 — — — 100 — Max. 8 ±1.5 ±1.0 ±0.9 AVss +2.0 LSB AVR 0.5 — — 10 AVR AVCC 300 1 Unit Remarks — — — — V0T VFST — — — IAIN — — bit LSB LSB LSB mV mV LSB tinst* tinst* µA V V µA µA AVR = AVCC AVss –1.0 LSB AVR 1 LSB = AVR/256 –3.0 LSB — — — — — 0.0 0.0 AVR = AVCC = 5.0 V — — * : For information on tinst, see “(4) Instruction Cycle.” 6. A/D Converter Glossary • Resolution Analog changes that are identifiable by the A/D converter When the number of bits is 8, analog voltage can be divided into 28 = 256. • Linearity error (unit: LSB) The deviation of the straight line connecting the zero transition point (“0000 0000” ↔ “0000 0001”) with the full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics • Differential linearity error (unit: LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value • Total error (unit: LSB) The difference between theoretical and actual conversion values 32 MB89680 Series Digital output 1111 1111 1111 • 1110 • • • • • • • • • • • • • • • • • • • Theoretical conversion value Actual conversion value (1 LSB × N + VOT) AVR 256 VNT – (1 LSB × N + VOT) 1 LSB V( N + 1 ) T – VNT – 1 1 LSB VNT – (1 LSB × N + 1 LSB) 1 LSB 1 LSB = Linearity error = Differential linearity error = Total error = 0010 0001 0000 VOT VNT V(N + 1)T VFST Analog input Linearity error 0000 0000 0000 7. Notes on Using A/D Converter • Input impedance of the analog input pins The A/D converter used for the MB89890 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after starting A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low (below 10 kΩ). Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of approx. 0.1 µF for the analog input pin. • Analog Input Equivalent Circuit Analog input pin Comparator If the analog input impedance is higher than 10 kΩ, it is recommended to connect an external capacitor of approx. 0.1 µF. R ≅ 6 kΩ Close for 8 instruction cycles after starting A/D conversion. Analog channel selector Sample hold circuit C ≅ 33 pF • Error The smaller the | AVR – AVSS |, the greater the error would become relatively. 33 MB89680 Series s INSTRUCTIONS (136 INSTRUCTIONS) Execution instructions can be divided into the following four groups: • • • • Transfer Arithmetic operation Branch Others Table 1 lists symbols used for notation of instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Instruction Symbols Meaning (Continued) 34 MB89680 Series (Continued) Symbol EP PC SP PS dr CCR RP Ri × (×) (( × )) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Meaning Columns indicate the following: Mnemonic: ~: #: Operation: TL, TH, AH: Assembler notation of an instruction The number of instructions The number of bytes Operation of an instruction A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: • • • • N, Z, V, C: OP code: “–” indicates no change. dH is the 8 upper bits of operation description data. AL and AH must become the contents of AL and AH prior to the instruction executed. 00 becomes 00. An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ← This indicates 48, 49, ... 4F. 35 MB89680 Series Table 2 Mnemonic MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP ,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP ,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP,A MOVW EP ,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP ,#d16 MOVW IX,A MOVW A,IX MOVW SP ,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP ,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC ~ 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 # 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 Transfer Instructions (48 instructions) Operation (dir) ← (A) ( (IX) +off ) ← (A) (ext) ← (A) ( (EP) ) ← (A) (Ri) ← (A) (A) ← d8 (A) ← (dir) (A) ← ( (IX) +off) (A) ← (ext) (A) ← ( (A) ) (A) ← ( (EP) ) (A) ← (Ri) (dir) ← d8 ( (IX) +off ) ← d8 ( (EP) ) ← d8 (Ri) ← d8 (dir) ← (AH),(dir + 1) ← (AL) ( (IX) +off) ← (AH), ( (IX) +off + 1) ← (AL) (ext) ← (AH), (ext + 1) ← (AL) ( (EP) ) ← (AH),( (EP) + 1) ← (AL) (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir + 1) (AH) ← ( (IX) +off), (AL) ← ( (IX) +off + 1) (AH) ← (ext), (AL) ← (ext + 1) (AH) ← ( (A) ), (AL) ← ( (A) ) + 1) (AH) ← ( (EP) ), (AL) ← ( (EP) + 1) (A) ← (EP) (EP) ← d16 (IX) ← (A) (A) ← (IX) (SP) ← (A) (A) ← (SP) ( (A) ) ← (T) ( (A) ) ← (TH),( (A) + 1) ← (TL) (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ↔ (AL) (dir): b ← 1 (dir): b ← 0 (AL) ↔ (TL) (A) ↔ (T) (A) ↔ (EP) (A) ↔ (IX) (A) ↔ (SP) (A) ← (PC) TL – – – – – AL AL AL AL AL AL AL – – – – – – – – – AL AL AL AL AL AL – – – – – – – – – – – – – – – AL AL – – – – TH – – – – – – – – – – – – – – – – – – – – – AH AH AH AH AH AH – – – – – – – – – – – – – – – – AH – – – – AH – – – – – – – – – – – – – – – – – – – – – dH dH dH dH dH dH dH – – dH – dH – – – dH – – AL – – – dH dH dH dH dH NZVC –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++++ –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– Notes: • During byte transfer to A, T ← A is restricted to low bytes. • Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family) 36 MB89680 Series Table 3 Mnemonic ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir ~ 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 # 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation (A) ← (A) + (Ri) + C (A) ← (A) + d8 + C (A) ← (A) + (dir) + C (A) ← (A) + ( (IX) +off) + C (A) ← (A) + ( (EP) ) + C (A) ← (A) + (T) + C (AL) ← (AL) + (TL) + C (A) ← (A) − (Ri) − C (A) ← (A) − d8 − C (A) ← (A) − (dir) − C (A) ← (A) − ( (IX) +off) − C (A) ← (A) − ( (EP) ) − C (A) ← (T) − (A) − C (AL) ← (TL) − (AL) − C (Ri) ← (Ri) + 1 (EP) ← (EP) + 1 (IX) ← (IX) + 1 (A) ← (A) + 1 (Ri) ← (Ri) − 1 (EP) ← (EP) − 1 (IX) ← (IX) − 1 (A) ← (A) − 1 (A) ← (AL) × (TL) (A) ← (T) / (AL),MOD → (T) (A) ← (A) ∧ (T) (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL) − (AL) (T) − (A) → C→A C ← A← (A) − d8 (A) − (dir) (A) − ( (EP) ) (A) − ( (IX) +off) (A) − (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ( (EP) ) (A) ← (AL) ∀ ( (IX) +off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) TL – – – – – – – – – – – – – – – – – – – – – – – dL – – – – – – – – – – – – – – – – – – – – – – – TH – – – – – – – – – – – – – – – – – – – – – – – 00 – – – – – – – – – – – – – – – – – – – – – – – AH – – – – – dH – – – – – – dH – – – – dH – – – dH dH 00 dH dH dH – – – – – – – – – – – – – – – – – – – – NZVC ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++– –––– –––– ++–– +++– –––– –––– ++–– –––– –––– ++R– ++R– ++R– ++++ ++++ ++–+ ++–+ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– OP code 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 (Continued) 37 MB89680 Series (Continued) Mnemonic AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP ,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP ~ 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 # 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) ← (AL) ∧ ( (EP) ) (A) ← (AL) ∧ ( (IX) +off) (A) ← (AL) ∧ (Ri) (A) ← (AL) ∨ (TL) (A) ← (AL) ∨ d8 (A) ← (AL) ∨ (dir) (A) ← (AL) ∨ ( (EP) ) (A) ← (AL) ∨ ( (IX) +off) (A) ← (AL) ∨ (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ← (SP) + 1 (SP) ← (SP) – 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 # 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 TL – – – – – – – – – – – – – – – TH – – – – – – – – – – – – – – – AH – – – – – – – – – – – – – – – NZVC ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++++ ++++ ++++ ++++ –––– –––– OP code 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 Branch Instructions (17 instructions) Operation TL – – – – – – – – – – – – – – – – – TH – – – – – – – – – – – – – – – – – AH – – – – – – – – – – – – – – dH – – NZVC –––– –––– –––– –––– –––– –––– –––– –––– –+–– –+–– –––– –––– –––– –––– –––– –––– Restore OP code FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 If Z = 1 then PC ← PC + rel If Z = 0 then PC ← PC + rel If C = 1 then PC ← PC + rel If C = 0 then PC ← PC + rel If N = 1 then PC ← PC + rel If N = 0 then PC ← PC + rel If V ∀ N = 1 then PC ← PC + rel If V ∀ N = 0 then PC ← PC + reI If (dir: b) = 0 then PC ← PC + rel If (dir: b) = 1 then PC ← PC + rel (PC) ← (A) (PC) ← ext Vector call Subroutine call (PC) ← (A),(A) ← (PC) + 1 Return from subrountine Return form interrupt Table 5 Other Instructions (9 instructions) Operation TL – – – – – – – – – TH – – – – – – – – – AH – dH – – – – – – – NZVC –––– –––– –––– –––– –––– –––R –––S –––– –––– OP code 40 50 41 51 00 81 91 80 90 Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI ~ 4 4 4 4 1 1 1 1 1 # 1 1 1 1 1 1 1 1 1 38 L RETI SETC PUSHW POPW MOV MOVW CLRI A A A,ext A,PS CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP SETI CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC H 3 4 5 6 7 8 9 A B C D E F 0 1 2 0 NOP SWAP RET 1 SUBC A A MULU DIVU A XCH XOR AND OR A, T A A A JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX 2 ROLC CMP ADDC A A A s INSTRUCTION MAP 3 XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS RORC CMPW ADDCW SUBCW XCHW XORW ANDW ORW MOVW MOVW CLRB BBC INCW DECW MOVW MOVW A A A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC 4 MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 5 SUBC MOV XOR AND OR MOV CMP MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP ,#d16 A,SP CLRB BBC MOVW MOVW MOVW XCHW dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX 6 MOV CMP ADDC A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 7 CMP CLRB BBC MOVW MOVW MOVW XCHW MOV CMP ADDC SUBC MOV XOR AND OR MOV ,#d8 @EP ,#d8 dir: 7 dir: 7,rel A,@EP @EP ,A EP ,#d16 A,EP A,@EP A,@EP A,@EP A,@EP @EP ,A A,@EP A,@EP A,@EP @EP 8 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel R0 R0 #0 rel rel rel rel 9 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel R1 R1 #1 A MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BP A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel R2 R2 #2 B MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BN A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel R3 R3 #3 C MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BNZ A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel R4 R4 #4 rel rel D MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BZ A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel R5 R5 #5 E MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BGE A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel R6 R6 #6 rel MB89680 Series F MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC DEC CALLV BLT A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel R7 R7 #7 rel 39 MB89680 Series s MASK OPTIONS Part number No. Specifying procedure Pull-up resistors P00 to P07, P10 to P17, P30 to P37, P60 to P67, P90 to P97, PA0 to PA7 Power-on reset (POR) With power-on reset Without power-on reset Oscillation stabilization time selection (OSC) The initial value of the main clock oscillation stabilization time can be set with WTM1 and WTM0 bit. Reset pin output (RST) With reset output Without reset output Clock mode selection (CLK) Dual-clock mode Single-clock mode MB89689 Spcify when ordering masking MB89P689 MB89W689 Set with EPROM programmer MB89PV680 Setting not possible 1 Selectable by pin Selectable by pin Fixed to without a pull-up resistor 2 Selectable Selectable WTM1 WTM0 0 0: 23/FCH 0 1: 212/FCH 1 0: 216/FCH 1 1: 218/FCH Selectable Selectable Selectable WTM1 WTM0 0 0: 23/FCH 0 1: 212/FCH 1 0: 216/FCH 1 1: 218/FCH Selectable Fixed to with power-on reset 3 Fixed to oscillation stabilization time of 218/FCH 4 Fixed to with reset output Fixed to dual clock 5 Selectable Selectable s ORDERING INFORMATION Part number MB89689PF MB89P689PF MB89W689CF MB89PV680CF Package 100-pin Plastic QFP (FPT-100P-M06) 100-pin Ceramic QFP (FPT-100C-A02) 100-pin Ceramic MQFP (MQP-100C-P01) Remarks 40 MB89680 Series s PACKAGE DIMENSIONS 100-pin Plastic QFP (FPT-100P-M06) 23.90±0.40(.941±.016) 80 81 3.35(.132)MAX (Mounting height) 20.00±0.20(.787±.008) 51 50 0.05(.002)MIN (STAND OFF) 14.00±0.20 (.551±.008) INDEX 100 31 17.90±0.40 (.705±.016) 12.35(.486) REF 16.30±0.40 (.642±.016) "A" LEAD No. 1 30 0.65(.0256)TYP 0.30±0.10 (.012±.004) 0.13(.005) M 0.15±0.05(.006±.002) Details of "A" part 0.25(.010) "B" 0.10(.004) 18.85(.742)REF 22.30±0.40(.878±.016) 0.30(.012) 0.18(.007)MAX 0.53(.021)MAX 0 10° 0.80±0.20 (.031±.008) Details of "B" part C 1994 FUJITSU LIMITED F100008-3C-2 Dimensions in mm (inches) 100-pin Ceramic QFP (FPT-100C-A02) 0.51(.020) TYP 8.89(.350)DIA TYP 12.34(.486) REF 17.91(.705) TYP 16.00(.630) 14.00±0.25 TYP (.551±.010) 16.31(.642) TYP INDEX AREA 0.30±0.05 0.65±0.15 (.0256±.0060) (.012±.002) 18.85(.742)REF 20.00±0.25 (.787±.010) 23.90(.941) TYP 22.00(.866) TYP 0.65±0.15 (.0256±.0060) 0.15±0.05 (.006±.002) 1.60(.063) TYP 4.45(.175)MAX 22.30(.878) TYP 0.80(.0315) TYP C 1994 FUJITSU LIMITED F100013SC-1-2 Dimensions in mm (inches) 41 MB89680 Series 100-pin Ceramic MQFP (MQP-100C-P01) 18.70(.736)TYP 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) 12.35(.486)TYP 1.20 –0.20 +.016 .047 –.008 +0.40 INDEX AREA 0.65±0.15 (.0256±.0060) 0.65±0.15 (.0256±.0060) 1.27±0.13 (.050±.005) 22.30±0.33 (.878±.013) 24.70(.972) TYP 0.30(.012) TYP 18.12±0.20 12.02(.473) (.713±.008) TYP 10.16(.400) 14.22(.560) TYP TYP 18.85(.742) TYP 1.27±0.13 (.050±.005) 0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP 0.30±0.08 (.012±.003) 0.30±0.08 (.012±.003) 1.20 –0.20 +.016 .047 –.008 +0.40 10.82(.426) 0.15±0.05 MAX (.006±.002) C 1994 FUJITSU LIMITED M100001SC-1-2 Dimensions in mm (inches) 42 MB89680 Series FUJITSU LIMITED All Rights Reserved. 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