MB90092

FUJITSU SEMICONDUCTOR DATA SHEET DS04-28824-3E ASSP for Screen Display Control CMOS ON-Screen Display Controller MB90092 s DESCRIPTION The MB90092 is the display controller for displaying text and graphics on the TV screen. The MB90092 incorporates display memory (VRAM), a font memory interface, and a video signal generator, allowing text and graphics to be displayed in conjunction with a small number of external components. The MB90092 can provide two screens, called the main screen and the sub-screen, either independently or overlayed one on top of the other. The main screen consists of 24 characters by 12 lines and allows data to be set for each character. The subscreen consists of 32 characters by 12 lines or up to 32 characters by 16 lines. Data can be set either for each line in the former configuration or collectively for the entire screen in the latter configuration. For output of video signals, the MB90092 has the composite video signal, Y/C-separated video signal, and RGB digital output pins. The MB90092 also has video signal input pins, allowing superimpose display over either composite video signals and Y/C-separated video signals. s PACKAGE 80-pin Plastic QFP (FPT-80P-M06) MB90092 s FEATURES • Main Screen Display • Screen display capacity:24 characters × 12 lines (up to 288 characters) • Character dot configuration:24 × 32 dots (per character) • Character types: 16384 different characters (when using a 16 M bit external clock) • Character sizes: Standard, double width, double height, double width × double height, quadruple width × double height (Setting possible for each line) • Display position control :Horizontal display position :Set in 1/3-character units Vertical display position :Set in raster units Line spacing control :Set in raster units (0 to 15 rasters) • Display priority control:Capable of controlling display priority over the sub-screen (for each line) • Sub-Screen Display Screen display position: Settable horizontally and vertically in 2-dot units • Normal screen mode:Screen capacity:32 characters × 12 lines (up to 384 characters) 256 horizontal dots × 384 vertical dots (graphics characters only) (The actual display screen depends on the television system and dot clock frequency.) Normal character/graphic character display selectable for each line (Header display character code is specified for each line.) Character string length:Selectable from among 1, 2, 4, 8, 16, 24, and 32 digits • Full-screen mode Screen capacity: 32 characters × 16 lines (up to 512 characters) 256 horizontal dots × 512 vertical dots (The actual display screen depends on the television system and dot clock frequency.) Virtual screen capacity:Mode A:32 characters × 16 lines (× 32 screens) 256 horizontal dots × 512 vertical dots Mode B:512 characters × 32 lines 4096 horizontal dots × 1024 vertical dots Screen Background Display Screen background color: 8 colors (set for the entire screen) Analog Inputs • Composite video signal input • Y/C-separated inputs Analog Outputs • Composite video signal output • Y/C-separated outputs Digital Outputs • G (Green), R (Red), and B (Blue) output • VOC (character) output, VOB (character + background) output • Characters, character background, line background, and screen background each capable of being displayed in eight colors Internal Synchronization Control (Video Signal Generator) • Internal video signal generator supporting the NTSC and PAL systems • Interlaced/noninterlaced display selectable (Continued) 2 MB90092 (Continued) External Synchronization Control • Separated sync signal input/composite sync signal input selectable External Interface • 8-bit serial inputs (3 signal input pins) Chip select: CS Serial clock: SCLK Serial data: SIN Package • QFP-80 Miscellaneous • Internal power-on reset circuit 3 MB90092 s PIN ASSIGNMENT (TOP VIEW) XD EXD TEST TSC VCC ADR20 ADR19 ADR18 ADR17 ADR16 ADR15 ADR14 ADR13 ADR12 ADR11 VSS TESTI VOC VOB VSS B R G CS SCLK SIN VCC EXHSYN EXVSYN HSYNC VSYNC VBLNK EXS XS TEST1 FSCO CBCK PDS VSS AVSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 ADR10 ADR9 VCC ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 VSS DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 READ VCC AVCC1 4 TEST2 TEST3 TEST4 TEST5 AVSS AVSS YOUT YIN AVCC2 COUT CIN AVSS VOUT VKIN VKOUT VIN (FPT-80P-M06) MB90092 s PIN DESCRIPTION Pin no. Pin name I/O Circuit type Function Test signal input pin. Input High level signal during normal operation. This pin also can be used as a reset signal input pin by Low-level input to the TEST pin. That is effective only after release of power-on reset. This pin is a hysteresis input with an internal pull-up resistor. Character interval signal output pin. The output signal represents the character dot output interval. Character/background internal signal output pin. During internal synchronization control operation, the output signal represents the character, character background, line background, or screen background output interval. Color signal output pins. These pins output the character, character background, line background, and screen background color signals. Chip select pin. For serial transfer, set this pin to the Low level. This pin is also used to release a power-on reset. The pin is a hysteresis input with an internal pull-up resistor. Shift clock input pin for serial transfer. This pin is a hysteresis input with an internal pull-up resistor. Serial data input pin. The pin is a hysteresis input with an internal pull-up resistor. External horizontal sync signal input pin. Input negative logic signal. This pin can also serve as a composite sync signal input pin depending on the internal register setting. The pin is a hysteresis input with an internal pull-up resistor. External vertical sync signal input pin. Input negative logic signal. Input to this pin is disabled when composite sync signal input has been selected by setting the internal register. The pin is a hysteresis input with an internal pull-up resistor. Horizontal sync signal output pin. This pin can also output composite sync signals depending on the internal register setting. The pin outputs the signal (FSC) resulting from dividing the 4FSC clock frequency by setting the TEST pin to the Low level. Vertical sync signal output pin. This pin is fixed at the High level when composite sync signal output has been selected by setting the internal register. The pin outputs the dot clock oscillator signal when the TEST pin goes into Low. Vertical blanking interval signal output pin. This pin outputs the Low-level signal in the vertical blanking interval. 1 TESTI I B 2 VOC O C 3 VOB O C 5 6 7 B R G O C 8 CS I B 9 10 SCLK SIN I I B B 12 EXHSYN I B 13 EXVSYN I B 14 HSYNC O C 15 VSYNC O C 16 VBLNK O C (Continued) 5 MB90092 Pin no. Pin name I/O Circuit type Function External circuit pins for color burst clock generator. Connect an external crystal oscillator (14.31818 MHz for NTSC or 17.734475 MHz for PAL) and load capacitance (C) to these pins to form a crystal oscillator circuit. Internal color burst clock output pin. This pin controls internal color burst clock output depending on the FO bit of command 7. External color burst clock input pin Pin for output of the result of color burst clock phase comparison Luminance signal output pin. This pin outputs a signal of 2 VP-P (pedestal level 1.57 V, sync tip level 1 V). Luminance signal input pin for superimpose display. This pin inputs a DC-reproduced (DC-clamped) signal of 2 VP-P (pedestal level 1.57 V, sync tip level 1 V). Saturation signal output pin. This pin outputs a signal at 1.57 VDC and a color burst signal amplitude of 0.57 VP-P. Saturation signal input pin for superimpose display. This pin inputs a signal at 1.57 VDC and a color burst signal amplitude of 0.57 VP-P. Composite video signal output pin. This pin outputs a signal of 2 VP-P (pedestal level 1.57 V, sync tip level 1 V). Background level control input pin for halftone background display of external input composite video signals (input to the VIN pin and output from the VOUT pin). Halftone background display is controlled by setting the KID bit of command 5 to “1”. Background level control output pin for halftone background display of external input composite video signals (input to the VIN pin and output from the VOUT pin). Halftone background display is controlled by setting the KID bit of command 5 to “1”. Composite video signal input pin for superimpose display. This pin inputs a DC-reproduced (DC-clamped) signal of 2 VP-P (pedestal level 1.57 V, sync tip level 1 V). External font memory read control pin. This pin outputs the Low-level signal in the font memory read period. The pin enters the high impedance state when the TSC pin inputs a Low-level signal. 17 18 EXS XS I O H 20 21 22 31 FSCO CBCK PDS YOUT O I O O C G D F 32 YIN I E 34 COUT O F 35 CIN I E 37 VOUT O F 38 VKIN I E 39 VKOUT O F 40 VIN I E 43 READ O D (Continued) 6 MB90092 Pin no. 44 45 46 47 48 49 50 51 Pin name DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 I/O Circuit type Function I A External font memory data input pins. These pins are inputs with an internal pull-up resistor. 53 54 55 56 57 58 59 60 61 63 64 66 67 68 69 70 71 72 73 74 75 ADR0 ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 ADR8 ADR9 ADR10 ADR11 ADR12 ADR13 ADR14 ADR15 ADR16 ADR17 ADR18 ADR19 ADR20 O D External font memory address output pins. These pins enter the high impedance state when the TSC pin inputs a Low-level signal. ADR0 ADR1 ADR2 Raster address ADR3 ADR4 ∗1 ∗2 ADR5 M0, SM0 ADR6 M1, SM1 ADR7 M2, SM2 ADR8 M3, SM3 Character code (Lower bits) ADR9 M4, SM4 ADR10 M5, SM5 ADR11 M6, SM6 ADR12 Data distinction bits ADR13 (12,13 = 00: Left, 10: Center, 01: Right) ADR14 M7, SM7 ADR15 M8, SM8 ADR16 M9, SM9 ADR17 MA, SMA Character code (Higher bits) ADR18 MB, SMB ADR19 MC, SMC ADR20 MD, SMD *1: M0 to MD are control bits for main screen character control data setting (the commands 1-1 and 2-1) *2: SM0 to SMD are control bits for sub-screen character control data setting (the commands 1-2 and 2-2) Tristate control input pin for external font memory control bus. When this pin inputs a Low-level signal, the ADR0 to ADR20 pins and the READ pin enter the high impedance state. The pin is a hysteresis input with an internal pull-up resistor. Test signal input pin. This pin usually inputs a High-level (fixed) signal. External circuit pins for display dot clock generator. Connect these pins to external “L” and “C” to form an LC oscillator circuit. 77 TSC I B 78 79 80 TEST EXD XD I I O B I (Continued) 7 MB90092 (Continued) Pin no. 19 25 26 27 28 11 42 62 76 4 23 52 65 41 33 24 29 30 36 Pin name TEST1 TEST2 TEST3 TEST4 TEST5 I/O Circuit type Function O — Leave these pins unconnected. VCC — — Power-supply pins (+5 V) VSS — — Ground pins AVCC1 AVCC2 — — — — Analog power pin for composite video signals (VIN-VOUT) Analog power pin for luminance (YIN-YOUT) and chroma (CIN-COUT) signals Analog circuit ground pins. Set these pins to the same level as the VSS pin. AVSS — — 8 MB90092 s I / O CIRCUIT TYPE Type Circuit Remarks A CMOS level input With pull-up resistor: approximately 50 kΩ B CMOS level, hysteresis input With pull-up resistor: approximately 50 kΩ C CMOS output D CMOS three state output (Continued) 9 MB90092 (Continued) Control signal E Analog input Analog input CMOS analog SW Control signal F Analog output Analog output CMOS analog SW Control signal G CMOS level, hysteresis input XS H EXS Crystal oscillation circuit Control signal XD EXD I LC oscillation circuit Control signal 10 Inside clock signal MB90092 s BLOCK DIAGRAM SIN SCLK CS TEST Serial input control Each control and data VIN YIN CIN VKIN EXHSYN EXVSYN Analog SW VOUT YOUT COUT VKOUT H/V separation circuit HSYNC VSYNC VBLNK NTSC/PAL signal generator Video signal generator Display memory control Output control B R G VOB VOC Display memory (VRAM) Font memory control ADR0 ~ ADR20 READ DA0 ~ DA7 TSC XS EXS 4FSC clock oscillator Each block Phase comparator (color burst) CBCK PDS FSCO XD EXD Dot clock oscillator Each block 11 MB90092 s DISPLAY CONTROL COMMANDS Command no. 0 1-1 2-1 1-2 2-2 1-3 2-3 3 4 5 6 7 8 9 10 11 12 13 14 15 First byte Function VRAM address setting Second byte Data 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 CA2 1 CA1 0 CA0 RA6 RA5 CA4 CA3 CG M6 CR M5 CB M4 MC M3 0 Command code/data 76543 2 1 10000 VSL RA8 RA7 10001 10010 MA M9 MB M8 AT M7 0 Main screen character control data setting 1* Main screen character control data setting 2 Sub-screen line control data setting 1 Sub-screen line control data setting 2 Main screen line control data setting 1 Main screen line control data setting 2 BG BR BB (GR)* (BS)* (MD)* M2 M1 SDC SM1 PR KR 0 P0 W1 N1 Y1 X1 M0 SMD SM0 PB KB 0 DC W0 N0 Y0 X0 RM0 UB SBB SY0 SX0 — — 10001 SMA SMB SCG SCR SCB SMC SGR SM6 SM5 SM4 SM3 0 SOC 0 EO 0 VD 0 CM 0 DG 0 ZM PC KC 0 NP W3 N3 Y3 X3 SF1 UC SM2 PG KG 0 P2 W2 N2 Y2 X2 10010 SM9 SM8 SM7 10001 OF1 OF0 10010 10011 10100 G2 FIL IE G1 0 IN 0 G0 0 EB VRAM write control Screen control 1 Screen control 2 Main screen line control Main screen vertical display position control Main screen horizontal display position control 10101 KID APC GYZ 10110 10111 11000 11001 11010 G2 EC SC 0 0 G1 LP 0 0 0 G0 FO FC GRM RB BH2 BH1 BH0 SOC 0 0 VD Y5 X5 DG Y4 X4 Main screen display mode control Color control Sub-screen control Sub-screen vertical display position control Sub-screen horizontal display position control RP1 RP0 S16 BK 0 CC BC DW4 RM1 UG UR SBR SY1 SX1 — — 11011 SG2 SG1 SG0 11100 SGA 11101 11110 11111 0 — — 0 SX8 — — SY7 SX7 — — SCC SBC SGC SBG SY2 SX2 — — SY6 SY5 SY4 SY3 SX6 SX5 SX4 SX3 — — — — — — — — (Reserved) (Reserved) *: Parenthesized bit names are used for extended graphics mode. Note: DC bit of screen control 1 (command 4) is initialized at “0” and display is off by reset. All command data and all VRAM are needed to set after release of power-on reset. 12 MB90092 s COMMAND 1. VRAM Address Setting (Command 0) MSB First byte MSB Second byte 0 RA6 RA5 CA4 CA3 CA2 CA1 1 0 0 0 0 VSL RA8 LSB RA7 LSB CA0 VSL : VRAM write control RA8 to RA5 : VRAM row address setting (0H to BH) CA4 to CA0 : VRAM column address setting (00H to 17H) 2. VRAM Data Settings 1 and 2 (Commands 1 and 2) (1) Writing main screen character control data (when command 0: VSL = 0) • Command 1-1 (Main screen character control data setting 1) MSB First byte MSB Second byte 0 CG CR CB MC BG (GR) BR (BS) 1 0 0 0 1 MA MB AT LSB BB (MD) * LSB *: Parenthesized bit names are used for extended graphics mode. • Command 2-1 (Main screen character control data setting 2) MSB First byte MSB Second byte 0 M6 M5 M4 M3 M2 M1 M0 1 0 0 1 0 M9 M8 LSB M7 LSB (MD), MC to M0 AT CG, CR, CB BG, BR, BB (GR) (BS) : Character code : Specify character attribute display. : Character colors : Character background colors : Specify normal character/graphic character display. : Specify shaded background display. 13 MB90092 (2) Writing sub-screen line control data (when command 0: VSL = 1, CA0 = 0) • Command 1-2 (Sub-screen line control data setting 1) MSB First byte MSB Second byte 0 SCG SCR SCB SMC SGR SDC 1 0 0 0 1 SMA SMB 0 LSB SMD LSB • Command 2-2 (Sub-screen line control data setting 2) MSB First byte MSB Second byte 0 SM6 SM5 SM4 SM3 SM2 SM1 1 0 0 1 0 SM9 SM8 LSB SM7 LSB SM0 SMD to SM0 SDC SGR SCG to SCB SCG SCR, SCB : Sub-screen line first character code : Sub-screen line output control : Sub-screen line character display control : Sub-screen line character colors (when SGR = 0) : Sub-screen line graphic color transparency control (when SGR = 1) : Sub-screen line graphic color phase control (when SGR = 1) 14 MB90092 (3) Writing main screen control data (when command 0: VSL = 1, CA0 = 1) • Command 1-3 (Main screen line control data setting 1) MSB First byte MSB Second byte 0 0 0 0 PC PG PR PB 1 0 0 0 1 OF1 OF0 0 LSB LSB • Command 2-3 (Main screen line control data setting 2) MSB First byte MSB Second byte 0 SOC VD DG KC KG KR KB 1 0 0 1 0 G2 G1 G0 LSB LSB OF1, OF0 PC PG, PR, PB G2, G1, G0 SOC VD DG KC KG, KR, KB : Character color phase control : Shaded pattern background color/monochrome control : Shaded pattern background color : Character size control : Output priority control : Video signal output control : Digital signal output control : Line background color/monochrome control : Line background color 3. VRAM Write Control (Command 3) MSB First byte MSB Second byte 0 0 0 0 0 0 0 0 1 0 0 1 1 FIL 0 0 LSB LSB FIL: VRAM fill control 15 MB90092 4. Screen Control 1 (Command 4) MSB First byte MSB Second byte 0 IE IN EB EO CM ZM NP P2, P0 DC EO CM ZM NP P2 P0 1 0 1 0 0 IE IN LSB EB LSB DC : Internal/external synchronization control : Interlaced/noninterlaced display control : Screen background display control : Field control : Color/monochrome display control : Zoom-in control : NTSC/PAL control : Pattern background control : Display control 5. Screen Control 2 (Command 5) MSB First byte MSB Second byte 0 BH2 BH1 BH0 W3 W2 W1 1 0 1 0 1 KID APC LSB GYZ LSB W0 KID APC GYZ BH2 to BH0 W3 to W0 : Halftone control : Reserve* : Main screen line enlargement control : Reserve* : Main screen line spacing control *: Reserve must be set at “ 0 ”. 16 MB90092 6. Main Screen Line Control (Command 6) MSB First byte MSB Second byte 0 G2 to G0 SOC VD DG N3 to N0 SOC VD DG N3 N2 N1 N0 1 0 1 1 0 G2 G1 G0 LSB LSB : Character size control : Output priority control : Video signal output control : Digital signal output control : Line specification 7. Main Screen Vertical Display Position Control (Command 7) MSB First byte MSB Second byte 0 EC LP FO Y5 to Y0 0 Y5 Y4 Y3 Y2 Y1 Y0 1 0 1 1 1 EC LP LSB FO LSB : Sync signal output control : Simple NTSC/PAL control : Color phase signal output control : Main screen vertical display position control 8. Main Screen Horizontal Display Position Control (Command 8) MSB First byte MSB Second byte 0 SC FC X5 to X0 0 X5 X4 X3 X2 X1 X0 1 1 0 0 0 SC 0 LSB FC LSB : Sync signal input control : Sync signal input 3 µs filter control : Main screen horizontal display position control 17 MB90092 9. Main Screen Display Mode Control (Command 9) MSB First byte MSB Second byte 0 RP1 RP0 S16 SF1 DW4 RM1 1 1 0 0 1 0 0 LSB GRM LSB RM0 GRM: Main screen display mode control RP1, RPO : Reserve 4* S16 : Reserve 3* SF1 : Reserve 2* DW4 : Reserve 1* RM1, RM0 : Reserve 0* *: Reserve 0 to reserve 4 must be set at “0”. 10. Color Control (Command 10) MSB First byte MSB Second byte RB BK CC BC 0 BK CC BC UC UG UR 1 1 0 1 0 0 0 LSB RB LSB UB : Main screen solid-fill background display control : Main screen blink display control : Main screen character color/monochrome control : Main screen character background color/monochrome control (Main screen graphic color/monochrome control) UC : Screen background color/monochrome control UG, UR, UB : Screen background color 18 MB90092 11. Sub-Screen Control (Command 11) MSB First byte MSB Second byte 0 0 SCC SBC SGC SBG SBR 1 1 0 1 1 SG2 SG1 LSB SG0 LSB SBB SG2 to SG0 SCC SBC SGC SBG, SBR, SBB : Sub-screen configuration control : Sub-screen character color/monochrome control : Sub-screen character background color/monochrome control : Sub-screen graphic color/monochrome control : Sub-screen pattern background color 12. Sub-Screen Vertical Display Position Control (Command 12) MSB First byte MSB Second byte 0 SY6 SY5 SY4 SY3 SY2 SY1 1 1 1 0 0 SGA 0 LSB SY7 LSB SY0 SGA : Sub-screen full-screen mode control SY7 to SY0 : Sub-screen vertical display position 13. Sub-Screen Horizontal Display Position Control (Command 13) MSB First byte MSB Second byte 0 SX6 SX5 SX4 SX3 SX2 SX1 1 1 1 0 1 0 SX8 LSB SX7 LSB SX0 SX8 to SX0 : Sub-screen horizontal display position 19 MB90092 s ABSOLUTE MAXIMUM RATINGS Parameter Symbol VCC Supply voltage Input voltage Output voltage Power consumption Operating temperature Storage temperature AVCC1 AVCC2 VIN VOUT Pd Ta Tstg Rating Min. VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 VSS – 0.3 — –40 –55 Max. VSS + 7.0 VSS + 7.0 VSS + 7.0 VSS + 7.0 VSS + 7.0 600 +85 +150 Unit V V V V V mW °C °C *1 *1 *1 *2 *2 Remarks *1: AVSS and VSS must have equal potential. *2: Neither VIN nor VOUT must exceed “VCC + 0.3 V.” WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. s RECOMMENDED OPERATING CONDITIONS (VSS = AVSS = 0 V) Parameter Symbol VCC Supply voltage AVCC1 AVCC2 “H” level input voltage “L” level input voltage Operating temperature Analog input voltage VIHS1 VIHS2 VILS1 VILS2 Ta AVIN Value Min. 4.5 4.5 4.5 2.2 0.8 × VCC –0.3 –0.3 –40 0 Max. 5.5 5.5 5.5 VCC + 0.3 VCC + 0.3 + 0.8 0.2 × VCC +85 VCC Unit V V V V V V V °C V Remarks Specification guarantee range *1, *2 *1, *3 DA0 to DA7 Except DA0 to DA7 DA0 to DA7 Except DA0 to DA7 *1: AVSS and VSS must have equal potential. *2: “AVCC1 = AVSS” is allowed if composite video signals (VIN-VOUT pins) are not used. *3: “AVCC2 = AVSS” is allowed if Y/C-separated video signals (YIN-YOUT and CIN-COUT pins) are not used. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 20 MB90092 s ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter Symbol Pin Conditions (Ta = –40°C to +85°C, VSS = AVSS = 0 V) Value Min. Typ. Max. Unit Remarks “H” level output voltage “L” level output voltage VOH VOL VOC, VOB, B, R, G, HSYNC, VSYNC, VBLNK, FSCO, READ, ADR0 to ADR20 TESTI, CS, SCLK, SIN, EXHSYN, EXVSYN, CBCK, DA0 to DA7, TSC, TEST VCC, AVCC1, AVCC2 VCC = 4.5 V IOH = –2 mA VCC = 4.5 V IOL = 4.0 mA 4.0 — — V — — 0.4 V Input current IIL VCC = 5.5 V VIL = 0.0 V –200 — –50 µA Supply current ICC VCC = AVCC1 = AVCC2 = 5.5 V 4fsc = 17.734475 MHz fDC = 16.0 MHz No load VCC = AVCC1 = AVCC2 = 5.5 V 4fsc = fDC = 0 MHz AVIN = 1.65 V No load — — 50 mA Analog supply current IA AVCC1, AVCC2 — — 30 mA ON resistance RON VIN-VOUT, YIN-YOUT, CIN-COUT, VIN-VKOUT, VKIN-VOUT VIN, YIN, CIN, VKIN VOUT, YOUT, COUT, VKOUT VCC = AVCC1 = AVCC2 = 4.5 V IOL = 100 µA — 100 320 Ω Off leakage current Output resistance IOFF VCC = AVCC1 = AVCC2 = 5.5 V AVIN = 5.5 V VCC = AVCC1 = AVCC2 = 4.5 V IOL = 100 µA — 0.1 10 µA Ω ROUT 100 — 1800 (Continued) 21 MB90092 (Ta = –40°C to +85°C, VSS = AVSS = 0 V) Parameter Symbol Pin Conditions Value Min. Typ. Max. Unit Remarks Yellow High level Yellow Low level Cyan High level Cyan Low level Green High level Green Low level Magenta High level Magenta Low level Red High level Red Low level Blue High level Blue Low level Color burst High level Color burst Low level VYELH VYELL VCYAH VCYAL VGREH VGREL VMAGH VOUT VMAGL VREDH VREDL VBLUH VBLUL VBSTH VBSTL VCC = AVCC1 = AVCC2 = 5.0 V 2.89 2.03 2.89 1.63 2.66 1.63 2.49 1.46 2.49 1.23 2.15 1.23 1.80 1.12 3.00 2.14 3.00 1.74 2.77 1.74 2.60 1.57 2.60 1.34 2.26 1.34 1.91 1.23 3.11 2.25 3.11 1.85 2.88 1.85 2.71 1.68 2.71 1.45 2.37 1.45 2.02 1.34 V V V V V V V V V V V V V V See Figure “VOUT output” (Continued) 22 MB90092 (Ta = –40°C to +85°C, VSS = AVSS = 0 V) Parameter Symbol Pin Conditions Values Min. Typ. Max. Unit Remarks White level 3 φ = – 270° White level 2 φ = – 180° White level 1 φ = – 90° White level 0 φ = 0° Gray level 6 Gray level 5 Gray level 4 Gray level 3 Gray level 2 Gray level 1 Black level 3 φ = – 270° Black level 2 φ = – 180° Black level 1 φ = – 90° Black level 0 φ = 0° Pedestal level SYNC level VWHT3 YWHT3 VWHT2 YWHT2 VWHT1 YWHT1 VWHT0 YWHT0 VGRY6 YGRY6 VGRY5 YGRY5 VGRY4 YGRY4 VGRY3 YGRY3 VGRY2 YGRY2 VGRY1 YGRY1 VBLK3 YBLK3 VBLK2 YBLK2 VBLK1 YBLK1 VBLK0 YBLK0 VPDS YPDS VTIP YTIP VOUT, YOUT VCC = AVCC1 = AVCC2 = 5.0 V 2.83 2.72 2.60 2.49 2.43 2.26 2.15 1.98 1.86 1.69 2.94 2.83 2.71 2.60 2.54 2.37 2.26 2.09 1.97 1.80 3.05 2.94 2.82 2.71 2.65 2.48 2.37 2.20 2.08 1.91 V V V V V V V V V V See Figures “VOUT Output” and “YOUT Output”. 1.92 2.03 2.14 V 1.80 1.91 2.02 V 1.69 1.80 1.91 V 1.57 1.68 1.79 V 1.46 0.84 1.57 1.00 1.68 1.16 V V (Continued) 23 MB90092 (Continued) Symbol CYELH CYELL CCYAH CCYAL CGREH CGREL CMAGH CMAGL CREDH CREDL CBLUH CBLUL CBSTH CBSTL CPDSC COUT VCC = AVCC1 = AVCC2 = 5.0 V (Ta = –40°C to +85°C, VSS = AVSS = 0 V) Value Unit Remarks Min. Typ. Max. 1.92 1.00 2.09 0.89 1.98 0.95 1.98 0.95 2.09 0.89 1.92 1.00 1.80 1.12 1.46 2.03 1.11 2.20 1.00 2.09 1.06 2.09 1.06 2.20 1.00 2.03 1.11 1.91 1.23 1.57 2.14 1.22 2.31 1.11 2.20 1.17 2.20 1.17 2.31 1.11 2.14 1.22 2.02 1.34 1.68 V V V V V V V V V V V V V V V See Figure “COUT Output” Parameter Yellow High level Yellow Low level Cyan High level Cyan Low level Green High level Green Low level Magenta High level Magenta Low level Red High level Red Low level Blue High level Blue Low level Color burst High level Color burst Low level Pedestal level Pin Conditions 24 MB90092 • VOUT Output VYELH VWHT0 − 3 VGRY6 VGRY5 VGRY4 VYELL VBSTH VPDS VBSTL VTIP VCYAL VGREL VMAGL VREDL VBLUL VCYAH VGREH VMAGH VREDH VBLUH VGRY3 VGRY2 VGRY1 VBLK0 − 3 VPDS • YOUT Output YWHT0 − 3 YGRY6 YGRY5 YGRY4 YGRY3 YGRY2 YPDS YGRY1 YBLK0 − 3 YPDS YTIP • COUT Output CCYAH CYELH CBSTH CPDS CBSTL CYELL CCYAL CGREH CMAGH CREDH CBLUH CBLUL CGREL CMAGL CREDL 25 MB90092 2. AC Characteristics Parameter Symbol Pin (Ta = –40°C to +85°C, VCC = 5.0 V±10%, VSS = 0 V) Value Min. Max. Unit Remarks Shift clock cycle time Shift clock pulse width Shift clock signal rise/fall time Shift clock start time Data setup time Data hold time Chip select end time Chip select signal rise/fall time Horizontal sync signal rise time Horizontal sync signal fall time Vertical sync signal rise time Vertical sync signal fall time Horizontal sync signal pulse width*1 Vertical sync signal pulse width *1 Vertical sync detection pulse width*2 Reset input pulse width ROM read cycle *4 Address valid delay READ active delay Read data setup time Read data hold time Address invalid delay READ inactive delay Tristate address delay Tristate READ delay tCYC SCLK tWCH tWCL tCR tCF tSS tSU tH tEC tCRC tCFC tHR tHF tVR tVF tWH tWV SCLK SCLK SCLK SIN SIN CS CS EXHSYN EXHSYN EXVSYN EXVSYN EXHSYN EXVSYN 1000 450 450 — — 200 200 100 500 — — — — — — 4.0 1 4.0 13 10 250 — — 30 30 0 0 — — — — — 200 200 — — — — 200 200 200 200 200 200 8.0 5 8.0 28 — 500 60 38 — — — — 100 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns See Figure “Vertical and Horizontal Sync ns Signal Input Timings”. µs H µs See Figure “Composite Sync µs Signal input Timings”. µs ns ns ns ns ns ns ns ns See Figure “Address and READ Signal Delays at TSC ns Signal Input” See Figure “Address Data Hold Timings”. See Figure “Reset Signal Input Timing”. See Figure “Serial Input Timings”. Horizontal sync detection pulse width *2 tWCSH EXHSYN tWCSV EXHSYN tWR trcyc tab tra tds tdh tai tri ttad ttrd READ DA0 to DA7 DA0 to DA7 ADR0 to ADR20 READ ADR0 to ADR20 READ TESTI (TEST = Low)*3 — ADR0 to ADR20 *1: The values assume H/V-separated sync signal input. *2: The values assume composite sync signal input. *3: When the TEST pin is a Low-level input, the TESTI pin serves as a reset pin input. (The TESTI and TEST pins can be Low level at the same time.) *4: Depends on the dot clock oscillation frequency. (trcyc = 4/fDC) 26 MB90092 • Serial Input Timings CS 0.8 VCC 0.2 VCC tSS tCFC 0.8 VCC 0.2 VCC tCRC tCYC tEC 0.8 VCC SCLK tWCH tCR tCF tH tSU 0.8 VCC tWCL 0.2 VCC SIN 0.2 VCC • Vertical and Horizontal Sync Signal Input Timings EXHSYN 0.8 VCC 0.2 VCC tHF tWH 0.8 VCC 0.2 VCC tHR EXVSYN 0.8 VCC 0.2 VCC tVF tWV 0.8 VCC 0.2 VCC tVR 27 MB90092 • Composite Sync Signal Input Timings EXHSYN 0.8 V CC 0.2 V CC tHF tWCSH 0.8 V CC 0.2 V CC tHR EXHSYN 0.8 V CC 0.2 V CC tWCSV 0.8 V CC 0.2 V CC H H EXHSYN tWCSV Vertical sync signal interval (3H) • Reset Signal Input Timing TESTI 0.2 VCC tWR 0.2 VCC 28 MB90092 • Address Data Hold Timings trcyc 4 EXD 1 2 3 4 1 2 3 4 1 0.8 VCC 0.2 VCC ADR0 to ADR20 Main screen data address * tab Sub-screen data address * tai 0.8 VCC 0.2 VCC READ tra DA0 to DA7 Main screen data * tri Sub-screen data * tds tdh 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC *: The main screen and sub-screen have the same address data timings. • Address and READ Signal Delays at TSC Signal Input ADR0 to ADR20 0.8 VCC 0.2 VCC READ 0.8 VCC 0.2 VCC TSC 0.2 VCC ttrd ttad 29 MB90092 3. Clock Timing Specifications Parameter Display dot clock* Color burst clock (NTSC)* Color burst clock (PAL)* Symbol fDC 4 fSC Pin EXD, XD EXS, XS Value Min. 8 — — Typ. — 14.318185 17.734475 Max. 16 — — Unit MHz MHz MHz Remarks * : Input the signal with a duty cycle of 50%. 4. Power-on Reset Specifications Value Min. 0.05 VCC Power-supply off time Time after power-supply rise Reset cancel pulse width toff tWIT tWRH tWRL CS 1 450 450 450 — — — — ms ns ns Max. 50 (Ta = –40°C to +85°C) Pin Unit Remarks Conditions which activate the power-on reset circuit (See Figure “Power ON/ OFF Timing”). Conditions in which the circuit repeatedly operate normally (See Figure “Power ON/OFF Timing”). Power-on reset cancel timing (See Figure “Power-on Reset Cancel Timing”). Parameter Symbol Power-supply rise time tr ms 30 MB90092 • Power ON/OFF Timing 4.5 V 0.2 V 0.2 V 0.2 V VCC tr toff Note: The power supply must be activated smoothly. • Power-on Reset Cancel Timing 4.5 V VCC Internal reset CS tWIT 0.8 V CC CS tWRL tCRC* tWRH tCFC* 0.2 V CC *: See Section 2, “AC Characteristics”. 31 MB90092 5. Recommended Input Timings (1) Composite sync signal input timing Parameter Number of frame scan lines Field frequency Line frequency Vertical retrace blanking interval First equalizing pulse interval Vertical sync pulse interval Second equalizing pulse interval Equalizing pulse width Equalizing pulse cycle Cut-in pulse width Cut-in pulse cycle Horizontal sync signal cycle Horizontal sync signal pulse width NTSC 525 60 (59.94) 15750 (15734.264) 19 to 21 3 3 3 2.29 to 2.54 0.5 3.81 to 5.34 0.5 63.492 (63.5555) 4.19 to 5.71 (4.7±0.1) PAL 625 50 15625 25 2.5 2.5 2.5 2.34 to 2.36 0.5 4.5 to 4.9 0.5 64 4.5 to 4.9 11.7 to 12.3 Unit Lines Hz Hz H H H H µs H µs H µs µs µs *1 *1 *2 *2 *1 *1 *2 *2 *2 *2 Remarks Horizontal retrace blanking interval 10.2 to 11.4 (10.5 to 11.4) *1: Parenthesized values are specifications for color information display. *2: 1 H is assumed to be one horizontal sync signal period. (2) H/V-separated sync signal input timing Parameter Vertical sync signal frequency Vertical sync signal pulse width Horizontal sync signal cycle Horizontal sync signal pulse width NTSC 60 (59.94) 1 to 5 63.492 (63.5555) 4.19 to 5.71 (4.7±0.1) PAL 50 1 to 4 64 4.5 to 4.9 Unit Hz H µs µs Remarks *1 *2 *1 *1 *1: Parenthesized values are specifications for color information display. *2: 1 H is assumed to be one horizontal sync signal period. 32 MB90092 6. Output Timings (1) Horizontal timing Symbol HPS EQP1E HPE BSTS BSTE HBLKE SEP1S EQP2S EQP2E SEP2S HBLKS IHCLR NTSC 0 34 68 76 112 143 388 455 489 842 888 910 PAL 0 42 84 100 140 186 484 568 610 1050 1106 1135 (1137)* See Figure “NTSC/PAL Horizontal Timings”. Remarks *: Parenthesized values assume the last raster in each V cycle (field). Note: The values in the above list are 4fSC count values. (2) Vertical timing Symbol VPS VPE EQPE VBLKE VBLKS VPS NTSC Interlaced 0 6 12 36 519 525 Noninterlaced 0 6 12 36 519 526 Interlaced 0 5 10 45 620 625 PAL Noninterlaced 0 5 10 45 620 624 See Figures “NTSC Vertical Timings” and “PAL Vertical Timings”. Remarks Note: The values in the above list are 1/2H count values. 33 MB90092 • NTSC/PAL Horizontal Timings Video signal Horizontal sync signal Horizontal retrace blanking interval Burst flag Equalizing pulse Cut-in pulse EQP2E EQP2S SEP1S HBLKE BSTE BSTS HPE EQP1E HPS HBLKS IHCLR HBLKS SEP2S 34 • NTSC Vertical Timings Even-numbered field Composite video signal Horizontal scanning line No. 521 522 523 524 525 1 2 3 4 5 6 7 ~ 18 19 20 ~ 258 259 260 261 262 263 Vertical sync interval Vertical retrace blanking interval Equalizing pulse interval VBLKS VPS VPE EQPE VBLKE VBLKS VPS Odd-numbered field Composite video signal 262 263 264 265 266 267 268 269 270 ~ 280 281 282 ~ 521 522 523 524 525 1 Horizontal scanning line No. 259 260 261 Vertical sync interval Vertical retrace blanking interval Equalizing pulse interval VBLKS VPS VPE EQPE VBLKE VBLKS VPS MB90092 35 36 Note1 Note 2 625 1 2 3 4 5 6 7 ~ 22 23 24 ~ 308 309 310 311 312 313 624 First field MB90092 • PAL Vertical Timings Color burst phase Composite video signal Horizontal scanning line No. Vertical sync interval Vertical retrace blanking interval Burst blanking interval Equalizing pulse interval 621 622 623 BSTE VBLKS VPS VPE EQPE BSTS VBLKE BSTE VBLKS VPS Second field 311 313 312 314 315 316 317 318 319 320 ~ 335 336 337 ~ 621 622 623 624 625 1 Color burst phase Composite video signal Horizontal scanning line No. Vertical sync interval Vertical retrace blanking interval Burst blanking interval Equalizing pulse interval 309 310 BSTE VBLKS VPS VPE EQPE BSTS VBLKE BSTE VBLKS VPS Third field 624 625 1 2 3 4 5 6 7 ~ 22 23 24 ~ 308 309 310 311 312 313 Color burst phase Composite video signal Horizontal scanning line No. Vertical sync interval Vertical retrace blanking interval Burst blanking interval Equalizing pulse interval 621 622 623 BSTE VBLKS VPS VPE EQPE, BSTS VBLKE BSTS, VBLKS VPS Forth field 311 313 312 314 315 316 317 318 319 320 ~ 335 336 337 ~ 621 622 623 624 625 1 Color burst phase Composite video signal Horizontal scanning line No. Vertical sync interval Vertical retrace blanking interval Burst blanking interval Equalizing pulse interval 309 310 BSTE, VBLKS VPS VPE EQPE BSTS VBLKE BSTE VBLKS VPS Notes 1: indicates the HSYNC positions in the equalizing pulse intervals. 2: The arrows marks indicate the phase of color subcarrier. (↑: +135°, ↓: –135°) MB90092 s SAMPLE CIRCUIT This is a standard example of the circuit to synthesize the character to input video signal or input internal generation video signal from the outside. Note that composition is different according to the system and parts used. Composite IN Video amplifer & clamp circuit Y/C IN Video amplifer & clamp circuit YIN CIN VIN MB90092 Composite OUT VOUT Buffer circuit Y/C OUT YOUT COUT Buffer circuit Sync separation circuit EXHSYN D0 D0 ∼ D7 CS Control microcontroller SCLK SIN ADR0 ADR20 ∼ ∼ D7 A0 ∼ ∼ ∼ A20 +5 V AVCC1 + +5 V + AVCC2 READ OE CE (16M − ROM) AVSS VCC EXS VSS XS XD 3.3 µH EXD 20 pF 20 pF (Approx. 14 MHz) NTSC : 14.31818 MHz PAL : 17.734475 MHz 37 MB90092 s ORDERING INFORMATION Part number MB90092PF Package 80-pin, plastic QFP (QFP-80P-M06) Remarks 38 MB90092 s PACKAGE DIMENSION 80-pin plastic QFP (FPT-80P-M06) Note : Pins width and pins thickness include plating thickness. 23.90±0.40(.941±.016) 20.00±0.20(.787±.008) 64 41 65 40 0.10(.004) 17.90±0.40 (.705±.016) 14.00±0.20 (.551±.008) INDEX Details of "A" part 80 25 0.25(.010) +0.30 3.05 –0.20 +.012 .120 –.008 (Mounting height) 1 24 0.80(.031) 0~8° M 0.37±0.05 (.015±.002) 0.20(.008) 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.30 –0.25 +0.10 +.004 "A" .012 –.010 (Stand off) C 2001 FUJITSU LIMITED F80010S-c-4-4 Dimensions in mm (inches). 39 MB90092 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. 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