MB90367SPMT

FUJITSU SEMICONDUCTOR DATA SHEET DS07-13736-1E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90360 Series MB90F362/T/S/TS, MB90362/T/S/TS, MB90F367/T/S/TS, MB90367/T/S/TS, MB90V340A-101, MB90V340A-102, MB90V340A-103, MB90V340A-104 ■ DESCRIPTION The MB90360-series with 1 channel FULL-CAN* interface and FLASH ROM is especially designed for automotive and other industrial applications. Its main feature is the on-board CAN Interfaces, which conform to Ver 2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN approach. With the new 0.35 µm CMOS technology, Fujitsu now offers on-chip FLASH-ROM program memory up to 64 Kbytes. The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates a major advantage in terms of EMI and power consumption. The internal PLL clock frequency multiplier provides an internal 42 ns instruction execution time from an external 4 MHz clock. Also, main and sub-clock can be monitored independently using the clock monitor function. The unit features a 4 channel input capture unit 1 channel 16-bit free running timer, 2-channel LIN-UART, and 16-channel 8/10-bit A/D converter as the peripheral resource. * : Controller Area Network (CAN) - License of Robert Bosch GmbH Note : F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED. ■ PACKAGE 48-pin Plastic LQFP (FPT-48P-M26) MB90360 Series ■ FEATURES • Clock • Built-in PLL clock frequency multiplication circuit • Selection of machine clocks (PLL clocks) is allowed among frequency division by 2 on oscillation clock and multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz) . • Operation by sub-clock (up to 50 kHz : 100 kHz oscillation clock divided two) is allowed (devices without Ssuffix only) . • Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock and 6-time multiplied PLL clock) . • Clock monitor function (MB90x367x only) • Main clock or sub-clock is monitored independently • Internal CR oscillation clock (100 kHz typical) can be used as sub-clock • Instruction system best suited to controller • 16 Mbytes CPU memory space • 24-bit internal addressing • Wide choice of data types (bit, byte, word, and long word) • Wide choice of addressing modes (23 types) • Enhanced multiply-divide instructions with sign and RETI instructions • Enhanced high-precision computing with 32-bit accumulator • Instruction system compatible with high-level language (C language) and multitask • Employing system stack pointer • Enhanced various pointer indirect instructions • Barrel shift instructions • Increased processing speed • 4-byte instruction queue • Powerful interrupt function • Powerful 8-level, 34-condition interrupt feature • Up to 8 channel external interrupts are supported • Automatic data transfer function independent of CPU • Expanded intelligent I/O service function (EI2OS) : up to 16 channels • Low-power consumption (standby) mode • Sleep mode (a mode that halts CPU operating clock) • Main timer mode (timebase timer mode that is transferred from main clock mode) • PLL timer mode (timebase timer mode that is transferred from PLL clock mode) • Watch mode (a mode that operates sub-clock and watch timer only, devices without S-suffix) • Stop mode (a mode that stops oscillation clock and sub-clock) • CPU blocking operation mode • Process • CMOS technology • I/O port • General-purpose input/output port (CMOS output) - 34 ports (devices without S-suffix) - 36 ports (devices with S-suffix) • Sub-clock pin (X0A and X1A) • Provided (used for external oscillation), devices without S-suffix • Not provided (used with internal CR oscillation in sub-clock mode) , devices with S-suffix (Continued) 2 MB90360 Series (Continued) • Timer • Timebase timer, watch timer (device without S-suffix) , watchdog timer : 1 channel • 8/16-bit PPG timer : 8-bit × 2 channels or 16-bit × 2 channels • 16-bit reload timer : 2 channels • 16- bit input/output timer - 16-bit free run timer : 1 channel (FRT0 : ICU 0/1/2/3) - 16- bit input capture : (ICU) : 4 channels • Full-CAN interface : up to 1 channel • Compliant with Ver 2.0A and Ver 2.0B CAN specifications • Flexible message buffering (mailbox and FIFO buffering can be mixed) • CAN wake-up function • UART (LIN/SCI) : up to 2 channels • Equipped with full-duplex double buffer • Clock-asynchronous or clock-synchronous serial transmission is available • DTP/External interrupt : up to 8 channels, CAN wakeup : up to 1 channel • Module for activation of expanded intelligent I/O service (EI2OS) and generation of external interrupt by external input. • Delay interrupt generator module • Generates interrupt request for task switching. • 8/10-bit A/D converter : 16 channels • Resolution is selectable between 8-bit and 10-bit. • Activation by external trigger input is allowed. • Conversion time : 3 µs (at 24-MHz machine clock, including sampling time) • Program patch function • Address matching detection for 6 address pointers. • Low voltage/CPU operation detection reset (devices with T-suffix) • Detects low voltage (4.0 V ± 0.3 V) and resets automatically • Resets automatically when program is runaway and counter is not cleared within interval time (approx. 262 ms : external 4 MHz) • Capable of changing input voltage for port • Automotive/CMOS-Schmitt (initial level is Automotive in single-chip mode) • FLASH memory security function • Protects the content of FLASH memory (FLASH memory device only) 3 MB90360 Series ■ PRODUCT LINEUP Features CPU System clock Sub-clock pin (X0A, X1A) Clock monitor function ROM RAM capacitance CAN interface Low voltage/CPU operation detection reset Package Emulator-specific power supply * Corresponding EVA product MB90V340A-102 No Yes LQFP-48P ⎯ MB90V340A-101 MASK ROM, 64 Kbytes 3 Kbytes 1 channel MB90362 MB90362T MB90362S MB90362TS MB90V340 A-101 MB90V340 A-102 F2MC-16LX CPU PLL clock multiplier ( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops) Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL × 6) Yes No No External 30 Kbytes 3 channels No Yes No Yes No PGA-299C Yes ⎯ * : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the Emulator hardware manual for the details. Features CPU MB90F362 MB90F362T 2 MB90F362S MB90F362TS F MC-16LX CPU PLL clock multiplier ( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops) Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL × 6) Yes No Flash memory, 64 Kbytes 3 Kbytes 1 channel No System clock Sub-clock pin (X0A, X1A) Clock monitor function ROM RAM capacitance CAN interface Low voltage/CPU operation detection reset Package Corresponding EVA product 4 No Yes LQFP-48P No Yes MB90V340A-102 MB90V340A-101 MB90360 Series Features CPU System clock Sub-clock pin (X0A, X1A) Clock monitor function ROM RAM capacitance CAN interface Low voltage/CPU operation detection reset Package Emulator-specific power supply * Corresponding EVA product MB90367 MB90367T MB90367S MB90367TS MB90V340 A-103 MB90V340 A-104 F2MC-16LX CPU PLL clock multiplier ( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops) Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL × 6) Yes No (internal CR oscillation can be used as sub-clock) Yes MASK ROM, 64 Kbytes 3 Kbytes 1 channel No Yes No LQFP-48P ⎯ MB90V340A-104 MB90V340A-103 Yes External 30 Kbytes 3 channels No PGA-299C Yes ⎯ Yes * : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the Emulator hardware manual for the details. Features CPU System clock MB90F367 MB90F367T MB90F367S MB90F367TS F2MC-16LX CPU PLL clock multiplier ( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops) Minimum instruction execution time : 42 ns (4 MHz oscillation clock, PLL × 6) Yes No (internal CR oscillation can be used as sub-clock) Yes Flash memory, 64 Kbytes 3 Kbytes 1 channel Sub-clock pin (X0A, X1A) Clock monitor function ROM RAM capacitance CAN interface Low voltage/CPU operation detection reset Package Corresponding EVA product No Yes LQFP-48P No Yes MB90V340A-104 MB90V340A-103 5 MB90360 Series ■ PIN ASSIGNMENT • MB90F362/T/S/TS, MB90362/T/S/TS, MB90F367/T/S/TS, MB90367/T/S/TS (TOP VIEW) (LQFP-48P) P82/SIN0/INT14R/TIN2 P84/SCK0/INT15R P83/SOT0/TOT2 P44/FRCK0 X1A/P41 *1 X0A/P40 *1 P42/RX1/INT9R P86/SOT1 P87/SCK1 38 48 AVss 47 46 45 44 43 42 41 40 39 37 P85/SIN1 P43/TX1 AVcc AVR P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6/PPGC(D) P67/AN7/PPGE(F) P80/ADTG/INT12R P50/AN8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 P20 *2 P21 *2 P22/PPGD(C) *2 P23/PPGF(E) *2 P24/IN0 P25/IN1 P26/IN2 P27/IN3 X1 X0 C Vss P51/AN9 P52/AN10 P54/AN12/TOT3/INT8 P55/AN13/INT10 P56/AN14/INT11 P57/AN15/INT13 MD2 MD1 P53/AN11/TIN3 MD0 (FPT-48P-M26) *1 : MB90F362/T, MB90362/T, MB90F367/T, MB90367/T : X0A, X1A MB90F362S/TS, MB90362S/TS, MB90F367S/TS, MB90367S/TS : P40, P41 *2 : High current port 6 RST Vcc MB90360 Series ■ PIN DESCRIPTION Pin No. LQFP-48P* 1 2 3 to 8 Pin name AVCC AVR P60 to P65 AN0 to AN5 P66, P67 9, 10 AN6, AN7 PPGC (D) , PPGE (F) P80 11 ADTG INT12R 12 to 14 P50 to P52 AN8 to AN10 P53 15 AN11 TIN3 P54 16 AN12 TOT3 INT8 P55 to P57 17 to 19 AN13 to AN15 INT10, INT11, INT13 20 21, 22 23 24 25 26 * : FPT-48P-M26 (Continued) MD2 MD1, MD0 RST VCC VSS C D C E ⎯ ⎯ I H H H H F H Circuit type I ⎯ H Function VCC power input pin for analog circuit. Power (Vref+) input pin for A/D converter. It should be below VCC. General-purpose I/O port. Analog input pin for A/D converter. General-purpose I/O port. Analog input pin for A/D converter. Output pin for PPG. General-purpose I/O port. Trigger input pin for A/D converter. External interrupt request input pin for INT12. General-purpose I/O port. (P50 has different I/O circuit type from MB90V340A.) Analog input pin for A/D converter. General-purpose I/O port. Analog input pin for A/D converter. Event input pin for reload timer 3. General-purpose I/O port. Analog input pin for A/D converter. Output pin for reload timer 3 External interrupt request input pin for INT8. General-purpose I/O port. Analog input pin for A/D converter. External interrupt request input pin for INT10, INT11, INT13. Input pin for operation mode specification. Input pin for operation mode specification. Reset input. Power input pin (3.5 V to 5.5 V) . Power input pin (0 V) . Power supply stabilization capacitor pin. It should be connected to a higher than or equal to 0.1 µF ceramic capacitor. 7 MB90360 Series Pin No. LQFP-48P* 27 28 Pin name X0 X1 P27 to P24 IN3 to IN0 Circuit type A Oscillation input pin. Oscillation output pin. Function 29 to 32 G General-purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. Event input pin for input capture 0 to 3. General-purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. High current output port. Output pin for PPG. General-purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. High current output port. General-purpose I/O port. Serial data input pin for UART1. General-purpose I/O port. Clock I/O pin for UART1. General-purpose I/O port. Serial data output pin for UART1. General-purpose I/O port. TX output pin for CAN1 interface. General-purpose I/O port. RX input pin for CAN1 interface. External interrupt request input pin for INT9 (Sub) . General-purpose I/O port. P23, P22 33, 34 PPGF (E) , PPGD (C) J 35, 36 P21, P20 J 37 38 39 40 P85 SIN1 P87 SCK1 P86 SOT1 P43 TX1 P42 RX1 INT9R P83 K F F F 41 F 42 SOT0 TOT2 P84 F Serial data output pin for UART0. Output pin for reload timer 2 General-purpose I/O port. 43 SCK0 INT15R F Clock I/O pin for UART0. External interrupt request input pin for INT15. (Continued) * : FPT-48P-M26 8 MB90360 Series (Continued) Pin No. LQFP-48P* Pin name P82 Circuit type General-purpose I/O port. K Function 44 SIN0 INT14R TIN2 Serial data input pin for UART0. External interrupt request input pin for INT14. Event input pin for reload timer 2. General-purpose I/O port. (Different I/O circuit type from MB90V340A.) Free-run timer 0 clock pin. General-purpose I/O port. (Devices with S-suffix and MB90V340A-101/103 only.) Oscillation input pin for sub-clock. (Devices without S-suffix and MB90V340A-102/104 only.) VSS power input pin for analog circuit. 45 P44 FRCK0 P40, P41 F F B I 46, 47 X0A, X1A 48 * : FPT-48P-M26 AVSS 9 MB90360 Series ■ I/O CIRCUIT TYPE Type X1 Circuit Remarks Oscillation circuit • High-speed oscillation feedback resistor = approx. 1 MΩ Xout A X0 Standby control signal X1A Xout Oscillation circuit • Low-speed oscillation feedback resistor = approx. 10 MΩ B X0A Standby control signal R C Hysteresis inputs Mask ROM device : • CMOS hysteresis input pin Flash device : • CMOS input pin R Hysteresis inputs Mask ROM device : • CMOS hysteresis input pin • Pull-down resistor value : approx. 50 kΩ Flash device : • CMOS input pin • No Pull-down CMOS hysteresis input pin • Pull-up resistor value : approx. 50 kΩ D Pull-down resistor E Pull-up resistor R Hysteresis inputs (Continued) 10 MB90360 Series Type Circuit Remarks • CMOS level output (IOL = 4 mA, IOH = −4 mA) • CMOS hysteresis inputs (With the standby-time input shutdown function) • Automotive input (With the standbytime input shutdown function) Pout Nout F R Hysteresis inputs Automotive inputs Standby control for input shutdown Pull-up control Pull-up resistor Pout Nout • CMOS level output (IOL = 4 mA, IOH = −4 mA) • CMOS hysteresis inputs (With the standby-time input shutdown function) • Automotive input (With the standbytime input shutdown function) • Settable pull-up resistor : approx. 50 kΩ G R Hysteresis inputs Automotive inputs Standby control for input shutdown Pout Nout R H • CMOS level output (IOL = 4 mA, IOH = −4 mA) • CMOS hysteresis inputs (With the standby-time input shutdown function) • Automotive input (With the standbytime input shutdown function) • A/D analog input Hysteresis inputs Automotive inputs Standby control for input shutdown Analog input (Continued) 11 MB90360 Series (Continued) Type Circuit Remarks • Power supply input protection circuit I Pull-up control Pull-up resistor Pout high current output Nout high current output • CMOS level output (IOL = 20 mA, IOH = −14 mA) • CMOS hysteresis inputs (With the standby-time input shutdown function) • Automotive input (With the standbytime input shutdown function) • Settable pull-up resistor : approx. 50 kΩ J R Hysteresis inputs Automotive inputs Standby control for input shutdown Pout Nout • CMOS level output (IOL = 4 mA, IOH = −4 mA) • CMOS input (With standby-time input shutdown function) • Automotive input (With standby-time input shutdown function) K R CMOS inputs Automotive inputs Standby control for input shutdown 12 MB90360 Series ■ HANDLING DEVICES Special care is required for the following when handling the device : • Preventing latch-up • Treatment of unused pins • Using external clock • Precautions for when not using a sub-clock signal • Notes on during operation of PLL clock mode • Power supply pins (VCC/VSS) • Pull-up/down resistors • Crystal oscillator circuit • Turning-on sequence of power supply to A/D converter and analog inputs • Connection of unused pins of A/D converter • Notes on energization • Stabilization of power supply voltage • Initialization • Notes on using CAN Function • Flash security function • Correspondence with +105 °C or more 1. Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions : • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between VCC and VSS. • The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. Use meticulous care not to exceed the rating. For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVR) exceed the digital power-supply voltage. 2. Treatment of unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore, they must be pulled up or pulled down through resistors. In this case, those resistors should be more than 2 kΩ . Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. 3. Using external clock To use external clock, drive the X0 pin and leave X1 pin open. MB90360 Series X0 Open X1 13 MB90360 Series 4. Precautions for when not using a sub-clock signal If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin and leave the X1A pin open. 5. Notes on during operation of PLL clock mode If the PLL clock mode is selected, the microcontroller attempts to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. 6. Power supply pins (VCC/VSS) • If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latch up. To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally. • Connect VCC and VSS to the device from the current supply source at a low impedance. • As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between VCC and VSS in the vicinity of VCC and VSS pins of the device. VCC VSS VCC VSS VCC MB90360 Series VSS VCC VSS VSS VCC 7. Pull-up/down resistors The MB90360 Series does not support internal pull-up/down resistors (Port 2 : built-in pull-up resistors) . Use external components where needed. 8. Crystal oscillator circuit Noises around X0 or X1 pin may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground area for stabilizing the operation. 9. Turning-on sequence of power supply to A/D converter and analog inputs Make sure to turn on the A/D converter power supply (AVCC and AVR) and analog inputs (AN0 to AN15) after turning-on the digital power supply (VCC) . Turn-off the digital power after turning off the A/D converter power supply and analog inputs. In this case, make sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable) . 14 MB90360 Series 10. Connection of unused pins of A/D converter if A/D converter is used Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVR = VSS. 11. Notes on energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 µs or more (0.2 V to 2.7 V) 12. Stabilization of power supply voltage A sudden change in the power supply voltage may cause the device to malfunction even within the specified VCC power supply voltage operating guarantee range. Therefore, the VCC power supply voltage should be stabilized. For reference, the power supply voltage should be controlled so that VCC ripple variations (peak-to-peak value) at commercial frequencies (50 Hz to 60 Hz) fall below 10% of the standard VCC power supply voltage and the coefficient of transient fluctuation does not exceed 0.1 V/ms at instantaneous power switching. 13. Initialization In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers, turn on the power again. 14. Notes on using CAN function To use CAN function, please set ’1’ to DIRECT bit of CAN direct mode register (CDMR) . If DIRECT bit is set to ’0’ (initial value) , wait states will be performed when accessing CAN registers. Note : Please refer to Hardware Manual of MB90360 series for detail of CAN Direct Mode Register. 15. Flash security function The security bit is located in the area of the flash memory. If protection code 01H is written in the security bit, the flash memory is in the protected state by security. Therefore, please do not write 01H in this address if you do not use the security function. Please refer to following table for the address of the security bit. Flash memory size MB90F362 MB90F362S MB90F362T MB90F362TS MB90F367 MB90F367S MB90F367T MB90F367TS Address for security bit Embedded 512 Kbit Flash Memory FF0001H 16. Correspondence with +105 °C or more If used exceeding TA = +105 °C, please contact Fujitsu for reliability limitations. 15 MB90360 Series ■ BLOCK DIAGRAMS • MB90V340A-101/102 X0, X1 X0A, X1A* RST Clock Controller F2MC-16LX Core 16-bit I/O Timer 0 Input Capture 8 channels FRCK0 IN7 to IN0 RAM 30 Kbytes Prescaler (5 channels) SOT4 to SOT0 SCK4 to SCK0 SIN4 to SIN0 AVCC AVSS AN23 to AN0 AVRH AVRL ADTG Output Compare 8 channels 16-bit I/O Timer 1 CAN controller 3 channels 16-bit Reload Timer 4 channels OUT7 to OUT0 FRCK1 UART 5 channels RX2 to RX0 TX2 to TX0 Internal data bus 8/10-bit A/D converter 24 channels TIN3 to TIN0 TOT3 to TOT0 AD15 to AD00 A23 to A16 ALE RD WRL WRH HRQ HAK RDY CLK DA01, DA00 10-bit D/A converter 2 channels 8/16-bit PPG 16 channels I2C interface 2 channels DMA External Bus PPGF to PPG0 SDA1, SDA0 SCL1, SCL0 DTP/ External Interrupt Clock Monitor INT15 to INT8 (INT15R to INT8R) INT7 to INT0 CKOT * : Only for MB90V340A-102 16 MB90360 Series • MB90V340A-103/104 X0, X1 X0A, X1A* RST Clock Controller/ monitor F2MC-16LX Core 16-bit I/O Timer 0 Input Capture 8 channels Output Compare 8 channels 16-bit I/O Timer 1 CAN controller 3 channels 16-bit Reload Timer 4 channels CR oscillator circuit FRCK0 IN7 to IN0 RAM 30 Kbytes Prescaler (5 channels) SOT4 to SOT0 SCK4 to SCK0 SIN4 to SIN0 AVCC AVSS AN23 to AN0 AVRH AVRL ADTG OUT7 to OUT0 FRCK1 UART 5 channels RX2 to RX0 TX2 to TX0 Internal data bus 8/10-bit A/D converter 24 channels TIN3 to TIN0 TOT3 to TOT0 AD15 to AD00 A23 to A16 ALE RD WRL WRH HRQ HAK RDY CLK DA01, DA00 10-bit D/A converter 2 channels 8/16-bit PPG 16 channels I2C interface 2 channels DMA External Bus PPGF to PPG0 SDA1, SDA0 SCL1, SCL0 DTP/ External Interrupt Clock Monitor INT15 to INT8 (INT15R to INT8R) INT7 to INT0 CKOT * : Only for MB90V340A-104 17 MB90360 Series • MB90F362/T/S/TS, MB90362/T/S/TS, MB90F367/T/S/TS, MB90367/T/S/TS X0, X1 X0A, X1A*1 RST Clock Controller/ monitor *3 F2MC-16LX Core CR oscillator circuit Low voltage detection *2 CPU operation detection *2 RAM 3 Kbytes Internal data bus Input Capture 4 channels 16-bit I/O Timer 0 IN0 to IN3 FRCK0 ROM 64 Kbytes CAN controller 1 channels 16-bit Reload Timer 2 channels RX1 TX1 TIN2, TIN3 TOT2, TOT3 Prescaler (2 channels) SOT0, SOT1 SCK0, SCK1 SIN0, SIN1 AVCC AVSS AN15 to AN0 AVR ADTG UART 2 channels 8/10-bit A/D converter 16 channels PPGF(E), PPGD(C), PPGC(D), PPGE(F) 8/16-bit PPG 2 channels DTP/ External Interrupt INT8, INT9R INT10, INT11 INT12R, INT13 INT14R, INT15R *1 : Only for devices without S-suffix *2 : Only for devices with T-suffix *3 : CR oscillation circuit/clock monitor correspond to MB90F367/T/S/TS and MB90367/T/S/TS only. 18 MB90360 Series ■ MEMORY MAP MB90F362/T/S/TS MB90362/T/S/TS MB90F367/T/S/TS MB90367/T/S/TS FFFFFFH ROM (FF bank) FF0000H FEFFFFH ROM (FE bank) FE0000H FDFFFFH ROM (FD bank) FD0000H FCFFFFH ROM (FC bank) FC0000H FBFFFFH ROM (FB bank) FB0000H FAFFFFH ROM (FA bank) FA0000H F9FFFFH ROM (F9 bank) F90000H F8FFFFH ROM (F8 bank) F80000H 00FFFFH 008000H 007FFFH 007900H 0078FFH 010000H 00FFFFH ROM (image of FF bank) Peripheral 008000H 007FFFH 007900H ROM (image of FF bank) Peripheral FF0000H FEFFFFH ROM (FF bank) MB90V340A-101/102/103/104 FFFFFFH RAM 30 Kbytes 000100H 0000EFH 000000H Peripheral 000CFFH 000100H 0000FFH 0000F0H 0000EFH 000000H RAM 3 Kbytes Peripheral : No access Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referred without using the far specification in the pointer declaration. For example, an attempt to access 00C000H accesses the value at FFC000H in ROM. The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00. The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF7FFFH is visible only in bank FF. 19 MB90360 Series ■ I/O MAP (Address : 000000H-0000FFH) Address 000000H, Reserved 000001H 000002H Port 2 Data Register 000003H Reserved 000004H Port 4 Data Register 000005H Port 5 Data Register 000006H Port 6 Data Register 000007H Reserved 000008H Port 8 Data Register 000009H, Reserved 00000AH 00000BH Port 5 Analog Input Enable Register 00000CH Port 6 Analog Input Enable Register 00000DH Reserved 00000EH Input Level Select Register 00000FH Input Level Select Register 000010H, Reserved 000011H 000012H Port 2 Direction Register 000013H Reserved 000014H Port 4 Direction Register 000015H Port 5 Direction Register 000016H Port 6 Direction Register 000017H Reserved 000018H Port 8 Direction Register 000019H Reserved 00001AH Port A Direction Register 00001BH to Reserved 00001DH 00001EH Port 2 Pull-up Control Register 00001FH Reserved (Continued) PUCR2 R/W Port 2 00000000B DDRA W Port A XXX00XXXB DDR8 R/W Port 8 000000X0B DDR4 DDR5 DDR6 R/W R/W R/W Port 4 Port 5 Port 6 XXX00000B 00000000B 00000000B DDR2 R/W Port 2 00000000B ILSR0 ILSR1 R/W R/W Ports Ports XXXX0XXXB XXXXXXXXB ADER5 ADER6 R/W R/W Port 5, A/D Port 6, A/D 11111111B 11111111B PDR8 R/W Port 8 XXXXXXXXB PDR4 PDR5 PDR6 R/W R/W R/W Port 4 Port 5 Port 6 XXXXXXXXB XXXXXXXXB XXXXXXXXB PDR2 R/W Port 2 XXXXXXXXB Register Abbreviation Access Resource name Initial value 20 MB90360 Series Address Register Abbreviation SMR0 SCR0 RDR0/ TDR0 SSR0 ECCR0 ESCR0 BGR00 BGR01 SMR1 SCR1 RDR1/ TDR1 SSR1 ECCR1 ESCR1 BGR10 BGR11 Access W, R/W W, R/W R/W R, R/W R, W, R/W R/W R/W, R R/W, R W, R/W W, R/W R/W R, R/W R, W, R/W R/W R/W, R R/W, R Resource name Initial value 00000000B 00000000B 00000000B 000020H Serial Mode Register 0 000021H Serial Control Register 0 000022H Reception/Transmission Data Register 0 000023H Serial Status Register 0 000024H Extended Communication Control Register 0 UART0 00001000B 000000XXB 00000100B 00000000B 00000000B 00000000B 00000000B 00000000B 000025H Extended Status/Control Register 0 000026H Baud Rate Generator Register 00 000027H Baud Rate Generator Register 01 000028H Serial Mode Register 1 000029H Serial Control Register 1 00002AH Reception/Transmission Data Register 1 00002BH Serial Status Register 1 00002CH Extended Communication Control Register 1 UART1 00001000B 000000XXB 00000100B 00000000B 00000000B 00002DH Extended Status/Control Register 1 00002EH Baud Rate Generator Register 10 00002FH Baud Rate Generator Register 11 000030H to Reserved 00003AH 00003BH Address Detect Control Register 1 00003CH to Reserved 000047H 000048H PPG C Operation Mode Control Register 000049H PPG D Operation Mode Control Register 00004AH PPG C/PPG D Count Clock Select Register PACSR1 R/W Address Match Detection 1 00000000B PPGCC PPGCD PPGCD W, R/W W, R/W R/W 16-bit PPG C/D 0X000XX1B 0X000001B 000000X0B 00004BH Reserved 00004CH PPG E Operation Mode Control Register 00004DH PPG F Operation Mode Control Register 00004EH PPG E/PPG F Count Clock Select Register PPGCE PPGCF PPGEF W, R/W W, R/W R/W 16-bit PPG E/F 0X000XX1B 0X000001B 000000X0B 00004FH Reserved (Continued) 21 MB90360 Series Address Register Abbreviation ICS01 ICE01 ICS23 ICE23 Access R/W R/W, R R/W R Resource name Input Capture 0/1 Input Capture 2/3 Initial value 00000000B XXX0X0XXB 00000000B XXXXXXXXB 000050H Input Capture Control Status 0/1 000051H Input Capture Edge 0/1 000052H Input Capture Control Status 2/3 000053H Input Capture Edge 2/3 000054H to Reserved 000063H 000064H Timer Control Status 2 000065H Timer Control Status 2 000066H Timer Control Status 3 000067H Timer Control Status 3 000068H A/D Control Status 0 000069H A/D Control Status 1 00006AH A/D Data 0 00006BH A/D Data 1 00006CH ADC Setting 0 00006DH ADC Setting 1 00006EH Low Voltage/CPU Operation Detection Reset Control Register TMCSR2 TMCSR2 TMCSR3 TMCSR3 ADCS0 ADCS1 ADCR0 ADCR1 ADSR0 ADSR1 LVRC ROMM R/W R/W R/W R/W R/W R/W, W R R R/W R/W R/W, W W 16-bit Reload Timer 2 16-bit Reload Timer 3 00000000B XXXX0000B 00000000B XXXX0000B 000XXXX0B 0000000XB 00000000B XXXXXX00B 00000000B 00000000B A/D Converter Low voltage/CPU operation detection reset ROM Mirror 00111000B XXXXXXX1B 00006FH ROM Mirror Function Select 000070H to Reserved 00007FH 000080H to Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS” 00008FH 000090H to Reserved 00009DH 00009EH Address Detect Control Register 0 00009FH Delayed Interrupt/Release Register Low-power Consumption Mode Control Register PACSR0 DIRR R/W R/W Address Match Detection 0 Delayed Interrupt generation module Low-Power consumption Control Circuit Low-Power consumption Control Circuit 00000000B XXXXXXX0B 0000A0H LPMCR W, R/W 00011000B 0000A1H Clock Selection Register CKSCR R, R/W 11111100B (Continued) 22 MB90360 Series Address 0000A2H to Reserved 0000A7H Register Abbreviation Access Resource name Initial value 0000A8H Watchdog Control Register 0000A9H Timebase Timer Control Register 0000AAH Watch Timer Control register 0000ABH to Reserved 0000ADH 0000AEH Flash Control Status (Flash Devices only. Otherwise reserved) WDTC TBTC WTC R, W W, R/W R, R/W Watchdog Timer Timebase Timer Watch Timer XXXXX111B 1XX00100B 1X001000B FMCS R, R/W Flash Memory 000X0000B 0000AFH Reserved 0000B0H Interrupt Control Register 00 0000B1H Interrupt Control Register 01 0000B2H Interrupt Control Register 02 0000B3H Interrupt Control Register 03 0000B4H Interrupt Control Register 04 0000B5H Interrupt Control Register 05 0000B6H Interrupt Control Register 06 0000B7H Interrupt Control Register 07 0000B8H Interrupt Control Register 08 0000B9H Interrupt Control Register 09 0000BAH Interrupt Control Register 10 0000BBH Interrupt Control Register 11 0000BCH Interrupt Control Register 12 0000BDH Interrupt Control Register 13 0000BEH Interrupt Control Register 14 0000BFH Interrupt Control Register 15 0000C0H to Reserved 0000C9H 0000CAH External Interrupt Enable 1 0000CBH External Interrupt Source 1 0000CCH 0000CDH Detection Level Setting 1 ENIR1 EIRR1 ELVR1 EISSR R/W R/W R/W R/W External Interrupt 1 00000000B XXXXXXXXB 00000000B 00000000B 00000000B (Continued) 23 ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W Interrupt Control 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 0000CEH External Interrupt Source Select MB90360 Series (Continued) Address Register Abbreviation PSCCR Access W Resource name PLL Initial value XXXX0000B 0000CFH PLL/Subclock Control Register 0000D0H to Reserved 0000FFH 24 MB90360 Series (Address : 7900H-7FFFH) Address 7900H to 7917H 7918H 7919H 791AH 791BH 791CH 791DH 791EH 791FH 7920H 7921H 7922H 7923H 7924H 7925H 7926H 7927H 7928H to 793FH 7940H 7941H 7942H 7943H 7944H to 794BH 794CH 794DH 794EH 794FH 7950H to 795FH Register Abbreviation Access Resource name Initial value Reserved Reload Register LC Reload Register HC Reload Register LD Reload Register HD Reload Register LE Reload Register HE Reload Register LF Reload Register HF Input Capture 0 Input Capture 0 Input Capture 1 Input Capture 1 Input Capture 2 Input Capture 2 Input Capture 3 Input Capture 3 Reserved Timer Data 0 Timer Data 0 Timer Control Status 0 Timer Control Status 0 Reserved TMR2/ TMRLR2 TMR3/ TMRLR3 R/W R/W R/W R/W 16-bit Reload Timer 2 16-bit Reload Timer 3 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB TCDT0 TCDT0 TCCSL0 TCCSH0 R/W R/W R/W R/W I/O Timer 0 00000000B 00000000B 00000000B 0XXXXXXXB PRLLC PRLHC PRLLD PRLHD PRLLE PRLHE PRLLF PRLHF IPCP0 IPCP0 IPCP1 IPCP1 IPCP2 IPCP2 IPCP3 IPCP3 R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R Input Capture 2/3 Input Capture 0/1 16-bit PPG E/F 16-bit PPG C/D XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Timer 2/Reload 2 Timer 3/Reload 3 Reserved (Continued) 25 MB90360 Series Address 7960H 7961H to 796DH 796EH 796FH to 79DFH 79E0H 79E1H 79E2H 79E3H 79E4H 79E5H 79E6H 79E7H 79E8H 79E9H to 79EFH 79F0H 79F1H 79F2H 79F3H 79F4H 79F5H 79F6H 79F7H 79F8H 79F9H to 7BFFH 7C00H to 7CFFH Register Clock Monitor Function Control Register Reserved CAN Direct Mode Register (MB90V340 only) Reserved Detect Address Setting 0 Detect Address Setting 0 Detect Address Setting 0 Detect Address Setting 1 Detect Address Setting 1 Detect Address Setting 1 Detect Address Setting 2 Detect Address Setting 2 Detect Address Setting 2 Reserved Detect Address Setting 3 Detect Address Setting 3 Detect Address Setting 3 Detect Address Setting 4 Detect Address Setting 4 Detect Address Setting 4 Detect Address Setting 5 Detect Address Setting 5 Detect Address Setting 5 Reserved Abbreviation CSVCR Access R, R/W Resource name Clock monitor Initial value 00011100B CDMR R/W CAN clock sync XXXXXXX0B PADR0 PADR0 PADR0 PADR1 PADR1 PADR1 PADR2 PADR2 PADR2 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Match Detection 0 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB PADR3 PADR3 PADR3 PADR4 PADR4 PADR4 PADR5 PADR5 PADR5 R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Match Detection 1 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS” (Continued) 26 MB90360 Series (Continued) Address 7D00H to 7DFFH 7E00H to 7FFFH Register Abbreviation Access Resource name Initial value Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS” Reserved Notes : • Initial value of “X” represents unknown value. • Any write access to reserved addresses in I/O map should not be performed. A read access to reserved addresses results in reading “X”. 27 MB90360 Series ■ CAN CONTROLLERS The CAN controller has the following features : • Conforms to CAN Specification Version 2.0 Part A and B • Supports transmission/reception in standard frame and extended frame formats • Supports transmitting of data frames by receiving remote frames • 16 transmitting/receiving message buffers • 29-bit ID and 8-byte data • Multi-level message buffer configuration • Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as ID acceptance mask • 2 acceptance mask registers in either standard frame format or extended frame formats • Bit rate programmable from 10 Kbps/s to 2 Mbps/s (when input clock is at 16 MHz) List of Control Registers (1) Address CAN1 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH Register Message buffer valid register Transmit request register Transmit cancel register Transmission complete register Receive complete register Remote request receiving register Receive overrun register Reception interrupt enable register Abbreviation BVALR TREQR TCANR TCR RCR RRTRR ROVRR RIER Access R/W R/W W R/W R/W R/W R/W R/W Initial Value 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 28 MB90360 Series List of Control Registers (2) Address CAN1 007D00H 007D01H 007D02H 007D03H 007D04H 007D05H 007D06H 007D07H 007D08H 007D09H 007D0AH 007D0BH 007D0CH 007D0DH 007D0EH 007D0FH 007D10H 007D11H 007D12H 007D13H 007D14H 007D15H 007D16H 007D17H 007D18H 007D19H 007D1AH 007D1BH Acceptance mask register 1 AMR1 R/W XXXXXXXXB XXXXXXXXB Acceptance mask register 0 AMR0 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Acceptance mask select register AMSR R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Register Control status register Last event indicator register Receive and transmit error counter Bit timing register IDE register Transmit RTR register Remote frame receive waiting register Transmit interrupt enable register Abbreviation CSR LEIR RTEC BTR IDER TRTRR Access R/W, W R/W, R R/W R R/W R/W R/W Initial Value 0XXXX0X1B 00XXX000B 000X0000B XXXXXXXXB 00000000B 00000000B 11111111B X1111111B XXXXXXXXB XXXXXXXXB 00000000B 00000000B XXXXXXXXB XXXXXXXXB 00000000B 00000000B XXXXXXXXB XXXXXXXXB RFWTR R/W TIER R/W 29 MB90360 Series List of Message Buffers (ID Registers) (1) Address CAN1 007C00H to 007C1FH 007C20H 007C21H 007C22H 007C23H 007C24H 007C25H 007C26H 007C27H 007C28H 007C29H 007C2AH 007C2BH 007C2CH 007C2DH 007C2EH 007C2FH 007C30H 007C31H 007C32H 007C33H 007C34H 007C35H 007C36H 007C37H 007C38H 007C39H 007C3AH 007C3BH 007C3CH 007C3DH 007C3EH 007C3FH 30 ID register 7 IDR7 R/W XXXXXXXXB XXXXXXXXB ID register 6 IDR6 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 5 IDR5 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 4 IDR4 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 3 IDR3 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 2 IDR2 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 1 IDR1 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 0 IDR0 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Register Abbreviation Access Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXXB XXXXXXXXB General-purpose RAM ⎯ R/W MB90360 Series List of Message Buffers (ID Registers) (2) Address CAN1 007C40H 007C41H 007C42H 007C43H 007C44H 007C45H 007C46H 007C47H 007C48H 007C49H 007C4AH 007C4BH 007C4CH 007C4DH 007C4EH 007C4FH 007C50H 007C51H 007C52H 007C53H 007C54H 007C55H 007C56H 007C57H 007C58H 007C59H 007C5AH 007C5BH 007C5CH 007C5DH 007C5EH 007C5FH ID register 15 IDR15 R/W XXXXXXXXB XXXXXXXXB ID register 14 IDR14 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 13 IDR13 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 12 IDR12 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 11 IDR11 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 10 IDR10 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 9 IDR9 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 8 IDR8 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Register Abbreviation Access Initial Value XXXXXXXXB XXXXXXXXB 31 MB90360 Series List of Message Buffers (DLC Registers and Data Registers) (1) Address CAN1 007C60H 007C61H 007C62H 007C63H 007C64H 007C65H 007C66H 007C67H 007C68H 007C69H 007C6AH 007C6BH 007C6CH 007C6DH 007C6EH 007C6FH 007C70H 007C71H 007C72H 007C73H 007C74H 007C75H 007C76H 007C77H 007C78H 007C79H 007C7AH 007C7BH 007C7CH 007C7DH 007C7EH 007C7FH Register DLC register 0 DLC register 1 DLC register 2 DLC register 3 DLC register 4 DLC register 5 DLC register 6 DLC register 7 DLC register 8 DLC register 9 DLC register 10 DLC register 11 DLC register 12 DLC register 13 DLC register 14 DLC register 15 Abbreviation DLCR0 DLCR1 DLCR2 DLCR3 DLCR4 DLCR5 DLCR6 DLCR7 DLCR8 DLCR9 DLCR10 DLCR11 DLCR12 DLCR13 DLCR14 DLCR15 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 32 MB90360 Series List of Message Buffers (DLC Registers and Data Registers) (2) Address CAN1 007C80H to 007C87H 007C88H to 007C8FH 007C90H to 007C97H 007C98H to 007C9FH 007CA0H to 007CA7H 007CA8H to 007CAFH 007CB0H to 007CB7H 007CB8H to 007CBFH 007CC0H to 007CC7H 007CC8H to 007CCFH 007CD0H to 007CD7H 007CD8H to 007CDFH 007CE0H to 007CE7H 007CE8H to 007CEFH Register Data register 0 (8 bytes) Data register 1 (8 bytes) Data register 2 (8 bytes) Data register 3 (8 bytes) Data register 4 (8 bytes) Data register 5 (8 bytes) Data register 6 (8 bytes) Data register 7 (8 bytes) Data register 8 (8 bytes) Data register 9 (8 bytes) Data register 10 (8 bytes) Data register 11 (8 bytes) Data register 12 (8 bytes) Data register 13 (8 bytes) Abbreviation Access Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB DTR0 R/W DTR1 R/W DTR2 R/W DTR3 R/W DTR4 R/W DTR5 R/W DTR6 R/W DTR7 R/W DTR8 R/W DTR9 R/W DTR10 R/W DTR11 R/W DTR12 R/W DTR13 R/W 33 MB90360 Series List of Message Buffers (DLC Registers and Data Registers) (3) Address CAN1 007CF0H to 007CF7H 007CF8H to 007CFFH Register Data register 14 (8 bytes) Data register 15 (8 bytes) Abbreviation Access Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB DTR14 R/W DTR15 R/W 34 MB90360 Series ■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER Interrupt cause Reset INT9 instruction Exception Reserved Reserved CAN 1 reception CAN 1 transmission/node status Reserved Reserved Reserved Reserved 16-bit reload timer 2 16-bit reload timer 3 Reserved Reserved PPG C/D PPG E/F Timebase timer External interrupt 8 to 11 Watch timer External interrupt 12 to 15 A/D converter I/O timer 0 Reserved Reserved Input capture 0 to 3 Reserved UART 0 reception UART 0 transmission UART 1 reception UART 1 transmission EI2OS corresponding N N N N N N N N N N N Y1 Y1 N N N N N Y1 N Y1 Y1 N N N Y1 N Y2 Y1 Y2 Y1 Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H Interrupt control register Number ⎯ ⎯ ⎯ ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 Address ⎯ ⎯ ⎯ 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH (Continued) 35 MB90360 Series (Continued) Interrupt cause Reserved Reserved Flash memory Delayed interrupt generation module Y1 : Usable Y2 : Usable, with EI2OS stop function N : Unusable Notes : • The peripheral resources sharing the ICR register have the same interrupt level. • When 2 peripheral resources share the ICR register, only one can use extended intelligent I/O service at a time. • When either of the 2 peripheral resources sharing the ICR register specifies extended intelligent I/O service, the other one cannot use interrupts. EI2OS corresponding N N N N Interrupt vector Number #39 #40 #41 #42 Address FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register Number ICR14 ICR15 Address 0000BEH 0000BFH 36 MB90360 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol VCC Power supply voltage*1 Input voltage* 1 Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 −2.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ −40 −40 −55 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 +2.0 40 15 40 4 30 125 160 40 40 −15 −40 −4 −30 −125 −160 −40 −40 300 +105 +125 +150 Unit V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mW °C °C °C *7 Remarks AVCC AVR VI VO ICLAMP Σ|ICLAMP| IOL1 IOL2 IOLAV1 IOLAV2 ΣIOL1 ΣIOL2 ΣIOLAV1 ΣIOLAV2 ΣIOLAV1 ΣIOLAV2 IOH1 IOH2 IOHAV1 IOHAV2 ΣIOH1 ΣIOH2 ΣIOHAV1 ΣIOHAV2 ΣIOHAV1 ΣIOHAV2 VCC = AVCC*2 AVCC ≥ AVR*2 *3 *3 *6 *6 *4 *5 *4 *5 *4 *5 *4 +105 °C < TA ≤ +125 °C *5 +105 °C < TA ≤ +125 °C *4 −40 °C ≤ TA ≤ +105 °C *5 −40 °C ≤ TA ≤ +105 °C *4 *5 *4 *5 *4 *5 *4 +105 °C < TA ≤ +125 °C *5 +105 °C < TA ≤ +125 °C *4 −40 °C ≤ TA ≤ +105 °C *5 −40 °C ≤ TA ≤ +105 °C MB90F362/T/S/TS, MB90F367/T/S/TS Output voltage*1 Maximum clamp current Total Maximum clamp current “L” level maximum output current “L” level average output current “L” level maximum overall output current “L” level average overall output current “H” level maximum output current “H” level average output current “H” level maximum overall output current “H” level average overall output current Power consumption Operating temperature Storage temperature PD TA TSTG (Continued) 37 MB90360 Series (Continued) *1 : This parameter is based on VSS = AVSS = 0 V. *2 : Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on. *3 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However, if the maximun current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4 : Applicable to pins : P24 to P27, P40 to P44, P50 to P57, P60 to P67, P80, P82 to P87 *5 : Applicable to pins : P20 to P23 *6 : Applicable to pins : P20 to P27, P40 to P44, P50 to P57, P60 to P67, P80, P82 to P87 • Use within recommended operating conditions. • Use at DC voltage (current) . • The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is inputted when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the +B input pin open. • Sample recommended circuits : • Input/output equivalent circuits Protective diode Limiting resistance +B input (0 V to 16 V) Nch VCC Pch R *7 : If used exceeding TA = +105 °C, please contact Fujitsu for reliability limitations. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 38 MB90360 Series 2. Recommended Conditions (VSS = AVSS = 0 V) Parameter Symbol Value Min 4.0 Power supply voltage VCC, AVCC 3.5 3.0 Typ 5.0 5.0 ⎯ Max 5.5 5.5 5.5 Unit V V V Remarks Under normal operation Under normal operation when not using the A/D converter and not Flash programming. Maintains RAM data in stop mode Use a ceramic capacitor or capacitor of better AC characteristics. Bypass capacitor at the VCC pin should be greater than this capacitor. * Smooth capacitor CS 0.1 ⎯ 1.0 µF Operating temperature TA −40 −40 ⎯ ⎯ +105 +125 °C °C * : If used exceeding TA = +105 °C, please contact Fujitsu for reliability limitations. • C Pin Connection Diagram C CS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 39 MB90360 Series 3. DC Characteristics (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Symbol Pin Condition Value Min Typ ⎯ Max VCC + 0.3 Unit Remarks Pin inputs if CMOS hysteresis input levels are selected (except P82, P85) Pin inputs if Automotive input levels are selected P82, P85 inputs if CMOS input levels are selected RST input pin (CMOS hysteresis) MD input pin Pin inputs if CMOS hysteresis input levels are selected (except P82, P85) Pin inputs if Automotive input levels are selected P82, P85 inputs if CMOS input levels are selected RST input pin (CMOS hysteresis) MD input pin VIHS ⎯ ⎯ 0.8 VCC V VIHA Input “H” voltage VIHS ⎯ ⎯ 0.8 VCC ⎯ VCC + 0.3 V ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.7 VCC ⎯ ⎯ ⎯ ⎯ VCC + 0.3 VCC + 0.3 VCC + 0.3 0.2 VCC V VIHR VIHM 0.8 VCC VCC − 0.3 VSS − 0.3 V V VILS V VILA Input “L” voltage VILS ⎯ ⎯ VSS − 0.3 ⎯ 0.5 VCC V ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ VSS − 0.3 VSS − 0.3 VSS − 0.3 VCC − 0.5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 50 50 0.3 VCC V VILR VILM Output “H” voltage Output “H” voltage Output “L” voltage Output “L” voltage Input leak current Pull-up resistance Pull-down resistance VOH VOHI VOL VOLI IIL RUP RDOWN 0.2 VCC VSS + 0.3 ⎯ ⎯ 0.4 0.4 1 100 100 V V V V V V µA kΩ kΩ Other than VCC = 4.5 V, P20 to P23 IOH = −4.0 mA P20 to P23 VCC = 4.5 V, VCC − 0.5 IOH = −14.0 mA ⎯ ⎯ −1 25 25 Other than VCC = 4.5 V, P20 to P23 IOL = 4.0 mA P20 to P23 ⎯ P20 to P27, RST MD2 VCC = 4.5 V, IOL = 20.0 mA VCC = 5.5 V, VSS < VI < VCC ⎯ ⎯ Except Flash devices (Continued) 40 MB90360 Series (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Symbol Pin Condition VCC = 5.0 V, Internal frequency : 24 MHz, At normal operation. ICC VCC = 5.0 V, Internal frequency : 24 MHz, At writing FLASH memory. VCC = 5.0 V, Internal frequency : 24 MHz, At erasing FLASH memory. ICCS VCC = 5.0 V, Internal frequency : 24 MHz, At sleep mode. VCC = 5.0 V, Internal frequency : 2 MHz, At main timer mode VCC = 5.0 V, Internal frequency : 24 MHz, At PLL timer mode, External frequency = 4 MHz VCC ICCL VCC = 5.0 V Internal frequency : 8 kHz, At sub operation, TA = +25°C Stopping clock monitor function Operating clock monitor function Stopping clock monitor function Operating clock monitor function Stopping clock monitor function Operating clock monitor function Stopping clock monitor function Operating clock monitor function Stopping clock monitor function Operating clock monitor function Stopping clock monitor function Operating clock monitor function Value Min Typ Max ⎯ 35 45 Unit Remarks mA ⎯ 50 60 mA Flash devices ⎯ 50 60 mA Flash devices ⎯ ⎯ ⎯ 12 0.3 0.4 20 0.8 1.0 mA Without T model mA With T model ICTS ICTSPLL6 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 4 7 mA Power supply current* 40 60 90 100 150 200 µA MB90F362, MB90F367, MB90362, MB90367 MB90F367, MB90367 MB90F362T, MB90F367T, MB90362T, MB90367T MB90F367T, MB90367T MB90F362, MB90F367, MB90362, MB90367 MB90F367, MB90367 MB90F362T, MB90F367T, MB90362T, MB90367T MB90F367T, MB90367T MB90F362, MB90F367, MB90362, MB90367 MB90F367, MB90367 MB90F362T, MB90F367T, MB90362T, MB90367T MB90F367T, MB90367T 110 250 10 30 60 80 8 30 60 80 5 50 50 100 150 200 30 70 130 170 25 130 µA µA µA µA ICCLS VCC = 5.0 V Internal frequency : 8 kHz, At sub sleep, TA = +25°C ICCT VCC = 5.0 V Internal frequency : 8 kHz, At watch mode, TA = +25°C ICCH VCC = 5.0 V, At stop mode, TA = +25°C Without T model With T model (Continued) 41 * : The power supply current is measured with an external clock. MB90360 Series (Continued) Symbol (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Pin Other than AVCC, AVSS, AVR, VCC, VSS, C Condition Value Min ⎯ Typ Max Unit Remarks Parameter Input capacity CIN ⎯ 5 15 pF 42 MB90360 Series 4. AC Characteristics (1) Clock Timing (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Symbol Pin Value Min 3 4 4 X0, X1 4 4 4 Clock frequency fC 3 4 4 X0, X1 4 4 4 fCL Clock cycle time tCYL tCYLL Input clock pulse width Input clock rise and fall time Internal operating clock frequency (machine clock) Internal operating clock cycle time (machine clock) PWH, PWL PWHL, PWLL tCR, tCF fCP fCPL tCP tCPL X0A, X1A X0, X1 X0, X1 X0A, X1A X0 X0A X0 ⎯ ⎯ ⎯ ⎯ — 62.5 41.67 10 10 5 ⎯ 1.5 ⎯ 41.67 20 ⎯ ⎯ ⎯ 32.768 ⎯ ⎯ 30.5 ⎯ 15.2 ⎯ ⎯ 8.192 ⎯ 122.1 8 6 4 100 333 333 — ⎯ ⎯ 5 24 50 666 ⎯ MHz MHz MHz kHz ns ns µs ns µs ns Duty ratio is about 30% to 70%. When using external clock When using an oscillation circuit When using an external clock ⎯ ⎯ ⎯ 24 24 12 MHz MHz MHz ⎯ ⎯ ⎯ 8 6 4 MHz MHz MHz Typ ⎯ ⎯ ⎯ Max 16 16 12 Unit MHz MHz MHz Remarks 1/2 when PLL stops, When using an oscillation circuit PLL × 1, When using an oscillation circuit PLL × 2, When using an oscillation circuit PLL × 3, When using an oscillation circuit PLL × 4, When using an oscillation circuit PLL × 6, When using an oscillation circuit 1/2 when PLL stops, When using an external clock PLL × 1, When using an external clock PLL × 2, When using an external clock PLL × 3, When using an external clock PLL × 4, When using an external clock PLL × 6, When using an external clock MHz When using main clock kHz ns µs When using sub clock When using main clock When using sub clock 43 MB90360 Series • Clock Timing tCYL X0 PWH tCF PWL tCR 0.8 VCC 0.2 VCC tCYLL X0A PWHL tCF PWLL tCR 0.8 VCC 0.2 VCC 44 MB90360 Series • Guaranteed PLL Operation Range Guaranteed operation range 5.5 Power supply voltage VCC (V) 4.0 3.5 Guaranteed PLL operation range Guaranteed A/D converter operation range 1.5 4 Internal clock fCP (MHz) 24 Guaranteed operation range of MB90360 series Guaranteed oscillation frequency range 24 ×6 ×4 ×3 ×2 ×1 Internal clock fCP (MHz) 16 12 8 4.0 1.5 34 8 12 16 24 ×1/2 (PLL off) External clock fC (MHz) * * : When using the oscillation circuit, the maximum oscillation clock frequency is 16 MHz. 45 MB90360 Series (2) Reset Standby Input (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Symbol Pin Value Min 500 Reset input time tRSTL RST Oscillation time of oscillator* + 100 µs 100 Max ⎯ ⎯ ⎯ Unit ns ns µs Remarks Under normal operation In stop mode, sub clock mode, sub sleep mode and watch mode In timebase timer mode * : Oscillation time of oscillator is the time that the amplitude reaches 90%. In the crystal oscillator, the oscillation time is between several ms and tens of ms. In FAR / ceramic oscillators, the oscillation time is between hundreds of µs and several ms. With an external clock, the oscillation time is 0 ms. • Under normal operation : tRSTL RST 0.2 VCC 0.2 VCC • In stop mode, sub clock mode, sub sleep mode, watch mode : tRSTL RST 0.2 VCC 90% of amplitude 0.2 VCC X0 Internal operation clock Oscillation time of oscillator 100 µs Oscillation stabilization waiting time Instruction execution Internal reset 46 MB90360 Series (3) Power-on Reset (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Power on rise time Power off time Symbol tR tOFF Pin VCC VCC Condition ⎯ Value Min 0.05 1 Max 30 ⎯ Unit ms ms Due to repetitive operation Remarks tR 2.7 V 0.2 V 0.2 V tOFF If you change the power supply voltage too rapidly, a power-on reset may occur. We recommend that you start up smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within 1 V/s, you can operate while using the PLL clock. 0.2 V VCC VCC 3V VSS Holds RAM data We recommend a rise of 50 mV/ms maximum. 47 MB90360 Series (4) UART0/1 (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V) Value Pin Condition Unit Remarks Min Max SCK0, SCK1 SCK0, SCK1, SOT0, SOT1 SCK0, SCK1, SIN0, SIN1 SCK0, SCK1, SIN0, SIN1 SCK0, SCK1 SCK0, SCK1 SCK0, SCK1, SOT0, SOT1 SCK0, SCK1, SIN0, SIN1 SCK0, SCK1, SIN0, SIN1 External shift clock mode output pins are CL = 80 pF + 1 TTL. Internal shift clock mode output pins are CL = 80 pF + 1 TTL. 8 tCP −80 100 60 4 tCP 4 tCP ⎯ 60 60 ⎯ +80 ⎯ ⎯ ⎯ ⎯ 150 ⎯ ⎯ ns ns ns ns ns ns ns ns ns Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Notes : • AC characteristic in CLK synchronized mode. • CL is load capacity value of pins when testing. • tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”. • Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V tSLOV 0.8 V SOT 2.4 V 0.8 V tIVSH tSHIX VIH VIL SIN VIH VIL 48 MB90360 Series • External Shift Clock Mode tSLSH tSHSL VIH VIL tSLOV VIL VIH SCK SOT 2.4 V 0.8 V tIVSH tSHIX VIH VIL SIN VIH VIL (5) Trigger Input Timing (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V) Value Pin Condition Unit Remarks Min Max INT8, INT9R INT10, INT11 INT12R, INT13 INT14R, INT15R ADTG Parameter Symbol Input pulse width tTRGH tTRGL ⎯ 5 tCP ⎯ ns Note : tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”. INT8, INT9R INT10, INT11 INT12R, INT13 INT14R, INT15R ADTG VIH VIH VIL tTRGH tTRGL VIL 49 MB90360 Series (6) Timer Related Resource Input Timing (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V) Value Parameter Symbol Pin Condition Unit Remarks Min Max Input pulse width tTIWH tTIWL TIN2, TIN3 IN0 to IN3 ⎯ 4 tCP ⎯ ns Note : tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock Timing”. VIH VIH VIL tTIWH tTIWL VIL TIN2, TIN3 IN0 to IN3 (7) Timer Related Resource Output Timing (TA = –40°C to +125°C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0 V) Value Parameter Symbol Pin Condition Unit Remarks Min Max CLK ↑ → TOUT change time tTO TOT2, TOT3 PPGC to PPGF ⎯ 30 ⎯ ns CLK 2.4 V TOT2, TOT3 PPGC to PPGF 2.4 V 0.8 V tTO 50 MB90360 Series 5. A/D Converter (TA = −40 °C to +125 °C, 3.0 V ≤ AVR − AVSS, VCC = AVCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Resolution Total error Nonlinearity error Differential nonlinearity error Zero reading voltage Full scale reading voltage Compare time Sampling time Analog port input current Analog input voltage range Reference voltage range Power supply current Reference voltage supply current Offset between input channels Symbol ⎯ ⎯ ⎯ ⎯ VOT VFST ⎯ ⎯ IAIN VAIN ⎯ IA IAH IR IRH ⎯ Pin ⎯ ⎯ ⎯ ⎯ Value Min ⎯ ⎯ ⎯ ⎯ Typ ⎯ ⎯ ⎯ ⎯ Max 10 ±3.0 ±2.5 ±1.9 Unit bit LSB LSB LSB Remarks AN0 to AN15 AVSS − 1.5 AVSS + 0.5 AVSS + 2.5 LSB AN0 to AN15 AVR − 3.5 AVR − 1.5 AVR + 0.5 LSB ⎯ ⎯ AN0 to AN15 AN0 to AN15 AVR AVCC AVCC AVR AVR AN0 to AN15 1.0 2.0 0.5 1.2 −0.3 AVSS AVSS + 2.7 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 3.5 ⎯ 600 ⎯ ⎯ 16,500 µs µs µA V V mA µA µA µA LSB * * 4.5 V ≤ AVCC ≤ 5.5 V 4.0 V ≤ AVCC < 4.5 V 4.5 V ≤ AVCC ≤ 5.5 V 4.0 V ≤ AVCC < 4.5 V ∞ +0.3 AVR AVCC 7.5 5 900 5 4 * : If A/D converter is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVR = 5.0 V) . (Continued) 51 MB90360 Series • About the external impedance of analog input and its sampling time • A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage changed to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. • Analog input circuit model R Analog input C Comparator During sampling : ON MB90F362/T/S/TS, MB90F367/T/S/TS R 2.0 kΩ (Max) 4.5 V ≤ AVCC ≤ 5.5 V 4.0 V ≤ AVCC < 4.5 V 8.2 kΩ (Max) C 16.0 pF (Max) 16.0 pF (Max) MB90362/T/S/TS, MB90367/T/S/TS, MB90V340A-101/102/103/104 R C 4.5 V ≤ AVCC ≤ 5.5 V 2.0 kΩ (Max) 14.4 pF (Max) 4.0 V ≤ AVCC < 4.5 V 8.2 kΩ (Max) 14.4 pF (Max) Note : The values are reference values. (Continued) 52 MB90360 Series (Continued) • To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. • The relationship between external impedance and minimum sampling time • At 4.5 V ≤ AVCC ≤ 5.5 V (External impedance = 0 kΩ to 100 kΩ) MB90362/T/S/TS, MB90367/T/S/TS, MB90V340A-101/102/103/104 (External impedance = 0 kΩ to 20 kΩ) MB90362/T/S/TS, MB90367/T/S/TS, MB90V340A-101/102/103/104 External impedance [kΩ] External impedance [kΩ] 100 90 80 70 60 50 40 30 20 10 0 20 18 16 14 12 10 8 6 4 2 0 0 MB90F362/T/S/TS, MB90F367/T/S/TS MB90F362/T/S/TS, MB90F367/T/S/TS 0 5 10 15 20 25 30 35 1 2 3 4 5 6 7 8 Minimum sampling time [µs] • At 4.0 V ≤ AVCC < 4.5 V (External impedance = 0 kΩ to 100 kΩ) MB90362/T/S/TS, MB90367/T/S/TS, MB90V340A-101/102/103/104 Minimum sampling time [µs] (External impedance = 0 kΩ to 20 kΩ) MB90362/T/S/TS, MB90367/T/S/TS, MB90V340A-101/102/103/104 External impedance [kΩ] External impedance [kΩ] 100 90 80 70 60 50 40 30 20 10 0 20 18 16 14 12 10 8 6 4 2 0 0 MB90F362/T/S/TS, MB90F367/T/S/TS MB90F362/T/S/TS, MB90F367/T/S/TS 0 5 10 15 20 25 30 35 1 2 3 4 5 6 7 8 Minimum sampling time [µs] Minimum sampling time [µs] • If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. • About errors As | AVR − AVSS | becomes smaller, values of relative errors grow larger. 53 MB90360 Series 6. Definition of A/D Converter Terms Resolution Non linearity error Differential linearity error Total error : Analog variation that is recognized by an A/D converter. : Deviation between a line across zero-transition line ( “00 0000 0000B” ← → “00 0000 0001B” ) and full-scale transition line ( “11 1111 1110B” ← → “11 1111 1111B” ) and actual conversion characteristics. : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. : Difference between an actual value and an theoretical value. A total error includes zero transition error, full-scale transition error, and linear error. Total error 3FFH 3FEH 3FDH Digital output {1 LSB × (N − 1) + 0.5 LSB} Actual conversion characteristics 1.5 LSB 004H 003H 002H 001H 0.5 LSB AVSS Analog input VNT (Actually-measured value) Actual conversion characteristics Ideal characteristics AVR Total error of digital output “N” = VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVR − AVSS 1 LSB = (Ideal value) [V] 1024 VOT (Ideal value) = AVSS + 0.5 LSB [V] VFST (Ideal value) = AVR − 1.5 LSB [V] [LSB] VNT : A voltage at which digital output transits from (N − 1) to N. (Continued) 54 MB90360 Series (Continued) Non linearity error 3FFH 3FEH 3FDH Digital output Actual conversion characteristics {1 LSB × (N − 1) + VOT } N+1 VFST (actual measurement value) VNT (actual measurement value) Actual conversion characteristics Actual conversion characteristics Differential linearity error Ideal characteristics Digital output N 004H 003H 002H N−1 V (N + 1) T (actual measurement value) VNT (actual measurement value) Actual conversion characteristics AVR Analog input Ideal characteristics 001H VOT (actual measurement value) AVSS Analog input AVR N−2 AVSS Non linearity error of digital output N = Differential linearity error of digital output N = 1 LSB = VNT − {1 LSB × (N − 1) + VOT} 1 LSB V (N+1) T − VNT 1 LSB VFST − VOT 1022 −1 LSB [LSB] [V] [LSB] VOT : Voltage at which digital output transits from “000H” to “001H.” VFST : Voltage at which digital output transits from “3FEH” to “3FFH.” 55 MB90360 Series 7. Notes on A/D Converter Section Use the device with external circuits of the following output impedance for analog inputs : • Recommended output impedance of external circuits are : Approx. 1.5 kΩ or lower (4.0 V ≤ AVCC ≤ 5.5 V, sampling period = 0.5 µs) • If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high as internal capacitor. • If output impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient. • Analog input circuit model Analog input R Comparator C 4.5 V ≤ AVCC ≤ 5.5 V : R = 2.52 kΩ, C = 10.7 pF : : 4.0 V ≤ AVCC < 4.5 V : R = 13.6 kΩ, C = 10.7 pF : : Note : Use the values in the figure only as a guideline. 8. Flash Memory Program/Erase Characteristics Parameter Chip erase time Word (16-bit width) programming time Program/Erase cycle Flash memory data retention time Conditions Value Min ⎯ ⎯ 10,000 20 Typ 1 16 ⎯ ⎯ Max 15 3,600 ⎯ ⎯ Unit s µs cycle Year * Remarks Excludes programming prior to erasure Except for the overhead time of the system level TA = +25 °C VCC = 5.0 V ⎯ Average TA = +85 °C * : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 °C) . 56 MB90360 Series ■ ORDERING INFORMATION Part number MB90F362PMT MB90F362TPMT MB90F362SPMT MB90F362TSPMT MB90F367PMT MB90F367TPMT MB90F367SPMT MB90F367TSPMT MB90362PMT MB90362TPMT MB90362SPMT MB90362TSPMT MB90367PMT MB90367TPMT MB90367SPMT MB90367TSPMT MB90V340A-101 MB90V340A-102 MB90V340A-103 MB90V340A-104 299-pin Ceramic PGA (PGA-299C-A01) For evaluation 48-pin Plastic LQFP (FPT-48P-M26) Package Remarks 57 MB90360 Series ■ PACKAGE DIMENSION 48-pin Plastic LQFP (FPT-48P-M26) 9.00±0.20(.354±.008)SQ Note 1) * : These dimensions include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. * 7.00 –0.10 .276 –.004 SQ 36 25 +0.40 +.016 0.145±0.055 (.006±.002) 37 24 0.08(.003) INDEX Details of "A" part 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) 48 13 "A" 0˚~8˚ LEAD No. 0.50(.020) 1 12 0.10±0.10 (.004±.004) (Stand off) 0.20±0.05 (.008±.002) 0.08(.003) M 0.25(.010) 0.60±0.15 (.024±.006) C 2003 FUJITSU LIMITED F48040S-c-2-2 Dimensions in mm (inches) Note : The values in parentheses are reference values. 58 MB90360 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. 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Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0501 © 2005 FUJITSU LIMITED Printed in Japan