MB90375

FUJITSU SEMICONDUCTOR DATA SHEET DS07-13729-1E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90370/375 Series MB90372/F372/F377/V370 s DESCRIPTION The MB90370/375 series is a line of general-purpose, 16-bit microcontrollers designed for those applications which require high-speed real-time processing. The instruction set is designed to be optimized for controller applications which inheriting the AT architecture of F2MC-16LX series and allow a wide range of control tasks to be processed efficiently at high speed. A built-in LPC interface, serial IRQ and PS/2 interface simplifies communication with host CPU and PS/2 devices in computer system. Moreover, SMbus compliant I2C*2, comparator for battery control and A/D converter implements the smart battery control. With these features, the MB90370/375 series matches itself as keyboard controller with smart battery control. (Continued) s PACKAGE 144-pin plastic LQFP (FPT-144P-M12) MB90370/375 Series (Continued) While inheriting the AT architecture of the F2MC*1 family, the instruction set for the F2MC-16LX CPU core of the MB90370/375 series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90370 has an on-chip 32-bit accumulator which enables processing of long-word data. *1 : F2MC stands for FUJITSU Flexible Microcontroller and a registered trademark of FUJITSU LIMITED. *2 : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. s FEATURES • Clock • Embedded PLL clock multiplication circuit • Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz to 16 MHz) . • Minimum instruction execution time of 62.5 ns (at oscillation of 4 MHz, four times the PLL clock, operation at VCC of 3.3 V) • CPU addressing space of 16M bytes • Internal 24-bit addressing • Instruction set optimized for controller applications • Rich data types (bit, byte, word, long word) • Rich addressing mode (23 types) • High code efficiency • Enhanced precision calculation realized by the 32-bit accumulator • Instruction set designed for high level language (C) and multi-task operations • Adoption of system stack pointer • Enhanced pointer indirect instructions • Barrel shift instructions • Program patch function (2 address pointer) • Improved execution speed • 4-byte instruction queue • Powerful interrupt function • Priority level programmable : 8 levels • 32 factors of stronger interrupt function • Automatic data transmission function independent of CPU operation • Extended intelligent I/O service function (EI2OS) • Maximum 16 channels • Low-power consumption (standby) mode • Sleep mode (mode in which CPU operating clock is stopped) • Timebase timer mode (mode in which operations other than timebase timer and watch timer are stopped) • Stop mode (mode in which all oscillations are stopped) • CPU intermittent operation mode • Watch mode • Package • LQFP-144 (FPT-144P-M12 : 0.4 mm pitch) • Process • CMOS technology 2 MB90370/375 Series s PRODUCT LINEUP Part number Parameter Classification ROM size RAM size MB90V370 — — 15.7K Bytes MB90F372 MB90F377 MB90372 Mask ROM Flash type ROM 64K Bytes 6K Bytes CPU function Number of instruction : 351 Minimum execution time : 62.5 ns / 4 MHz (PLL × 4) Addressing mode : 23 Data bit length : 1, 8, 16 bits Maximum memory space : 16M Bytes I/O port (N-channel) : 16 I/O port (CMOS) : 72 I/O port (CMOS with pull-up control) : 32 Total : 120 Reload timer : 4 channels Reload mode, single-shot mode or event count mode selectable PPG timer : 3 channels PWM mode or single-shot mode selectable Bit decoder : 1 channel Parity generator : 1 channel Selectable odd/even parity PS/2 interface : 3 channels 4 selectable sampling clocks LPC bus interface : 1 channel Universal peripheral Interface : 4 channels GA20 output control : for UPI channel 0 only Data buffer array : 48 bytes Yes No Yes No I/O port 16-bit reload timer 16-bit PPG timer Bit decoder Parity generator PS/2 interface LPC interface LPC Standby (able to work in Stop/TBT/Watch mode) Serial IRQ controller Serial IRQ request : 6 channels LPC clock monitor / control With full-duplex double buffer (variable data length) Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively used I2C (SMbus compliant) : 1 channel Support I2C bus of Philips and the SMbus proposed by Intel Selectable packet error check Timeout detection function No No Yes No UART I2C PC Arbitration under a paticular condition*2 (Continued) 3 MB90370/375 Series (Continued) Part number Parameter MB90V370 MB90F372 MB90F377 MB90372 Multi-address I2C Multi-address I2C (SMbus compliant) : 1 channel Support I2C bus of Philips and the SMbus proposed by Intel Selectable packet error check Timeout detection function 6 addresses support ALERT function Three bus connection routes can be switched by I2C / multi-address I2C A comparator that can change the hysteresis width is contained Battery voltage, mounting/dismounting and instantaneous interruption can be detected Parallel and serial charging/discharging 6 independent channels Selectable causes : Rise/fall edge, fall edge, “L” level or “H” level 8 independent channels Causes : “L” level 8/10-bit resolution : 12 channels Conversion time : Less than 6.13 µs (16 MHz internal clock) 8-bit resolution : 2 channels Up to 9 SEG × 4 COM Without LCD Selectable LCD output or CMOS I/O port controller/driver Same as MB90F372 Bridge circuit Comparator External interrupt Key-on wake-up interrupt 8/10-bit A/D converter 8-bit D/A converter LCD controller/driver*3 Low-power consumption Process Package Operating voltage Stop mode / Sleep mode / CPU intermittent operation mode / Watch mode CMOS PGA256 LQFP-144 (FPT-144P-M12 : 0.4 mm pitch) 3.0 V to 3.6 V @ 16 MHz *1 *1 : Varies with conditions such as the operating frequency (see Section “s ELECTRICAL CHARACTERISTICS”) , Assurance for the MB90V370 is given only for operation with a tool at power supply voltage of 3.0 V to 3.6 V, an operating temperature of 0 °C to +25 °C, and an operating frequency of 1 MHz to 16 MHz. *2 : I2C can detect the arbitration lost when another I2C starts another communication at the same time. *3 : After reset, PF5 to PF7 serve as general purpose I/O pins in MB90F377; however, these pins serve as V1, V2 and V3 function in other products. 4 MB90370/375 Series s PACKAGE AND CORRESPONDING PRODUCTS Package PGA256 FPT-144P-M12 : Available X : Not available Note : For more information about each package, see Section “s PACKAGE DIMENSIONS”. X MB90V370 MB90F372 X MB90F377 X MB90372 X s DIFFERENCES AMONG PRODUCTS Memory size In evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. The following items must be taken into consideration. • The MB90V370 does not have an internal ROM, however, operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the development tool. • In the MB90V370, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH are mapped to bank FF only. (This setting can be changed by the development tool configuration.) • In the MB90372/F372, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH are mapped to bank FF only. 5 MB90370/375 Series s PIN ASSIGNMENT • MB90372/F372 (TOP VIEW) P37/ADTG P36 P35 P34 P33 P32 P31 P30 P27 P26 P25 P24 P23 P22 P21 X1 X0 Vss Vcc P20 P17 P16 P15 P14 P13 P12 P11 P10 P07/KSI7 P06/KSI6 P05/KSI5 P04/KSI4 P03/KSI3 P02/KSI2 P01/KSI1 P00/KSI0 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 P40/PSCK0 P41/PSDA0 P42/PSCK1 P43/PSDA1 P44/PSCK2 P45/PSDA2 P46/CLKRUN P47/SERIRQ P50/GA20 P51/LFRAME P52/LRESET P53/LCK P54/LAD0 P55/LAD1 P56/LAD2 P57/LAD3 RST Vcc Vss X0A X1A PA0/ALR1 PA1/ALR2 PA2/ALR3 PA3/ACO PA4/OFB1 PA5/OFB2 PA6/OFB3 CVcc CVRH1 CVRH2 CVRL CVss PB0/DCIN PB1/DCIN2 PB2/VOL1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP-144 P77/PPG1 P76/UI3 P75/UO3 P74/UCK3 P73/UI2 P72/UO2 P71/UCK2 P70/UI1 P67/UO1 P66/UCK1 P65/INT5 P64/INT4 P63/INT3 P62/INT2 P61/INT1 P60/INT0 PD7/PPG3 Vss Vcc PF7/V3* PF6/V2* PF5/V1* PF4/COM3* PF3/COM2* PF2/COM1* PF1/COM0* PF0/SEG8* PE7/TO4/SEG7 PE6/TIN4/SEG6 PE5/TO3/SEG5 PE4/TIN3/SEG4 PE3/TO2/SEG3 PE2/TIN2/SEG2 PE1/TO1/SEG1 PE0/TIN1/SEG0 P82/ALERT * : High current pins 6 PB3/VSI1 PB4/VOL2 PB5/VSI2 PB6/VOL3 PB7/VSI3 AVcc AVR AVss PC0/AN0/SW1 PC1/AN1/SW2 PC2/AN2/SW3 PC3/AN3 PC4/AN4 PC5/AN5 PC6/AN6 PC7/AN7 PD0/AN8 Vcc Vss MD2 MD1 MD0 PD1/AN9 PD2/AN10 PD3/AN11 PD4/DA1 PD5/DA2 PD6/PPG2 P90/SCL2 P91/SDA2 P92/SCL3 P93/SDA3 P94/SCL4 P95/SDA4 P80/SCL1 P81/SDA1 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 (FPT-144P-M12) MB90370/375 Series • MB90F377 (TOP VIEW) P37/ADTG P36 P35 P34 P33 P32 P31 P30 P27 P26 P25 P24 P23 P22 P21 X1 X0 Vss Vcc P20 P17 P16 P15 P14 P13 P12 P11 P10 P07/KSI7 P06/KSI6 P05/KSI5 P04/KSI4 P03/KSI3 P02/KSI2 P01/KSI1 P00/KSI0 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 P40/PSCK0 P41/PSDA0 P42/PSCK1 P43/PSDA1 P44/PSCK2 P45/PSDA2 P46/CLKRUN P47/SERIRQ P50/GA20 P51/LFRAME P52/LRESET P53/LCK P54/LAD0 P55/LAD1 P56/LAD2 P57/LAD3 RST Vcc Vss X0A X1A PA0/ALR1 PA1/ALR2 PA2/ALR3 PA3/ACO PA4/OFB1 PA5/OFB2 PA6/OFB3 CVcc CVRH1 CVRH2 CVRL CVss PB0/DCIN PB1/DCIN2 PB2/VOL1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP-144 P77/PPG1 P76/UI3 P75/UO3 P74/UCK3 P73/UI2 P72/UO2 P71/UCK2 P70/UI1 P67/UO1 P66/UCK1 P65/INT5 P64/INT4 P63/INT3 P62/INT2 P61/INT1 P60/INT0 PD7/PPG3 Vss Vcc PF7* PF6* PF5* PF4* PF3* PF2* PF1* PF0* PE7/TO4 PE6/TIN4 PE5/TO3 PE4/TIN3 PE3/TO2 PE2/TIN2 PE1/TO1 PE0/TIN1 P82/ALERT * : High current pins PB3/VSI1 PB4/VOL2 PB5/VSI2 PB6/VOL3 PB7/VSI3 AVcc AVR AVss PC0/AN0/SW1 PC1/AN1/SW2 PC2/AN2/SW3 PC3/AN3 PC4/AN4 PC5/AN5 PC6/AN6 PC7/AN7 PD0/AN8 Vcc Vss MD2 MD1 MD0 PD1/AN9 PD2/AN10 PD3/AN11 PD4/DA1 PD5/DA2 PD6/PPG2 P90/SCL2 P91/SDA2 P92/SCL3 P93/SDA3 P94/SCL4 P95/SDA4 P80/SCL1 P81/SDA1 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 (FPT-144P-M12) 7 MB90370/375 Series s PIN DESCRIPTION Pin no. LQFP-144 128, 129 20, 21 17 58, 57, 56 Pin name X0, X1 X0A, X1A RST MD0 to MD2 P00 to P07 109 to 116 KSI0 to KSI7 D I/O Pin status circuit during reset A A B C Oscillating Oscillating Main oscillation pins. Sub-clock oscillation pins. Input pin for operation mode specification. Connect this pin directly to Vcc or Vss. General-purpose I/O ports. Can be used as key-on wake-up interrupt input channel 0 to channel 7. Input is enabled when 1 is set in EICR : EN0 to EN7 in standby mode. General-purpose I/O ports. General-purpose I/O ports. General-purpose I/O ports. General-purpose I/O ports. External trigger input pin (ADTG) for the A/D converter. General-purpose N-ch open-drain I/O port. F Serial clock I/O pin for PS/2 interface channel 0. This function is selected when PS/2 interface channel 0 is enabled. General-purpose N-ch open-drain I/O port. F Port input P42 3 PSCK1 P43 4 PSDA1 P44 5 PSCK2 P45 6 PSDA2 P46 7 CLKRUN G F F F F Serial data I/O pin for PS/2 interface channel 0. This function is selected when PS/2 interface channel 0 is enabled. General-purpose N-ch open-drain I/O port. Serial clock I/O pin for PS/2 interface channel 1. This function is selected when PS/2 interface channel 1 is enabled. General-purpose N-ch open-drain I/O port. Serial data I/O pin for PS/2 interface channel 1. This function is selected when PS/2 interface channel 1 is enabled. General-purpose N-ch open-drain I/O port. Serial clock I/O pin for PS/2 interface channel 2. This function is selected when PS/2 interface channel 2 is enabled. General-purpose N-ch open-drain I/O port. Serial data I/O pin for PS/2 interface channel 2. This function is selected when PS/2 interface channel 2 is enabled. General-purpose N-ch open-drain I/O port. LPC clock status / restart request I/O pin for serial IRQ controller. This function is selected when serial IRQ and LPC clock restart request is enabled. Function Reset input External reset input pin. Mode input 117 to 124 P10 to P17 125, P20 to P27 130 to 136 137 to 143 P30 to P36 144 P37 ADTG P40 1 PSCK0 P41 2 PSDA0 E E E E (Continued) 8 MB90370/375 Series Pin no. LQFP-144 8 Pin name P47 SERIRQ P50 I/O Pin status circuit during reset General-purpose I/O port. H Function Serial IRQ data I/O pin for serial IRQ controller. This function is selected when serial IRQ is enabled. General-purpose I/O port. GA20 output for LPC interface. This function is selected when GA20 function is enabled. General-purpose I/O port. LFRAME input for LPC interface. This function is selected when LPC interface is enabled. General-purpose I/O port. Reset input for LPC interface. This function is selected when LPC interface is enabled. General-purpose I/O port. Clock input for LPC interface. This function is selected when LPC interface is enabled. General-purpose I/O ports. Address/Data I/O for LPC interface. This function is selected when LPC interface is enabled. General-purpose I/O ports. Can be used as DTP/external interrupt request input channel 0 to 5. Input is enabled when 1 is set in ENIR : EN0 to EN5 in standby mode. General-purpose I/O port. Serial clock I/O pin for UART channel 1. This function is enabled when UART channel 1 enables clock output. General-purpose I/O port. Serial data output pin for UART channel 1. This function is enabled when UART channel 1 enables data output. General-purpose I/O port. Serial data input pin for UART channel 1. While UART channel 1 is operating for input, the input of this pin is used as required and must not be used for any other input. General-purpose I/O port. Serial clock I/O pin for UART channel 2. This function is enabled when UART channel 2 enables clock output. 9 GA20 P51 H 10 LFRAME P52 H 11 LRESET P53 H 12 LCK P54 to P57 H 13 to 16 LAD0 to LAD3 P60 to P65 H Port input 93 to 98 INT0 to INT5 P66 I 99 UCK1 P67 I 100 UO1 P70 I 101 UI1 P71 I 102 UCK2 I (Continued) 9 MB90370/375 Series Pin no. LQFP-144 103 Pin name P72 UO2 P73 I/O Pin status circuit during reset General-purpose I/O port. I Function Serial data output pin for UART channel 2. This function is enabled when UART channel 2 enables data output. General-purpose I/O port. Serial data input pin for UART channel 2. While UART channel 2 is operating for input, the input of this pin is used as required and must not be used for any other input. General-purpose I/O port. Serial clock I/O pin for UART channel 3. This function is enabled when UART channel 3 enables clock output. General-purpose I/O port. Serial data output pin for UART channel 3. This function is enabled when UART channel 3 enables data output. General-purpose I/O port. Serial data input pin for UART channel 3. While UART channel 3 is operating for input, the input of this pin is used as required and must not be used for any other input. Port input General-purpose I/O port. Output pin for PPG channel 1. This function is enabled when PPG channel 1 output is enabled. General-purpose N-ch open-drain I/O port. Serial clock I/O pin for multi-address I2C. General-purpose N-ch open-drain I/O port. Serial data I/O pin for multi-address I2C. General-purpose N-ch open-drain I/O port. ALERT output pin for multi-address I2C. General-purpose N-ch open-drain I/O port. Serial clock I/O pin for bridge circuit. General-purpose N-ch open-drain I/O port. Serial data I/O pin for bridge circuit. General-purpose N-ch open-drain I/O port. Serial clock I/O pin for bridge circuit. General-purpose N-ch open-drain I/O port. Serial data I/O pin for bridge circuit. 104 UI2 P74 I 105 UCK3 P75 I 106 UO3 P76 I 107 UI3 P77 I 108 PPG1 P80 SCL1 P81 SDA1 P82 ALERT P90 SCL2 P91 SDA2 P92 SCL3 P93 SDA3 I 71 72 73 65 66 67 68 T T J T T T T (Continued) 10 MB90370/375 Series Pin no. LQFP-144 69 70 Pin name P94 SCL4 P95 SDA4 PA0 to PA2 ALR1 to ALR3 PA3 ACO PA4 to PA6 OFB1 to OFB3 PB0 to PB1 DCIN to DCIN2 PB2 I/O Pin status circuit during reset T T Function General-purpose N-ch open-drain I/O port. Serial clock I/O pin for bridge circuit. General-purpose N-ch open-drain I/O port. Serial data I/O pin for bridge circuit. General-purpose I/O ports. Alarm signal output when battery 1 to 3 run down in comparator circuit. General-purpose I/O port. AC power set signal output in comparator circuit. General-purpose I/O ports. Battery 1 to 3 discharge control signal output in comparator circuit. General-purpose I/O ports. 22 to 24 H Port input 25 H 26 to 28 H 34, 35 K AC power monitoring input in comparator circuit. General-purpose I/O ports. 36 VOL1 PB3 VSI1 PB4 K Battery 1 power instantaneous interruption monitoring input in comparator circuit. General-purpose I/O ports. Battery 1 indicator monitoring input in comparator circuit. Comparator General-purpose I/O ports. input Battery 2 power instantaneous interruption monitoring input in comparator circuit. General-purpose I/O ports. Battery 2 indicator monitoring input in comparator circuit. General-purpose I/O ports. Battery 3 power instantaneous interruption monitoring input in comparator circuit. General-purpose I/O ports. Battery 3 indicator monitoring input in comparator circuit. General-purpose I/O ports. Comparator input Battery 1 to 3 mount / dismount detection input in comparator or circuit. A/D input A/D converter analog input pin 0 to 2. This function is enabled when the analog input specification is enabled (ADER1) . 37 K 38 VOL2 PB5 VSI2 PB6 K 39 K 40 VOL3 PB7 VSI3 PC0 to PC2 K 41 K 45 to 47 SW1 to SW3 AN0 to AN2 L (Continued) 11 MB90370/375 Series Pin no. LQFP-144 Pin name PC3 to PC7 I/O circuit Pin status during reset Function General-purpose I/O ports. 48 to 52 AN3 to AN7 PD0 to PD3 M A/D input M A/D converter analog input pin 3 to 7. This function is enabled when the analog input specification is enabled (ADER1) . General-purpose I/O ports. A/D converter analog input pin 8 to 11. This function is enabled when the analog input specification is enabled (ADER2) . General-purpose I/O ports. D/A converter analog output 1 to 2. This function is selected when D/A converter is enabled. General-purpose I/O port. Output pin for PPG channel 2 to 3. This function is selected when PPG channel 2 to 3 output is enabled. General-purpose I/O port. Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. External clock input pin for reload timer 1. General-purpose I/O port. 53, 59 to 61 AN8 to AN11 PD4 to PD5 62 to 63 DA1 to DA2 PD6 to PD7 N 64, 92 PPG2 to PPG3 PE0 H 74 SEG0*1 TIN1 PE1 O1 (O2 for MB90F377) 75 SEG1*1 TO1 PE2 O1 (O2 for MB90F377) Port input Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. Event output pin for reload timer 1. General-purpose I/O port. Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. External clock input pin for reload timer 2. General-purpose I/O port. 76 SEG2*1 TIN2 PE3 O1 (O2 for MB90F377) 77 SEG3*1 TO2 PE4 O1 (O2 for MB90F377) Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. Event output pin for reload timer 2. General-purpose I/O port. 78 SEG4*1 TIN3 PE5 O1 (O2 for MB90F377) Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. External clock input pin for reload timer 3. General-purpose I/O port. 79 SEG5*1 TO3 O1 (O2 for MB90F377) Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. Event output pin for reload timer 3. (Continued) 12 MB90370/375 Series (Continued) Pin no. LQFP-144 Pin name PE6 I/O circuit O1 (O2 for MB90F377) Pin status during reset Function General-purpose I/O port. Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. External clock input pin for reload timer 4. General-purpose I/O port. 80 SEG6*1 TIN4 PE7 81 SEG7*1 TO4 PF0 O1 (O2 for MB90F377) P1 (P2 for MB90F377) P1 (P2 for MB90F377) Port input Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. Event output pin for reload timer 4. General-purpose I/O port. Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. General-purpose I/O port. COM output pin for LCD controller/driver. This function is selected when LCD COM output is enabled. 82 SEG8*1 PF1 to PF4 83 to 86 COM0 to COM3*2 PF5 to PF7 87 to 89 42 43 44 29 30 31 32 33 19, 55, 91, 127 18, 54, 90, 126 V1 to V3*2 AVCC AVR AVSS CVCC CVRH1 CVRH2 CVRL CVSS Vss Vcc General-purpose I/O port. Q1 (Q2 for Power input Power input pin for LCD controller/driver. This function is MB90F377) selected when external voltage divider is enabled. R S R R R R R R – Power input – Power (3.3 V) input pin. Vss power input pin for analog circuits. Power (0 V) input pin. Power input Standard power input pin of the comparator. Vcc power input pin for analog circuits. Power input Vref+ input pin for the A/D converter. This voltage must not exceed Vcc. Vref- is fixed to AVSS. Vss power input pin for analog circuits. Vcc power input pin for analog circuits. *1 : It doesn’t exist in MB90F377. *2 : They don’t exist in MB90F377. 13 MB90370/375 Series s I/O CIRCUIT TYPE Type X1/X1A N-ch P-ch Xout P-ch N-ch Standby mode control Circuit Remarks Main/Sub clock (main/sub clock crystal oscillator) • High-rate oscillation feedback resistor of approximately 1 MΩ • Low-rate oscillation feedback resistor of approximately 10 MΩ • Hysteresis input • Pull-up resistor approximately 50 kΩ • Hysteresis input A X0/X0A B R C • CMOS output • Hysteresis input • Selectable pull-up resistor approximately 50 kΩ • IOL = 4 mA R P-ch Pull-up control P-ch Pout Nout D N-ch Hysteresis input Standby mode control R P-ch Pull-up control P-ch Pout Nout E N-ch • CMOS output • CMOS input • Selectable pull-up resistor approximately 50 kΩ • IOL = 4 mA CMOS input Standby mode control N-ch F N-ch Nout • • • • N-ch open-drain output Hysteresis input IOL = 4 mA 5 V tolerant Hysteresis input Standby mode control (Continued) 14 MB90370/375 Series Type P-ch Circuit Remarks • N-ch open-drain output • CMOS input • IOL = 4 mA Nout G N-ch CMOS input Standby mode control P-ch Pout Nout • CMOS output • CMOS input • IOL = 4 mA H N-ch CMOS input Standby mode control P-ch Pout Nout • CMOS output • Hysteresis input • IOL = 4 mA I N-ch Hysteresis input Standby mode control N-ch J N-ch Nout • • • • N-ch open-drain output CMOS input IOL = 4 mA 5 V tolerant CMOS input Standby mode control P-ch Pout Nout N-ch • • • • CMOS output CMOS input Comparator input IOL = 4 mA K CMOS input Standby mode control + − Comparator input (Continued) 15 MB90370/375 Series Type P-ch Circuit • • • • • Remarks CMOS output CMOS input Comparator input A/D analog input IOL = 4 mA Pout Nout N-ch L + − CMOS input Standby mode control Comparator input Analog input P-ch Pout Nout M N-ch • • • • CMOS output CMOS input A/D analog input IOL = 4 mA CMOS input Standby mode control Analog input P-ch Pout Nout N-ch • • • • CMOS output CMOS input D/A analog output IOL = 4 mA N CMOS input Standby mode control Analog input P-ch Pout Nout N-ch • • • • CMOS output CMOS input Segment output IOL = 4 mA O1 CMOS input Standby mode control Segment output (Continued) 16 MB90370/375 Series Type P-ch Circuit Remarks • CMOS output • CMOS input • IOL = 4 mA Pout Nout O2 N-ch CMOS input Standby mode control P-ch Pout Nout N-ch • • • • CMOS output CMOS input Segment output IOL = 12 mA P1 CMOS input Standby mode control Segment output P-ch Pout Nout • CMOS output • CMOS input • IOL = 12 mA P2 N-ch CMOS input Standby mode control P-ch Pout Nout N-ch • • • • CMOS output CMOS input LCD driving power supply IOL = 12 mA Q1 CMOS input Standby mode control LCD driving power supply P-ch Pout Nout • CMOS output • CMOS input • IOL = 12 mA Q2 N-ch CMOS input Standby mode control (Continued) 17 MB90370/375 Series (Continued) Type Circuit Remarks • Power supply input protection circuit P-ch R N-ch IN P-ch Analog input enable IN • A/D converter reference voltage (AVR) input pin with protection circuit S N-ch Analog input enable N-ch T N-ch Nout • • • • N-ch open-drain output CMOS input IOL = 4 mA 5 V tolerant CMOS input Standby mode control 18 MB90370/375 Series s HANDLING DEVICES • Be sure that the maximum rated voltage is not exceeded (latch-up prevention) . A latch-up may occur on a CMOS IC if a voltage higher than VCC or lower than VSS is applied to an input or output pin other than medium-to-high voltage pins. A latch-up may also occur if a voltage higher than the rating is applied between VCC and VSS. A latch-up causes a rapid increase in the power supply current, which can result in thermal damage to an element. Take utmost care that the maximum rated voltage is not exceeded. When turning the power on or off to analog circuits, be sure that the analog supply voltages (AVCC, CVCC, AVR, CVRH1, CVRH2 and CVRL) and analog input voltage do not exceed the digital supply voltage (VCC) . • Stabilize the supply voltages Even within the operation guarantee range of the VCC supply voltage, a malfunction can be caused if the supply voltage undergoes a rapid change. For voltage stabilization guidelines, the VCC ripple fluctuations (P-P value) at commercial frequencies (50 Hz to 60 Hz) should be suppressed to 10% or less of the reference VCC value. During a momentary change such as when switching a supply voltage, voltage fluctuations should also be suppressed so that the transient fluctuation rate is 0.1 V/ms or less. • Power-on To prevent a malfunction in the built-in voltage drop circuit, secure 50 µs (between 0.2 V and 1.8 V) or more for the voltage rise time during power-on. • Treatment of unused input pins An unused input pin may cause a malfunction if it is left open. Every unused input pin should be pulled up or down. • Treatment of A/D converter, D/A converter and comparator power pin When the A/D converter, D/A converter and comparator is not used, connect the pins as follows : AVCC = CVCC = VCC, AVSS = AVR = CVSS = CVRL = CVRH1 = CVRH2 = VSS. • Notes on external clock When an external clock is used, the oscillation stabilization wait time is required at power-on reset or at cancellation of sub-clock mode or stop mode. As shown in diagram below, when an external clock is used, connect only the X0 pin and leave the X1 pin open. X0 MB90370/375 series Open X1 • Power supply pins When a device has two or more VCC or VSS pins, the pins that should have equal potential are connected within the device in order to prevent a latch-up or other malfunction. To reduce extraneous emission, to prevent a malfunction of the strobe signal due to an increase in the group level, and to maintain the local output current rating, connect all these power supply pins to an external power supply and ground them. The current source should be connected to the VCC and VSS pins of the device with minimum impedance. It is recommended that a bypass capacitor of about 0.1 µF be connected near the terminals between VCC and VSS. 19 MB90370/375 Series • Analog power-on sequence of A/D converter, D/A converter and comparator The power to the A/D converter, D/A converter and comparator (AVCC, CVCC, AVR, CVRH1, CVRH2 and CVRL) and analog inputs (AN0 to AN11, VOL1 to VOL3, VSI1 to VSI3, SW1 to SW3, DCIN and DCIN2) must be turned on after the power to the digital circuits (VCC) is turned on. When turning off the power, turn off the power to the digital circuits (VCC) after turning off the power to the A/D converter, D/A converter, comparator and analog inputs. When the power is turned on or off, AVR should not exceed AVCC. And CVRH1, CVRH2 and CVRL should not exceed CVCC. Also, when a pin that is used for A/D analog input is used as an input port, the input voltage should not exceed AVCC. And when comparator analog input is also used as an input port, the input voltage should not exceed CVCC. (The power to the analog circuits and the power to the digital circuits can be simultaneously turned on or off.) • Caution on Operations during PLL Clock Mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. 20 MB90370/375 Series s BLOCK DIAGRAM • MB90372/F372/V370 X0, X0A X1, X1A RST Clock control circuit Reset circuit (Watchdog timer) Interrupt controller Timebase timer P00/KSI0 to P07/KSI7 P10 to P17 P20 to P27 8 8 8 CMOS I/O port 0, 1, 2, 3* 8 I2C bus I2C bus (Multi-address) CPU series core Other pins Vss x 4, Vcc x 4, MD0-2, AVcc, AVss, CVcc, CVss F2MC-16LX Delayed interrupt generator N-ch open-drain I/O port 8, 9 P80/SCL1 P81/SDA1 P82/ALERT P90/SCL2 P91/SDA2 P92/SCL3 P93/SDA3 P94/SCL4 P95/SDA4 6 P30 to P36 8 P37/ADTG P40/PSCK0 P41/PSDA0 P42/PSCK1 P43/PSDA1 P44/PSCK2 P45/PSDA2 P46/CLKRUN P47/SERIRQ P50/GA20 P51/LFRAME P52/LRESET P53/LCK P54/LAD0 P55/LAD1 P56/LAD2 P57/LAD3 Key-on wake-up interrupt Bridge circuit N-ch open-drain I/O port 4 (P47 is CMOS I/O port) 6 2 3CH PS/2 interface CMOS I/O port A, B Comparator F2MC-16LX bus Serial IRQ (6 channels) LPC Interface GateA20 control Bus interface Battery select circuit 7 8 Voltage comparator 3 7 UPI (Ch0, 1, 2, 3) PA0/ALR1 to PA2/ALR3 PA3/ACO PA4/OFB1 to PA6/OFB3 PB0/DCIN PB1/DCIN2 PB2/VOL1 PB3/VSI1 PB4/VOL2 PB5/VSI2 PB6/VOL3 PB7/VSI3 CVRH1, CVRH2, CVRL AVR CMOS I/O port 5 P60/INT0 to 6 P65/INT5 P66/UCK1 P67/UO1 P70/UI1 P71/UCK2 P72/UO2 P73/UI2 P74/UCK3 P75/UO3 P76/UI3 P77/PPG1 6 A/D converter (8/10 bit) 12 DTP/External interrupt 2 D/A converter UART (Ch1, 2, 3) 16-bit PPG (Ch1) 16-bit PPG (Ch2, 3) CMOS I/O port C, D PC0/AN0/SW1 PC1/AN1/SW2 PC2/AN2/SW3 PC3/AN3 to PC7/AN7 PD0/AN8 to PD3/AN11 PD4/DA1 PD5/DA2 PD6/PPG2 PD7/PPG3 PE0/TIN1 PE1/TO1 PE2/TIN2 PE3/TO2 PE4/TIN3 PE5/TO3 PE6/TIN4 PE7/TO4 PF0 PF1 to PF4 PF5 to PF7 CMOS I/O port 6, 7 CMOS I/O port E, F RAM ROM 16-bit reload timer (Ch1, 2, 3, 4) ROM correction ROM mirroring * : P00 to P07, P10 to P17, P20 to P27, P30 to P37 : With registers that can be used as input pull-up resistors Note: PF0 to PF7 : High current pins 21 MB90370/375 Series • MB90F377 X0, X0A X1, X1A RST Clock control circuit Reset circuit (Watchdog timer) Interrupt controller Timebase timer P00/KSI0 to P07/KSI7 P10 to P17 P20 to P27 8 8 8 CMOS I/O port 0, 1, 2, 3* 8 I2C bus I2C bus (Multi-address) CPU F2MC-16LX series core Other pins Vss x 4, Vcc x 4, MD0-2, AVcc, AVss, CVcc, CVss Delayed interrupt generator N-ch open-drain I/O port 8, 9 P80/SCL1 P81/SDA1 P82/ALERT P90/SCL2 P91/SDA2 P92/SCL3 P93/SDA3 P94/SCL4 P95/SDA4 6 P30 to P36 8 P37/ADTG P40/PSCK0 P41/PSDA0 P42/PSCK1 P43/PSDA1 P44/PSCK2 P45/PSDA2 P46/CLKRUN P47/SERIRQ P50/GA20 P51/LFRAME P52/LRESET P53/LCK P54/LAD0 P55/LAD1 P56/LAD2 P57/LAD3 Key-on wake-up interrupt Bridge circuit N-ch open-drain I/O port 4 (P47 is CMOS I/O port) 6 2 3CH PS/2 interface CMOS I/O port A, B Comparator F2MC-16LX bus Serial IRQ (6 channels) LPC Interface GateA20 control Bus interface Battery select circuit 7 8 Voltage comparator 3 7 UPI (Ch0, 1, 2, 3) PA0/ALR1 to PA2/ALR3 PA3/ACO PA4/OFB1 to PA6/OFB3 PB0/DCIN PB1/DCIN2 PB2/VOL1 PB3/VSI1 PB4/VOL2 PB5/VSI2 PB6/VOL3 PB7/VSI3 CVRH1, CVRH2, CVRL AVR CMOS I/O port 5 P60/INT0 to 6 P65/INT5 P66/UCK1 P67/UO1 P70/UI1 P71/UCK2 P72/UO2 P73/UI2 P74/UCK3 P75/UO3 P76/UI3 P77/PPG1 6 A/D converter (8/10 bit) 12 DTP/External interrupt 2 D/A converter UART (Ch1, 2, 3) 16-bit PPG (Ch1) 16-bit PPG (Ch2, 3) CMOS I/O port C, D PC0/AN0/SW1 PC1/AN1/SW2 PC2/AN2/SW3 PC3/AN3 to PC7/AN7 PD0/AN8 to PD3/AN11 PD4/DA1 PD5/DA2 PD6/PPG2 PD7/PPG3 PE0/TIN1 PE1/TO1 PE2/TIN2 PE3/TO2 PE4/TIN3 PE5/TO3 PE6/TIN4 PE7/TO4 PF0 PF1 to PF4 PF5 to PF7 CMOS I/O port 6, 7 CMOS I/O port E, F RAM ROM 16-bit reload timer (Ch1, 2, 3, 4) ROM correction ROM mirroring * : P00 to P07, P10 to P17, P20 to P27, P30 to P37 : With registers that can be used as input pull-up resistors Note: PF0 to PF7 : High current pins 22 MB90370/375 Series s MEMORY MAP Single-chip mode (with ROM mirroring function) FFFFFFH ROM area Address #1 FC0000H 010000H ROM area (FF bank image) Address #2 004000H 003FC0H Address #3 Peripheral area RAM area 000100H 0000F8H 000000H Peripheral area : Access not allowed : Internal access memory Register Model MB90372 MB90F372/F377 MB90V370 Address #1 Address #2 Address #3 FF0000H FF0000H FF0000H* 004000H 004000H 004000H* 001900H 001900H 003FC0H * : The MB90V370 does not contain ROM. Assume that the development tool uses these area for its ROM decode areas. Note : ROM data in the FF bank can be seen as an image in the higher 00 bank to validate the small model C compiler. Because addresses of the 16 low-order bits in the FF bank are the same, the table in ROM can be referenced without the “far” specification. For example, when 00C000H is accessed, the contents of ROM at FFC000H are actually accessed. The ROM area in the FF bank exceeds 48 kilobytes, and all areas cannot be seen as images in the 00 bank. Because ROM data from FF4000H to FFFFFFH is seen as an image at 004000H to 00FFFFH, the ROM data table should be stored in the area from FF4000H to FFFFFFH. 23 MB90370/375 Series s F2MC-16LX CPU PROGRAMMING MODEL • Dedicated registers AH AL Accumulator (A) USP SSP PS PC User Stack Pointer (USP) System Stack Pointer (SSP) Processor Status (PS) Program Counter (PC) DPR Direct Page Register (DPR) PCB DTB USB SSB ADB 8 bits 16 bits 32 bits Program Bank Register (PCB) Data Bank Register (DTB) User Stack Bank Register (USB) System Stack Bank Register (SSB) Additional Data Bank Register (ADB) 24 MB90370/375 Series • General-purpose registers CPU Dedicated register Accumulator User stack pointer System stack pointer Internal bus Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register RAM RAM General-purpose register • Processor status (PS) 15 PS Default value 7  Default value  ILM 000 6 I 0 5 S 1 4 T X 1312 RP 00000 3 N X 2 Z X 1 V X 0 C X : CCR 87 CCR -01XXXXX 0 B4 B3 B2 B1 Default value 0 0 0 0 B0 0 ILM0 0 : RP ILM2 Default value 0 ILM1 0 : ILM - : Not used X : Undefined 25 MB90370/375 Series s I/O MAP Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH 00000CH 00000DH 00000EH 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H 00001AH 00001BH 00001CH 00001DH 00001EH 00001FH Abbreviation PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PDRB PDRC PDRD PDRE PDRF DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 PGDR PGCSR DDRA DDRB DDRC DDRD DDRE DDRF Register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Port B data register Port C data register Port D data register Port E data register Port F data register Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Parity generator data register Parity generator control status register Port A direction register Port B direction register Port C direction register Port D direction register Port E direction register Port F direction register Byte Word access access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Parity generator Port A Port B Port C Port D Port E Port F Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Port C Port D Port E Port F Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB X1111111B XXXXXXXXB XXXXXXXXB XXXXXXXXB -----111B --111111B -XXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00000000B 00000000B 0-------B 00000000B 00000000B 00000000B XXXXXXXXB X------0B -0000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued) 26 MB90370/375 Series Address 000020H 000021H 000022H 000023H 000024H 000025H 000026H 000027H 000028H 000029H 00002AH 00002BH 00002CH 00002DH 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H Abbreviation SMR1 SCR1 SIDR1/ SODR1 SSR1 M2CR1 CDCR1 ENIR EIRR ELVR ADER1 ADER2 BRSR ADC0 ADCR0 ADCR1 ADCS0 ADCS1 SICRL SICRH SIFR1 SIFR2 SIFR3 SIFR4 Register Serial mode register 1 Serial control register 1 Input data register 1 / Output data register 1 Serial status register 1 Mode 2 control register 1 Clock division control register 1 Interrupt / DTP enable register Interrupt / DTP cause register Request level setting register Analog input enable register 1 Analog input enable register 2 Bridge circuit selection register A/D control register A/D data register A/D control status register Serial interrupt request register Serial interrupt control register Serial interrupt frame number register 1 Serial interrupt frame number register 2 Serial interrupt frame number register 3 Serial interrupt frame number register 4 Byte Word access access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Initial value 00000-00B 00000100B UART1 XXXXXXXXB 00001000B ----1000B Communication prescaler 1 0---0000B --000000B DTP/external interrupt --XXXXXXB 00000000B ----0000B 11111111B ----1111B --000000B 00000000B XXXXXXXXB Port C, A/D Port D, A/D Bridge circuit 8/10-bit A/D converter 00000-XXB 00--------B 00000000B 00000000B 00000000B --000000B Serial IRQ --000000B --000000B --000000B (Continued) 27 MB90370/375 Series Address 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 00003FH 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H 000059H Abbreviation PDCRL1 PDCRH1 PCSRL1 PCSRH1 PDUTL1 PDUTH1 PCNTL1 PCNTH1 PDCRL2 PDCRH2 PCSRL2 PCSRH2 PDUTL2 PDUTH2 PCNTL2 PCNTH2 PDCRL3 PDCRH3 PCSRL3 PCSRH3 PDUTL3 PDUTH3 PCNTL3 PCNTH3 PSCR0 PSSR0 PSCR1 PSSR1 PSCR2 PSSR2 PSDR0 PSDR1 PSDR2 PSMR Register PPG1 down counter register PPG1 period setting register PPG1 duty setting register PPG1 control status register PPG2 down counter register PPG2 period setting register PPG2 duty setting register PPG2 control status register PPG3 down counter register PPG3 period setting register PPG3 duty setting register PPG3 control status register PS/2 interface control register 0 PS/2 interface status register 0 PS/2 interface control register 1 PS/2 interface status register 1 PS/2 interface control register 2 PS/2 interface status register 2 PS/2 interface data register 0 PS/2 interface data register 1 PS/2 interface data register 2 PS/2 interface mode register Byte Word access access       R/W R/W       R/W R/W       R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R W W W W R/W R/W R R W W W W R/W R/W R R W W W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Initial value 11111111B 11111111B XXXXXXXXB 16-bit PPG timer (CH1) XXXXXXXXB XXXXXXXXB XXXXXXXXB --000000B 00000000B 11111111B 11111111B XXXXXXXXB 16-bit PPG timer (CH2) XXXXXXXXB XXXXXXXXB XXXXXXXXB --000000B 00000000B 11111111B 11111111B XXXXXXXXB 16-bit PPG timer (CH3) XXXXXXXXB XXXXXXXXB XXXXXXXXB --000000B 00000000B 0--00000B 00000000B 0--00000B 00000000B 0--00000B 00000000B 00000000B 00000000B 00000000B ----0000B 3-channel PS/2 interface (Continued) 28 MB90370/375 Series Address 00005AH 00005BH 00005CH 00005DH 00005EH 00005FH 000060H 000061H 000062H 000063H 000064H 000065H 000066H 000067H 000068H 000069H 00006AH 00006BH 00006CH 00006DH 00006EH 00006FH 000070H 000071H 000072H 000073H Abbreviation DAT0 DAT1 DACR0 DACR1 UPAL1 UPAH1 UPAL2 UPAH2 UPAL3 UPAH3 UPCL UPCH UPDI0/ UPDO0 UPS0 UPDI1/ UPDO1 UPS1 UPDI2/ UPDO2 UPS2 UPDI3/ UPDO3 UPS3 LCR ROMM TMCSRL1 TMCSRH1 TMR1/ TMRD1 Register D/A converter data register 0 D/A converter data register 1 D/A control register 0 D/A control register 1 UPI1 address register (lower) UPI1 address register (upper) UPI2 address register (lower) UPI2 address register (upper) UPI3 address register (lower) UPI3 address register (upper) UPI control register (lower) UPI control register (upper) UPI0 data input register / data output register UPI0 status register UPI1 data input register / data output register UPI1 status register UPI2 data input register / data output register UPI2 status register UPI3 data input register / data output register UPI3 status register LPC control register ROM mirroring function selection register Timer control status register CH1 (lower) Timer control status register CH1 (upper) 16-bit timer/reload register CH1 Byte Word access access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R/W   R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R/W R/W R/W Resource name Initial value XXXXXXXXB D/A converter XXXXXXXXB -------0B -------0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B -000-000B XXXXXXXXB LPC interface 00000000B XXXXXXXXB 00000000B XXXXXXXXB 00000000B XXXXXXXXB 00000000B -----000B ROM mirroring function ------01B 00000000B 16-bit reload timer (CH1) ----0000B XXXXXXXXB XXXXXXXXB (Continued) 29 MB90370/375 Series Address 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH Abbreviation TMCSRL2 TMCSRH2 TMR2/ TMRD2 TMCSRL3 TMCSRH3 TMR3/ TMRD3 TMCSRL4 TMCSRH4 TMR4/ TMRD4 IBCRL IBCRH IBSRL IBSRH IDAR IADR ICCR ITCR ITOC ITOD ISTO IMTO RDR0 RDR1 RDR2 RDR3 Register Timer control status register CH2 (lower) Timer control status register CH2 (upper) 16-bit timer/reload register CH2 Timer control status register CH3 (lower) Timer control status register CH3 (upper) 16-bit timer/reload register CH3 Timer control status register CH4 (lower) Timer control status register CH4 (upper) 16-bit timer/reload register CH4 I C bus control register (lower) I C bus control register (upper) I2C bus status register (lower) I2C bus status register (upper) I C data register I C address register I2C clock control register I2C timeout control register I C timeout clock register I C timeout data register I2C slave timeout register I2C master timeout register Port 0 pull-up resistor setting register Port 1 pull-up resistor setting register Port 2 pull-up resistor setting register Port 3 pull-up resistor setting register 2 2 2 2 2 2 Byte Word access access R/W R/W   R/W R/W   R/W R/W   R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Initial value 00000000B 16-bit reload timer (CH2) ----0000B XXXXXXXXB XXXXXXXXB 00000000B 16-bit reload timer (CH3) ----0000B XXXXXXXXB XXXXXXXXB 00000000B 16-bit reload timer (CH4) ----0000B XXXXXXXXB XXXXXXXXB ----0000B 00000000B 00000000B --000000B XXXXXXXXB -XXXXXXXB 0-000000B -0-00000B 00000000B 00000000B 00000000B 00000000B I2C Port 0 Port 1 Port 2 Port 3 00000000B 00000000B 00000000B 00000000B (Continued) 30 MB90370/375 Series Address 000090H to 9DH 00009EH 00009FH 0000A0H 0000A1H 0000A2H to A7H 0000A8H 0000A9H 0000AAH 0000ABH 0000ACH 0000ADH 0000AEH 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH Abbreviation Register Byte Word access access Prohibited area Resource name Initial value PACSR DIRR LPMCR CKSCR Program address detect control status register Delayed interrupt cause / clear register Low-power consumption mode register Clock selection register R/W R/W R/W R/W R/W R/W R/W R/W ROM correction Delayed interrupt Low-power consumption control register ----0000B -------0B 00011000B 11111100B Prohibited area WDTC TBTC WTC EICR EIFR FMCS Watchdog control register Timebase timer control register Watch timer control register Wake-up interrupt control register Wake-up interrupt flag register Flash memory control status register Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 R/W R/W R/W Prohibited area R/W R/W R/W Prohibited area ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B R/W R/W R/W Wake-up interrupt Flash memory interface circuit 00000000B -------0B 00010000B R/W R/W R/W Watchdog timer Timebase timer Watch timer X-XXX111B 1--00100B 10001000B (Continued) 31 MB90370/375 Series Address 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H 0000C1H 0000C2H 0000C3H 0000C4H 0000C5H 0000C6H 0000C7H 0000C8H 0000C9H 0000CAH 0000CBH 0000CCH 0000CDH 0000CEH 0000CFH 0000D0H 0000D1H 0000D2H 0000D3H 0000D4H 0000D5H 0000D6H 0000D7H Abbreviation ICR11 ICR12 ICR13 ICR14 ICR15 MBCRL MBCRH MBSRL MBSRH MDAR MALR MADR1 MADR2 MADR3 MADR4 MADR5 MADR6 MCCR MTCR MTOC MTOD MSTO MMTO SMR2 SCR2 SIDR2/ SODR2 SSR2 M2CR2 CDCR2 Register Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 MI C bus control register (lower) MI2C bus control register (upper) MI2C bus status register (lower) MI C bus status register (upper) MI C data register MI2C alert register MI2C address register 1 MI C address register 2 MI C address register 3 MI2C address register 4 MI2C address register 5 MI C address register 6 MI C clock control register MI2C timeout control register MI2C timeout clock register MI C timeout data register MI C slave timeout register MI2C master timeout register Serial mode register 2 Serial control register 2 Input data register 2 / output data register 2 Status register 2 Mode 2 control register 2 Clock division control register 2 2 2 2 2 2 2 2 2 2 Byte Word access access R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Initial value 00000111B 00000111B Interrupt controller 00000111B 00000111B 00000111B ----0000B 00000000B 00000000B --000000B XXXXXXXXB ----0000B -XXXXXXXB -XXXXXXXB -XXXXXXXB -XXXXXXXB -XXXXXXXB -XXXXXXXB 0-000000B -0-00000B 00000000B 00000000B 00000000B 00000000B 00000-00B 00000100B MI2C UART2 XXXXXXXXB 00001000B ----1000B Communication prescaler 2 0---0000B (Continued) 32 MB90370/375 Series Address 0000D8H 0000D9H 0000DAH 0000DBH 0000DCH 0000DDH 0000DEH 0000DFH 0000E0H 0000E1H 0000E2H 0000E3H 0000E4H 0000E5H 0000E6H 0000E7H 0000E8H 0000E9H 0000EAH 0000EBH to EDH 0000EEH 0000EFH 0000F0H to F4H 0000F5H to F7H 0000F8H to FFH Abbreviation COCRL COCRH COSRL1 COSRH1 CICRL CICRH COSRL2 COSRH2 CIER BDR BRRL BRRH SMR3 SCR3 SIDR3/ SODR3 SSR3 M2CR3 CDCR3 PDL3 Register Comparator control register (lower) Comparator control register (upper) Comparator status register 1 (lower) Comparator status register 1 (upper) Comparator interrupt control register (lower) Comparator interrupt control register (upper) Comparator status register 2 (lower) Comparator status register 2 (upper) Comparator input enable register Bit data register Bit result register (lower) Bit result register (upper) Serial mode register 3 Serial control register 3 Input data register 3 / output data register 3 Status register 3 Mode 2 control register 3 Clock division control register 3 Port 3 data latch register Byte Word access access R/W R/W R/W R/W R/W R/W R R R/W R/W R R R/W R/W R/W R/W R/W R/W R/W Prohibited area R/W R/W R/W R/W R/W R/W R R R/W R/W R R R/W R/W R/W R/W R/W R/W R/W Resource name Initial value --000000B 00011111B 00000000B --000000B Voltage comparator 00000000B --000000B XXXXXXXXB --XXXXXXB ---11111B ----XXXXB Bit decoder XXXXXXXXB XXXXXXXXB 00000-00B 00000100B UART3 XXXXXXXXB 00001000B ----1000B Communication prescaler 3 Port 3 data latch 0---0000B 00000000B LCRL*1 LCRH* 1 LCD control register 0*2 LCD control register 1* LCD display RAM*2 2 R/W R/W R/W Prohibited area External area R/W R/W  LCD controller / driver 00010000B 00000000B XXXXXXXXB VRAM*1 (Continued) 33 MB90370/375 Series Address 001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H 003FC0H 003FC1H 003FC2H 003FC3H 003FC4H 003FC5H 003FC6H 003FC7H 003FC8H 003FC9H 003FCAH 003FCBH 003FCCH 003FCDH 003FCEH 003FCFH 003FD0H 003FD1H 003FD2H 003FD3H Abbreviation Register Program address detection register 0 Byte Word access access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB PADR0 Program address detection register 1 Program address detection register 2 Program address detection register 3 ROM correction R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB LPC data buffer XXXXXXXXB array XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB PADR1 Program address detection register 4 Program address detection register 5 UDRL0 UDRH0 UDRL1 UDRH1 UDRL2 UDRH2 UDRL3 UDRH3 UDRL4 UDRH4 UDRL5 UDRH5 UDRL6 UDRH6 UDRL7 UDRH7 UDRL8 UDRH8 UDRL9 UDRH9 UP data register 0 (lower) UP data register 0 (upper) UP data register 1 (lower) UP data register 1 (upper) UP data register 2 (lower) UP data register 2 (upper) UP data register 3 (lower) UP data register 3 (upper) UP data register 4 (lower) UP data register 4 (upper) UP data register 5 (lower) UP data register 5 (upper) UP data register 6 (lower) UP data register 6 (upper) UP data register 7 (lower) UP data register 7 (upper) UP data register 8 (lower) UP data register 8 (upper) UP data register 9 (lower) UP data register 9 (upper) (Continued) 34 MB90370/375 Series (Continued) Address 003FD4H 003FD5H 003FD6H 003FD7H 003FD8H 003FD9H 003FDAH 003FDBH 003FDCH 003FDDH 003FDEH 003FDFH 003FE0H 003FE1H 003FE2H 003FE3H 003FE4H 003FE5H 003FE6H 003FE7H 003FE8H 003FE9H 003FEAH 003FEBH 003FECH 003FEDH 003FEEH 003FEFH 003FF0H 003FF1H 003FF2H to 003FFFH Abbreviation UDRLA UDRHA UDRLB UDRHB UDRLC UDRHC UDRLD UDRHD UDRLE UDRHE UDRLF UDRHF DNDL0 DNDH0 DNDL1 DNDH1 DNDL2 DNDH2 DNDL3 DNDH3 DNDL4 DNDH4 DNDL5 DNDH5 DNDL6 DNDH6 DNDL7 DNDH7 DBAAL DBAAH Register UP data register A (lower) UP data register A (upper) UP data register B (lower) UP data register B (upper) UP data register C (lower) UP data register C (upper) UP data register D (lower) UP data register D (upper) UP data register E (lower) UP data register E (upper) UP data register F (lower) UP data register F (upper) DOWN data register 0 (lower) DOWN data register 0 (upper) DOWN data register 1 (lower) DOWN data register 1 (upper) DOWN data register 2 (lower) DOWN data register 2 (upper) DOWN data register 3 (lower) DOWN data register 3 (upper) DOWN data register 4 (lower) DOWN data register 4 (upper) DOWN data register 5 (lower) DOWN data register 5 (upper) DOWN data register 6 (lower) DOWN data register 6 (upper) DOWN data register 7 (lower) DOWN data register 7 (upper) Data buffer array address register (lower) Data buffer array address register (upper) Byte Word access access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R R R R R/W R/W Resource name Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB LPC data buffer XXXXXXXXB array XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Prohibited area 35 MB90370/375 Series • Meaning of abbreviations used for reading and writing R/W : Read and write enabled R: Read-only W: Write-only • Explanation of initial values 0: The bit is initialized to 0. 1: The bit is initialized to 1. X: The initial value of the bit is undefined. -: The bit is not used. Its initial value is undefined. • Instruction using IO addressing e.g. MOV A, io, is not supported for registers area 003FC0H to 003FFFH. *1 : It doesn’t exist in MB90F377. *2 : Prohibited area in MB90F377. 36 MB90370/375 Series s INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER Interrupt cause Reset INT9 instruction Exception processing A/D converter conversion termination Timebase timer UPI0 IBF / LPC reset UPI1 IBF UPI2 IBF UPI3 IBF DTP/ext. interrupt channels 0/1 detection DTP/ext. interrupt channels 2/3 detection DTP/ext. interrupt channels 4/5 detection Wake-up interrupt detection UPI0/1/2/3 OBE 16-bit PPG timer 1 PS/2 interface 0/1 PS/2 interface 2 Watch timer I2C transfer complete / bus error 16-bit PPG timer 2/3 Voltage comparator 1 MI2C transfer complete / bus error Voltage comparator 2 I2C timeout / standby wake-up 16-bit reload timer 1/2 underflow MI2C timeout / standby wake-up 16-bit reload timer 3/4 underflow UART1 receive UART1 send UART2 receive UART2 send UART3 receive UART3 send Flash memory status Delayed interrupt generator module EI2OS support X X X Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 09H Address FFFFD8H Interrupt control register ICR    Address    High Priority*2 08H FFFFDCH 0AH FFFFD4H 0BH FFFFD0H 0CH FFFFCCH 0DH FFFFC8H 0EH FFFFC4H 0FH 11H 12H 13H 15H 16H 17H 18H 19H 1AH 1BH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH FFFFC0H FFFFB8H FFFFB4H FFFFB0H FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H 10H FFFFBCH ICR00 0000B0H*1 ICR01 0000B1H*1 ICR02 0000B2H*1 ICR03 0000B3H*1 ICR04 0000B4H*1 ICR05 0000B5H*2 ICR06 0000B6H*1 ICR07 0000B7H*1 ICR08 0000B8H*1 ICR09 0000B9H*1 ICR10 0000BAH*1 ICR11 0000BBH*1 ICR12 0000BCH*1 ICR13 0000BDH*1 ICR14 0000BEH*1 ICR15 0000BFH*1 Low 14H FFFFACH 1CH FFFF8CH 37 MB90370/375 Series : Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal. × : Cannot be used. : Can be used and support the EI2OS stop request. : Can be used. *1 : • For peripheral functions that share the ICR register, the interrupt level will be the same. • If the extended intelligent I/O service is to be used with a peripheral function that shares the ICR register with another peripheral function, the service can be started by either of the function. And if EI2OS clear is supported, both interrupt request flags for the two interrupt causes are cleared by EI2OS interrupt clear signal. It is recommended to mask either of the interrupt request during the use of EI2OS. • EI2OS service cannot be started multiple times simultaneously. Interrupt other than the operating interrupt is masked during EI2OS operation. It is recommended to mask either of the interrupt requests during the use of EI2OS. *2 : This priority is applied when interrupts of the same level occur simultaneously. 38 MB90370/375 Series s PERIPHERAL RESOURCES 1. Low-power Consumption Control Circuit The MB90370/375 series has the following CPU operating mode selected by the configuration of an operating clock and clock operation control. • Clock Mode • PLL clock mode In this mode, a PLL clock that is a multiple of the oscillation clock (HCLK) is used to operate the CPU and peripheral functions. • Main clock mode In this mode, the main clock, with the oscillation clock (HCLK) frequency divided by 2 is used to operate the CPU and peripheral functions. In the main clock mode, the PLL multiplier circuit is inactive. • Sub-clock mode In this mode, the sub-clock, with the sub-clock (SCLK) frequency divided by 4 is used to operate the CPU and peripheral functions. In the sub-clock mode, the main clock and PLL multiplier circuit are inactive. • CPU Intermittent Operating Mode In this mode, the CPU is operated intermittently while high-speed clock pluses are supplied to peripheral functions, thereby reducing power consumption. In this mode, intermittent clock pulses are supplied only to the CPU while it is accessing a register, internal memory, or peripheral function. • Standby Mode In this mode, the low-power consumption control circuit stops supplying the clock to the CPU (sleep mode) or the CPU and peripheral functions (timebase timer mode) or stops the oscillation clock itself (stop mode) , thereby reducing power consumption. • PLL sleep mode The PLL sleep mode is activated to stop the CPU operating clock in the PLL clock mode. Components excluding the CPU operate on the PLL clock. • Main sleep mode The main sleep mode is activated to stop the CPU operating clock in the main clock mode. Components excluding the CPU operate on the main clock. • Sub-sleep mode The sub-sleep mode is activated to stop the CPU operating clock in the sub-clock mode. Components excluding the CPU operate on the divided-by-four sub-clock. • Timebase timer mode The timebase timer mode causes the operation of functions, excluding the oscillation clock, timebase timer, and watch timer, to stop. All functions other than the timebase timer and watch timer are inactivated. • Watch mode and main watch mode The watch mode and main watch mode operates the watch timer only. The sub-clock operates but the main clock and PLL multiplier circuit stop. • Stop mode The stop mode causes the oscillation to stop. All functions are inactivated. Note : Because the stop mode turns the oscillation clock off, data can be retained by the lowest power consumption. 39 MB90370/375 Series (1) Register configuration Clock Selection Register 15 14 MCM R 1 13 WS1 R/W 1 12 WS0 R/W 1 11 SCS R/W 1 10 MCS R/W 1 9 CS1 R/W 0 8 CS0 R/W 0 Address : 0000A1H Read/write Initial value SCM R 1 Bit number CKSCR Lower Power Consumption Mode Control Register 7 6 SLP W 0 5 SPL R/W 0 4 RST W 1 3 TMD W 1 2 CG1 R/W 0 1 CG0 R/W 0 0 Reserved Address : 0000A0H Read/write Initial value STP W 0 Bit number LPMCR R/W 0 (2) Block diagram Low power consumption mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 RESV Pin highimpedance control circuit RST Pin CPU intermittent operation selector Pin Hi-Z control Internal reset Internal reset generation circuit Intermittent cycle selection CPU clock control circuit CPU clock pulse 2 Interrupt clearing Standby control circuit Stop and sleep signals Stop signal Machine clock Oscillation stabilization wait clearing Clock selector Divideby-4 Subclock PLL multiplier circuit System clock generation circuit X0 Pin X1 Pin 2 2 Peripheral clock control circuit Peripheral clock Clock generation part Oscillation stabilization wait time selector Subclock generation circuit X0A Pin X1A Pin SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock selection register (CKSCR) Divideby-2 Main clock Divideby-8 Divideby-16 Divideby-128 Divideby-4 Divideby-4 Timebase timer 40 MB90370/375 Series 2. I/O Ports (1) Outline of I/O ports Each I/O port outputs data from the CPU to the I/O pins or inputs signals from the I/O pins to the CPU as directed by the port data register (PDR) . Each CMOS I/O port can also designate the direction of a data flow (input or output) at the I/O pins in bit units using the port data direction register (DDR) . Or N-channel open-drain port can designate the direction of a data flow (input or output) at the I/O pins in bit units using the port data register (PDR) . The function of each port and the resources using it are described below : • • • • • • • • • • • • • • • • Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Port C Port D Port E Port F : : : : : : : : : : : : : : : : General-purpose I/O port/resource (Key-on wake-up interrupt) General-purpose I/O port General-purpose I/O port General-purpose I/O port/resource (A/D converter external trigger) General-purpose I/O port/resource (PS/2 interface / serial IRQ controller) General-purpose I/O port/resource (LPC interface) General-purpose I/O port/resource (DTP / UART1) General-purpose I/O port/resource (UART1 / UART2 / UART3 / PPG1) General-purpose I/O port/resource (Multi-address I2C) General-purpose I/O port/resource (I2C / Multi-address I2C) General-purpose I/O port/resource (Comparator) General-purpose I/O port/resource (Comparator) General-purpose I/O port/resource (Comparator / A/D converter) General-purpose I/O port/resource (A/D converter / D/A converter / PPG2 / PPG3) General-purpose I/O port/resource (Reload timer1 to 4 / LCD controller*) General-purpose I/O port/resource (LCD controller*) * : LCD controller doesn’t exist in MB90F377, and so Port E and F of MB90F377 are not used for this purpose. (2) Register configuration Register Port 0 data register (PDR0) Port 1 data register (PDR1) Port 2 data register (PDR2) Port 3 data register (PDR3) Port 4 data register (PDR4) Port 5 data register (PDR5) Port 6 data register (PDR6) Port 7 data register (PDR7) Port 8 data register (PDR8) Port 9 data register (PDR9) Port A data register (PDRA) Port B data register (PDRB) Port C data register (PDRC) Port D data register (PDRD) Port E data register (PDRE) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH 00000CH 00000DH 00000EH Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB X1111111B XXXXXXXXB XXXXXXXXB XXXXXXXXB -----111B --111111B -XXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) 41 MB90370/375 Series (Continued) Register Port F data register (PDRF) Port 0 data direction register (DDR0) Port 1 data direction register (DDR1) Port 2 data direction register (DDR2) Port 3 data direction register (DDR3) Port 4 data direction register (DDR4) Port 5 data direction register (DDR5) Port 6 data direction register (DDR6) Port 7 data direction register (DDR7) Port A data direction register (DDRA) Port B data direction register (DDRB) Port C data direction register (DDRC) Port D data direction register (DDRD) Port E data direction register (DDRE) Port F data direction register (DDRF) Analog data input enable register (ADER1) Analog data input enable register (ADER2) Comparator input enable register (CIER) LCD control register 1 (LCRH) Port 0 pull-up resistor setting register (RDR0) Port 1 pull-up resistor setting register (RDR1) Port 2 pull-up resistor setting register (RDR2) Port 3 pull-up resistor setting register (RDR3) Port 3 data latch register (PDL3) R/W X : Read/write enabled : Undefined : Not used Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 00001AH 00001BH 00001CH 00001DH 00001EH 00001FH 00002AH 00002BH 0000E0H 0000EFH 00008CH 00008DH 00008EH 00008FH 0000EAH Initial value XXXXXXXXB 00000000B 00000000B 00000000B 00000000B 0-------B 00000000B 00000000B 00000000B -0000000B 00000000B 00000000B 00000000B 00000000B 00000000B 11111111B ----1111B ---11111B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 42 MB90370/375 Series (3) Block diagram of I/O ports • Block diagram of port 0 pins RDR Resource input Port data register (PDR) Pull-up resistor About 50 kΩ PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write Internal data bus Internal data bus DDR read Standby control (SPL = 1) • Block diagram of port 1 pins RDR Port data register (PDR) Pull-up resistor About 50 kΩ PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL = 1) 43 MB90370/375 Series • Block diagram of port 2 pins RDR Port data register (PDR) Pull-up resistor About 50 kΩ PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write Internal data bus Internal data bus DDR read Standby control (SPL = 1) • Block diagram of port 3 pins RDR Port data register (PDR) Resource input Pull-up resistor About 50 kΩ PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Port data latch register (PDL) Input latch R Standby control (SPL = 1) 44 MB90370/375 Series • Block diagram of port 47 pin Resource output Port data register (PDR) Resource input Resource output enable PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write • Block diagram of port 46 pin Resource output Port data register (PDR) Internal data bus Resource input Resource output enable Internal data bus DDR read Standby control (SPL = 1) PDR read Output latch PDR write Pin Read-Modify-Write instruction Standby control (SPL = 1) 45 MB90370/375 Series • Block diagram of port 45 to 40 pins Resource output Port data register (PDR) Internal data bus Internal data bus Resource input Resource output enable PDR read Output latch PDR write Pin Read-Modify-Write instruction Standby control (SPL = 1) • Block diagram of port 5 pins Resource output Port data register (PDR) Resource input Resource output enable PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL = 1) 46 MB90370/375 Series • Block diagram of port 6 pins Resource output Port data register (PDR) Resource input Resource output enable PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write • Block diagram of port 7 pins Resource output Port data register (PDR) Resource input Resource output enable Internal data bus Internal data bus DDR read Standby control (SPL = 1) PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL = 1) 47 MB90370/375 Series • Block diagram of port 8 pins Resource output Port data register (PDR) Internal data bus Internal data bus Resource input Resource output enable PDR read Output latch PDR write Pin Read-Modify-Write instruction Standby control (SPL = 1) • Block diagram of port 9 pins Resource output Port data register (PDR) Resource input Resource output enable PDR read Output latch PDR write Pin Read-Modify-Write instruction Standby control (SPL = 1) 48 MB90370/375 Series • Block diagram of port A pins Resource output Resource output enable Port data register (PDR) PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write • Block diagram of port B pins Internal data bus Internal data bus DDR read Standby control (SPL = 1) CIER Port data register (PDR) PDR read Output latch PDR write Port data direction register (DDR) Direction latch DDR write Standby control (SPL = 1) DDR read Comparator input Comparator operation enable Pin 49 MB90370/375 Series • Block diagram of port C7 to C3 pins ADER Port data register (PDR) Internal data bus Internal data bus PDR read Output latch PDR write Port data direction register (DDR) Direction latch DDR write Standby control (SPL = 1) DDR read to A/D converter analog input A/D converter channel selection bit Pin • Block diagram of port C2 to C0 pins CIER ADER Port data register (PDR) Comparator Comparator operation enable bit (COCRH) PDR read Output latch PDR write Port data direction register (DDR) Direction latch DDR write Standby control (SPL = 1) DDR read to A/D converter analog input A/D converter channel selection bit Pin 50 MB90370/375 Series • Block diagram of port D7 and D6 pins Resource output Resource output enable Port data register (PDR) PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write • Block diagram of port D5 and D4 pins Internal data bus Internal data bus DDR read Standby control (SPL = 1) Port data register (PDR) PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Analog output D/A output enable Standby control (SPL = 1) 51 MB90370/375 Series • Block diagram of port D3 to D0 pins ADER Port data register (PDR) Internal data bus Internal data bus A/D input PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL = 1) • Block diagram of port E pins (not for MB90F377) Resource output Port data register (PDR) Resource input Resource output enable PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL = 1) LCD output LCD output enable 52 MB90370/375 Series • Block diagram of port F7 to F5 pins (not for MB90F377) LCRH VS LCD input (V1 to V3) Port data register (PDR) Internal data bus Internal data bus PDR read Output latch PDR write Port data direction register (DDR) Direction latch DDR write Pin DDR read Standby control (SPL = 1) • Block diagram of port F4 to F0 pins (not for MB90F377) Port data register (PDR) PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL = 1) LCD output LCD output enable 53 MB90370/375 Series 3. Timebase timer The timebase timer is an 18-bit free-running counter (timebase counter) that counts up in synchronization with the internal count clock (one-half of the source oscillation) . Features of timebase timer : • Interrupt generated when counter overflow • EI2OS supported • Interval timer function : An interrupt generated at four different time intervals • Clock supply function : Four different clocks can be selected as watchdog timer’s count clock. Supply clock for oscillation stabilization (1) Register configuration Timebase Timer Control Register 15 14    13    12 TBIE R/W 0 11 TBOF R/W 0 10 TBR R/W 1 9 TBC1 R/W 0 8 TBC0 R/W 0 Address : 0000A9H Read/write Initial value Reserved Bit number TBTC R/W 1 (2) Block diagram of timebase timer Timebase timer counter Divide-by -two HCLK ×21 ×22 ×23 ×27 × 28 ×29 ×210 ×211 ×212 ×213 ×214 ×215 ×216 ×217 ×218 OF OF OF OF To watchdog timer To the oscillation stabilization wait time selector in the clock control section Power-on reset Stop mode start CKSCR : MCS = 1 → 0 (*1) SCS = 1 → 0 (*2) Timebase timer interrupt signal #12 (0CH) RESV   TBIE TBOF TBR TBC1 TBC0 Timebase timer interrupt register (TBTC) Counter clear circuit Interval timer selector TBOF set  : Unused OF : Overflow HCLK : Oscillation clock *1 : Switching of the machine clock from the oscillation clock to the PLL clock *2 : Switching from main clock to sub-clock 54 MB90370/375 Series 4. Watchdog timer The watchdog timer is a 2-bit counter that uses the timebase timer’s supply clock as the count clock. After activation, if the watchdog timer is not cleared within a given period, the CPU will be reset. • Features of watchdog timer : Reset CPU at four different time intervals Status bits to indicate the reset causes (1) Register configuration of watchdog timer Watchdog Timer Control Register 7 6    5 WRST R X 4 ERST R X 3 SRST R X 2 WTE W 1 1 WT1 W 1 0 WT0 W 1 Address : 0000A8H Read/write Initial value PONR R X Bit number WDTC (2) Block diagram of watchdog timer Watchdog timer control register (WDTC) PONR  WRST ERST SRST WTE 2 Activation with CLR Start of watch mode Start of sleep mode Start of stop mode reset generation Counter clear control circuit Count clock selector CLK 4 (Timebase timer counter) One-half of HCLK ×21 ×22 ×28 ×29 ×210 ×211 ×212 ×213 ×214 ×215 ×216 ×217 ×218 2-bit counter CLR To the internal reset generator 4 WT1 WT0 WDCS (from watch timer control register, WTC) Watchdog timer Overflow Watchdog reset generator Sub-clock divide by 4 ×21 ×22 ×210 ×211 ×212 ×213 ×214 ×215 Watch timer counter HCLK : Oscillation clock 55 MB90370/375 Series 5. Watch timer The watch timer is a 15-bit timer that uses sub-clocks and can generate an interval interrupt. It can also be used as the watchdog timer clock source and sub-clock oscillation wait time. Features of the watch timer : • Provides the watchdog timer clock source • Sub-clock oscillation stabilization wait timer function • Interval timer function that generates interrupts in a given cycle (1) Register configuration of watch timer Watch Timer Control Register 7 6 SCE R 0 5 WTIE R/W 0 4 WTOF R/W 0 3 WTR W 1 2 WTC2 R/W 0 1 WTC1 R/W 0 0 WTC0 R/W 0 Bit number WTC Address : 0000AAH Read/write Initial value WDCS R/W 1 (2) Block diagram of watch timer Watch timer control register (WTC) WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 Clear 28 29 210 211 212 213 214 215 Interval selector The subclock divided by 4 Watch counter Interrupt generator Watch timer interrupt 210 213 214 215 To the watchdog timer 56 MB90370/375 Series 6. 16-bit PPG timer (× 3) The 16-bit PPG (Programmable Pulse Generator) timer consists of a 16-bit down counter, prescaler, 16-bit period setting register, 16-bit duty setting register, 16-bit control register and a PPG output pin. Features of 16-bit PPG timer : • 8 types of counter operation clock (φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128) can be selected (φ is the machine clock) • An interrupt is generated when there is a trigger or a counter borrow or when PPG rising (normal polarity) / PPG falling (inverted polarity) . • PPG output operation The 16-bit PPG timer can output pulse waveforms with variable period and duty ratio. Also, it can be used as D/A converter in conjunction with an external circuit. (1) Register configuration of PPG timer PPG Down Counter Register (Upper) Address : ch1 000039H 15 14 13 12 11 10 9 8 ch2 000041H ch3 000049H DC15 DC14 DC13 DC12 DC11 DC10 DC09 DC08 Read/write Initial value R 1 R 1 R 1 R 1 R 1 R 1 R 1 R 1 Bit number PDCRH1 to PDCRH3 PPG Down Counter Register (Lower) Address : ch1 000038H 7 6 5 4 3 2 1 0 ch2 000040H ch3 000048H DC07 DC06 DC05 DC04 DC03 DC02 DC01 DC00 Read/write Initial value R 1 R 1 R 1 R 1 R 1 R 1 R 1 R 1 Bit number PDCRL1 to PDCRL3 PPG Period Setting Buffer Register (Upper) Address : ch1 00003BH 15 14 13 12 11 10 9 8 ch2 000043H ch3 00004BH CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08 Read/write Initial value W X W X W X W X W X W X W X W X Bit number PCSRH1 to PCSRH3 PPG Period Setting Buffer Register (Lower) Address : ch1 00003AH 7 6 5 4 3 2 1 0 ch2 000042H ch3 00004AH CS07 CS06 CS05 CS04 CS03 CS02 CS01 CS00 Read/write Initial value W X W X W X W X W X W X W X W X Bit number PCSRL1 to PCSRL3 (Continued) 57 MB90370/375 Series (Continued) PPG Duty Setting Buffer Register (Upper) Address : ch1 00003DH 15 14 13 12 11 10 9 8 ch2 000045H ch3 00004DH DU15 DU14 DU13 DU12 DU11 DU10 DU09 DU08 Read/write Initial value W X W X W X W X W X W X W X W X Bit number PDUTH1 to PDUTH3 PPG Duty Setting Buffer Register (Lower) Address : ch1 00003CH 7 6 5 4 3 2 1 0 ch2 000044H ch3 00004CH DU07 DU06 DU05 DU04 DU03 DU02 DU01 DU00 Read/write Initial value W X W X W X W X W X W X W X W X Bit number PDUTL1 to PDUTL3 PPG Control Status Register (Upper) Address : ch1 00003FH 15 14 13 12 11 10 9 8 ch2 000047H ch3 00004FH CNTE STGR MDSE RTRG CKS2 CKS1 CKS0 PGMS Read/write Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit number PCNTH1 to PCNTH3 PPG Control Status Register (Lower) Address : ch1 00003EH 7 ch2 000046H ch3 00004EH   Read/write Initial value     6 IREN R/W 0 5 IRQF R/W 0 4 IRS1 R/W 0 3 IRS0 R/W 0 2 POEN R/W 0 1 OSEL R/W 0 0 Bit number PCNTL1 to PCNTL3 Note : Registers PDCR1 to PDCR3, PCSR1 to PCSR3 and PDUT1 to PDUT3 are word access only. 58 MB90370/375 Series (2) Block diagram of PPG timer Period setting buffer register 1/2/3 Prescaler CKS2 CKS1 CKS0 Period setting register 1/2/3 Duty setting buffer register 1/2/3 Duty setting register 1/2/3 F2MC-16LX bus 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/128 Machine clock φ Down counter register 1/2/3 CLK LOAD Comparator 16-bit down counter STOP START BORROW MDSE PGMS OSEL POEN P77/PPG1 or PD6/PPG2 or PD7/PPG3 Pin S R Q Interrupt selection Interrupt #22 (for PPG1) or #27 (for PPG2/3) Gate input IRS1 IRS0 IRQF IREN STGR CNTE RTRG 59 MB90370/375 Series 7. 16-bit reload timer (× 4) The 16-bit reload timer provides two operating modes, internal clock mode and event count mode. In each operating mode, the 16-bit down counter can be reloaded (reload mode) or stopped when underflow (one-shot mode) . Output pins TO1 to TO4 are able to output different waveform according to the counter operating mode. TO1 to TO4 toggles when counter underflow if counter is operated as reload mode. TO1 to TO4 output specified level (“H” or “L”) when counter is counting if the counter is in one-shot mode. Features of the 16-bit reload timer : • Interrupt generated when timer underflow • EI2OS supported • Internal clock operating mode : Three internal count clocks can be selected. Counter can be activated by software or external trigger (signal at TIN1 to TIN4 pin) . Counter can be reloaded or stopped when underflow after activated. • Event count operating mode : Counter counts down by one when specified edge at TIN1 to TIN4 pin. Counter can be reloaded or stopped when underflow. (1) Register configuration of reload timer Timer Control Status Register (Upper) Address : ch1 000071H ch2 000075H 15 14 ch3 000079H   ch4 00007DH Read/write     Initial value Timer Control Status Register (Lower) Address : ch1 000070H ch2 000074H 7 6 ch3 000078H MOD0 OUTE ch4 00007CH Read/write R/W R/W 0 0 Initial value 13    12    11 CSL1 R/W 0 10 CSL0 R/W 0 9 MOD2 R/W 0 8 MOD1 R/W 0 Bit number TMCSRH1 to TMCSRH4 5 OUTL R/W 0 4 RELD R/W 0 3 INTE R/W 0 2 UF R/W 0 1 CNTE R/W 0 0 TRG R/W 0 Bit number TMCSRL1 to TMCSRL4 16-bit Timer Register / 16-bit Reload Register (Upper) Address : ch1 000073H ch2 000077H 15 14 13 12 ch3 00007BH D15 D14 D13 D12 ch4 00007FH Read/write R/W R/W R/W R/W Initial value X X X X 16-bit Timer Register / 16-bit Reload Register (Lower) Address : ch1 000072H ch2 000076H 7 6 5 4 ch3 00007AH D07 D06 D05 D04 ch4 00007EH Read/write R/W R/W R/W R/W Initial value X X X X 11 D11 R/W X 10 D10 R/W X 9 D09 R/W X 8 D08 R/W X Bit number TMR1 to TMR4/ TMRD1 to TMRD4 3 D03 R/W X 2 D02 R/W X 1 D01 R/W X 0 D00 R/W X Bit number TMR1 to TMR4/ TMRD1 to TMRD4 60 MB90370/375 Series (2) Block diagram of reload timer F2MC-16LX Bus TMRD1*1 16-bit reload register Reload signal 16-bit timer register Count clock generation circuit Machine clock 3 CLK Gate input TMR1*1 Reload control circuit Prescaler Valid clock judgment circuit CLK Wait signal To UART1*1 Output control circuit Clear PE0/TIN1/SEG0 PE2/TIN2/SEG2 PE4/TIN3/SEG4 PE6/TIN4/SEG6 Pin Input control circuit Internal clock External clock Clock selector Output signal generation Invert circuit EN Pin PE1/TO1/SEG1 PE3/TO2/SEG3 PE5/TO3/SEG5 PE7/TO4/SEG7 Operation control circuit 3 Function selection 2 Select signal     CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG Timer control status register TMCSR1*1 Interrupt request signal #32 (20H)*1, *2 *1 : This register includes channel 1, 2, 3 and 4. The register enclosed in “” indicates the channel 2, 3 and 4 register. *2 : Interrupt numbers : channel 1 and 2 share one interrupt number, channel 3 and 4 share another. 61 MB90370/375 Series 8. I2C The I2C (Inter IC Bus) interface is a simple structure bidirectional bus consisting of two wires : a serial data line (SDA) and a serial clock line (SCL) . Among the devices connected with these two wires, information is transmitted to one another. By recognizing the unique address of each device, it can operate as a transmitting or receiving device in accordance with the function of each device. Among these devices, the master/slave relation is established. The I2C interface can connect two or more devices to the bus provided the upper limit of the bus capacitance does not exceed 400 pF. It is a full-fledged multi-master bus equipped with collision detection and communication adjustment procedures designed to avoid the destruction of data if two or more masters attempt to start data transfer simultaneously. The communication adjustment procedure permits only one master to control the bus when two or more masters attempt to control the bus so that messages are not lost or the contents of messages are not changed. Multimaster means that multiple masters attempt to control the bus simultaneously without losing messages. This I2C interface includes MCU standby mode wake-up function, and a CRC-8 calculator that performs automatic Packet Error Code (PEC) generation and verification. (1) Register configuration of I2C I2C Bus Control Register (Lower) 7 6    5    4    3 RES R/W 0 2 PECE R/W 0 1 LBT R/W 0 0 WUE R/W 0 Address : 000080H Read/write Initial value    Bit number IBCRL I2C Bus Control Register (Upper) 15 14 BEIE R/W 0 13 SCC R/W 0 12 MSS R/W 0 11 ACK R/W 0 10 GCAA R/W 0 9 INTE R/W 0 8 INT R/W 0 Address : 000081H Read/write Initial value BER R/W 0 Bit number IBCRH I2C Bus Status Register (Lower) 7 6 RSC R 0 5 AL R 0 4 LRB R 0 3 TRX R 0 2 AAS R 0 1 GCA R 0 0 FBT R 0 Address : 000082H Read/write Initial value BB R 0 Bit number IBSRL I2C Bus Status Register (Upper) 15 14    13 PMATCH 12 WUF R/W 0 11 TDR R/W 0 10 TCR R/W 0 9 MTR R/W 0 8 STR R/W 0 Address : 000083H Read/write Initial value I2C Data Register    Bit number IBSRH R 0 7 6 D6 R/W X 5 D5 R/W X 4 D4 R/W X 3 D3 R/W X 2 D2 R/W X 1 D1 R/W X 0 D0 R/W X Address : 000084H Read/write Initial value D7 R/W X Bit number IDAR (Continued) 62 MB90370/375 Series (Continued) I2C Address Register 15 14 A6 R/W X 13 A5 R/W X 12 A4 R/W X 11 A3 R/W X 10 A2 R/W X 9 A1 R/W X 8 A0 R/W X Address : 000085H Read/write Initial value I2C Clock Control Register    Bit number IADR 7 6    5 EN R/W 0 4 CS4 R/W 0 3 CS3 R/W 0 2 CS2 R/W 0 1 CS1 R/W 0 0 CS0 R/W 0 Address : 000086H Read/write Initial value DMBP R/W 0 Bit number ICCR I2C Timeout Control Register 15 14 AAC R/W 0 13    12 TOE R/W 0 11 EXT R/W 0 10 TS2 R/W 0 9 TS1 R/W 0 8 TS0 R/W 0 Address : 000087H Read/write Initial value I2C Timeout Clock Register    Bit number ITCR 7 6 C6 R/W 0 5 C5 R/W 0 4 C4 R/W 0 3 C3 R/W 0 2 C2 R/W 0 1 C1 R/W 0 0 C0 R/W 0 Address : 000088H Read/write Initial value I2C Timeout Data Register C7 R/W 0 Bit number ITOC 15 14 D6 R/W 0 13 D5 R/W 0 12 D4 R/W 0 11 D3 R/W 0 10 D2 R/W 0 9 D1 R/W 0 8 D0 R/W 0 Address : 000089H Read/write Initial value D7 R/W 0 Bit number ITOD I2C Slave Timeout Register 7 6 S6 R/W 0 5 S5 R/W 0 4 S4 R/W 0 3 S3 R/W 0 2 S2 R/W 0 1 S1 R/W 0 0 S0 R/W 0 Address : 00008AH Read/write Initial value S6 R/W 0 Bit number ISTO I2C Master Timeout Register 15 14 M6 R/W 0 13 M5 R/W 0 12 M4 R/W 0 11 M3 R/W 0 10 M2 R/W 0 9 M1 R/W 0 8 M0 R/W 0 Address : 00008BH Read/write Initial value M7 R/W 0 Bit number IMTO 63 MB90370/375 Series (2) Block diagram of I2C I2C enable ICCR DMBP EN CS4 CS3 CS2 CS1 CS0 IBSRL BB RSC LRB TRX FBT AL F2MC16LX Internal bus IBCRH BER BEIE Interrupt #26 INTE INT SCC MSS ACK GCAA IBCRL LBT IBSRL AAS GCA Slave General call IADR register Slave address comparator CRC-8 calculator End Start Master Enables ACK Enables GC-ACK Start/stop condition generator First byte Arbitration lost detector Bus busy Repeat start Last bit Transmission/ reception Start/stop condition detector Error 4 8 Clock frequency divider 2 16 32 64 128 256 512 Sync Shift clock generator Clock selector 1 Clock frequency divider 1 5 6 7 8 Peripheral clock Clock selector 2 Shift clock edge IDAR register ITCR IBSRH TDR ITOD TCR MTR STR Timeout detector SCL line SDA line IBCRL ITOC ISTO IMTO IBSRH WUE WUF Interrupt #31 64 MB90370/375 Series 9. MI2C The Multi-address I2C (Inter IC Bus) interface is a simple structure bidirectional bus consisting of two wires : a serial data line (SDA) and a serial clock line (SCL) . Among the devices connected with these two wires, information is transmitted to one another. By recognizing the unique address of each device, it can operate as a transmitting or receiving device in accordance with the function of each device. Among these devices, the master/slave relation is established. The Multi-address I2C interface can connect two or more devices to the bus provided the upper limit of the bus capacitance does not exceed 400 pF. It is a full-fledged multi-master bus equipped with collision detection and communication adjustment procedures designed to avoid the destruction of data if two or more masters attempt to start data transfer simultaneously. This macro provides 6 addresses to implement the multi-address function. The communication adjustment procedure permits only one master to control the bus when two or more masters attempt to control the bus so that messages are not lost or the contents of messages are not changed. Multimaster means that multiple masters attempt to control the bus simultaneously without losing messages. This Multi-address I2C interface includes MCU standby mode wake-up function, and a CRC-8 calculator that performs automatic Packet Error Code (PEC) generation and verification. (1) Register configuration of MI2C Multi-address I2C Bus Control Register (Lower) 7 6    5    4    3 RES R/W 0 2 PECE R/W 0 1 LBT R/W 0 0 WUE R/W 0 Address : 0000C0H Read/write Initial value    Bit number MBCRL Multi-address I2C Bus Control Register (Upper) 15 14 BEIE R/W 0 13 SCC R/W 0 12 MSS R/W 0 11 ACK R/W 0 10 GCAA R/W 0 9 INTE R/W 0 8 INT R/W 0 Address : 0000C1H Read/write Initial value BER R/W 0 Bit number MBCRH Multi-address I2C Bus Status Register (Lower) 7 6 RSC R 0 5 AL R 0 4 LRB R 0 3 TRX R 0 2 AAS R 0 1 GCA R 0 0 FBT R 0 Address : 0000C2H Read/write Initial value BB R 0 Bit number MBSRL Multi-address I2C Bus Status Register (Upper) 15 14    13 PMATCH 12 WUF R/W 0 11 TDR R/W 0 10 TCR R/W 0 9 MTR R/W 0 8 STR R/W 0 Address : 0000C3H Read/write Initial value    Bit number MBSRH R 0 Multi-address I2C Data Register 7 6 D6 R/W X 5 D5 R/W X 4 D4 R/W X 3 D3 R/W X 2 D2 R/W X 1 D1 R/W X 0 D0 R/W X Address : 0000C4H Read/write Initial value D7 R/W X Bit number MDAR (Continued) 65 MB90370/375 Series Multi-address I2C Alert Register 15 14    13    12    11 ARAE R/W 0 10 ARO R/W 0 9 ARF R/W 0 8 AEN R/W 0 Address : 0000C5H Read/write Initial value    Bit number MALR Multi-address I2C Address Register 1/3/5 Address ch1 : 0000C6H 7 6 5 Address ch3 : 0000C8H Address ch5 : 0000CAH A6  A5 4 A4 A3 3 A2 2 A1 1 A0 0 Bit number MADR1/3/5 Read/write R/W R/W R/W R/W R/W R/W R/W  X X X X X X X  Initial value 2C Address Register 2/4/6 Multi-address I Address ch2 : 0000C7H 15 14 13 12 11 10 9 8 Address ch4 : 0000C9H Address ch6 : 0000CBH  A5 A4 A3 A2 A1 A0 A6 Read/write  R/W  X Initial value 2C Clock Control Register Multi-address I 7 6    R/W X R/W X R/W X R/W X R/W X R/W X Bit number MADR2/4/6 5 EN R/W 0 4 CS4 R/W 0 3 CS3 R/W 0 2 CS2 R/W 0 1 CS1 R/W 0 0 CS0 R/W 0 Address :0000CCH Read/write Initial value DMBP R/W 0 Bit number MCCR Multi-address I2C Timeout Control Register 15 14 AAC R/W 0 13    12 TOE R/W 0 11 EXT R/W 0 10 TS2 R/W 0 9 TS1 R/W 0 8 TS0 R/W 0 Address :0000CDH Read/write Initial value    Bit number MTCR Multi-address I2C Timeout Clock Register 7 6 C6 R/W 0 5 C5 R/W 0 4 C4 R/W 0 3 C3 R/W 0 2 C2 R/W 0 1 C1 R/W 0 0 C0 R/W 0 Address : 0000CEH Read/write Initial value C7 R/W 0 Bit number MTOC Multi-address I2C Timeout Data Register 15 14 D6 R/W 0 13 D5 R/W 0 12 D4 R/W 0 11 D3 R/W 0 10 D2 R/W 0 9 D1 R/W 0 8 D0 R/W 0 Address : 0000CFH Read/write Initial value D7 R/W 0 Bit number MTOD (Continued) 66 MB90370/375 Series (Continued) Multi-address I2C Slave Timeout Register 7 6 S6 R/W 0 5 S5 R/W 0 4 S4 R/W 0 3 S3 R/W 0 2 S2 R/W 0 1 S1 R/W 0 0 S0 R/W 0 Address : 0000D0H Read/write Initial value S6 R/W 0 Bit number MSTO Multi-address I2C Master Timeout Register 15 14 M6 R/W 0 13 M5 R/W 0 12 M4 R/W 0 11 M3 R/W 0 10 M2 R/W 0 9 M1 R/W 0 8 M0 R/W 0 Address : 0000D1H Read/write Initial value M7 R/W 0 Bit number MMTO 67 MB90370/375 Series (2) Block diagram of MI2C Multi-address I2C enable MCCR DMBP EN CS4 CS3 CS2 CS1 CS0 MBSRL BB RSC LRB TRX FBT AL F2MC16LX Internal bus MBCRH BER BEIE Interrupt #29 INTE INT SCC MSS ACK GCAA MBCRL LBT MDAR register MBSRL AAS GCA Slave General call MADR1~6 registers MTCR MBSRH TDR TCR MTR STR MTOD MALR ARAE ARO ARF AEN MBSRH MBCRL ALERT line WUE WUF Interrupt #33 MMTO MTOC MSTO SDA line Slave address comparator CRC-8 calculator End Start Master Enables ACK Enables GC-ACK Start/stop condition generator First byte Arbitration lost detector Bus busy Repeat start Last bit Transmission/ reception Start/stop condition detector Error 4 8 Clock frequency divider 2 16 32 64 128 256 512 Sync Shift clock generator Clock selector 1 Clock frequency divider 1 5 6 7 8 Peripheral clock Clock selector 2 Shift clock edge Timeout detector SCL line 68 MB90370/375 Series 10. Bridge circuit The bridge circuit can switch the I/O path of each port to I2C or Multi-address I2C. (1) Register configuration of bridge circuit Bridge Circuit Selection Register 7 6    5 BM4 R/W 0 4 BI4 R/W 0 3 BM3 R/W 0 2 BI3 R/W 0 1 BM2 R/W 0 0 BI2 R/W 0 Address : 00002CH Read/write Initial value    Bit number BRSR (2) Block diagram of bridge circuit I2C I/O Multi-address I2C BRSR P91/SDA2 P90/SCL2 BM2 P93/SDA3 P92/SCL3 BM3 P95/SDA4 P94/SCL4 BM4 P81/SDA1 P80/SCL1 I2 C BI2 BI3 BI4 69 MB90370/375 Series 11. Comparator This comparator circuit monitors voltage of up to three batteries and automatically controls electric discharge. Either parallel discharge or sequential discharge can be selected. • Parallel discharge control In parallel discharge control, all batteries are allowed to discharge when power is not being supplied from the AC adapter. • If power is being supplied from the AC adapter, the permission/prohibition of discharge for batteries is controlled by software. • Sequential discharge control In sequential discharge control, the comparator controls discharge in a specified order, while monitoring intermittent interruption of power, voltage level, and mount/dismount of batteries, when power is not being supplied from the AC adapter. • If power is being supplied from the AC adapter, the permission/prohibition of discharge for batteries is controlled by software. • Up to three batteries can be controlled, and the order of discharge can be selected. • The affect of intermittent interruption of power is automatically filtered. • Mount/dismount of batteries is automatically detected and discharge is controlled. • Battery voltage is monitored, and if battery voltage is below the specified voltage, a change over to the next battery is automatically done. 70 MB90370/375 Series (1) Register configuration of comparator Comparator Control Register (Lower) 7 6    5 BOF3 R/W 0 4 BOF2 R/W 0 3 BOF1 R/W 0 2 SPM2 R/W 0 1 SPM1 R/W 0 0 SPM0 R/W 0 Address : 0000D8H Read/write Initial value    Bit number COCRL Comparator Control Register (Upper) 15 14 SPL2 R/W 0 13 SPL1 R/W 1 12 B3 R/W 1 11 B2 R/W 1 10 B1 R/W 1 9 DC2 R/W 1 8 DC1 R/W 1 Address : 0000D9H Read/write Initial value SPL3 R/W 0 Bit number COCRH Comparator Status Register 1 (Lower) 7 6 COR7 R/W 0 5 COR6 R/W 0 4 COR5 R/W 0 3 COR4 R/W 0 2 COR3 R/W 0 1 COR2 R/W 0 0 COR1 R/W 0 Address : 0000DAH Read/write Initial value COR8 R/W 0 Bit number COSRL1 Comparator Status Register 1 (Upper) 15 14    13 SWR3 R/W 0 12 SWR2 R/W 0 11 SWR1 R/W 0 10 VAR3 R/W 0 9 VAR2 R/W 0 8 VAR1 R/W 0 Address : 0000DBH Read/write Initial value    Bit number COSRH1 Comparator Interrupt Control Register (Lower) 7 6 CEN7 R/W 0 5 CEN6 R/W 0 4 CEN5 R/W 0 3 CEN4 R/W 0 2 CEN3 R/W 0 1 CEN2 R/W 0 0 CEN1 R/W 0 Address :0000DCH Read/write Initial value CEN8 R/W 0 Bit number CICRL (Continued) 71 MB90370/375 Series (Continued) Comparator Interrupt Control Register (Upper) 15 14    13 SEN3 R/W 0 12 SEN2 R/W 0 11 SEN1 R/W 0 10 VEN3 R/W 0 9 VEN2 R/W 0 8 VEN1 R/W 0 Address :0000DDH Read/write Initial value    Bit number CICRH Comparator Status Register 2 (Lower) 7 6 COS7 R X 5 COS6 R X 4 COS5 R X 3 COS4 R X 2 COS3 R X 1 COS2 R X 0 COS1 R X Address : 0000DEH Read/write Initial value COS8 R X Bit number COSRL2 Comparator Status Register 2 (Upper) 15 14    13 SWS3 R X 12 SWS2 R X 11 SWS1 R X 10 VAL3 R X 9 VAL2 R X 8 VAL1 R X Address : 0000DFH Read/write Initial value    Bit number COSRH2 Comparator Input Enable Register 7 6    5    4 BIE3 R/W 1 3 BIE2 R/W 1 2 BIE1 R/W 1 1 DIE2 R/W 1 0 DIE1 R/W 1 Address : 0000E0H Read/write Initial value    Bit number CIER 72 MB90370/375 Series (2) Block diagram of comparator Pin PB0/DCIN Pin CVRH2 Pin CVRL Pin PB1/DCIN2 Pin CVRH1 Pin PB4/VOL2 Pin PB5/VSI2 Pin PC1/AN1/SW2 IN OUT RH (Voltage RL comparator 5) IN OUT RH (Voltage RL comparator 6) − + Comparator 2 Pin PB6/VOL3 Pin PB7/VSI3 Pin PC2/AN2/SW3 IN OUT RH (Voltage RL comparator 7) IN OUT RH (Voltage RL comparator 8) + − VOL SPL VALID Battery VSI supervisory circuit 3 ALARM SW OFB O13 VOL SPL VALID O12 + − Comparator 1 IN OUT RH RL (Voltage comparator 2) Battery selection circuit SW Pin PA3/ACO SW Pin PA4/OFB1 Battery VSI supervisory circuit 2 ALARM SW OFB SW Pin PA1/ALR2 SW Pin PA2/ALR3 Comparator 3 Pin PB2/VOL1 Pin PB3/VSI1 Pin PC0/AN0/SW1 Pin XOA Pin X1A Pin VCC Pin RST IN OUT RH (Voltage RL comparator 3) IN OUT RH (Voltage RL comparator 4) + − VOL SPL VALID O21 O23 Battery VSI supervisory circuit 1 ALARM SW OFB SW Pin PA5/OFB2 Pin PA0/ALR1 SW Comparator 4 Watch prescaler O31 Power-on reset O32 SW Pin PA6/OFB3 3 8 3 SPL3 SPL2 SPL1 B3 B2 B1 DC2 DC1 3 3 6 COS8 COS7 COS6 COS5 COS4 COS3 COS2 COS1 (COCRH) Comparator control register (upper) (COSRL2) Comparator status register 2 (lower) SWR3 SWR2 SWR1 VAR3 VAR2 VAR1 COR8 COR7 COR6 COR5 COR4 COR3 COR2 COR1 (COSRH1) Comparator status register 1 (upper) interrupt request #30 (CICRH) Comparator interrupt control register (upper) SEN3 SEN2 SEN1 VEN3 VEN2 VEN1 Decoder interrupt request #28 (COSRL1) Comparator status register 1 (lower) (CICRL) Comparator interrupt control register (lower) CEN8 CEN7 CEN6 CEN5 CEN4 CEN3 CEN2 CEN1 SWS3 SWS2 SWS1 VAL3 VAL2 VAL1 (COSRH2) Comparator status register 2 (upper) BOF3 BOF2 BOF1 SPM2 SPM1 SPM0 (COCRL) Comparator control register (lower) Internal data bus 73 MB90370/375 Series 12. UART (× 3) The UART (Universal Asychronous Receiver Transmitter) is a serial I/O port for asynchronous (start-stop) communication or clock-synchronous communication. The UART has the following features : • Full-duplex double buffering • Capable of asynchronous (start-stop bit) and CLK-synchronous communications • Support for the multiprocessor mode • Various method of baud rate generation : - External clock input possible - Internal clock (a clock supplied from 16-bit reload timer can be used) - Embedded dedicated baud rate generator Operation Baud rate Asynchronous CLK synchronous 76923 / 38461 / 19230 / 9615 / 500K / 250K bps 16M / 8M / 4M / 2M / 1M / 500K bps • Error detection functions (parity, framing, overrun) • NRZ (Non Return to Zero) signal format • Interrupt request : - Receive interrupt (receive complete, receive error detection) - Transmit interrupt (transmission complete) - Transmit / receive conforms to extended intelligent I/O service (EI2OS) 74 MB90370/375 Series (1) Register configuration of UART Serial Mode Register Address : ch1 000020H ch2 0000D2H ch3 0000E4H Read/write Initial value Serial Control Register Address : ch1 000021H ch2 0000D3H ch3 0000E5H Read/write Initial value 7 MD1 R/W 0 MD0 R/W 0 6 CS2 R/W 0 5 CS1 R/W 0 4 CS0 R/W 0 3    2 SCKE R/W 0 1 SOE R/W 0 0 Bit number SMR1/2/3 15 PEN R/W 0 P R/W 0 14 SBL R/W 0 13 CL R/W 0 12 A/D R/W 0 11 REC W 1 10 RXE R/W 0 9 TXE R/W 0 8 Bit number SCR1/2/3 UART Input Data Register / Output Data Register Address : ch1 000022H 7 6 5 4 3 2 1 0 ch2 0000D4H ch3 0000E6H D7 D5 D4 D3 D2 D1 D0 D6 Read/write Initial value UART Status Register Address : ch1 000023H ch2 0000D5H ch3 0000E7H Read/write Initial value R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X Bit number SIDR1/2/3 SODR1/2/3 15 PE R 0 ORE R 0 14 FRE R 0 13 RDRF R 0 12 TFRE R 1 11 BDS R/W 0 10 RIE R/W 0 9 TIE R/W 0 8 Bit number SSR1/2/3 Clock Division Control Register Address : ch1 000025H 15 14 13 12 11 10 9 8 ch2 0000D7H ch3 0000E9H MD   DIV3 DIV2 DIV1 DIV0  Read/write R/W   R/W R/W R/W R/W  0   0 0 0 0  Initial value Mode 2 Control Register Address : ch1 000024H ch2 0000D6H ch3 0000E8H Read/write Initial value Bit number CDCR1/2/3 7       6    5    4 SCKL R/W 1 3 M2L2 R/W 0 2 M2L1 R/W 0 1 M2L0 R/W 0 0 Bit number M2CR1/2/3 75 MB90370/375 Series (2) Block diagram of UART From communication prescaler Baud rate generator Clock selection circuit Transmission clock Reception clock Reception control circuit Start bit detection circuit Reception bit counter Reception parity counter 16-bit reload timer 1/2/3 P66/UCK1 External clock P70/UI1 Reception interrupt #35 (23H)* Transmission interrupt #36 (24H)* Transmission control circuit Start of transmission Control bus SCKL M2L2 M2L1 M2L0 Transmission start circuit Transmission bit counter Transmission parity counter P67/UO1 Reception status judgement circuit Reception shifter End of reception Transmission shifter SIDR1/2/3 EI2OS reception error signal (to CPU) SODR1/2/3 F2MC-16LX bus SMR1/2/3 registers MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR1/2/3 registers PEN P SBL CL A/D REC RXE TXE SSR1/2/3 registers PE ORE FRE RDRF TDRE BDS RIE TIE M2CR1/2/3 registers Control signal * : Interrupt number 76 MB90370/375 Series 13. LCD controller/driver (not for MB90F377) The LCD (Liquid Crystal Display) controller/driver function displays the contents of a display data memory directly to the LCD panel by segment and common outputs. • Up to nine segment outputs (SEG0 to SEG8) and four common outputs (COM0 to COM3) may be used. • Built-in display RAM. • Three selectable duty ratios (1/2, 1/3, and 1/4) . However, not all duty ratios are available with all bias settings. • Either the main or sub-clock can be selected as the drive clock. • LCD can be driven directly. Table below shows the duty ratios available with each bias setting. Part number Bias 1/2 duty ratio MB90370 series : Recommended mode X : Do not use (1) Register configuration of LCD LCDC Control Register (Upper) 15 14 VS R/W 0 13 CS1 R/W 0 12 CS0 R/W 0 11 SS3 R/W 0 10 SS2 R/W 0 9 SS1 R/W 0 8 SS0 R/W 0 1/3 duty ratio X 1/4 duty ratio X 1/2 bias 1/3 bias X Address : 0000EFH Read/write Initial value SS4 R/W 0 Bit number LCRH LCDC Control Register (Lower) Address : 0000EEH Read/write Initial value 7 CSS R/W 0 6 LCEN R/W 0 5 VSEL R/W 0 4 BK R/W 1 3 MS1 R/W 0 2 MS0 R/W 0 1 FP1 R/W 0 0 FP0 R/W 0 Bit number LCRL 77 MB90370/375 Series (2) Block diagram of LCD LCDC supply voltage (V1 to V3) LCDC control register (LCR) HCLK / 28 Prescaler Internal bus Sub-clock (32 kHz) Timing controller 4 4 Common output driver COM0 COM1 COM2 COM3 V/I converter 9 Display RAM 9 x 4 bit Controller Driver 78 Segment output driver SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 MB90370/375 Series 14. A/D converter The A/D (Analog to Digital) converter converts the analog voltage input to an analog input pin (input voltage) to a digital value. The converter has the following features : • The minimum conversion time is 6.13 µs (for a machine clock of 16 MHz; includes the sampling time) . • The minimum sampling time is 3.75 µs (for a machine clock of 16 MHz) . • The converter uses the RC-type successive approximation conversion method with a sample and hold circuit. • A resolution of 10 bits or 8 bits can be selected. • Up to twelve channels for analog input pins can be selected by a program. • Various conversion modes : - Single conversion mode : Selectively convert one channel. - Scan conversion mode : Continuously convert multiple channels. Maximum of 12 selectable channels. - Continuous conversion mode : Repeatedly convert specified channels. - Stop conversion mode : Convert one channel then halt until the next activation. (Enables synchronization of the conversion start timing.) • At the end of A/D conversion, an interrupt request can be generated and EI²OS can be activated. • In the interrupt-enabled state, the conversion data protection function prevents any part of the data from being lost through continuous conversion. • The conversion can be activated by software, 16-bit reload timer 4 (rise edge) and ADTG. (1) Register configuration of A/D converter Analog Input Enable Register 2 15 14    13    12    11 ADE11 R/W 1 10 ADE10 R/W 1 9 ADE9 R/W 1 8 ADE8 R/W 1 Address : 00002BH Read/write Initial value Analog Input Enable Register 1    Bit number ADER2 7 6 ADE6 R/W 1 5 ADE5 R/W 1 4 ADE4 R/W 1 3 ADE3 R/W 1 2 ADE2 R/W 1 1 ADE1 R/W 1 0 ADE0 R/W 1 Address : 00002AH Read/write Initial value A/D Control Status Register 1 ADE7 R/W 1 Bit number ADER1 15 14 INT R/W 0 13 INTE R/W 0 12 PAUS R/W 0 11 STS1 R/W 0 10 STS0 R/W 0 9 STRT W 0 8 RESV R/W 0 Address : 000031H Read/write Initial value A/D Control Status Register 0 BUSY R/W 0 Bit number ADCS1 7 6 MD0 R/W 0 5    4    3    2    1    0    Address : 000030H Read/write Initial value MD1 R/W 0 Bit number ADCS0 (Continued) 79 MB90370/375 Series (Continued) A/D Control Register 15 14 ANS2 R/W 0 13 ANS1 R/W 0 12 ANS0 R/W 0 11 ANE3 R/W 0 10 ANE2 R/W 0 9 ANE1 R/W 0 8 ANE0 R/W 0 Address : 00002DH Read/write Initial value A/D Data Register (Upper) ANS3 R/W 0 Bit number ADC0 15 14 ST1 W 0 13 ST0 W 0 12 CT1 W 0 11 CT0 W 0 10    9 D9 R X 8 D8 R X Address : 00002FH Read/write Initial value A/D Data Register (Lower) S10 R/W 0 Bit number ADCR1 7 6 D6 R X 5 D5 R X 4 D4 R X 3 D3 R X 2 D2 R X 1 D1 R X 0 D0 R X Address : 00002EH Read/write Initial value D7 R X Bit number ADCR0 (2) Block diagram of A/D converter AVCC AVR AVSS MP AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 D/A converter Input circuit Sequential comparison register Comparator F2MC-16LX bus Data register ADCR0/1 ADCS0/1 Operation clock Prescalar Sample and holding circuit Decoder A/D control register A/D control status register 0 A/D control status register 1 16-bit reload timer 4 P37/ADTG φ φ : Machine clock 80 MB90370/375 Series 15. D/A converter The D/A (Digital to Analog) converter is used to generate an analog output from an 8-bit digital input. By setting the enable bit in the D/A control register (DACR) to 1, it will enable the corresponding D/A output channel. Hence, setting this bit to 0 will disable that channel. If D/A output is disabled, the analog switch inserted to the output of each D/A converter channel in series is turned off. In the D/A converter, the bit is cleared to 0 and the direct-current path is shut off. The above is also true in the stop mode. The output voltage of the D/A converter ranges from 0 V to 255/256 x AVCC. The D/A converter output does not have the internal buffer amplifier. The analog switch ( = 100 Ω) is inserted to the output in series. To apply load to the output externally, estimate a sufficient stabilization time. Table below lists the theoretical values of output voltage of the D/A converter. Value written to DA07 to DA00 and DA17 to DA10 Theoretical value of output voltage 00H 01H 02H : FDH FEH FFH 0/256 × AVCC ( = 0 V) 1/256 × AVCC 2/256 × AVCC : 253/256 × AVCC 254/256 × AVCC 255/256 × AVCC 81 MB90370/375 Series (1) Register configuration of D/A converter D/A converter register 1 15 14 DA16 R/W X 13 DA15 R/W X 12 DA14 R/W X 11 DA13 R/W X 10 DA12 R/W X 9 DA11 R/W X 8 DA10 R/W X Address : 00005BH Read/write Initial value D/A converter register 0 DA17 R/W X Bit number DAT1 7 6 DA06 R/W X 5 DA05 R/W X 4 DA04 R/W X 3 DA03 R/W X 2 DA02 R/W X 1 DA01 R/W X 0 DA00 R/W X Address : 00005AH Read/write Initial value D/A control register 1 DA07 R/W X Bit number DAT0 15 14    13    12    11    10    9    8 DAE1 R/W 0 Address : 00005DH Read/write Initial value D/A control register 0    Bit number DACR1 7 6    5    4    3    2    1    0 DAE0 R/W 0 Address : 00005CH Read/write Initial value    Bit number DACR0 82 MB90370/375 Series (2) Block diagram of D/A converter F2MC-16LX BUS DA DA DA DA DA DA DA DA 17 16 15 14 13 12 11 10 DA DA DA DA DA DA DA DA 07 06 05 04 03 02 01 00 AVCC DA17 2R R DA16 2R R DA15 DA05 DA06 DA07 AVCC 2R R 2R R DA11 2R R DA10 2R 2R DAE1 Standby control DA01 2R R DA00 2R 2R DAE0 Standby control DA output ch.1 DA output ch.0 83 MB90370/375 Series 16. LPC interface The LPC (Low Pin Count) interface consists of an LPC bus interface, universal parallel interface (UPI × 4 channels) , gate address A20 function and LPC data buffer array. By using the LPC bus interface and UPI, data can be exchanged with an external host CPU synchronously via an external LPC bus. • LPC bus interface The LPC bus interface provides direct access of host CPU to UPI. • It supports I/O read and I/O write cycle only. Other cycle types will be ignored. • It supports LPC clock running at 33 MHz. • Universal parallel interface, UPI × 4 channels The UPI is used to exchange parallel data to serial data in LPC bus with host CPU. • An 8-bit data will be transmitted or received. • A buffer function is available for independent input and output. • The I/O buffer status can be output externally through LPC bus interface. • Gate address A20 function for UPI channel 0 The GA20 (Gate Address A20) is intended to implement the memory management in a PC architecture. This allows the access to the extended memory needed by the operating system. On-chip logic is provided to speed up the generation of GA20. • Data buffer array The data buffer array is consisted of 32 bytes UP data register and 16 bytes DOWN data register to speed up the data transfer between MCU and external host through LPC bus. (1) Register configuration of LPC bus interface register LPC Control Register 7 6    5    4    3    2 LRF R/W 0 1 LRIE R/W 0 0 LPE R/W 0 Address : 00006EH Read/write Initial value    Bit number LCR 84 MB90370/375 Series (2) Register configuration of UPI registers UPI Address Register (Upper) Address : ch1 00005FH 15 14 13 12 11 10 9 8 ch2 000061H ch3 000063H UPA15 UPA14 UPA13 UPA12 UPA11 UPA10 UPA09 UPA08 Read/write R/W R/W R/W R/W R/W R/W R/W R/W X X X X X X X X Initial value UPI Address Register (Lower) Address : ch1 00005EH 7 6 5 4 3 2 1 0 ch2 000060H ch3 000062H UPA07 UPA06 UPA05 UPA04 UPA03 UPA02 UPA01 UPA00 Read/write R/W X Initial value UPI Control Register (Upper) 15 R/W X R/W X R/W X R/W X R/W X R/W X R/W X Bit number UPAH1 to UPAH3 Bit number UPAL1 to UPAL3 14 UPE3 R/W 0 13 IBFE3 R/W 0 12 OBEE3 R/W 0 11    10 UPE2 R/W 0 9 IBFE2 R/W 0 8 OBEE2 R/W 0 Address : 000065H Read/write Initial value UPI Control Register (Lower)    Bit number UPCH 7 6 UPE1 R/W 0 5 IBFE1 R/W 0 4 3 2 UPE0 R/W 0 1 IBFE0 R/W 0 0 OBEE0 R/W 0 Address : 000064H Read/write Initial value DBAE R/W 0 OBEE1 GA20E R/W 0 R/W 0 Bit number UPCL UPI Status Register Address : ch0 000067H 15 14 13 12 11 10 9 8 ch1 000069H ch2 00006BH UF4 UF3 UF2 UF1 A2 UF0 IBF OBF ch3 00006DH Read/write R/W R/W R/W R/W R R/W R R 0 0 0 0 0 0 0 0 Initial value UPI Data Input Register / Data Output Register Address : ch0 000066H 7 6 5 4 3 2 1 0 ch1 000068H ch2 00006AH UPD7 UPD6 UPD5 UPD4 UPD3 UPD2 UPD1 UPD0 ch3 00006CH Read/write R/W R/W R/W R/W R/W R/W R/W R/W X X X X X X X X Initial value Bit number UPS0 to UPS3 Bit number UPDI0 to UPDI3/ UPDO0 to UPDO3 85 MB90370/375 Series (3) Register configuration of LPC data buffer registers Data Buffer Array Address Register (Upper) 15 14 DA14 R/W X 13 DA13 R/W X 12 DA12 R/W X 11 DA11 R/W X 10 DA10 R/W X 9 DA09 R/W X 8 DA08 R/W X Address : 003FF1H Read/write Initial value DA15 R/W X Bit number DBAAH Data Buffer Array Address Register (Lower) 7 6 DA06 R/W X 5 DA05 R/W X 4 DA04 R/W X 3 DA03 R/W X 2 DA02 R/W X 1 DA01 R/W X 0 DA00 R/W X Address : 003FF0H Read/write Initial value UP Data Register (upper) Address : ch0 003FC1H ch1 003FC3H to chF 003FDFH DA07 R/W X Bit number DBAAL 15 UP15 R/W UP14 R/W 14 UP13 R/W 13 UP12 R/W 12 UP11 R/W 11 UP10 R/W 10 UP09 R/W 9 UP08 R/W 8 Bit number UDRH0 to UDRHF Read/write X X X X X X X X Initial value UP Data Register (lower) Address : ch0 003FC0H 7 6 5 4 3 2 1 0 ch1 003FC2H to UP07 UP05 UP04 UP03 UP02 UP01 UP00 UP06 chF 003FDEH Read/write R/W R/W R/W R/W R/W R/W R/W R/W X X X X X X X X Initial value DOWN Data Register (upper) Address : ch0 003FE1H 15 14 13 12 11 10 9 8 ch1 003FE3H to DN15 DN14 DN13 DN12 DN11 DN10 DN09 DN08 ch7 003FEFH Read/write R R R R R R R R X X X X X X X X Initial value DOWN Data Register (lower) Address : ch0 003FE0H 7 6 5 4 3 2 1 0 ch1 003FE2H to DN07 DN06 DN05 DN04 DN03 DN02 DN01 DN00 ch7 003FEEH Read/write R R R R R R R R X X X X X X X X Initial value Bit number UDRL0 to UDRLF Bit number DNDH0 to DNDH7 Bit number DNDL0 to DNDL7 (Continued) 86 MB90370/375 Series (Continued) Index Register 7 6    5 IX05 R/W 0 4 IX04 R/W 0 3 IX03 R/W 0 2 IX02 R/W 0 1 IX01 R/W 0 0 IX00 R/W 0 Address :     Bit number IXR Read/write Initial value Data Port Register 7 6 DP06 R/W X 5 DP05 R/W X 4 DP04 R/W X 3 DP03 R/W X 2 DP02 R/W X 1 DP01 R/W X 0 DP00 R/W X Address :  DP07 R/W X Bit number DPR Read/write Initial value (4) Block diagram of LPC interface Address comparator UPI address register, UPAH1 to UPAH3, UPAL1 to UPAL3 Data buffer array address register, DBAA UPE LPC/RW DBAE UPI0 to UPI3 UPE UPC F2MC-16LX internal data bus IBFE OBEE R/W comp match Interrupt request #16 Interrupt request #15 Interrupt request #14 Interrupt request #13 Interrupt request #21 OBF0 to OBF3 LCR UPS UF4 UPDI UPD7 UPD6 UPD5 UPD4 UPD3 UPD2 UPD1 UPD0 UPDO UPD7 UPD6 UPD5 UPD4 UPD3 UPD2 UPD1 UPD0 UF3 UF2 UF1 A2 UF0 IBF OBF LPC internal data bus LRF LRIE LPE LA3 LA2 LA1 LA0 EN R/W State machine 4 UPC GA20E EN for UPI0 only GA20 output generator LFRAME LRESET LCLK LAD3 to LAD0 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 LPC bus interface GA20 DBAE UPC Data buffer array IXR Index register Data port register DPR UP data register (32 bytes) DOWN data register (16 bytes) 87 MB90370/375 Series 17. Serial IRQ controller The serial IRQ controller consists of a 6-channel serial IRQ control circuit and an LPC clock monitor / control circuit. By using this serial IRQ controller, host interrupt requests can be transferred serially through a single signal wire (SERIRQ) , synchronized with the LPC clock. 6-channel serial IRQ control circuit • The 6-channel serial IRQ control circuit consists of a serial interrupt control register (SICR) , 4 serial interrupt frame number registers (SIFR1 to SIFR4) , a protocol state machine and a serial interrupt data latch and output control. • For channel 0A, 0B and 1 to 3, if SICR : OBE bit (OBF controlled enable bit) = 0, then serial IRQ can be controlled by software setting of SICR : IRR bit. If SICR : OBE bit = 1, then software control is disabled and serial IRQ is controlled by OBF flag (Output buffer full flag) from LPC UPI0 to UPI3. • For channel 4, serial IRQ can be controlled by software setting of SICR : IRR bit. • For channel 0A and 0B, additional enable bit (SICR : EN0A/0B bit) can be used to latch and keep the OBF0 or IRR0A/0B bit status. • The serial interrupt data latch transfers serial IRQs serially according to their frame number. The frame number for channel 0A is fixed to “IRQ1”, for channel 0B is fixed to “IRQ12”, and the frame number for channel 1 to channel 4 are software programmable (IRQ1 to IRQ15, and IRQ21 to IRQ31) by setting the SIFR1 to SIFR4. • By monitoring the SERIRQ and the LPC clock pin, the protocol state machine can detect the START frame condition. Then it starts counting the DATA frame and transfers its serial IRQs through SERIRQ. Finally it can switch to continuous/quiet mode operation by determine the STOP frame condition. • The serial interrupt output control support both continuous and quiet mode operation. In continuous mode operation, only the host can initiate the serial IRQs transfer; In quiet mode operation, both the host and slave (e.g. the serial IRQ controller) can initiate the serial IRQs transfer. LPC clock monitor / control circuit • The LPC clock monitor / control circuit consists of a clock-run monitor / control circuit. By monitoring the clockrun pin (CLKRUN) , the clock monitor / control circuit can determine whether the host has stopped LPC clock in quiet mode operation or not. If LPC clock is stopped and the controller wants to initiate the serial IRQs transfer, then it can request the host to restart the LPC clock by controlling the CLKRUN pin. 88 MB90370/375 Series (1) Register configuration of serial IRQ controller Serial Interrupt Control Register (Lower) 7 6 EN0A R/W 0 5 IRR4 R/W 0 4 IRR3 R/W 0 3 IRR2 R/W 0 2 IRR1 R/W 0 1 IRR0B R/W 0 0 IRR0A R/W 0 Address : 000032H Read/write Initial value EN0B R/W 0 Bit number SICRL Serial Interrupt Control Register (Upper) 15 14 RSEN R/W 0 13 BUSY R 0 12 OBE3 R/W 0 11 OBE2 R/W 0 10 OBE1 R/W 0 9 8 Address : 000033H Read/write Initial value IRQEN R/W 0 OBE0B OBE0A R/W 0 R/W 0 Bit number SICRH Serial Interrupt Frame Number Register 1 7 6    5 LV1 R/W 0 4 FR14 R/W 0 3 FR13 R/W 0 2 FR12 R/W 0 1 FR11 R/W 0 0 FR10 R/W 0 Address : 000034H Read/write Initial value    Bit number SIFR1 Serial Interrupt Frame Number Register 2 15 14    13 LV2 R/W 0 12 FR24 R/W 0 11 FR23 R/W 0 10 FR22 R/W 0 9 FR21 R/W 0 8 FR20 R/W 0 Address : 000035H Read/write Initial value    Bit number SIFR2 Serial Interrupt Frame Number Register 3 7 6    5 LV3 R/W 0 4 FR34 R/W 0 3 FR33 R/W 0 2 FR32 R/W 0 1 FR31 R/W 0 0 FR30 R/W 0 Address : 000036H Read/write Initial value    Bit number SIFR3 Serial Interrupt Frame Number Register 4 15 14    13 LV4 R/W 0 12 FR44 R/W 0 11 FR43 R/W 0 10 FR42 R/W 0 9 FR41 R/W 0 8 FR40 R/W 0 Address : 000037H Read/write Initial value    Bit number SIFR4 89 MB90370/375 Series (2) Block diagram of the serial IRQ controller Serial IRQ controller OBF0 OBF1 OBF2 OBF3 OBF0 OBF1 OBF2 OBF3 6-channel serial IRQ control circuit from UPI0 to UPI3 in LPC interface SIRQ Pin SERIRQ LCLK LCLK stop status F2MC-16LX bus LRESET Pin LCK Pin LRESET LCLK restart request LPC clock monitor / control circuit LCLK LRESET CRUN Pin CLKRUN 90 MB90370/375 Series (3) Block diagram of the 6-channel serial IRQ control circuit IRQEN Serial interrupt control register (upper) SERIRQ busy SIRQ enable OBE0A, OBE0B, OBE1 to OBE3 OBF0 OBF1 OBF2 OBF3 Register write disable Serial interrupt control register (lower) F2MC-16LX bus IRR0A, IRR0B, IRR1 to IRR3 Software Hardware control control Serial IRQ control selector for channel 0A, 0B, 1 to 3 IRR4 EN0A, EN0B Latches for channel 0A, 0B channel 1 to channel 4 SIRQO LCK LRESET Serial interrupt frame number register Serial interrupt data latch and output control Serial IRQs frame no. for channel 1 to channel 4 Serial IRQ sample cycle Frame cycle count Initiate serial IRQ transfer request Protocol state machine SIRQI LCK stop status LCK restart request 91 MB90370/375 Series (4) Block diagram of the LPC clock monitor / control circuit RSEN IRQEN CRUNO enable F2MC-16LX bus LCK restart request LCK restart request Clock-run monitor / control LCK stop status CRUNO CRUNI LCK LRESET 92 MB90370/375 Series 18. 3-channel PS/2 interface The 3-channel PS/2 interface consists of 3 individual channels of PS/2 interface that can be operated concurrently. PS/2 interface is a two wires, bidirectional serial bus providing economical way for data exchange between host (keyboard controller) and device (keyboard / mouse, etc) . (1) Register configuration of 3-channel PS/2 interface PS/2 Interface Mode Register 15 14    13    12    11 NFS1 R/W 0 10 NFS0 R/W 0 9 DIV1 R/W 0 8 DIV0 R/W 0 Address : 000059H Read/write Initial value    Bit number PSMR PS/2 Interface Data Register (Ch 1) 15 14 D6 R/W 0 13 D5 R/W 0 12 D4 R/W 0 11 D3 R/W 0 10 D2 R/W 0 9 D1 R/W 0 8 D0 R/W 0 Address : 000057H Read/write Initial value Address : ch1 000056H ch2 000058H D7 R/W 0 Bit number PSDR1 PS/2 Interface Data Register (Ch 0, Ch 2) 7 D7 D6 R/W 0 6 D5 R/W 0 5 D4 R/W 0 4 D3 R/W 0 3 D2 R/W 0 2 D1 R/W 0 1 D0 R/W 0 0 Bit number PSDR0/2 Read/write Initial value R/W 0 PS/2 Interface Status Register Address : ch0 000051H 15 14 13 12 11 10 9 8 ch1 000053H ch2 000055H TS TBC BNR TC PE FED FRE/NAK RAF Read/write Initial value R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 Bit number PSSR0/1/2 PS/2 Interface Control Register Address : ch0 000050H 7 ch1 000052H ch2 000054H PS2E Read/write Initial value R/W 0 6       5 FEDE R/W 0 4 IE R/W 0 3 BREQ R/W 0 2 TE R/W 0 1 RE R/W 0 0 Bit number PSCR0/1/2 93 MB90370/375 Series (2) Block diagram of 3-channel PS/2 interface F2MC-16LX bus PSCKI0  PSMR    NFS1 NFS0 DIV1 DIV0 2 PSDAI0 Noise filter Noise filter Channel 0 transmission/ reception circuit PSCKO0 PSDAO0 Interrupt request 0 PSCKI1 PSDAI1 Noise filter Noise filter Channel 1 transmission/ reception circuit PSCKO1 PSDAO1 Interrupt request 1 PSCKI2 Prescaler circuit 1/4 Selector 1/8 1/16 1/32 PSDAI2 Noise filter Noise filter φ Channel 2 transmission/ reception circuit PSCKO2 PSDAO2 Interrupt request 2 Sampling clock 94 MB90370/375 Series (3) Block diagram of PS/2 interface transmission/reception circuit (1 channel) F2MC-16LX bus Sampling clock PSDAI PSCKI Synchronous circuit SYNDA SYNCK PSDR D7 D6 D5 D4 D3 D2 D1 D0 PSDAO Start of reception Start of transmission Reception control circuit Reception completion detector Parity checker Reception start bit detection circuit Reception enable Reception status judgment circuit Transmission control circuit Acknowledge reception generator Parity generator Transmission completion detector Transmission enable PE & FRE Reception Reception active complete Transfer break request Acknowledge Transmission result complete Transfer complete processing circuit PSCKO Transfer status flags clear Falling edge detection PS2E  Error flags PS/2 interface interrupt #23 (17H)* ch0/1 #24 (18H)* ch2  FEDE IE BREQ TE RE PE FED FRE/ RAF NAK TS TBC BNR TC PSCR PSSR F2MC-16LX bus * : Interrupt number 95 MB90370/375 Series 19. Parity generator The parity generator is a simple circuit that generates odd / even parity based on the input data. It consists of a parity generator data register (PGDR) , an odd / even parity generation logic and a parity generator control status register (PGCSR) . An 8-bit data can be loaded into PGDR, then the parity generator will generate odd / even parity based on the input data. Either odd or even parity can be generated by setting the PGCSR. For odd parity generation, if the number of “1”s in the PGDR is even number, then the parity bit in PGCSR will be set to “1”, otherwise the parity bit will be set to “0”. For even parity generation, if the number of “1”s in the PGDR is even number, then the parity bit in PGCSR will be set to “0”, otherwise the parity bit will be set to “1”. Table shows some examples of odd / even parity generation. Input data Parity bit (odd parity) 0000 0000B 0101 0101B 1000 0000B 1010 1011B (1) Register configuration of parity generator Parity Generator Data Register 7 6 D6 R/W X 5 D5 R/W X 4 D4 R/W X 3 D3 R/W X 2 D2 R/W X 1 D1 R/W X 0 D0 R/W X Parity bit (even parity) 0 0 1 1 1 1 0 0 Address : 000018H Read/write Initial value D7 R/W X Bit number PGDR Parity Generator Control Status Register 15 14    13    12    11    10    9    8 PSEL R/W 0 Address : 000019H Read/write Initial value PRTY R X Bit number PGCSR 96 MB90370/375 Series (2) Block diagram of parity generator 8 Parity generator data register F2MC16LX Internal bus 8 Parity generation logic result odd / even 2 Parity generator control status register 97 MB90370/375 Series 20. Bit decoder The bit decoder is a simple one-hot decoder that can be used together with the keyscan inputs. It consists of a bit data register (BDR) , a decoder logic and a bit result register (BRR) . A 4-bit encoded data can be loaded into BDR, then the decoder logic will decode the data and store the 16-bit resulted data into BRR. A table below shows the decoder’s logic. 4-bit encoded data 16-bit resulted data 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH (1) Register configuration of bit decoder Bit Data Register 15 14    13    12    11 D3 R/W X 10 D2 R/W X 9 D1 R/W X 8 D0 R/W X 0000 0000 0000 0001B 0000 0000 0000 0010B 0000 0000 0000 0100B 0000 0000 0000 1000B 0000 0000 0001 0000B 0000 0000 0010 0000B 0000 0000 0100 0000B 0000 0000 1000 0000B 0000 0001 0000 0000B 0000 0010 0000 0000B 0000 0100 0000 0000B 0000 1000 0000 0000B 0001 0000 0000 0000B 0010 0000 0000 0000B 0100 0000 0000 0000B 1000 0000 0000 0000B Address : 0000E1H Read/write Initial value Bit Result Register (Upper)    Bit number BDR 15 14 R14 R X 13 R13 R X 12 R12 R X 11 R11 R X 10 R10 R X 9 R9 R X 8 R8 R X Address : 0000E3H Read/write Initial value Bit Result Register (Lower) R15 R X Bit number BRRH 7 6 R6 R X 5 R5 R X 4 R4 R X 3 R3 R X 2 R2 R X 1 R1 R X 0 R0 R X Address : 0000E2H Read/write Initial value R7 R X Bit number BRRL 98 MB90370/375 Series (2) Block diagram of bit decoder 4 Bit data register F2MC16LX Internal bus 4 Decoder logic 16 16 Bit result register 99 MB90370/375 Series 21. Wake-up interrupt The wake-up interrupt circuit detects the signals of the “L” levels input to the external interrupt pins and to generate interrupt request to the CPU. These interrupts can wake up the CPU from standby mode. Wake-up interrupt pins : 8 pins (P00/KSI0 to P07/KSI7) . Wake-up interrupt sources : “L” level signal input to a wake-up interrupt pin. Enables or disables to input wake-up interrupt controlled by wake-up interrupt control Interrupt control : register (EICR) . IRQ flag bit of wake-up interrupt flag register (EIFR) . Flag set Interrupt flag : when there is an IRQ. Interrupt request : Interrupt request #20 is generated if any enabled external interrupt pin goes LOW. (1) Register configuration of wake-up interrupt Wake-up Interrupt Flag Register 15 14    13    12    11    10    9    8 WIF R/W 0 Address : 0000ADH Read/write Initial value    Bit number EIFR Wake-up Interrupt Control Register 7 6 EN6 R/W 0 5 EN5 R/W 0 4 EN4 R/W 0 3 EN3 R/W 0 2 EN2 R/W 0 1 EN1 R/W 0 0 EN0 R/W 0 Address : 0000ACH Read/write Initial value EN7 R/W 0 Bit number EICR (2) Block diagram of wake-up interrupt 7 6 5 3 2 1 0 EICR 4 P07/KSI7 P06/KSI6 P05/KSI5 P04/KSI4 P03/KSI3 P02/KSI2 P01/KSI1 P00/KSI0 Interrupt Request Generator EIFR 100 MB90370/375 Series 22. DTP/External interrupts The DTP (Data Transfer Peripheral) /external interrupt circuit is activated by the signal supplied to a DTP/external interrupt pin. The CPU accepts the signal using the same as procedure used for normal hardware interrupts and generates external interrupts or activates the extended intelligent I/O service (EI2OS) . Features of DTP/External interrupt : • Total 6 external interrupt channels • Two request levels (“H” and “L”) are provided for the intelligent I/O service. • Four request levels (rise/fall edge, fall edge, “H” level and “L” level) are provided for external interrupt requests . (1) Register configuration DTP/Interrupt Source Register 15 14    13 ER5 R/W 0 12 ER4 R/W 0 11 ER3 R/W 0 10 ER2 R/W 0 9 ER1 R/W 0 8 ER0 R/W 0 Address : 000027H Read/write Initial value DTP/Interrupt Enable Register Address : 000026H Read/write Initial value    Bit number EIRR 7    6    5 EN5 R/W 0 4 EN4 R/W 0 3 EN3 R/W 0 2 EN2 R/W 0 1 EN1 R/W 0 0 EN0 R/W 0 Bit number ENIR Request Level Setting Register (Upper) 15 14    13    12    11 LB5 R/W 0 10 LA5 R/W 0 9 LB4 R/W 0 8 LA4 R/W 0 Address : 000029H Read/write Initial value    Bit number ELVRH Request Level Setting Register (Lower) Address : 000028H Read/write Initial value 7 LB3 R/W 0 6 LA3 R/W 0 5 LB2 R/W 0 4 LA2 R/W 0 3 LB1 R/W 0 2 LA1 R/W 0 1 LB0 R/W 0 0 LA0 R/W 0 Bit number ELVRL 101 MB90370/375 Series (2) Block diagram of DTP/External interrupts Request level setting register (ELVR) LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 2 2 2 2 2 2 Selector Pin P60/INT0 Selector Pin P61/INT1 Pin Internal data bus P65/INT5 Selector Selector Pin P62/INT2 Pin P64/INT4 Selector Selector Pin P63/INT3 DTP/interrupt cause register (EIRR) ER5 ER4 ER3 ER2 ER1 ER0 Interrupt request number #17(11H) #18(12H) #19(13H) EN5 EN4 EN3 EN2 EN1 EN0 DTP/interrupt enable register (ENIR) 102 MB90370/375 Series 23. Delayed interrupt generation module The delayed interrupt generation module is used to generate a task switching interrupt. Interrupt requests to the F2MC-16LX CPU can be generated and cleared by software using this module. (1) Register configuration Delayed Interrupt Generator Module Register 15 14    13    12    11    10    9    8 R0 R/W 0 Address : 00009FH Read/write Initial value    Bit number DIRR (2) Block diagram F2MC-16LX bus Delayed interrupt cause issuance / cancellation decoder Interrupt cause latch 103 MB90370/375 Series 24. ROM correction function When an address matches the value set in the address detection register, the instruction code to be loaded into the CPU is forced to be replaced with the INT9 instruction code (01H) . When executing a set instruction, the CPU executes the INT9 instruction. The ROM correction function is implemented by processing using the INT9 interrupt routine. The device contains two address detection registers, each provided with a compare enable bit. When the value set in the address detection register matches an address and the interrupt enable bit is “1”, the instruction code to be loaded into the CPU is forced to be replaced with the INT9 instruction code. (1) Register configuration Program Address Detection Control / Status Register 7 6    5    4    3 AD1E R/W 0 2 AD1D R/W 0 1 AD0E R/W 0 0 AD0D R/W 0 Address : 00009EH Read/write Initial value    Bit number PACSR Program Address Detection Register 0 (Upper Byte) 7 6 5 4 3 2 1 0 Address : 001FF2H Read/write Initial value R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X Bit number PADRH0 Program Address Detection Register 0 (Middle Byte) 15 14 13 12 11 10 9 8 Address : 001FF1H Read/write Initial value R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X Bit number PADRM0 Program Address Detection Register 0 (Lower Byte) 7 6 5 4 3 2 1 0 Address : 001FF0H Read/write Initial value R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X Bit number PADRL0 (Continued) 104 MB90370/375 Series (Continued) Program Address Detection Register 1 (Upper Byte) 15 14 13 12 11 10 9 8 Address : 001FF5H Read/write Initial value R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X Bit number PADRH1 Program Address Detection Register 1 (Middle Byte) Address : 001FF4H Read/write Initial value 7 6 5 4 3 2 1 0 Bit number PADRM1 R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X Program Address Detection Register 1 (Lower Byte) 15 14 13 12 11 10 9 8 Address : 001FF3H Read/write Initial value R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X Bit number PADRL1 (2) Block diagram Address latch Comparator Address detection register 0/1 F2MC-16LX bus INT9 command F2MC-16LX CPU AD0E/AD1E AD0D/AD1D PACSR 105 MB90370/375 Series 25. ROM mirroring function selection module The ROM mirroring function selection module can select what the FF bank allocated the ROM sees through the 00 bank according to register settings. (1) Register configuration ROM Mirror Function Selection Register 15 14    13    12    11    10    9    8 M1 W 1 Address : 0006FH Read/write Initial value    Bit number ROMM (2) Block diagram ROM mirroring register Address area F2MC-16LX bus FF bank 00 bank ROM 106 MB90370/375 Series 26. 512K bit flash memory The 512K bit flash memory is allocated in the FFH banks on the CPU memory map. Like masked ROM, flash memory is read-accessible and program-accessible to the CPU using the flash memory interface circuit. The flash memory can be programmed/erased by the instruction from the CPU via the flash memory interface circuit. The flash memory can therefore be reprogrammed (updated) while still on the circuit board under integrated CPU control, allowing program code and data to be improved efficiently. Note that sector operations such as “enable sector protect” cannot be used. Features of 512K bit flash memory : • 64 Kwords × 8 bits / 32 Kwords × 16 bits (16 K + 8 K + 8 K + 32 K) sector configuration • Automatic program algorithm (same as the Embedded Algorithm* : MBM29F400TA) • Installation of the deletion temporary stop/delete restart function • Write/delete completion detected by the data polling or toggle bit • Write/delete completion detected by the CPU interrupt • Compatibility with the JEDEC standard-type command • Each sector deletion can be executed (Sectors can be freely combined) . • Number of write/delete operations 10,000 times guaranteed * : Embedded Algorithm is a trademark of Advanced Micro Devices, Inc. (1) Register configuration Flash Memory Control Status Register 7 6 RDYINT R/W 0 5 WE R/W 0 4 RDY R 1 3 Reserved 2 LPM1 R/W 0 1 Reserved 0 LPM0 R/W 0 Address : 0000AEH Read/write Initial value INTE R/W 0 Bit number FMCS W 0 W 0 107 MB90370/375 Series (2) Sector configuration of 512K bits flash memory The 512K bits flash memory has the sector configuration illustrated below. The addresses in the illustration are the upper and lower addresses of each sector. When accessed from the CPU, SA0 and SA1 to SA3 are allocated in the FF bank registers, respectively. Flash memory CPU address FFFFFFH SA3 (16 Kbytes) FFC000H FFBFFFH SA2 (8 Kbytes) FFA000H FF9FFFH SA1 (8 Kbytes) FF8000H SA0 (32 Kbytes) FF7FFFH FF0000H 7A000H 79FFFH 78000H 77FFFH 70000H 7C000H 7BFFFH *Writer address 7FFFFH * : Writer addresses correspond to CPU addresses when data is programmed in flash memory by a parallel writer. Writer addresses are used to program/erase data using a general-purpose writer. 108 MB90370/375 Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 −2.0     Max VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 6.0 VSS + 4.0 +2.0 20 10 20 4 (VSS = AVSS = CVSS = 0.0 V) Unit V V V V VCC ≥ CVCC *1 VCC ≥ AVCC *1 AVCC ≥ AVR, AVR ≥ AVSS CVCC ≥ CVRH1, CVRH1 ≥ CVSS CVCC ≥ CVRH2, CVRH2 ≥ CVSS CVCC ≥ CVRL, CVRL ≥ CVSS V1 to V3 must not exceed VCC Not for MB90F377 All pins except P40 to P45, P80 to P82, P90 to P95 *2 P40 to P45, P80 to P82, P90 to P95 *2 *4 *4 All pins except PF0 to PF7*3 PF0 to PF7*3 All pins except PF0 to PF7 Average output current = operating current × operating efficiency PF0 to PF7 Average output current = operating current × operating efficiency Remarks Parameter Symbol VCC Power supply voltage A/D converter reference input voltage Comparator reference input voltage LCD power supply voltage CVCC AVCC AVR CVRH1 CVRH2 CVRL V1 to V3 VI1 VI2 V V V V V mA mA mA mA mA Input voltage Output voltage Maximum clamp current Total maximum clamp current “L” level maximum output current VO ICLAMP Σ|ICLAMP| IOL1 IOL2 IOLAV1 “L” level average output current IOLAV2 “L” level total maximum output current “L” level total average output current “H” level maximum output current “H” level average output current “H” level total maximum output current “H” level total average output current ΣIOL ΣIOLAV IOH IOHAV ΣIOH ΣIOHAV        12 mA 100 50 −10 −3 −100 −50 mA mA mA mA mA mA Average output current = operating current × operating efficiency Average output current = operating current × operating efficiency *3 Average output current = operating current × operating efficiency (Continued) 109 MB90370/375 Series (Continued) Rting Min  −40 −55 Max 200 +85 +150 (VSS = AVSS = CVSS = 0.0 V) Symbol PD TA Tstg Unit mW °C °C Remarks Parameter Power consumption Operating temperature Storage temperature *1 : Set AVCC, CVCC and VCC at the same voltage. Take care so that AVR, CVRH1, CVRH2 and CVRL do not exceed VCC + 0.3 V when the power is turned on. *2 : VI and VO shall never exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *3 : The maximum output current is a peak value for a corresponding pin. *4 : Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P47, P50 to P57, P60 to P67, P70 to P77, PA0 to PA6, PC3 to PC7, PD0 to PD3, PD6, PD7 Use within recommended operating conditions. Use at DC voltage (current) . The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the Vcc pin, and this may affect other devices. Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0V) , the power supply is provided from the pins, so that incomplete operation may result. Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. Care must be taken not to leave the +B input pin open. Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. Sample recommended circuits : Input/Output Equivalent circuits Protective diode Vcc Limiting resistance +B input (0V to 16V) N-ch P-ch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 110 MB90370/375 Series 2. Recommended Operating Conditions Value Min 3.0 3.3 1.8 0 Max 3.6 3.6 3.6 AVCC (VSS = AVSS = CVSS = 0.0 V) Unit V V V V Remarks Normal operation assurance range Retains the RAM state in stop mode Normal operation assurance range V1 to V3 pins (The optimum value is dependent on the LCD element in use.) Not for MB90F377 Parameter Symbol VCC Power supply voltage *1 A/D converter reference input voltage *2 LCD power supply voltage Operating temperature CVCC VCC AVR V1 to V3 VSS VCC V TA −40 +85 °C *1 : Set AVCC, CVCC and VCC at the same voltage. *2 : Take care so that AVR, CVRH1, CVRH2 and CVRL do not exceed VCC + 0.3 V when power is turned on. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 111 MB90370/375 Series 3. DC Characteristics (VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C) Pin name P10 to P17 P20 to P27 P30 to P37 P46, P47 P50 to P57 PA0 to PA6 PB0 to PB7 PC0 to PC7 PD0 to PD7 PF0 to PF7 P00 to P07 P60 to P67 P70 to P77 PE0 to PE7 RST Condition Value Min Typ Max Unit Remarks Parameter Symbol VIH 0.7 VCC  VCC + 0.3 V CMOS input pins “H” level input voltage VIHS 0.8 VCC  VCC + 0.3 V CMOS hysteresis input pins 5 V tolerant CMOS hysteresis input pins 5 V tolerant CMOS input pin SMbus input pins Mode pins VIHS5 P40 to P45 0.8 VCC  VSS + 5.5 V VIH5 P82 P80, P81 P90 to P95 MD0 to MD2 P10 to P17 P20 to P27 P30 to P37 P46, P47 P50 to P57 P82 PA0 to PA6 PB0 to PB7 PC0 to PC7 PD0 to PD7 PF0 to PF7 P00 to P07 P40 to P45 P60 to P67 P70 to P77 PE0 to PE7 RST  0.7 VCC    VSS + 5.5 VSS + 5.5 VCC + 0.3 V VIHSM VIHM 2.1 VCC − 0.3 V V VIL “L” level input voltage VSS − 0.3  0.3 VCC V CMOS input pins VILS VSS − 0.3  0.2 VCC V CMOS hysteresis input pins (Continued) 112 MB90370/375 Series (VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter “L” level input voltage Open-drain output pin application voltage Symbol VILSM VILM VD5 VD Pin name P80, P81 P90 to P95 MD0 to MD2 P40 to P45 P80 to P82 P90 to P95 P46 All port pins except P40 to P46 P80 to P82 P90 to P95 PF0 to PF7 PF0 to PF7 All port pins except PF0 to PF7 PF0 to PF7  VSS − 0.3 VSS − 0.3   VSS + 5.5 VCC + 0.3 V V Condition Value Min VSS − 0.3 VSS − 0.3 Typ   Max 0.8 VSS + 0.3 Unit V V Remarks SMbus input pins Mode pins “H” level output voltage VOH1 VCC = 3.0 V IOH1 = −4.0 mA VCC − 0.5   V VOH2 VCC = 3.0 V IOH2 = −8.0 mA IOL1 = 4.0 mA IOL2 = 12.0 mA VCC = 3.3 V, VSS < VI < VCC VCC − 0.5   −5      0.4 0.4 +5 V “L” level output voltage Input leakage current (High-Z output leakage current) Open-drain output leakage current VOL1 VOL2 V V µA IIL All input pins ILEAK P40 to P46 P80 to P82 P90 to P95  VCC = 3.3 V, Internal operation at 16 MHz VCC = 3.3 V, Internal operation at 16 MHz, In sleep mode VCC = 3.3 V, External 32 kHz, Internal operation at 8 kHz, In sub-clock mode, TA = +25 °C      37 30 5 µA mA MB90F372 / F377 ICC 45 35 mA MB90372 ICCS Power supply current* VCC 15 20 mA ICCL  23 80 µA (Continued) 113 MB90370/375 Series (VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Condition VCC = 3.3 V, External 32 kHz, Internal operation at 8 kHz, In sub-clock sleep mode, TA = +25 °C VCC = 3.3 V, External 32 kHz, Internal operation at 8 kHz, In watch mode, TA = +25 °C VCC = 3.3 V, Internal operation at 16 MHz, In timebase timer mode VCC = 3.3 V, In stop mode, TA = +25 °C All input pins except VCC, AVCC, CVCC, VSS, AVSS, CVSS  Between VCC and V3 at VCC = 3.3 V LCD divided resistance RLCD  Between V3 and V2 Between V2 and V1 Between V1 and VSS at VCC = 3.3 V Value Min Typ Max Unit Remarks ICCLS  10 50 µA Power supply current* ICCWAT VCC  1.5 30 µA ICCT  1.3 2 mA ICCH  1 20 µA Input capacitance CIN  5 15 pF 100 200 400 kΩ Not for MB90F377 50 100 200 COM0 to COM3 output impedance SEG0 to SEG8 output impedance LCD leakage current RVCOM COM0 to COM3 V1 to V3 = 3.3 V   5 kΩ Not for MB90F377 RVSEG SEG0 to SEG8 V1 to V3 COM0 to COM3 SEG0 to SEG8   5 kΩ Not for MB90F377 LLCDL    ±1 µA (Continued) 114 MB90370/375 Series (Continued) (VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name P00 to P07 P10 to P17 P20 to P27 P30 to P37 RST MD2 Condition Value Min Typ Max Unit Remarks Parameter Pull-up resistance RUP  25 50 100 kΩ Pull-down resistance RDOWN  25 50 100 kΩ MB90V370, MB90372 only * : The power supply current is measured with an external clock. 115 MB90370/375 Series 4. AC Characteristics (1) Clock Timings (VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C) Value Symbol Pin name Condition Unit Remarks Min Typ Max FCH Clock frequency FCH FCL Clock cycle time tHCYL tLCYL PWH PWL PWHL PWLL tCR tCF fCP fLCP tCP tLCP X0, X1 X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0      3 3  31.25  5   1.5  62.5    32.768  30.5  15.2   8.192  122.1 16 32  333    5 16  666  MHz Crystal oscillator* MHz External clock* kHz ns µs ns µs ns Recommend duty ratio of 30% to 70% Recommend duty ratio of 30% to 70% External clock operation Parameter Input clock pulse width Input clock rise/fall time Internal operating clock frequency Internal operating clock cycle time MHz Main clock operation kHz Sub-clock operation ns µs Main clock operation Sub-clock operation * : When selecting the PLL clock, the range of clock frequency is limited. Use this product within range as mentioned in “Relationship between oscillating frequency and internal operating clock frequency” of “• PLL operation guarantee range”. X0, X1 clock timing tHCYL 0.8 VCC X0 PWH tCF PWL tCR 0.2 VCC X0A, X1A clock timing tLCYL 0.8 VCC 0.2 VCC X0A PWHL tCF PWLL tCR 116 MB90370/375 Series • PLL operation guarantee range Relationship between internal operating clock frequency and power supply voltage Power supply voltage VCC (V) 3.6 Operation guarantee range of PLL 3.0 Normal operation guarantee range 1.5 4 8 Internal operating clock fCP (MHz) 16 Relationship between oscillating frequency and internal operating clock frequency Multiplied- Multipliedby-4 by-3 16 12 9 8 Multipliedby-2 Multipliedby-1 Internal operating clock fCP (MHz) Not multiplied 4 3 4 8 Oscillation clock FC (MHz) 16 117 MB90370/375 Series The AC ratings are measured for the following measurement reference voltages : • Input signal waveform Hysteresis input pin 0.8 VCC 0.2 VCC • Output signal waveform Output pin 2.4 V 0.8 V CMOS input pin 0.7 VCC 0.3 VCC SMbus input pin 2.1 V 0.8 V 118 MB90370/375 Series (2) Reset Input Timing (VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C) Pin name Condition Value Min 16 tCP Max   Unit ns Remarks Normal operation In stop mode and sub-clock mode Parameter Symbol Reset input time tRSTL RST  Oscillation time of oscillator* + 16 tCP ms * : Oscillation time of oscillator is the time to reach to 90% of the oscillation amplitude from stand still. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR/ceramic oscillator, the oscillation time is between hundreds of µs to several ms. In the external clock, the oscillation time is 0 ms. • In stop mode and sub-clock mode tRSTL RST 0.2 Vcc 0.2 Vcc 90% of the oscillation amplitude X0 Internal operation clock Oscillation time of oscillator 16 tCP Oscillator stabilization time Instruction execution Internal reset 119 MB90370/375 Series (3) Power-on Reset Parameter Power supply rise time Power supply cut-off time (VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C) Value Symbol Pin name Condition Unit Remarks Min Max tR tOFF VCC* VCC*   1 50  ms ms Due to repeated operations * : VCC must be kept lower than 0.2 V before power-on. Notes : • The above values are used for causing a power-on reset. Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn on the power supply using the above values. • Make sure that power supply rises within the selected oscillation stabilization time. If the power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR 2.2 V 0.2 V 0.2 V tOFF VCC 0.2 V Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommneded to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V or fewer per second, however, you can use the PLL clock. VCC 1.8 V RAM data hold It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower. VSS 120 MB90370/375 Series (4) UART1 to UART3 (VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name UCK1 to UCK3 UCK1 to UCK3 CL = 80 pF + 1 TTL UO1 to UO3 for an output pin of UCK1 to UCK3 internal shift clock UI1 to UI3 mode UCK1 to UCK3 UI1 to UI3 UCK1 to UCK3 UCK1 to UCK3 UCK1 to UCK3 CL = 80 pF + 1 TTL UO1 to UO3 for an output pin of external shift clock UCK1 to UCK3 mode UI1 to UI3 UCK1 to UCK3 UI1 to UI3 Condition Value Min 8 tCP −80 100 tCP 4 tCP 4 tCP  60 60 Max  +80     150   Unit Remarks ns ns ns ns ns ns ns ns ns Parameter Serial clock cycle time UCK ↓ → UO delay time Valid UI → UCK ↑ UCK ↑ → valid UI hold time Serial clock “H” pulse width Serial clock “L” pulse width UCK ↓ → UO delay time Valid UI → UCK ↑ UCK ↑ → valid UI hold time Notes : • These are AC ratings in the CLK synchronous mode. • CL is the load capacitance value connected to pins while testing. • tCP is the internal operating clock cycle time. 121 MB90370/375 Series • Internal shift clock mode tSCYC UCK 0.8 V tSLOV 2.4 V 2.4 V 0.8 V UO 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC UI 0.2 VCC • External shift clock mode tSLSH tSHSL 0.8 VCC 0.2 VCC tSLOV 2.4 V 0.2 VCC 0.8 VCC UCK UO 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC UI 0.2 VCC 122 MB90370/375 Series (5) Resources Input Timing (VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Timer input pulse width Symbol tTIWH tTIWL Pin name TIN1 to TIN4 Condition  Value Min 4 tCP Max  Unit ns Remarks 0.8 VCC 0.8 VCC 0.2 VCC tTIWH tTIWL 0.2 VCC TIN1 to TIN4 (6) Trigger Input Timing Parameter (VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C) Value Symbol Pin name Condition Unit Remarks Min Max tTRGH tTRGL ADTG INT0 to INT5 KSI0 to KSI7  5 tCP 1   ns µs Normal operation Stop mode Input pulse width 0.8 VCC 0.8 VCC 0.2 VCC tTRGH tTRGL 0.2 VCC INT0 to INT5 KSI0 to KSI7 0.7 VCC 0.7 VCC 0.3 VCC tTRGH tTRGL 0.3 VCC ADTG 123 MB90370/375 Series (7) I2C / MI2C Timing Parameter Start condition output Stop condition output Start condition detect Stop condition detect Restart condition output Restart condition detect SCL output “L” width SCL output “H” width SDA output delay SDA output setup time after interrupt SCL input “L” pulse SCL input “H” pulse SDA output setup time SDA hold time (VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C) Value Symbol Pin name Unit Remarks Min Max tSTA tSTO tSTA tSTO tSTASU tSTASU tLOW tHIGH tDO tDOSU*3 tLOW tHIGH tSU tHO SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SCL SDA SDA SCL SCL SDA SDA tCP (m × n/2 − 1) - 20 tCP (m × n/2 − 1) + 20 tCP (m × n/2 + 3) - 20 tCP (m × n/2 + 3) + 20 tCP + 40 tCP + 40   ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *1 *2 Master mode Master mode Master mode Master mode Master mode tCP (m × n/2 + 3) - 20 tCP (m × n/2 + 3) + 20 tCP + 40 tCP × m x n/2 - 20  tCP × m × n/2 + 20 tCP (m × n/2 + 2) - 20 tCP (m × n/2 + 2) + 20 tCP × 3 − 20 tCP × m × n/2 − 20 tCP × 4 − 20 tCP × 3 + 40 tCP + 40 40 0 tCP × 3 + 20       *1 : At the stop condition or transferring of next byte. *2 : After setting register bit IBCRH : SCC/MBCRH : SCC at restart. *3 : tDOSU is longer than the “L” width of SCL. Notes : • tCP is the internal operating clock cycle time. • m is the setting bit of shift clock oscillation defined in the “ICCR register (CS4 to CS3) ” and “MCCR register (CS4 to CS3) ”. Please refer to the MB90370/375 series H/W manual for details. • n is the setting bit of shift clock oscillation defined in the “ICCR register (CS2 to CS0) ” and “MCCR register (CS2 to CS0) ”. Please refer to the MB90370/375 series H/W manual for details. • SDA and SCL output value is specified on condition that the rise/fall time is “0 ns”. 124 MB90370/375 Series • Data transmit (master / slave) tDO tDO tSU tHO tDOSU SDA tSTASU tSTA tLOW tHO 1 ACK SCL 9 • Data receive (master / slave) tSU tHO tDO ACK tHIGH 6 7 tLOW 8 9 tSTO tDO tDOSU SDA SCL 125 MB90370/375 Series (8) PS/2 Interface Timing Parameter PSCK clock cycle time PSCK ↓ → PSDA Valid PSDA → PSCK ↓ PSCK ↓ → valid PSDA hold time PSCK clock “H” pulse width PSCK clock “L” pulse width Symbol tPCYC tPLOV tPIVSH tPHIX tPHSL (VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Condition Unit Remarks Min Typ Max PSCK0 to PSCK2 PSDA0 to PSDA2  4 tCP 2 tCP 1 tCP 1 tCP 2 tCP  2 tCP   ns           ns ns ns ns ns PSCK0 to PSCCK2 Transmission PSDA0 to PSDA2 Mode PSCK0 to PSCK2 PSDA0 to PSDA2 PSCK0 to PSCK2 PSDA0 to PSDA2 PSCK0 to PSCK2 PSDA0 to PSDA2 Reception Mode PSCK0 to PSCK2 tPLSH PSDA0 to PSDA2 Note : tCP is the internal operating clock cycle time. tPCYC PSCK0 PSCK1 PSCK2 0.8 VCC 0.2 VCC 0.8 VCC • Transmission Mode PSDA0 PSDA1 PSDA2 tPLOV 2.4 V 0.8 V tPIVSH tPHIX • Reception Mode PSDA0 PSDA1 PSDA2 0.8 VCC 0.2 VCC 126 MB90370/375 Series (9) LPC Timing Parameter LCLK cycle time LCLK high time LCLK low time (VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C) Value Symbol Pin name Condition Unit Remarks Min Typ Max tCYCLE tHIGH tLOW       30 12 12       ns ns ns LCLK AC timing tCYCLE tHIGH 0.7 VCC 0.3 VCC LCLK tLOW 127 MB90370/375 Series LAD, LFRAME, GA20 AC timing 0.4 VCC LCLK tVAL OUTPUT Delay tON Tri-state OUTPUT tOFF 0.4 VCC LCLK tS tH INPUT 128 MB90370/375 Series 5. A/D Converter Electrical Characteristics (2.7 V ≤ AVR − AVSS, VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin Parameter Symbol Unit Remarks name Min Typ Max             AVSS − 1.5 LSB AVR − 3.5 LSB     AVSS + 0.5 LSB AVR − 1.5 LSB 10 ±3.0 ±2.5 ±1.9 AVSS + 5.5 LSB AVSS + 2.5 LSB AVR + 0.5 LSB bit LSB LSB LSB For MB90V370 mV For MB90F372/F377/372 mV Actual value is specified as a sum of values specified in ADCR0 : CT1, CT0 and ADCR0 : ST1, ST0. Be sure that the setting value is greater than the Min value. Actual value is specified in ADCR0 : ST1, ST0 bits. Be sure that the setting value is greater than the Min value. Resolution Total error Non-linear error Differential linearity error Zero transition voltage Full-scale transition voltage VOT AN0 to AN11 AN0 to AN11 VFST Conversion time   3.1   µs Sampling period   AN0 to AN11 AN0 to AN11 AVR AVCC AVR AN0 to AN11 2   µs Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Offset between channels IAIN VAIN  IA IAH IR IRH —  AVSS AVSS + 2.7      0.1   1.4  94   10 AVR AVCC 6.4 5 300 5 4 µA V V mA µA µA µA LSB * * * : The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVR = 3.0 V) . 129 MB90370/375 Series 6. A/D Converter Glossary Analog changes that are identifiable with the A/D converter. The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics. Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value. Total error : The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. Resolution : Linearity error : Total error 3FF 3FE 3FD Digital output Actual conversion value 0.5 LSB {1 LSB × (N − 1) + 0.5 LSB} 004 003 002 001 0.5 LSB AVRL Analog input AVRH VNT (Measured value) Actual conversion value Theoretical characteristics Total error for digital output N = 1 LSB = (Theoretical value) VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVR − AVss [V] 1024 [LSB] VOT (Theoretical value) = AVss + 0.5 LSB [V] VFST (Theoretical value) = AVR − 1.5 LSB [V] VNT : Voltage at a transition of digital output from (N - 1) to N (Continued) 130 MB90370/375 Series (Continued) Linearity error 3FF 3FE 3FD Digital output Actual conversion value {1 LSB × (N − 1) + VOT } Digital output VFST (Measured value) N+1 Differential linearity error Theoretical characteristics Actual conversion value N V (N + 1) T (Measured value) VNT (Measured value) N−2 Actual conversion value 004 003 002 001 AVRL VNT (Measured value) Actual conversion value Theoretical characteristics VOT (Measured value) AVRH Analog input N−1 AVRL Analog input AVRH Linearity error of = digital output N Differential linearity error = of digital output N 1 LSB = VNT − {1 LSB × (N − 1) + VOT} 1 LSB V (N + 1) T − VNT 1 LSB VFST − VOT 1022 − 1 [LSB] [V] [LSB] VOT : Voltage at transition of digital output from “000H” to “001H” VFST : Voltage at transition of digital output from “3FEH” to “3FFH” 131 MB90370/375 Series 7. Notes on Using A/D Converter Select the output impedance value for the external circuit of analog input according to the following conditions. Output impedance values of the external circuit of 4 kΩ or lower are recommended. When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient. • Equipment of analog input circuit model Sampling and hold circuit Analog input Comparator R C R : about 1.9 kΩ C : about 32.3 pF Note : Listed values must be considered as standards. • Error The smaller the | AVR - AVSS | is, the greater the error would become relatively. 8. D/A Electrical Characteristics Parameter Resolution Differential linearity error Non-linearity error Conversion time Analog output impedance Power supply Current (VCC = AVCC = CVCC = 3.0 V to 3.6V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C) Value Symbol Pin name Condition Unit Remarks Min Typ Max      IDVR IDVRS      AVCC AVCC      2.0   8   0.6 2.9  0.1  ±0.9 ±1.5  3.8 460  bit LSB LSB µs kΩ µA µA D/A stops * * : With load capacitance is 20 pF. 132 MB90370/375 Series 9. Comparator Electrical Characteristics (VCC = AVCC = CVCC = 3.3 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C) Pin name CVRH2 Condition Value Min 1.1  CVRL 1.1      CVSS Typ        Max 2.9 2.9 CVRH1 ±1 50 10 Unit V V V µA µA µA V active inactive * Remarks Parameter Symbol Reference voltage  CVRH1 CVRL CVRH2 CVRH1 CVRL CVCC DCIN DCIN2 VOL1 to VOL3 VSI1 to VSI3 Reference voltage supply current Comparator supply current ICR ICV Analog input voltage VIH  CVCC *: Please use the reference voltage of CVRH2, CVRH1 and CVRL to 0.5VCC for MB90F377. 10. Serial IRQ Electrical Characteristics Parameter “H” level input voltage “L” level input voltage “H” level output voltage “L” level output voltage (VCC = AVCC = CVCC = 3.0 V to 3.6 V, VSS = AVSS = CVSS = 0.0 V, TA = −40 °C to +85 °C) Value Symbol Pin name Condition Unit Remarks Min Typ Max VIH VIL VOH VOL         0.7VCC VSS VCC − 0.5      VCC 0.3VCC  0.4 V V V V 11. Flash Memory Program/Erase Characteristics Parameter Sector erase time Chip erase time Word (16 bit width) programing time Program/Erase cycle  TA = +25 °C VCC = 3.0 V Condition Value Min    10,000 Typ 1 4 16  Max 15  3,600  Unit s s µs cycle Remarks Excludes 00H programming prior to erasure Excludes 00H programming prior to erasure Except for the over head time of the system 133 MB90370/375 Series s EXAMPLE CHARACTERISTICS • MB90F372 VCC vs. ICC 50.0 Ta 18.0 25 °C FCH = 16.0 MHz 16.0 40.0 FCH = 12.0 MHz 12.0 ICCS (mA) ICC (mA) 30.0 FCH = 10.0 MHz FCH = 8.0 MHz 20.0 10.0 8.0 6.0 FCH = 4.0 MHz 10.0 FCH = 2.0 MHz 0.0 2.0 4.0 2.0 0.0 2.0 FCH = 4.0 MHz FCH = 2.0 MHz 14.0 FCH = 12.0 MHz FCH = 10.0 MHz FCH = 8.0 MHz Ta 25 °C FCH = 16.0 MHz VCC vs. ICCS 2.5 3.0 3.5 4.0 4.5 2.5 3.0 VCC (V) 3.5 4.0 4.5 VCC (V) VCC vs. ICCL 30.0 Ta 25.0 25 °C FCL = 32.0 kHz 20.0 ICCL ( A) 15.0 10.0 5.0 0.0 2.0 2.5 3.0 VCC (V) 3.5 4.0 4.5 (Continued) 134 MB90370/375 Series (Continued) IOH1 vs. VCC - VOH1 2.0 Ta 25 °C 0.6 1.5 0.5 VCC - VOH1 (V) Vcc = 2.5 V IOH2 vs. VCC - VOH2 0.7 Ta 25 °C VCC - VOH2 (V) Vcc = 2.5 V 0.4 Vcc = 3.0 V 1.0 Vcc = 3.0 V 0.3 Vcc = 3.5 V Vcc = 3.5 V 0.5 0.2 0.1 0.0 0 -2 -4 -6 -8 -10 0.0 0 -2 -4 -6 -8 -10 IOH2 (mA) IOH1 (mA) IOL1 vs. VOL1 0.8 Ta 0.6 25 °C Vcc = 2.5 V Vcc = 3.0 V IOL2 vs. VOL2 0.3 Ta 25 °C 0.2 VOL1 (V) Vcc = 3.5 V Vcc = 2.5 V Vcc = 3.0 V VOL2 (V) 0.4 Vcc = 3.5 V 0.1 0.2 0.0 0 2 4 IOL1 (mA) 6 8 10 0.0 0 2 4 6 IOL2 (mA) 8 10 135 MB90370/375 Series • MB90372t VCC vs. ICC 40.0 Ta 25 °C 18.0 FCH = 16.0 MHz 16.0 30.0 14.0 FCH = 12.0 MHz 12.0 ICCS (mA) FCH = 10.0 MHz ICC (mA) 20.0 FCH = 8.0 MHz 10.0 8.0 6.0 10.0 FCH = 4.0 MHz FCH = 2.0 MHz 0.0 1.5 4.0 2.0 0.0 1.5 FCH = 4.0 MHz FCH = 2.0 MHz FCH = 12.0 MHz FCH = 10.0 MHz FCH = 8.0 MHz Ta 25 °C FCH = 16.0 MHz VCC vs. ICCS 2.0 2.5 3.0 VCC (V) 3.5 4.0 4.5 2.0 2.5 3.0 VCC (V) 3.5 4.0 4.5 VCC vs. ICCL 30.0 Ta = + 25 °C 25.0 20.0 FCL = 32.0 kHz ICCL (mA) 15.0 10.0 5.0 0.0 1.5 2.0 2.5 3.0 VCC (V) 3.5 4.0 4.5 (Continued) 136 MB90370/375 Series (Continued) IOH1 vs. VCC - VOH1 1.0 Ta 0.8 25 °C 0.4 Ta Vcc = 2.5 V Vcc = 3.0 V IOH2 vs. VCC - VOH2 25 °C Vcc = 2.5 V 0.3 VCC - VOH2 (V) Vcc = 3.0 V VCC - VOH1 (V) 0.6 Vcc = 3.5 V Vcc = 3.5 V 0.2 0.4 0.2 0.1 0.0 0 -2 -4 -6 -8 -10 0.0 0 -2 -4 -6 -8 -10 IOH1 (mA) IOH2 (mA) IOL1 vs. VOL1 0.8 Ta 25 °C Vcc = 2.5 V IOL2 vs. VOL2 0.25 Ta 0.20 25 °C Vcc = 2.5 V Vcc = 3.0 V 0.6 Vcc = 3.0 V Vcc = 3.5 V VOL1 (V) 0.4 VOL2 (V) Vcc = 3.5 V 0.15 0.10 0.2 0.05 0.0 0 2 4 6 8 10 0.0 0 2 4 6 8 10 IOL1 (mA) IOL2 (mA) 137 MB90370/375 Series s ORDERING INFORMATION Part number MB90F372PFF-G MB90F377PFF-G MB90372PFF-G-XXX Package 144-pin Plastic LQFP (FPT-144P-M12) Remarks XXX is the ROM release number. 138 MB90370/375 Series s PACKAGE DIMENSION 144-pin plastic LQFP (FPT-144P-M12) Note 1) * : These dimensions include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 18.00±0.20(.709±.008)SQ +0.40 +.016 *16.00 –0.10 .630 –.004 SQ 108 73 109 72 0.08(.003) Details of "A" part 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) INDEX 0~8˚ 144 37 "A" 0.60±0.15 (.024±.006) 0.10±0.05 (.004±.002) (Stand off) 0.25(.010) LEAD No. 1 36 +0.05 +.002 –.001 0.40(.016) 0.18±0.035 .007±.001 0.07(.003) M 0.145 –0.03 .006 C 2003 FUJITSU LIMITED F144024S-c-3-3 Dimensions in mm (inches). Note: The values in parentheses are reference values. 139 MB90370/375 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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