FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13740-1E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90378 Series
MB90F378/V378
■ DESCRIPTION
The MB90378 series is a line of general-purpose, 16-bit microcontrollers designed for those applications which require high-speed real-time processing. The instruction set is designed to be optimized for controller applications which inheriting the AT architecture of F2MC-16LX family and allow a wide range of control tasks to be processed efficiently at high speed. A built-in LPC interface, serial IRQ and PS/2 interface simplifies communication with host CPU and PS/2 devices in computer system. Moreover, SMbus compliant I2C*2 and A/D converter implements the smart battery control. With these features, the MB90378 series matches itself as keyboard controller with smart battery control. While inheriting the AT architecture of the F2MC*1 family, the instruction set for the F2MC-16LX CPU core of the MB90378 series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90378 series has an on-chip 32-bit accumulator which enables processing of long-word data. *1 : F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED. *2 : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
■ PACKAGE
144-pin plastic LQFP
(FPT-144P-M12)
MB90378 Series
■ FEATURES
• Clock • Embedded PLL clock multiplication circuit • Operating clock (PLL clock) can selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz to 20 MHz) • Minimum instruction execution time of 50 ns (at oscillation of 5 MHz, four times the PLL clock, operation at VCC of 3.3 V) • CPU addressing space of 16 Mbytes Internal 24-bit addressing • Instruction set optimized for controller applications • Rich data types (bit, byte, word, long word) • Rich addressing mode (23 types) • High code efficiency • Enhanced precision calculation realized by the 32-bit accumulator • Instruction set designed for high level language (C) and multi-task operations • Adoption of system stack pointer • Enhanced pointer indirect instructions • Barrel shift instructions • Program patch function (2 address pointer) • Improved execution speed 4-byte instruction queue • Powerful interrupt function • Priority level programmable : 8 levels • 32 factors of stronger interrupt function • Automatic data transmission function independent of CPU operation • Extended intelligent I/O service function (EI2OS) • Maximum 16 channels • Low-power consumption (standby) mode • Sleep mode (mode in which CPU operating clock is stopped) • Timebase timer mode (mode in which operations other than timebase timer and watch timer are stopped) • Stop mode (mode in which all oscillations are stopped) • CPU intermittent operation mode • Watch mode • Dual operation flash Upper and lower banks of flash memory can be used to execute erase/program and read operation concurrently (MB90F378) • Package LQFP-144 (FPT-144P-M12 : 0.4 mm pitch) • Process CMOS technology
2
MB90378 Series
■ PRODUCT LINEUP
Part number Parameter Classification ROM size RAM size MB90F378 Flash type ROM 128 Kbytes (112 Kbytes + 16 Kbytes) Dual operation 6 Kbytes Number of instruction : 351 Minimum execution time : 50 ns/5 MHz (PLL x 4) Addressing mode : 23 Data bit length : 1, 8, 16 bits Maximum memory space : 16 Mbytes I/O port (Nch) I/O port (CMOS) I/O port (CMOS with pull-up control) Total : 25 : 68 : 32 : 125 MB90V378 ⎯ ⎯ 15.6 Kbytes
CPU function
I/O port
16-bit reload timer 8/16-bit PPG timer 16-bit PPG timer Bit decoder Parity generator PS/2 interface
Reload timer : 6 channels Reload mode, single-shot mode or event count mode selectable PPG timer : 2 channels (8-bit mode, 4 channels) PPG timer : 3 channels PWM mode or single-shot mode selectable Bit decoder : 1 channel Parity generator : 1 channel Selectable odd/even parity PS/2 interface : 3 channels 4 selectable sampling clocks LPC bus interface Universal peripheral Interface GA20 output control Data buffer array : 1 channel : 4 channels : for UPI ch 0 only : 80 bytes
LPC interface
Serial IRQ controller
Serial IRQ request : 6 channels LPC clock monitor/control With full-duplex double buffer (variable data length) Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively used I2C (SMbus compliant) : 1 channel Support I2C bus of PHILIPS and the SMbus proposed by Intel I2C bus Selectable packet error check Timeout detection function Multi-address I2C (SMbus compliant) : 1 channel Support I2C bus of PHILIPS and the SMbus proposed by Intel I2C bus Selectable packet error check Timeout detection function 6 addresses support ALERT function (Continued) 3
UART
I2C
Multi-address I2C
MB90378 Series
(Continued) Part number Parameter Bridge circuit DTP/external interrupt Extended external interrupt Key-on wake-up interrupt 8/10-bit A/D converter 8-bit D/A converter LCD controller/driver Low-power consumption Process Package Operating voltage LQFP-144 (FPT-144P-M12 : 0.4 mm pitch) 2.7 V to 3.6 V at 20 MHz* MB90F378 MB90V378
Three bus connection routes can be switched by I2C/multi-address I2C 8 independent channels Selectable causes : Rise/fall edge, fall edge, “L” level or “H” level 8 multiplex channels × 2 set Selectable causes : Rise/fall edge, fall edge, rise edge or “L” level 8 independent channels Causes : “L” level 8/10-bit resolution : 12 channels Conversion time : Less than 4.2 µs (20 MHz internal clock) 8-bit resolution : 2 channels Up to 9 SEG × 4 COM Selectable LCD output or CMOS I/O port Stop mode/Sleep mode/CPU intermittent operation mode/Watch mode CMOS PGA299
* : Varies with conditions such as the operating frequency (see “■ ELECTRICAL CHARACTERISTICS”). Assurance for the MB90V378 is given only for operation with a tool at power supply voltage of 2.7 V to 3.6 V, an operating temperature of 0 °C to +25 °C, and an operating frequency of 1 MHz to 20 MHz.
■ PACKAGE AND CORRESPONDING PRODUCTS
Package FPT-144P-M12 PGA299 X : Available : Not available X MB90F378 MB90V378 X
Note : For more information about each package, see “■ PACKAGE DIMENSIONS”.
■ DIFFERENCES AMONG PRODUCTS
Memory size In evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. The following items must be taken into consideration. • The MB90V378 does not have an internal ROM, however, operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the development tool. • In the MB90V378, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH are mapped to bank FF only. (This setting can be changed by the development tool configuration.) • In the MB90F378, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH are mapped to bank FF only. 4
MB90378 Series
■ PIN ASSIGNMENT
TOP VIEW
P37/ADTG P36 P35 P34 P33/PG11 P32/PG10 P31/PG01 P30/PG00 P27 P26 P25 P24 P23 P22 P21 X1 X0 VSS VCC P20 P17 P16 P15 P14 P13 P12 P11 P10 P07/KSI7 P06/KSI6 P05/KSI5 P04/KSI4 P03/KSI3 P02/KSI2 P01/KSI1 P00/KSI0
P40/PSCK0 P41/PSDA0 P42/PSCK1 P43/PSDA1 P44/PSCK2 P45/PSDA2 P46/CLKRUN P47/SERIRQ P50/GA20 P51/LFRAME P52/LRESET P53/LCK P54/LAD0 P55/LAD1 P56/LAD2 P57/LAD3 RST VCC VSS X0A X1A PA0/EEI0 PA1/EEI1 PA2/EEI2 PA3/EEI3 PA4/EEI4 PA5/EEI5 PA6/EEI6 PA7/EEI7 P83/INT6 P84/INT7 P85 P86 PB0/EEI8 PB1/EEI9 PB2/EEI10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
LQFP-144
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
P77/PPG1 P76/UI3 P75/UO3 P74/UCK3 P73/UI2 P72/UO2 P71/UCK2 P70/UI1 P67/UO1 P66/UCK1 P65/INT5 P64/INT4 P63/INT3 P62/INT2 P61/INT1 P60/INT0 PD7/PPG3 VSS VCC PF7/V3* PF6/V2* PF5/V1* PF4/COM3* PF3/TO6/COM2* PF2/TIN6/COM1* PF1/TO5/COM0* PF0/TIN5/SEG8* PE7/TO4/SEG7 PE6/TIN4/SEG6 PE5/TO3/SEG5 PE4/TIN3/SEG4 PE3/TO2/SEG3 PE2/TIN2/SEG2 PE1/TO1/SEG1 PE0/TIN1/SEG0 P82/ALERT
* : Heavy current pins
PB3/EEI11 PB4/EEI12 PB5/EEI13 PB6/EEI14 PB7/EEI15 AVCC AVR AVSS PC0/AN0 PC1/AN1 PC2/AN2 PC3/AN3 PC4/AN4 PC5/AN5 PC6/AN6 PC7/AN7 PD0/AN8 VCC VSS MD2 MD1 MD0 PD1/AN9 PD2/AN10 PD3/AN11 PD4/DA1 PD5/DA2 PD6/PPG2 P90/SCL2 P91/SDA2 P92/SCL3 P93/SDA3 P94/SCL4 P95/SDA4 P80/SCL1 P81/SDA1
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
(FPT-144P-M12)
5
MB90378 Series
■ PIN DESCRIPTION
Pin no. LQFP-144 128,129 20,21 17 58, 57, 56 Pin name X0,X1 X0A,X1A RST MD0 to MD2 P00 to P07 109 to 116 KSI0 to KSI7 D E E I/O circuit A A B C Pin status during reset Oscillating Main oscillation I/O pins. Oscillating Sub-clock oscillation I/O pins. Reset input External reset input pin. Mode input Input pin for operation mode specification. Connect this pin directly to Vcc or Vss. General-purpose I/O ports. Can be used as key-on wake-up interrupt input ch 0 to 7. Input is enabled when 1 is set in EICR : EN0 to 7 in standby mode. General-purpose I/O ports. General-purpose I/O ports. General-purpose I/O ports. E 8/16-bit PPG timer output pins. 8-bit x 2 channels mode use : Event output from PG00/PG01 16-bit x 1channel mode use : Event output from PG00 General-purpose I/O ports. E 8/16-bit PPG timer output pins. 8-bit x 2 channels mode use : Event output from PG10/PG11. 16-bit x 1channel mode use : Event output from PG10. Port input General-purpose I/O ports. General-purpose I/O port. External trigger input pin (ADTG) for the A/D converter. General-purpose Nch open-drain I/O port. F Serial clock I/O pin for PS/2 interface ch 0. This function is selected when PS/2 interface ch 0 is enabled. General-purpose Nch open-drain I/O port. F Serial data I/O pin for PS/2 interface ch 0. This function is selected when PS/2 interface ch 0 is enabled. General-purpose Nch open-drain I/O port. F Serial clock I/O pin for PS/2 interface ch 1. This function is selected when PS/2 interface ch 1 is enabled. General-purpose Nch open-drain I/O port. F Serial data I/O pin for PS/2 interface ch 1. This function is selected when PS/2 interface ch 1 is enabled. (Continued) Function
117 to 124 P10 to P17 125, P20 to P27 130 to 136 P30, P31 137, 138 PG00, PG01 P32, P33 139, 140 PG10, PG11
141 to 143 P34 to P36 144 P37 ADTG P40 1 PSCK0 P41 2 PSDA0 P42 3 PSCK1 P43 4 PSDA1
E E
6
MB90378 Series
Pin no. LQFP-144 5 Pin name P44 PSCK2 P45 6 PSDA2 P46 7 CLKRUN P47 8 SERIRQ P50 9 GA20 P51 10 LFRAME P52 11 LRESET P53 12 LCK P54 to P57 13 to 16 LAD0 to LAD3 P60 to P65 93 to 98 INT0 to INT5 P66 99 UCK1 I I H H H H Port input J H G F F Pin status during reset
I/O circuit
Function General-purpose Nch open-drain I/O port. Serial clock I/O pin for PS/2 interface ch 2. This function is selected when PS/2 interface ch 2 is enabled. General-purpose Nch open-drain I/O port. Serial data I/O pin for PS/2 interface ch 2. This function is selected when PS/2 interface ch 2 is enabled. General-purpose Nch open-drain I/O port. LPC clock status / restart request I/O pin for serial IRQ controller. This function is selected when serial IRQ and LPC clock restart request is enabled. General-purpose I/O port. Serial IRQ data I/O pin for serial IRQ controller. This function is selected when serial IRQ is enabled. General-purpose Nch open-drain I/O port. GA20 output for LPC interface. This function is selected when GA20 function is enabled. General-purpose I/O port. LFRAME input for LPC interface. This function is selected when LPC interface is enabled. General-purpose I/O port. Reset input for LPC interface. This function is selected when LPC interface is enabled. General-purpose I/O port. Clock input for LPC interface. This function is selected when LPC interface is enabled. General-purpose I/O ports. Address/Data I/O for LPC interface. This function is selected when LPC interface is enabled. General-purpose I/O ports. Can be used as DTP/external interrupt request input ch 0 to 5. Input is enabled when 1 is set in ENIR: EN0 to 5 in standby mode. General-purpose I/O port. Serial clock I/O pin for UART ch 1. This function is enabled when UART ch 1 enables clock output. (Continued)
7
MB90378 Series
Pin no. LQFP-144 100 Pin name P67 UO1 P70 101 UI1 P71 102 UCK2 P72 103 UO2 P73 104 UI2 P74 105 UCK3 P75 106 UO3 P76 107 UI3 P77 108 PPG1 P80 SCL1 P81 SDA1 I I I I I Port input I I I I Pin status during reset General-purpose I/O port. Serial data output pin for UART ch 1. This function is enabled when UART ch 1 enables data output. General-purpose I/O port. Serial data input pin for UART ch 1. While UART ch 1 is operating for input, the input of this pin is used as required and must not be used for any other input. General-purpose I/O port. Serial clock I/O pin for UART ch 2. This function is enabled when UART ch 2 enables clock output. General-purpose I/O port. Serial data output pin for UART ch 2. This function is enabled when UART ch 2 enables data output. General-purpose I/O port. Serial data input pin for UART ch 2. While UART ch 2 is operating for input, the input of this pin is used as required and must not be used for any other input. General-purpose I/O port. Serial clock I/O pin for UART ch 3. This function is enabled when UART ch 3 enables clock output. General-purpose I/O port. Serial data output pin for UART ch 3. This function is enabled when UART ch 3 enables data output. General-purpose I/O port. Serial data input pin for UART ch 3. While UART ch 3 is operating for input, the input of this pin is used as required and must not be used for any other input. General-purpose I/O port. Output pin for PPG ch 1. This function is enabled when PPG ch 1 output is enabled. General-purpose Nch open-drain I/O port. Serial clock I/O pin for multi-address I2C. General-purpose Nch open-drain I/O port. Serial data I/O pin for multi-address I2C. (Continued)
I/O circuit
Function
71 72
T T
8
MB90378 Series
Pin no. LQFP-144 73 Pin name P82 ALERT P83, P84 30, 31 32 33 65 66 67 68 69 70 INT6, INT7 P85 P86 P90 SCL2 P91 SDA2 P92 SCL3 P93 SDA3 P94 SCL4 P95 SDA4 PA0 to PA7 22 to 29 EEI0 to EEI7 PB0 to PB7 34 to 41 EEI8 to EEI15 PC0 to PC7 45 to 52 AN0 to AN7 PD0 to PD3 AN8 to AN11 M M A/D input I I I I I T T T Port input T T T Pin status during reset
I/O circuit J
Function General-purpose Nch open-drain I/O port. ALERT output pin for multi-address I2C. General-purpose I/O ports. Can be used as DTP/external interrupt request input ch6, 7. Input is enabled when 1 is set in ENIR: EN6, 7 in standby mode. General-purpose I/O port. General-purpose I/O port. General-purpose Nch open-drain I/O port. Serial clock I/O pin for bridge circuit. General-purpose Nch open-drain I/O port. Serial data I/O pin for bridge circuit. General-purpose Nch open-drain I/O port. Serial clock I/O pin for bridge circuit. General-purpose Nch open-drain I/O port. Serial data I/O pin for bridge circuit. General-purpose Nch open-drain I/O port. Serial clock I/O pin for bridge circuit. General-purpose Nch open-drain I/O port. Serial data I/O pin for bridge circuit. General-purpose I/O ports. External IRQ input pin for Extend External Interrupt request ch0 to 7. When IRQ detect, prepare to the CPU Interrupt. (Multiplex) General-purpose I/O ports. External IRQ input pin for Extend External Interrupt request ch8 to 15. When IRQ detect, prepare to the CPU Interrupt. (Multiplex) General-purpose I/O ports. A/D converter analog input pin 0 to 7. This function is enabled when the analog input specification is enabled (ADER1). General-purpose I/O ports. A/D converter analog input pin 8 to 11. This function is enabled when the analog input specification is enabled (ADER2). (Continued)
53, 59 to 61
9
MB90378 Series
Pin no. LQFP-144 62, 63 Pin name PD4, PD5 DA1, DA2 PD6, PD7 64, 92 PPG2, PPG3 PE0 74 SEG0 TIN1 PE1 75 SEG1 TO1 PE2 76 SEG2 TIN2 PE3 77 SEG3 TO2 PE4 78 SEG4 TIN3 PE5 79 SEG5 TO3 PE6 80 SEG6 TIN4 O O O O O Port input O O H N Pin status during reset
I/O circuit
Function General-purpose I/O ports. D/A converter analog output 1, 2. This function is selected when D/A converted is enabled. General-purpose I/O ports. Output pin for PPG ch 2, 3. This function is selected when PPG ch 2, 3 output is enabled. General-purpose I/O port. Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. External clock input pin for reload timer 1. General-purpose I/O port. Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. Event output pin for reload timer 1. General-purpose I/O port. Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. External clock input pin for reload timer 2. General-purpose I/O port. Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. Event output pin for reload timer 2. General-purpose I/O port. Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. External clock input pin for reload timer 3. General-purpose I/O port. Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. Event output pin for reload timer 3. General-purpose I/O port. Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. External clock input pin for reload timer 4. (Continued)
10
MB90378 Series
(Continued) Pin no. LQFP-144 Pin name PE7 81 SEG7 TO4 PF0 82 SEG8 TIN5 PF1 83 COM0 TO5 PF2 84 COM1 TIN6 PF3 85 COM2 TO6 PF4 86 COM3 PF5 to PF7 V1 to V3 42 43 44 19,55,91, 127 18,54,90, 126 AVCC AVR AVSS VSS VCC R S R – – Source Power input Power input P P P P Port input P O I/O circuit Pin status during reset General-purpose I/O port. Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. Event output pin for reload timer 4. General-purpose Nch Open-drain I/O port. Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. External clock input pin for reload timer 5. General-purpose Nch Open-drain I/O port. COM output pin for LCD controller/driver. This function is selected when LCD COM output is enabled. Event output pin for reload timer 5. General-purpose Nch Open-drain I/O port. COM output pin for LCD controller/driver. This function is selected when LCD COM output is enabled. External clock input pin for reload timer 6. General-purpose Nch Open-drain I/O port. COM output pin for LCD controller/driver. This function is selected when LCD COM output is enabled. Event output pin for reload timer 6. General-purpose Nch Open-drain I/O port. COM output pin for LCD controller/driver. This function is selected when LCD COM output is enabled. General-purpose Nch Open-drain I/O ports. Q Power input Power input pin for LCD controller/driver. This function is selected when external voltage divider is enabled. Vcc power input pin for analog circuits. Vref+ input pin for the A/D converter. This voltage must not exceed Vcc. Vref- is fixed to AVSS. Vss power input pin for analog circuits. Power (0 V) input pin. Power (3.3 V) input pin. Function
87 to 89
11
MB90378 Series
■ I/O CIRCUIT TYPE
Type
X1/X1A Nch Pch Pch
Circuit
Xout
Remarks
A
X0/X0A
Nch
Main/Sub clock (main/sub clock crystal oscillator) • At an oscillation feedback resistor of approximately 1 MΩ
Standby mode control
B
R
• CMOS hysteresis input • Pull-up resistor approximately 50 kΩ
CMOS hysteresis input
• CMOS hysteresis input C
CMOS hysteresis input
R
Pch
Pull-up control
Pch
Pout Nout CMOS hysteresis input Standby mode control
D
Nch
• CMOS output • CMOS hysteresis input • Selectable pull-up resistor approximately 50 kΩ • IOL = 4 mA
R
Pch
Pull-up control
Pch
Pout Nout CMOS input Standby mode control
E
Nch
• CMOS output • CMOS input • Selectable pull-up resistor approximately 50 kΩ • IOL = 4 mA
Nch
F
Nch
Nout CMOS hysteresis input Standby mode control
• • • •
Nch open-drain output CMOS hysteresis input IOL = 4 mA 5 V tolerant
(Continued)
12
MB90378 Series
Type
Pch
Circuit
Remarks • Nch open-drain output • CMOS input • IOL = 4 mA
Nout CMOS input
G
Nch
Standby mode control
Pch
Pout Nout CMOS input Standby mode control
• CMOS output • CMOS input • IOL = 4 mA
H
Nch
Pch
Pout Nout CMOS hysteresis input Standby mode control
• CMOS output • CMOS hysteresis input • IOL = 4 mA
I
Nch
Nch
J
Nch
Nout CMOS input Standby mode control
• • • •
Nch open-drain output CMOS input IOL = 4 mA 5 V tolerant
Pch
Pout Nout CMOS input Standby mode control Analog input
M
Nch
• • • •
CMOS output CMOS input A/D analog input IOL = 4 mA
(Continued)
13
MB90378 Series
Type
Pch
Circuit • • • •
Remarks CMOS output CMOS input D/A analog output IOL = 4 mA
Pout Nout CMOS input Standby mode control Analog input
N
Nch
Pch
Pout Nout CMOS hysteresis input
O
Nch
• • • •
CMOS output CMOS hysteresis input Segment output IOL = 4 mA
R
Standby mode control Segment output
Nch
P
Nch
Nout CMOS hysteresis input
• • • •
Nch open-drain output CMOS hysteresis input Segment output IOL = 12 mA
R
Standby mode control Segment output
Nch
Q
Nch
Nout CMOS hysteresis input Standby mode control LCD driving power supply
• • • •
Nch open-drain output CMOS hysteresis input LCD driving power supply IOL = 12 mA
(Continued)
14
MB90378 Series
(Continued) Type Circuit Remarks • Power supply input protection circuit
Pch
R
Nch
IN
Pch
Analog input enable IN
• A/D converter reference voltage (AVR) input pin with protection circuit
S
Nch
Analog input enable
Nch
T
Nch
Nout CMOS input Standby mode control
• • • •
Nch open-drain output CMOS input IOL = 4 mA 5 V tolerant
15
MB90378 Series
■ HANDLING DEVICES
1. Be sure that the maximum rated voltage is not exceeded (latch-up prevention).
A latch-up may occur on a CMOS IC if a voltage higher than VCC or lower than VSS is applied to an input or output pin other than medium-to-high voltage pins. A latch-up may also occur if a voltage higher than the rating is applied between VCC pin and VSS pin. A latch-up causes a rapid increase in the power supply current, which can result in thermal damage to an element. Take utmost care that the maximum rated voltage is not exceeded. When turning the power on or off to analog circuits, be sure that the analog supply voltages (AVCC, AVR) and analog input voltage do not exceed the digital supply voltage (VCC).
2. Stabilize the supply voltages
Even within the operation guarantee range of the VCC supply voltage, a malfunction can be caused if the supply voltage undergoes a rapid change. For voltage stabilization guidelines, the VCC ripple fluctuations (P-P value) at commercial frequencies (50 Hz to 60 Hz) should be suppressed to "10%" or less of the reference VCC value. During a momentary change such as when switching a supply voltage, voltage fluctuations should also be suppressed so that the "transient fluctuation rate" is 0.1 V/ms or less.
3. Power-on
To prevent a malfunction in the built-in voltage drop circuit, secure "50 µs (between 0.2 V and 1.8 V)" or more for the voltage rise time during power-on.
4. Treatment of unused input pins
An unused input pin may cause a malfunction if it is left open. Every unused input pin should be pulled up or down.
5. Treatment of A/D converter, and D/A converter power pin
When the A/D converter, D/A converter and comparator is not used, connect the pins as follows: AVCC = VCC, AVSS = AVR = VSS.
6.
Notes on external clock
When an external clock is used, the oscillation stabilization wait time is required at power-on reset or at cancellation of sub-clock mode or stop mode. As shown in diagram below, when an external clock is used, connect only the X0 pin and leave the X1 pin open.
X0 MB90378 series Open X1
16
MB90378 Series
7. Power supply pins
When a device has two or more VCC or VSS pins, the pins that should have equal potential are connected within the device in order to prevent a latch-up or other malfunction. To reduce extraneous emission, to prevent a malfunction of the strobe signal due to an increase in the group level, and to maintain the local output current rating, connect all these power supply pins to an external power supply and ground them. The current source should be connected to the VCC and VSS pins of the device with minimum impedance. It is recommended that a bypass capacitor of about 0.1 µF be connected near the terminals between VCC and VSS.
8. Analog power-on sequence of A/D converter and D/A converter
The power to the A/D converter and D/A converter (AVCC, AVR) and analog inputs (AN0 to AN11) must be turned on after the power to the digital circuits (VCC) is turned on. When turning off the power, turn off the power to the digital circuits (VCC) after turning off the power to the A/D converter, D/A converter and analog inputs. When the power is turned on or off, AVR should not exceed AVCC. Also, when a pin that is used for A/D analog input is also used as an input port, the input voltage should not exceed AVCC. (The power to the analog circuits and the power to the digital circuits can be simultaneously turned on or off.)
17
MB90378 Series
■ BLOCK DIAGRAM
CPU F2MC-16LX family core Other pins VSS x 4, VCC x4, MD0 to MD2, AVCC, AVSS, AVR
X0, X0A X1, X1A RST
Clock control circuit Reset circuit (Watchdog timer) Interrupt controller Timebase timer
Delayed interrupt generator Nch open-drain I/O port 8, 9 I2C bus (Multi-address) I2C bus P80/SCL1 P81/SDA1 P82/ALERT P90/SCL2 P91/SDA2 P92/SCL3 P93/SDA3 P94/SCL4 P95/SDA4
6
P00/KSI0 to P07/KSI7 P10 to P17 P20 to P27 P30/PG00 to P33/PG11 P34 to P36 P37/ADTG P40/PSCK0 P41/PSDA0 P42/PSCK1 P43/PSDA1 P44/PSCK2 P45/PSDA2 P46/CLKRUN P47/SERIRQ
8
CMOS I/O port 0, 1, 2, 3*
8 8 8 8 6
Key-on wake-up interrupt 8/16-bit PPG timer (ch1, ch2)
Nch open-drain I/O port 4 (P47 is CMOS I/O port)
Bridge circuit CMOS I/O port A, B, 8 Extend external interrupt 1 (8 channels)
6 2
8
8 8
3ch PS/2 interface Serial IRQ (6 channels) LPC Interface
PA0/EEI0 to PA7/EEI7 PB0/EEI8 to PB7/EEI15 P83/INT6 P84/INT7 P85 P86
F2MC-16LX bus
8 Extend external interrupt 2 (8 channels)
P50/GA20 P51/LFRAME P52/LRESET P53/LCK P54/LAD0 P55/LAD1 P56/LAD2 P57/LAD3
DTP/external interrupt (ch6, ch7)
2
Bus interface
GA20 control
UPI (ch0, ch1, ch2, ch3)
7
8/10-bit A/D converter (12 channels) 8-bit D/A converter (2 channels) 16-bit PPG (ch2, ch3) CMOS I/O port C, D
12
Nch open-drain I/O P50 CMOS I/O P51 to P57
2
P60/INT0 to P65/INT5 P66/UCK1 P67/UO1 P70/UI1 P71/UCK2 P72/UO2 P73/UI2 P74/UCK3 P75/UO3 P76/UI3 P77/PPG1
6
6 3 3 6
DTP/external interrupt ch0, 1, 2, 3, 4, 5 UART (ch1, ch2, ch3) 16-bit PPG (ch1) CMOS I/O port 6, 7 RAM 6KB FLASH 128 KB Mirroring Flash security
PC0/AN0 to PC7/AN7 PD0/AN8 to PD3/AN11 PD4/DA1 PD5/DA2 PD6/PPG2 PD7/PPG3
2
CMOS I/O port E Nch open-drain I/O port F
16-bit reload timer
(ch1, ch2, ch3, ch4, ch5, ch6)
6 6
LCD controller/driver (9SEG x 4COM)
16
PE0/TIN1/SEG0 PE1/TO1/SEG1 PE2/TIN2/SEG2 PE3/TO2/SEG3 PE4/TIN3/SEG4 PE5/TO3/SEG5 PE6/TIN4/SEG6 PE7/TO4/SEG7 PF0/SEG8/TIN5* PF1/COM0/TO5* PF2/COM1/TIN6* PF3/COM2/TO6* PF4/COM3* PF5/V1* to PF7/V3*
* : P00 to P07, P10 to P17, P20 to P27, P30 to P37 : With resistors that can be used as input pull-up resistors. PF0 to PF7 : High current pins
18
MB90378 Series
■ MEMORY MAP
Single-chip mode (with ROM mirroring function) FFFFFFH ROM area Address #1
FC0000H
010000H ROM area (FF bank image) Address #2 004000H 003F80H Address #3 Peripheral area RAM area 000100H 0000F8H 000000H Peripheral area : Access not allowed : Internal access memory
Register
Model MB90F378 MB90V378
Address #1 FE0000H FE0000H*
Address #2 004000H 004000H*
Address #3 001900H 003F80H
* : The MB90V378 does not contain ROM. Assume that the development tool uses these area for its ROM decode areas. Notes : • If single-chip mode (without ROM mirroring function) is selected, see Chapter 32, "ROM Mirroring Function Selection Module" of the MB90378 series H/W manual. • ROM data in the FF bank can be seen as an image in the higher 00 bank to validate the small model C compiler. Because addresses of the 16 low-order bits in the FF bank are the same, the table in ROM can be referenced without the "far" specification. For example, when 00C000H is accessed, the contents of ROM at FFC000H are actually accessed. The ROM area in the FF bank exceeds 48 Kbytes, and all areas cannot be seen as images in the 00 bank. Because ROM data from FF4000H to FFFFFFH is seen as an image at 004000H to 00FFFFH, the ROM data table should be stored in the area from FF4000H to FFFFFFH.
19
MB90378 Series
■ F2MC-16LX CPU PROGRAMMING MODEL
• Dedicated registers
AH
AL USP SSP PS PC DPR PCB DTB USB SSB ADB 8-bit 16-bit 32-bit
Accumulator (A) User Stack Pointer (USP) System Stack Pointer (SSP) Processor Status (PS) Program Counter (PC) Direct Page Register (DPR) Program Bank Register(PCB) Data Bank Register (DTB) User Stack Bank Register (USB) System Stack Bank Register (SSB) Additional Data Bank Register (ADB)
• General-purpose registers
CPU Dedicated register Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register Internal bus RAM RAM
General-purpose register
20
MB90378 Series
• Processor status (PS)
15 PS Default value 7 Default value ILM 000 6 I 0 5 S 1 4 T X 13 12 RP 00000 3 N X 2 Z X 1 V X 0 C X : CCR 87 CCR -01XXXXX 0
B4 B3 B2 B1 B0 Default value 0 0 0 0 0
: RP
ILM2 Default value 0
ILM1 0
ILM0 0
: ILM
- : Not used X : Undefined
21
MB90378 Series
■ I/O MAP
Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH 00000CH 00000DH 00000EH 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H 00001AH 00001BH 00001CH 00001DH 00001EH 00001FH Abbreviation PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PDRB PDRC PDRD PDRE PDRF DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 PGDR PGCSR DDRA DDRB DDRC DDRD DDRE DDR8 Register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Port B data register Port C data register Port D data register Port E data register Port F data register Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Parity generator data register Parity generator control status register Port A direction register Port B direction register Port C direction register Port D direction register Port E direction register Port 8 direction register Byte Word Resource name access access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Port C Port D Port E Port F Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Parity generator Port A Port B Port C Port D Port E Port 8 Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB X1111111B XXXXXXX1B XXXXXXXXB XXXXXXXXB -XXXX111B --111111B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 11111111B 00000000B 00000000B 00000000B 00000000B 0-------B 0000000-B 00000000B 00000000B XXXXXXXXB X------0B 00000000B 00000000B 00000000B 00000000B 00000000B -0000---B (Continued)
22
MB90378 Series
Address 000020H 000021H 000022H 000023H 000024H 000025H 000026H 000027H 000028H 000029H 00002AH 00002BH 00002CH 00002DH 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 00003FH
Abbreviation SMR1 SCR1 SIDR1/ SODR1 SSR1 M2CR1 CDCR1 ENIR EIRR ELVR ADER1 ADER2 BRSR ADC0 ADCR0 ADCR1 ADCS0 ADCS1 SICRL SICRH SIFR1 SIFR2 SIFR3 SIFR4 PDCRL1 PDCRH1 PCSRL1 PCSRH1 PDUTL1 PDUTH1 PCNTL1 PCNTH1
Register Serial mode register 1 Serial control register 1 Input data register 1/ Output data register 1 Serial status register 1 Mode 2 control register 1 Clock division control register 1 Interrupt/DTP enable register Interrupt/DTP cause register Request level setting register Analog input enable register 1 Analog input enable register 2 Bridge circuit selection register A/D control register A/D data register A/D control status register Serial interrupt request register Serial interrupt control register Serial interrupt frame number register 1 Serial interrupt frame number register 2 Serial interrupt frame number register 3 Serial interrupt frame number register 4 PPG1 down counter register PPG1 period setting register PPG1 duty setting register PPG1 control status register
Byte Word Resource name access access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R W W W W R/W R/W 16-bit PPG timer (ch1) Serial IRQ 8/10-bit A/D converter Port C, A/D Port D, A/D Bridge circuit DTP/external interrupt Communication prescaler 1 UART1
Initial value 00000-00B 00000100B XXXXXXXXB 00001000B ----1000B 00--0000B 00000000B XXXXXXXXB 00000000B 00000000B 11111111B ----1111B --000000B 00000000B XXXXXXXXB 00000-XXB 00--------B 00000000B 00000000B 00000000B --000000B --000000B --000000B --000000B 11111111B 11111111B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB --000000B 00000000B (Continued) 23
MB90378 Series
Address 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H 000059H 00005AH 00005BH 00005CH 00005DH
Abbreviation PDCRL2 PDCRH2 PCSRL2 PCSRH2 PDUTL2 PDUTH2 PCNTL2 PCNTH2 PDCRL3 PDCRH3 PCSRL3 PCSRH3 PDUTL3 PDUTH3 PCNTL3 PCNTH3 PSCR0 PSSR0 PSCR1 PSSR1 PSCR2 PSSR2 PSDR0 PSDR1 PSDR2 PSMR DAT0 DAT1 DACR0 DACR1
Register PPG2 down counter register PPG2 period setting register PPG2 duty setting register PPG2 control status register PPG3 down counter register PPG3 period setting register PPG3 duty setting register PPG3 control status register PS/2 interface control register 0 PS/2 interface status register 0 PS/2 interface control register 1 PS/2 interface status register 1 PS/2 interface control register 2 PS/2 interface status register 2 PS/2 interface data register 0 PS/2 interface data register 1 PS/2 interface data register 2 PS/2 interface mode register D/A converter data register 0 D/A converter data register 1 D/A control register 0 D/A control register 1
Byte Word Resource name access access ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ R/W R/W ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R W W W W R/W R/W R R W W W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8-bit D/A converter 3-channel PS/2 interface 16-bit PPG timer (ch3) 16-bit PPG timer (ch2)
Initial value 11111111B 11111111B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB --000000B 00000000B 11111111B 11111111B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB --000000B 00000000B 0--00000B 00000000B 0--00000B 00000000B 0--00000B 00000000B 00000000B 00000000B 00000000B ----0000B XXXXXXXXB XXXXXXXXB -------0B -------0B (Continued)
24
MB90378 Series
Address 00005EH 00005FH 000060H 000061H 000062H 000063H 000064H 000065H 000066H 000067H 000068H 000069H 00006AH 00006BH 00006CH 00006DH 00006EH 00006FH 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H
Abbreviation UPAL1 UPAH1 UPAL2 UPAH2 UPAL3 UPAH3 UPCL UPCH UPDI0/ UPDO0 UPS0 UPDI1/ UPDO1 UPS1 UPDI2/ UPDO2 UPS2 UPDI3/ UPDO3 UPS3 LCR ROMM TMCSRL1 TMCSRH1 TMR1/ TMRD1 TMCSRL2 TMCSRH2 TMR2/ TMRD2
Register UPI1 address register (lower) UPI1 address register (upper) UPI2 address register (lower) UPI2 address register (upper) UPI3 address register (lower) UPI3 address register (upper) UPI control register (lower) UPI control register (upper) UPI0 data input register/ data output register UPI0 status register UPI1 data input register/ data output register UPI1 status register UPI2 data input register/ data output register UPI2 status register UPI3 data input register/ data output register UPI3 status register LPC control register ROM mirroring function selection register Timer control status register CH1 (lower) Timer control status register CH1 (upper) 16-bit timer/reload register CH1 Timer control status register CH2 (lower) Timer control status register CH2 (upper) 16-bit timer/reload register CH2
Byte Word Resource name access access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R/W ⎯ ⎯ R/W R/W ⎯ ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W 16-bit reload timer (ch2) 16-bit reload timer (ch1) ROM mirroring function LPC interface
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B -000-000B XXXXXXXXB 00000000B XXXXXXXXB 00000000B XXXXXXXXB 00000000B XXXXXXXXB 00000000B -----000B -------1B 00000000B ----0000B XXXXXXXXB XXXXXXXXB 00000000B ----0000B XXXXXXXXB XXXXXXXXB (Continued)
25
MB90378 Series
Address 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH 000090H to 00009DH 00009EH 00009FH
Abbreviation TMCSRL3 TMCSRH3 TMR3/ TMRD3 TMCSRL4 TMCSRH4 TMR4/ TMRD4 IBCRL IBCRH IBSRL IBSRH IDAR IADR ICCR ITCR ITOC ITOD ISTO IMTO RDR0 RDR1 RDR2 RDR3
Register Timer control status register CH3 (lower) Timer control status register CH3 (upper) 16-bit timer/reload register CH3 Timer control status register CH4 (lower) Timer control status register CH4 (upper) 16-bit timer/reload register CH4 I C bus control register (lower) I C bus control register (upper) I C bus status register (lower) I2C bus status register (upper) I2C data register I2C address register I C clock control register I C timeout control register I C timeout clock register I C timeout data register I C slave timeout register I2C master timeout register Port 0 pull-up resistor setting register Port 1 pull-up resistor setting register Port 2 pull-up resistor setting register Port 3 pull-up resistor setting register
2 2 2 2 2 2 2 2
Byte Word Resource name access access R/W R/W ⎯ ⎯ R/W R/W ⎯ ⎯ R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 I2C 16-bit reload timer (ch4) 16-bit reload timer (ch3)
Initial value 00000000B ----0000B XXXXXXXXB XXXXXXXXB 00000000B ----0000B XXXXXXXXB XXXXXXXXB ----0000B 00000000B 00000000B --000000B XXXXXXXXB -XXXXXXXB 0-000000B -0-00000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B
Prohibited area Program address detect control status register Delayed interrupt cause/ clear register Address match detection Delayed interrupt
PACSR DIRR
R/W R/W
R/W R/W
00000000B -------0B (Continued)
26
MB90378 Series
Address 0000A0H 0000A1H 0000A2H, 0000A3H 0000A4H 0000A5H to 0000A7H 0000A8H 0000A9H 0000AAH 0000ABH 0000ACH 0000ADH 0000AEH 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH
Abbreviation LPMCR CKSCR
Register Low-power consumption mode register Clock selection register
Byte Word Resource name access access R/W R/W Prohibited area R/W R/W Low-power consumption control register
Initial value 00011000B 11111100B
CKMC
Clock modulation control register
R/W
R/W
Clock modulation
-------0B
Prohibited area WDTC TBTC WTC Watchdog control register Timebase timer control register Watch timer control register Wake-up interrupt control register Wake-up interrupt flag register Flash memory control status register Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 R/W R/W R/W R/W R/W R/W Watchdog timer Timebase timer Watch timer X-XXX111B 1--00100B 10001000B
Prohibited area EICR EIFR FMCS R/W R/W R/W R/W R/W R/W Key-on wake-up interrupt Flash memory interface circuit 00000000B -------0B 000X0000B
Prohibited area ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B (Continued)
27
MB90378 Series
Address 0000C0H 0000C1H 0000C2H 0000C3H 0000C4H 0000C5H 0000C6H 0000C7H 0000C8H 0000C9H 0000CAH 0000CBH 0000CCH 0000CDH 0000CEH 0000CFH 0000D0H 0000D1H 0000D2H 0000D3H 0000D4H 0000D5H 0000D6H 0000D7H 0000D8H 0000D9H 0000DAH 0000DBH 0000DCH 0000DDH 0000DEH 0000DFH 0000E0H
Abbreviation MBCRL MBCRH MBSRL MBSRH MDAR MALR MADR1 MADR2 MADR3 MADR4 MADR5 MADR6 MCCR MTCR MTOC MTOD MSTO MMTO SMR2 SCR2 SIDR2/ SODR2 SSR2 M2CR2 CDCR2 EENR1 EERR1 EELR1 EENR2 EERR2 EELR2 PDL3
Register MI2C bus control register (lower) MI2C bus control register (upper) MI2C bus status register (lower) MI C bus status register (upper) MI C data register MI2C alert register MI2C address register 1 MI C address register 2 MI C address register 3 MI2C address register 4 MI2C address register 5 MI C address register 6 MI C clock control register MI2C timeout control register MI2C timeout clock register MI C timeout data register MI C slave timeout register MI2C master timeout register Serial mode register 2 Serial control register 2 Input data register 2/ output data register 2 Status register 2 Mode 2 control register 2 Clock division control register 2 Interrupt enable register Interrupt cause register Request level setting register Interrupt enable register Interrupt cause register Request level setting register Port 3 data latch register
2 2 2 2 2 2 2 2
Byte Word Resource name access access R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port 3 data latch Extend External Interrupt 2 Extend External Interrupt 1 Communication prescaler 2 UART2 Multi-address I2C
Initial value ----0000B 00000000B 00000000B --000000B XXXXXXXXB ----0000B -XXXXXXXB -XXXXXXXB -XXXXXXXB -XXXXXXXB -XXXXXXXB -XXXXXXXB 0-000000B -0-00000B 00000000B 00000000B 00000000B 00000000B 00000-00B 00000100B XXXXXXXXB 00001000B ----1000B 00--0000B 00000000B XXXXXXXXB 00000000B 00000000B 00000000B XXXXXXXXB 00000000B 00000000B 00000000B (Continued)
28
MB90378 Series
Address 0000E1H 0000E2H 0000E3H 0000E4H 0000E5H 0000E6H 0000E7H 0000E8H 0000E9H 0000EAH 0000EBH 0000ECH 0000EDH 0000EEH 0000EFH 0000F0H to 0000F4H 0000F5H to 0000F7H 0000F8H to 0000FFH 000100H to 0018FFH 001FF0H 001FF1H 001FF2H
Abbreviation BDR BRRL BRRH SMR3 SCR3 SIDR3 / SODR3 SSR3 M2CR3 CDCR3 TMCSRL5 TMCSRH5 TMR5/ TMRD5 LCRL LCRH VRAM
Register Bit data register Bit result register (lower) Bit result register (upper) Serial mode register 3 Serial control register 3 Input data register 3/ output data register 3 Status register 3 Mode 2 control register 3 Clock division control register 3 Timer control status register CH5 (lower) Timer control status register CH5 (upper) 16-bit timer/reload register CH5 LCD control register 0 LCD control register 1 LCD display RAM
Byte Word Resource name access access R/W R R R/W R/W R/W R/W R/W R/W R/W R/W ⎯ ⎯ R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W LCD controller/driver 16-bit reload timer (ch5) Communication prescaler 3 UART3 Bit decoder
Initial value ----XXXXB XXXXXXXXB XXXXXXXXB 00000-00B 00000100B XXXXXXXXB 00001000B ----1000B 00--0000B 00000000B ----0000B XXXXXXXXB XXXXXXXXB 00010000B 00000000B XXXXXXXXB
Prohibited area
External area
Prohibited area (RAM area) Program address detection register 0 PADR0 Program address detection register 1 Program address detection register 2
R/W R/W R/W
R/W R/W R/W Address match detection
XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued)
29
MB90378 Series
Address 001FF3H 001FF4H 001FF5H 001FF6H to 003F7FH 003F80H 003F81H 003F82H 003F83H 003F84H 003F85H 003F86H 003F87H 003F88H 003F89H 003F8AH 003F8BH 003F8CH 003F8DH 003F8EH 003F8FH 003F90H 003F91H 003F92H 003F93H 003F94H 003F95H 003F96H 003F97H 003F98H 003F99H 003F9AH 003F9BH
Abbreviation
Register Program address detection register 3
Byte Word Resource name access access R/W R/W R/W R/W R/W R/W Address match detection
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB
PADR1
Program address detection register 4 Program address detection register 5
Prohibited area UDRL10 UDRH10 UDRL11 UDRH11 UDRL12 UDRH12 UDRL13 UDRH13 UDRL14 UDRH14 UDRL15 UDRH15 UDRL16 UDRH16 UDRL17 UDRH17 UDRL18 UDRH18 UDRL19 UDRH19 UDRL1A UDRH1A UDRL1B UDRH1B UDRL1C UDRH1C UDRL1D UDRH1D UP data register 10 (lower) UP data register 10 (upper) UP data register 11 (lower) UP data register 11 (upper) UP data register 12 (lower) UP data register 12 (upper) UP data register 13 (lower) UP data register 13 (upper) UP data register 14 (lower) UP data register 14 (upper) UP data register 15 (lower) UP data register 15 (upper) UP data register 16 (lower) UP data register 16 (upper) UP data register 17 (lower) UP data register 17 (upper) UP data register 18 (lower) UP data register 18 (upper) UP data register 19 (lower) UP data register 19 (upper) UP data register 1A (lower) UP data register 1A (upper) UP data register 1B (lower) UP data register 1B (upper) UP data register 1C (lower) UP data register 1C (upper) UP data register 1D (lower) UP data register 1D (upper) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W LPC data buffer array-Extend XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued)
30
MB90378 Series
Address 003F9CH 003F9DH 003F9EH 003F9FH 003FA0H 003FA1H 003FA2H 003FA3H 003FA4H 003FA5H to 003FAEH 003FAFH 003FB0H 003FB1H 003FB2H 003FB3H 003FB4H 003FB5H 003FB6H 003FB7H to 003FBFH 003FC0H 003FC1H 003FC2H 003FC3H 003FC4H 003FC5H 003FC6H 003FC7H 003FC8H 003FC9H
Abbreviation UDRL1E UDRH1E UDRL1F UDRH1F DBACLR
Register UP data register 1E (lower) UP data register 1E (upper) UP data register 1F (lower) UP data register 1F (upper) Data buffer array clear register
Byte Word Resource name access access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W LPC data buffer array LPC data buffer array-Extend
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB -----000B
Prohibited area FWR0 FWR1 SSR0 FLASH programming control register 0 FLASH programming control register 1 Sector switching register R/W R/W R/W Prohibited area PCKCR PRLL2 PRLH2 PRLL3 PRLH3 PPGC2 PPGC3 PCS23 PLL clock control register PPG reload register (lower) PPG reload register (upper) PPG reload register (lower) PPG reload register (upper) PPG control register ch2 PPG control register ch3 PPG clock control register W R/W R/W R/W R/W R/W R/W R/W Prohibited area UDRL0 UDRH0 UDRL1 UDRH1 UDRL2 UDRH2 UDRL3 UDRH3 UDRL4 UDRH4 UP data register 0 (lower) UP data register 0 (upper) UP data register 1 (lower) UP data register 1 (upper) UP data register 2 (lower) UP data register 2 (upper) UP data register 3 (lower) UP data register 3 (upper) UP data register 4 (lower) UP data register 4 (upper) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W LPC data buffer array XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) W R/W R/W R/W R/W R/W R/W R/W 8/16-bit PPG timer 2 PLL XXXX0000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000001B 00000001B 000000XXB R/W R/W R/W Dual operating FLASH 00000000B 00000000B 00XXXXX0B
31
MB90378 Series
Address 003FCAH 003FCBH 003FCCH 003FCDH 003FCEH 003FCFH 003FD0H 003FD1H 003FD2H 003FD3H 003FD4H 003FD5H 003FD6H 003FD7H 003FD8H 003FD9H 003FDAH 003FDBH 003FDCH 003FDDH 003FDEH 003FDFH 003FE0H 003FE1H 003FE2H 003FE3H 003FE4H 003FE5H 003FE6H 003FE7H 003FE8H 003FE9H 003FEAH 003FEBH 003FECH 003FEDH
Abbreviation UDRL5 UDRH5 UDRL6 UDRH6 UDRL7 UDRH7 UDRL8 UDRH8 UDRL9 UDRH9 UDRLA UDRHA UDRLB UDRHB UDRLC UDRHC UDRLD UDRHD UDRLE UDRHE UDRLF UDRHF DNDL0 DNDH0 DNDL1 DNDH1 DNDL2 DNDH2 DNDL3 DNDH3 DNDL4 DNDH4 DNDL5 DNDH5 DNDL6 DNDH6
Register UP data register 5 (lower) UP data register 5 (upper) UP data register 6 (lower) UP data register 6 (upper) UP data register 7 (lower) UP data register 7 (upper) UP data register 8 (lower) UP data register 8 (upper) UP data register 9 (lower) UP data register 9 (upper) UP data register A (lower) UP data register A (upper) UP data register B (lower) UP data register B (upper) UP data register C (lower) UP data register C (upper) UP data register D (lower) UP data register D (upper) UP data register E (lower) UP data register E (upper) UP data register F (lower) UP data register F (upper) DOWN data register 0 (lower) DOWN data register 0 (upper) DOWN data register 1 (lower) DOWN data register 1 (upper) DOWN data register 2 (lower) DOWN data register 2 (upper) DOWN data register 3 (lower) DOWN data register 3 (upper) DOWN data register 4 (lower) DOWN data register 4 (upper) DOWN data register 5 (lower) DOWN data register 5 (upper) DOWN data register 6 (lower) DOWN data register 6 (upper)
Byte Word Resource name access access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R R LPC data buffer array
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued)
32
MB90378 Series
(Continued) Address 003FEEH 003FEFH 003FF0H 003FF1H 003FF2H, 003FF3H 003FF4H 003FF5H 003FF6H 003FF7H 003FF8H 003FF9H 003FFAH 003FFBH 003FFCH 003FFDH 003FFEH 003FFFH TMCSRL6 TMCSRH6 TMR6/ TMRD6 PRLL0 PRLH0 PRLL1 PRLH1 PPGC0 PPGC1 PCS01 Abbreviation DNDL7 DNDH7 DBAAL DBAAH Register DOWN data register 7 (lower) DOWN data register 7 (upper) Data buffer array address register (lower) Data buffer array address register (upper) Byte Word Resource name access access R R R/W R/W Prohibited area Timer control status register CH6 (lower) Timer control status register CH6 (upper) 16-bit timer/reload register CH6 PPG reload register (lower) PPG reload register (upper) PPG reload register (lower) PPG reload register (upper) PPG control register ch0 PPG control register ch1 PPG clock control register R/W R/W ⎯ ⎯ R/W R/W R/W R/W R/W R/W R/W Prohibited area R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8/16-bit PPG timer 1 16-bit reload timer (ch6) 00000000B ----0000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000001B 00000001B 000000XXB R R R/W R/W LPC data buffer array Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
• Meaning of abbreviations used for reading and writing R/W : Readable and writable R : Read-only W : Write-only • Explanation of initial values 0 : The bit is initialized to 0. 1 : The bit is initialized to 1. X : The initial value of the bit is undefined. - : The bit is not used. Its initial value is undefined. • Instruction using IO addressing e.g. MOV A, io, is not supported for registers area 003F80H to 003FFFH.
33
MB90378 Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt cause Reset INT9 instruction Exception processing A/D converter conversion termination Timebase timer UPI0 IBF/LPC reset UPI1 IBF UPI2 IBF UPI3 IBF DTP/ext. interrupt channels 0/1 detection DTP/ext. interrupt channels 2/3 detection DTP/ext. interrupt channels 4/5 detection Key-on wake-up interrupt detection UPI0/1/2/3 OBE 16-bit PPG timer 1 / 8/16-bit PPG timer 0/1 PS/2 interface 0/1 PS/2 interface 2 Watch timer I C transfer complete / bus error 16-bit PPG timer 2/3 DTP/ext. interrupt channels 6/7 detection Multi-address I2C transfer complete / bus error Extend External Interrupt 00 to 07/08 to 15 I C timeout / standby wake-up 16-bit reload timer 1/2/5 underflow Multi-address I2C timeout / standby wake-up 16-bit reload timer 3/4/6 underflow UART1 receive UART1 send UART2 receive UART2 send UART3 receive UART3 send Flash memory status Delayed interrupt generator module
2 2
EI2OS support × × ×
Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H
Interrupt control register ICR ⎯ ⎯ ⎯ ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 Address ⎯ ⎯ ⎯ 0000B0H*1 0000B1H*1 0000B2H*1 0000B3H*1 0000B4H*1 0000B5H*2 0000B6H*1 0000B7H*1 0000B8H*1
Priority*2 High
ICR09
0000B9H*1
ICR10 ICR11 ICR12 ICR13 ICR14 ICR15
0000BAH*1 0000BBH*1 0000BCH*1 0000BDH*1 0000BEH*1 0000BFH*1
Low (Continued)
34
MB90378 Series
(Continued) × : : : : Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal. Cannot be used. Can be used and support the EI2OS stop request. Can be used.
*1 : • For peripheral functions that share the ICR register, the interrupt level will be the same. • If the extended intelligent I/O service is to be used with a peripheral function that shares the ICR register with another peripheral function, the service can be started by either of the function. And if EI2OS clear is supported, both interrupt request flags for the two interrupt causes are cleared by EI2OS interrupt clear signal. It is recommended to mask either of the interrupt request during the use of EI2OS. • EI2OS service cannot be started multiple times simultaneously. Interrupt other than the operating interrupt is masked during EI2OS operation. It is recommended to mask either of the interrupt requests during the use of EI2OS. *2 : This priority is applied when interrupts of the same level occur simultaneously.
35
MB90378 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Rating
Parameter Power supply voltage*1 A/D converter reference input voltage*1 LCD power supply voltage*1 Input voltage*1 Output voltage*
1
Symbol VCC AVCC AVR V1 to V3 VI1 VI2 VO ICLAMP Σ|ICLAMP| IOL1 IOL2 IOLAV1
Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 − 2.0 ⎯ ⎯ ⎯ ⎯ Max VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 6.0 VSS + 4.0 + 2.0 20 10 20 4
Unit V V V V V V V mA mA mA mA mA VCC ≥ AVCC *2
Remarks
AVCC ≥ AVR, AVR ≥ AVSS V1 to V3 must not exceed VCC All pins except P40 to P45, P80 to P82, P90 to P95 *3 P40 to P45, P80 to P82, P90 to P95 *3 *5 *5 All pins except PF0 to PF7 *4 PF0 to PF7 *4 All pins except PF0 to PF7 Average output current = operating current × operating efficiency PF0 to PF7 Average output current = operating current × operating efficiency
Maximum clamp current Total maximum clamp current “L” level maximum output current
“L” level average output current IOLAV2 “L” level total maximum output current “L” level total average output current “H” level maximum output current “H” level average output current “H” level total maximum output current “H” level total average output current Power consumption Operating temperature Storage temperature ΣIOL ΣIOLAV IOH IOHAV ΣIOH ΣIOHAV PD TA Tstg ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ − 40 − 55 12 mA
100 50 − 10 −3 − 100 − 50 200 + 85 + 150
mA mA mA mA mA mA mW °C °C (Continued) Average output current = operating current × operating efficiency Average output current = operating current × operating efficiency *4 Average output current = operating current × operating efficiency
36
MB90378 Series
(Continued) *1 : This parameter is based on VSS = AVSS = 0.0 V. *2 : Set AVCC and VCC at the same voltage. Take care so that AVR does not exceed VCC + 0.3 V when the power is turned on. *3 : VI and VO shall never exceed VCC + 0.3 V. *4 : The maximum output current is a peak value for a corresponding pin. *5 : • Use within recommended operating conditions. • Use at DC voltage (current). • The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the Vcc pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to poerate the power-on reset. • Care must be taken not to leave the +B input pin open. • Note that analog system input/output pins other than the A/D input pins (LCD drive pins, etc.) cannot accept +B signal input. • Sample recommended circuits : • Input/output equivalent circuits
Protective diode
VCC
Limiting resistance +B input (0 V to 16 V)
Pch
Nch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
37
MB90378 Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V) Parameter Power supply voltage *2 A/D converter reference input voltage *3 LCD power supply voltage Operating temperature Symbol VCC VCC AVR Value Min 2.7 *1 1.8 0 Max 3.6 3.6 AVCC Unit V V V Remarks Normal operation assurance range Retains the RAM state in stop mode Normal operation assurance range V1 to V3 pins (The optimum value is dependent on the LCD element in use.)
V1 to V3 TA
VSS − 40
VCC + 85
V °C
*1 : The operating voltage varies with the operation frequency. *2 : Set AVCC and VCC at the same voltage. *3 : Take care so that AVR does not exceed VCC + 0.3 V when power is turned on. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
38
MB90378 Series
3. DC Characteristics
(VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name P10 to P17, P20 to P27, P30 to P37, P46, P47, P51 to P57, PC0 to PC7, PD0 to PD7 P00 to P07, P60 to P67, P70 to P77, P83 to P86, PA0 to PA7, PB0 to PB7, PE0 to PE7, PF0 to PF7, RST ⎯ VIHS5 P40 to P45 0.8 VCC ⎯ VSS + 5.5 V Condition Value Min 0.7 VCC Typ ⎯ Max VCC + 0.3 Unit Remarks
VIH
V
CMOS input pins
VIHS
0.8 VCC
⎯
VCC + 0.3
V
CMOS hysteresis input pins 5 V tolerant CMOS hysteresis input pins 5 V tolerant CMOS input pins SMbus input pins Mode pins CMOS input pins
“H” level input voltage
VIH5 VIHSM VIHM VIL
P50, P82 P80, P81, P90 to P95 MD0 to MD2 P10 to P17, P20 to P27, P30 to P37, P46, P47, P50 to P57, P82, PC0 to PC7, PD0 to PD7 P00 to P07, P40 to P45, P60 to P67, P70 to P77, P83 to P86, PA0 to PA7, PB0 to PB7, PE0 to PE7, PF0 to PF7, RST P80, P81, P90 to P95 MD0 to MD2 P40 to P45, P50, P80 to P82, P90 to P95 P46, PF0 to PF7 ⎯ ⎯
0.7 VCC 2.1 VCC − 0.3 VSS − 0.3
⎯ ⎯ ⎯ ⎯
VSS + 5.5 VSS + 5.5 VCC + 0.3 0.3 VCC
V V V V
“L” level input voltage
VILS
VSS − 0.3
⎯
0.2 VCC
V
CMOS hysteresis input pins SMbus input pins Mode pins
VILSM VILM Open-drain output pin application voltage “H” level output voltage “L” level output voltage VD5 VD
VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3
⎯ ⎯ ⎯ ⎯ ⎯
0.8 VSS + 0.3 VSS + 5.5 VCC + 0.3 ⎯
V V V V
VOH1
All port pins except P40 to P46, P50, VCC = 3.0 V VCC − 0.5 P80 to P82, P90 to P95, IOH1 = − 4.0 mA PF0 to PF7 All port pins except PF0 to PF7 PF0 to PF7 IOL1 = 4.0 mA IOL2 = 12.0 mA ⎯ ⎯
V
VOL1 VOL2
⎯ ⎯
0.4 0.4
V V (Continued)
39
MB90378 Series
Parameter Input leakage current (Hi-Z output leakage current) Open-drain output leakage current
Symbol
Pin name
Condition VCC = 3.3 V, VSS < VI < VCC
Value Min −5 Typ ⎯ Max 5
Unit
Remarks
IIL
All input pins P40 to P46, P50, P80 to P82, P90 to P95, PF0 to PF7
µA
ILEAK
⎯ VCC = 3.3 V, Internal operation at 20 MHz VCC = 3.3 V, Internal operation at 20 MHz, In sleep mode VCC = 3.3 V, External 32 kHz, Internal operation at 8 kHz, In sub-clock mode, TA = + 25 °C VCC = 3.3 V, External 32 kHz, Internal operation at 8 kHz, In sub-clock sleep mode, TA = + 25 °C VCC = 3.3 V, External 32 kHz, Internal operation at 8 kHz, In watch mode, TA = + 25 °C VCC = 3.3 V, Internal operation at 20 MHz, In timebase timer mode VCC = 3.3 V, In stop mode, TA = + 25 °C
⎯
⎯
5
µA
ICC
⎯
56
68
mA
ICCS
⎯
23
30
mA
ICCL Power supply current*
⎯
23
80
µA
VCC
ICCLS
⎯
10
50
µA
ICCWAT
⎯
1.5
30
µA
ICCT Power supply current* ICCH Input capacitance CIN All input pins except VCC, AVCC, VSS, AVSS VCC
⎯
2.0
3
mA
⎯ ⎯
1 10
20 80
µA pF (Continued)
⎯
40
MB90378 Series
(Continued) Parameter Symbol Pin name Condition Between VCC and V3 at VCC = 3.3 V LCD divided resistance RLCD ⎯ Between V3 and V2 Between V2 and V1 Between V1 and VSS at VCC = 3.3 V Value Min 100 Typ 200 Max 400 kΩ 50 100 200 Unit Remarks
COM0 to COM3 output impedance SEG0 to SEG8 output impedance LCD leakage current Pull-up resistance Pull-down resistance
RVCOM
COM0 to COM3 V1 to V3 = 3.3 V
⎯
⎯
5
kΩ
RVSEG
SEG0 to SEG8 V1 to V3, COM0 to COM3, SEG0 to SEG8 P00 to P07,P10 to P17, P20 to P27,P30 to P37, RST MD2
⎯
⎯
5
kΩ
LLCDL
⎯
⎯
⎯
±1
µA
RUP RDOWN
⎯ ⎯
25 25
50 50
100 100
kΩ kΩ MB90V378 only
* : The current value is preliminary value and may be subject to change for enhanced characteristics without previous notice. The power supply current is measured with an external clock.
41
MB90378 Series
4. AC Characteristics
(1) Clock Timings (VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Condition Value Min 3 Typ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 32.768 ⎯ 30.5 ⎯ ⎯ 15.2 ⎯ ⎯ 8.192 ⎯ 122.1 Max 16 Unit Remarks
× 1/2 (When PLL stops) MHz When using an oscillation circuit MHz MHz MHz MHz PLL × 1 When using an oscillation circuit PLL × 2 When using an oscillation circuit PLL × 3 When using an oscillation circuit PLL × 4 When using an oscillation circuit
4 4 4 4 Clock frequency fCH X0, X1 ⎯ 3
16 10 6.67 5
32
× 1/2 (When PLL stops) MHz When using an external clock MHz MHz MHz MHz kHz ns µs % ns µs ns Recommend duty ratio of 30% to 70% Recommend duty ratio of 30% to 70% External clock operation PLL × 1 When using an external clock PLL × 2 When using an external clock PLL × 3 When using an external clock PLL × 4 When using an external clock
4 4 4 4 fCL Clock cycle time Frequency fluctuation rate locked* Input clock pulse width Input clock rise/fall time Internal operating clock frequency Internal operating clock cycle time 42 tHCYL tLCYL ∆f PWH PWL PWHL PWLL tCR tCF fCP fLCP tCP tLCP X0A, X1A X0, X1 X0A, X1A ⎯ X0 X0A X0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 31.25 ⎯ ⎯ 5 ⎯ ⎯ 1.5 ⎯ 50 ⎯
20 10 6.67 5 ⎯ 333 ⎯ 5 ⎯ ⎯ 5 20 ⎯ 666 ⎯
MHz Main clock operation kHz Sub-clock operation ns µs Main clock operation Sub-clock operation
MB90378 Series
• X0, X1 clock timing
tHCYL
0.8 VCC X0 PWH tCF
0.8 VCC 0.2 VCC PWL tCR
0.8 VCC 0.2 VCC
• X0A, X1A clock timing
tLCYL
0.8 VCC X0A PWHL tCF
0.8 VCC 0.2 VCC PWLL tCR
0.8 VCC 0.2 VCC
43
MB90378 Series
• PLL operation guarantee range
Relationship between machine clock frequency and power supply voltage
Power supply voltage VCC (V)
3.6
3.0 2.7
1.5 3 4
16
20
Machine clock fCP (MHz) Operation guarantee range of PLL Normal operation guarantee range Guaranteed oscillation frequency range
Relationship between external clock frequency and machine clock frequency
Guaranteed oscillation frequency range
×3 ×2
20
×4
×1
Machine clock fCP (MHz)
16
× 1 (PLL off) 2
12
8
4
1.5 3 45 6.67 8 10 12 16 20 24 32
External clock FC (MHz)*
* : When using a crystal oscillator or a ceramic oscillator, the maximum oscillation clock frequency is 16 MHz. 44
MB90378 Series
The AC ratings are measured for the following measurement reference voltages : • Input signal waveform • Output signal waveform
Hysteresis input pin
Output pin
0.8 VCC 0.2 VCC
2.4 V 0.8 V
CMOS input pin
0.7 VCC 0.3 VCC
SMbus input pin
2.1 V 0.8 V
45
MB90378 Series
(2) Reset Input Timing (VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Condition Value Min 16 tCP Reset input time tRSTL RST ⎯ Oscillation time of oscillator* + 16 tCP Max ⎯ ⎯ Unit ns Remarks Normal operation In stop mode and sub-clock mode
ms
* : Oscillation time of oscillator is the time to reach to 90% of the oscillation amplitude from stand still. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR/ceramic oscillator, the oscillation time is between hundreds of µs to several ms. In the external clock, the oscillation time is 0 ms. Note : tCP is the internal operating clock cycle time. Refer to “(1) Clock Timings” rating for tCP .
• In stop mode
tRSTL
RST
0.2 VCC 90% of oscillation amplitude 0.2 VCC
X0
Internal operation clock
Oscillation time of oscillator
16 tCP Oscillation stabilization time Instruction execution
Internal reset
46
MB90378 Series
(3) Power-on Reset (VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Power supply rise time Power supply cut-off time Symbol Pin name Condition tR tOFF VCC* VCC* ⎯ Value Min ⎯ 1 Max 50 ⎯ Unit ms ms Due to repeated operations Remarks
* : VCC must be kept lower than 0.2 V before power-on. Notes : • The above values are used for causing a power-on reset. Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn on the power supply using the above values. • Make sure that power supply rises within the selected oscillation stabilization time. If the power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR 2.2 V 0.2 V VCC 0.2 V
tOFF
0.2 V
Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V or fewer per second, however, you can use the PLL clock.
VCC
1.8 V RAM data hold VSS
It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower.
47
MB90378 Series
(4) UART1 to UART3 (VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Serial clock cycle time UCK ↓ → UO delay time Valid UI → UCK ↑ UCK ↑ → valid UI hold time Serial clock “H” pulse width Serial clock “L” pulse width UCK ↓ → UO delay time Valid UI → UCK ↑ UCK ↑ → valid UI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name UCK1 to UCK3 UCK1 to UCK3, CL = 80 pF + 1 TTL UO1 to UO3 for an output pin of UCK1 to UCK3, internal shift clock UI1 to UI3 mode UCK1 to UCK3, UI1 to UI3 UCK1 to UCK3 UCK1 to UCK3 UCK1 to UCK3, CL = 80 pF + 1 TTL UO1 to UO3 for an output pin of external shift clock UCK1 to UCK3, mode UI1 to UI3 UCK1 to UCK3, UI1 to UI3 Condition Value Min 4 tCP −80 100 tCP 4 tCP 4 tCP ⎯ 60 60 Max ⎯ 80 ⎯ ⎯ ⎯ ⎯ 150 ⎯ ⎯ Unit Remarks ns ns ns ns ns ns ns ns ns
Notes : • These are AC ratings in the CLK synchronous mode. • CL is the load capacitance value connected to pins while testing. • tCP is the internal operating clock cycle time. Refer to “(1) Clock Timings” rating for tCP .
48
MB90378 Series
• Internal shift clock mode
tSCYC UCK 2.4 V 0.8 V tSLOV 0.8 V
2.4 V UO 0.8 V
tIVSH 0.8 VCC UI 0.2 VCC
tSHIX 0.8 VCC 0.2 VCC
• Internal shift clock mode
tSLSH UCK 0.8 VCC 0.2 VCC tSLOV 0.2 VCC 0.8 VCC tSHSL
2.4 V UO 0.8 V
tIVSH 0.8 VCC UI 0.2 VCC
tSHIX 0.8 VCC 0.2 VCC
49
MB90378 Series
(5) Resources Input Timing (VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Parameter Symbol Pin name Condition Unit Remarks Min Max Timer input pulse width tTIWH tTIWL TIN1 to TIN6 ⎯ 4 tCP ⎯ ns
Note : tCP is the internal operating clock cycle time. Refer to “(1) Clock Timings” rating for tCP .
0.8 VCC TIN1 to TIN6
0.8 VCC 0.2 VCC tTIWH tTIWL 0.2 VCC
(6) Trigger Input Timing (VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name ADTG, INT0 to INT7, EEI0 to EEI15, KSI0 to KSI7 Condition Value Min 5 tCP ⎯ 1 Max ⎯ ⎯ Unit ns µs Remarks Normal operation Stop mode
Input pulse width
tTRGH tTRGL
Note : tCP is the internal operating clock cycle time. Refer to “(1) Clock Timings” rating for tCP .
INT0 to INT7 EEI0 to EEI15 KSI0 to KSI7
0.8 VCC
0.8 VCC 0.2 VCC tTRGH tTRGL 0.2 VCC
0.7 VCC ADTG
0.7 VCC 0.3 VCC tTRGH tTRGL 0.3 VCC
50
MB90378 Series
(7) I2C / Multi-address I2C Timing (VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Start condition output Stop condition output Start condition detect Stop condition detect Restart condition output Restart condition detect SCL output “L” width SCL output “H” width SDA output delay SDA output setup time after interrupt SCL input “L” pulse SCL input “H” pulse SDA output setup time SDA hold time Symbol Pin name tSTA tSTO tSTA tSTO tSTASU tSTASU tLOW tHIGH tDO tDOSU tLOW tHIGH tSU tHO SCL, SDA SCL, SDA SCL, SDA SCL, SDA SCL, SDA SCL, SDA SCL SCL SDA SDA SCL SCL SDA SDA Value Min Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *1 *2 Master mode Master mode Master mode Remarks Master mode Master mode
tCP (m x n/2 − 1) − 20 tCP (m x n/2 − 1) + 20 tCP (m x n/2 + 3) - 20 tCP + 40 tCP + 40 tCP (m x n/2 + 3) + 20 ⎯ ⎯
tCP (m x n/2 + 3) − 20 tCP (m x n/2 + 3) + 20 tCP + 40 tCP x m x n/2 − 20 ⎯ tCP x m x n/2 + 20
tCP (m x n/2 + 2) − 20 tCP (m x n/2 + 2) + 20 tCP x 3 − 20 tCP x m x n/2 − 20 tCP x 4 − 20 tCP x 3 + 40 tCP + 40 40 0 tCP x 3 + 20 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
. Notes : • tCP is the internal operating clock cycle time. Refer to “(1) Clock Timings” rating for tCP • m is the setting bit of shift clock oscillation defined in the “ICCR register (CS4, CS3)” and “MCCR register (CS4, CS3)”. Please refer to the MB90378 series H/W manual for details. • n is the setting bit of shift clock oscillation defined in the “ICCR register (CS2 to CS0)” and “MCCR register (CS2 to CS0)”. Please refer to the MB90378 series H/W manual for details. • tDOSU is shown in the interrupt time is longer than the “L” width of SCL. • SDA and SCL output value is specified on condition that the rise/fall time is “0 ns”. *1 : At the stop condition or transferring of next byte. *2 : After setting register bit IBCRH : SCC at restart.
51
MB90378 Series
• Data transmit (master/slave)
tDO tSU tHO tDOSU
tDO
SDA tSTASU tSTA tLOW tHO 1
ACK
SCL
9
• Data receive (master/slave)
tSU
tHO
tDO ACK
tDO
tDOSU
SDA tHIGH 6 7 tLOW 8
tSTO 9
SCL
52
MB90378 Series
(8) PS/2 Interface Timing (VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter PSCK clock cycle time PSCK↓ → PSDA Valid PSDA → PSCK↓ PSCK↓ → valid PSDA hold time PSCK clock “H” pulse width PSCK clock “L” pulse width Symbol tPCYC tPLOV tPIVSH tPHIX tPHSL tPLSH Pin name PSCK0 to PSCK2, PSDA0 to PSDA2 Condition ⎯ Value Min 4 tCP 2 tCP 1 tCP Reception Mode 1 tCP 2 tCP ⎯ 2 tCP ⎯ ⎯ ns ⎯ ⎯ ⎯ ⎯ ns ns Typ ⎯ ⎯ ⎯ Max ⎯ ⎯ ⎯ Unit Remarks ns ns ns
PSCK0 to PSCK2, Transmission Mode PSDA0 to PSDA2 PSCK0 to PSCK2, PSDA0 to PSDA2 PSCK0 to PSCK2, PSDA0 to PSDA2 PSCK0 to PSCK2, PSDA0 to PSDA2 PSCK0 to PSCK2, PSDA0 to PSDA2
Note : tCP is the internal operating clock cycle time. Refer to “(1) Clock Timings” rating for tCP .
tPCYC
PSCK0 PSCK1 PSCK2
0.8 VCC 0.2 VCC
0.8 VCC
• Transmission Mode
PSDA0 PSDA1 PSDA2
tPLOV
2.4 V 0.8 V
• Reception Mode
PSDA0 PSDA1 PSDA2
tPIVSH 0.8 VCC 0.2 VCC
tPHIX
53
MB90378 Series
(9) LPC Timing (VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter LCLK cycle time LCLK high time LCLK low time Symbol tCYCLE tHIGH tLOW Pin name ⎯ ⎯ ⎯ Condition ⎯ ⎯ ⎯ Value Min 30 12 12 Typ ⎯ ⎯ ⎯ Max ⎯ ⎯ ⎯ Unit Remarks ns ns ns
• LCLK AC timing
tCYCLE tHIGH 0.7 VCC 0.3 VCC LCLK tLOW
54
MB90378 Series
Parameter Output valid delay Float to active delay Active to float delay Input setup time Input hold time
Symbol Pin name Condition tVAL tON tOFF tS tH ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Value Min 2 2 ⎯ 7 0 Typ ⎯ ⎯ ⎯ ⎯ ⎯ Max 12 ⎯ 28 ⎯ ⎯
Unit ns ns ns ns ns
Remarks
• LAD, LFRAME, GA20 AC timing
0.4 VCC
LCLK
tVAL
OUTPUT Delay tON Tri-state OUTPUT tOFF
0.4 VCC
LCLK tS tH
INPUT
55
MB90378 Series
5. A/D Converter Electrical Characteristics
(2.7 V ≤ AVR − AVSS, VCC = AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Resolution Total error Non-linear error Differential linearity error Zero transition voltage Full-scale transition voltage Symbol ⎯ ⎯ ⎯ ⎯ Pin name ⎯ ⎯ ⎯ ⎯ AN0 to AN11 AN0 to AN11 Value Min ⎯ ⎯ ⎯ ⎯ AVSS − 1.5 LSB AVR − 3.5 LSB Typ ⎯ ⎯ ⎯ ⎯ AVSS + 0.5 LSB AVR − 1.5 LSB Max 10 ± 3.0 ± 2.5 ± 1.9 AVSS + 5.5 LSB AVSS + 2.5 LSB AVR + 0.5 LSB Unit bit LSB LSB LSB For MB90V378 mV For MB90F378 mV Actual value is specified as a sum of values specified in ADCR0 : CT1, CT0 and ADCR0 : ST1, ST0. Be sure that the setting value is greater than the min value Actual value is specified in ADCR0 : ST1, ST0 bits. Be sure that the setting value is greater than the min value Remarks
VOT
VFST
Conversion time
⎯
⎯
3.1
⎯
⎯
µs
Sampling period Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Offset between channels
⎯
⎯ AN0 to AN11 AN0 to AN11 AVR AVCC AVR AN0 to AN11
2
⎯
⎯
µs
IAIN VAIN ⎯ IA IAH IR IRH —
⎯ AVSS AVSS + 2.7 ⎯ ⎯ ⎯ ⎯ ⎯
0.1 ⎯ ⎯ 1.4 ⎯ 94 ⎯ ⎯
10 AVR AVCC 6.4 5 300 5 4
µA V V mA µA µA µA LSB * *
*: The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVR = 3.0 V).
56
MB90378 Series
6. A/D Converter Glossary
Resolution : Analog changes that are identifiable with the A/D converter. Linearity error : The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics. Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value. Total error : The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error.
Total error
3FFH 3FEH 3FDH Actual conversion value 0.5 LSB
Digital output
{1 LSB × (N − 1) + 0.5 LSB}
004H 003H 002H 001H AVRL Analog input
VNT (Measured value) Actual conversion value Theoretical characteristics 0.5 LSB AVRH
Total error for digital output N = 1 LSB (Theoretical value) =
VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVR − AVss [V] 1024
[LSB]
VOT (Theoretical value) = AVss + 0.5 LSB [V] VFST (Theoretical value) = AVR − 1.5 LSB [V] VNT : Voltage at a transition of digital output from (N − 1) to N
(Continued)
57
MB90378 Series
(Continued) Linearity error
3FFH 3FEH 3FDH Digital output Actual conversion value {1 LSB × (N − 1) + VOT } VFST (Measured value) Digital output N VNT (Measured value) Actual conversion value N+1
Differential linearity error
Theoretical characteristics Actual conversion value
004H 003H 002H
N−1
V (N + 1) T (Measured value) VNT (Measured value)
Theoretical characteristics 001H VOT (Measured value) AVRL Analog input AVRH
N−2
Actual conversion value AVRH Analog input
AVRL
Linearity error of = digital output N
VNT − {1 LSB × (N − 1) + VOT} 1 LSB − 1 [LSB] [V]
[LSB]
Differential linearity error V (N + 1) T − VNT = 1 LSB of digital output N 1 LSB = VFST − VOT 1022
VOT : Voltage at transition of digital output from “000H” to “001H” VFST : Voltage at transition of digital output from “3FEH” to “3FFH”
58
MB90378 Series
7. Notes on Using A/D Converter
• About the external impedance of the analog input and its sampling time • A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sampling and hold capacitor is insufficient, adversely affecting A/D conversion precision. • Analog input circuit model
R
Analog input ↑ During sampling : ON Comparator
C
Note : The values are reference values.
MB90F378/V378
R 1.9 kΩ (Max)
C 25 pF (Max)
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. • The relationship between the external impedance and minimum sampling time [External impedance = 0 kΩ to 100 kΩ]
100 90
[External impedance = 0 kΩ to 20 kΩ]
20 18
External impedance (kΩ)
External impedance (kΩ)
80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35
16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8
MB90F378/V378
MB90F378/V378
Minimum sampling time (µs)
Minimum sampling time (µs)
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. • About errors As |AVR − AVSS| becomes smaller, values of relative errors grow larger.
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MB90378 Series
8. D/A Electrical Characteristics
(VCC = AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Resolution Differential linearity error Non-linearity error Conversion time Analog output impedance Power supply current Symbol Pin name ⎯ ⎯ ⎯ ⎯ ⎯ IDVR IDVRS ⎯ ⎯ ⎯ ⎯ ⎯ AVCC AVCC ⎯ Condition Value Min ⎯ ⎯ ⎯ ⎯ 2.0 ⎯ ⎯ Typ 8 ⎯ ⎯ 0.6 2.9 ⎯ 0.1 Max ⎯ ± 0.9 ± 1.5 ⎯ 3.8 460 ⎯ Unit bit LSB LSB µs kΩ µA µA D/A stops * Remarks
* : With load capacitance is 20 pF.
9. Serial IRQ Electrical Characteristics
(VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter “H” level input voltage “L” level input voltage “H” level output voltage “L” level output voltage Symbol Pin name Condition VIH VIL VOH VOL ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Value Min 0.7 VCC VSS VCC − 0.5 ⎯ Typ ⎯ ⎯ ⎯ ⎯ Max VCC 0.3 VCC ⎯ 0.4 Unit V V V V Remarks
10. Flash Memory Program/Erase Characteristics
Parameter Sector erase time (4 Kbytes sector) Sector erase time (16 Kbytes sector) Chip erase time Byte (8-bit width) programing time Program/Erase cycle ⎯ TA = +25 °C VCC = 3.0 V Condition Value Min ⎯ ⎯ ⎯ ⎯ 10,000 Typ 0.2 0.5 4.6 32 ⎯ Max 0.5 7.5 ⎯ 3,600 ⎯ Unit s s s µs cycle Remarks Excludes 00H programming prior to erasure Excludes 00H programming prior to erasure Excludes 00H programming prior to erasure Except for the over head time of the system
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MB90378 Series
■ EXAMPLE CHARACTERISTICS (MB90F378)
• Power Supply Current
ICC [mA]
50.0
TA = +25 [°C] Fcin = 16 MHz
ICCS [mA]
18.0
TA = +25 [°C] Fcin = 16 MHz
16.0
40.0
Fcin = 12 MHz Fcin = 10 MHz
14.0
Fcin = 12 MHz
12.0
30.0
Fcin = 10 MHz
Fcin = 8 MHz
10.0
Fcin = 8 MHz
20.0
8.0
Fcin = 4 MHz
10.0
6.0
Fcin = 4 MHz
4.0
Fcin = 2 MHz
2.0
Fcin = 2 MHz
0.0 2.0 2.5 3.0 3.5
0.0 2.0 2.5 3.0 3.5
VCC [V]
4.0
VCC [V]
4.0
2.5
ICCH [µA]
TA = +25 [°C]
2.0
1.5
1.0
0.5
0.0 2.5 3.0 3.5 4.0
VCC [V]
(Continued)
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MB90378 Series
(Continued)
2.0
VCC − VOH1 [V]
TA = +25 [°C]
0.7
VCC − VOH2 [V]
TA = +25 [°C]
0.6 1.5 0.5
VCC = 2.5 [V] VCC = 2.5 [V]
1.0 0.4 0.3 0.2 0.1
VCC = 3.0 [V] VCC = 3.5 [V] VCC = 4.0 [V]
VCC = 3.0 [V] VCC = 3.5 [V] VCC = 4.0 [V]
0.5
0.0 0 −2 −4 −6 −8 −10
IOH1 [mA]
0.0 0 −2 −4 −6 −8 −10
IOH2 [mA]
VOL1 [V]
0.8
TA = +25 [°C]
VOL2 [V]
0.3
TA = +25 [°C]
VCC = 2.5 [V]
0.6
VCC = 3.0 [V] VCC = 4.0 [V] VCC = 3.5 [V]
0.2
0.4
VCC = 2.5 [V] VCC = 3.0 [V] VCC = 3.5 [V] VCC = 4.0 [V]
0.1 0.2
0.0 0 2 4 6 8 10
IOL1 [mA]
0.0 0 2 4 6 8 10
IOL2 [mA]
62
MB90378 Series
■ ORDERING INFORMATION
Part number MB90F378PFF-GE1 Package 144-pin Plastic LQFP (FPT-144P-M12) Remarks
63
MB90378 Series
■ PACKAGE DIMENSION
144-pin plastic LQFP (FPT-144P-M12)
18.00±0.20(.709±.008)SQ +0.40 +.016 *16.00 –0.10 .630 –.004 SQ
108 73
Note 1) * : These dimensions include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
109
72
0.08(.003)
Details of "A" part 1.50 –0.10 .059 –.004
+0.20 +.008
(Mounting height)
INDEX
0~8˚
144 37
"A" 0.60±0.15 (.024±.006) 0.10±0.05 (.004±.002) (Stand off) 0.25(.010)
LEAD No.
1
36
+0.05 +.002 –.001
0.40(.016)
0.18±0.035 .007±.001
0.07(.003)
M
0.145 –0.03 .006
C
2003 FUJITSU LIMITED F144024S-c-3-3
Dimensions in mm (inches). Note: The values in parentheses are reference values.
64
MB90378 Series
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
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