MB90497GPF

FUJITSU SEMICONDUCTOR DATA SHEET DS07-13713-3E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90495G Series MB90497G/F497G/F498G/V495G s DESCRIPTION The MB90495G Series is a general-purpose, high-performance 16-bit microcontroller. It was designed for devices like consumer electronics, which require high-speed, real-time process control. This series features an on-chip full-CAN interface. In addition to being backwards compatible with the F2MC* family architecture, the instruction set has been expanded to add support for high-level language instructions, expanded addressing mode, and enhanced multiply/ divide and bit processing instructions. A 32-bit accumulator is also provided, making it possible to process long word (32-bit) data. The MB90495G Series peripheral resources include on chip 8/10-bit A/D converter, UART (SCI) 0/1, 8/16-bit PPG timer, 16-bit I/O timer (16-bit free-run timer, input capture 0, 1, 2, 3 (ICU) ) , and CAN controller. * : F2MC is abbreviation for Fujitsu Flexible Microcontroller. F2MC is a registered trademark of Fujitsu Limited. s FEATURES • Models that support +125 °C • Clock •Built-in PLL clock multiplier circuit •Choose 1/2 oscillation clock or ×1 to ×4 multiplied oscillation clock (for a 4-MHz oscillation clock, 4 to 16 MHz) machine (PLL) clock (Continued) s PACKAGES 64-pin plastic QFP 64-pin plastic LQFP (FPT-64P-M06) (FPT-64P-M09) MB90495G Series (Continued) •Select subclock behavior (8.192 kHz) •Minimum instruction execution time : 62.5 ns (operating with 4-MHz oscillation clock and × 4 PLL clock) • 16-MByte CPU memory space •24-bit internal addressing •External access possible through selection of 8/16-bit bus width (external bus mode) • Optimum instruction set for controller applications •Wealth of data types (Bit, Byte, Word, Long Word) •Wealth of addressing modes (23 different modes) •Enhanced signed multiply-divide instructions and RETI instruction functions •Enhanced high-precision arithmetic employing 32-bit accumulator • Instruction set supports high-level programming language (C) and multitasking •Employs system stack pointer •Enhanced indirect instructions with all pointer types •Barrel shift instructions • Improved execution speed •4-byte instruction queue • Powerful interrupt feature •Powerful 8-level, 34-condition interrupt feature • CPU-independent automated data forwarding •Extended intelligent I/O service feature (EI2OS) : maximum 16 channels • Low-power consumption (Standby) Mode •Sleep mode (CPU operation clock stopped) •Time-base timer mode (oscillation clock and subclock, time-base timer and watch timer only operational) •Watch mode (subclock and watch timer only operational) •Stop mode (oscillation clock and subclock stopped) •CPU intermittent operation mode • Process •CMOS technology • I/O Ports •Generic I/O ports (CMOS output) : 49 • Timer •Time-base timer, watch timer, watchdog timer : 1 channel •8/16-bit PPG timer : four 8-bit channels, or two 16-bit channels •16-bit reload timer : 2 channels •16-bit I/O timer •16-bit free-run timer : 1 channel •16-bit input capture (ICU) : 4 channels Generates interrupt requests by latching onto the count value of the 16-bit free-run timer with pin input edge detection (Continued) 2 MB90495G Series (Continued) • CAN Controller : 1 channel •CAN specifications conform to versions 2.0A and 2.0B •8 on-chip message buffers •Forwarding rate 10 Kbps to 1 Mbps (with 16-MHz machine clock) • UART0 (SCI) /UART1 (SCI) : 2 channels •All with full duplex double buffer •Use clock-asynchronous or clock-synchronous serial forwarding • DTP/external interrupt : 8 channels •A module for launching extended intelligent I/O service (EI2OS) and generating external interrupts through external output • Delayed interrupt generation module •Generates interrupt requests for switching tasks • 8/10-bit A/D converter : 8 channels •Switch between 8-bit and 10-bit resolution •Launch through external trigger input •Conversion time : 6.13 µs (with 16-MHz machine clock, including sampling time) • Program batch function •2-address pointer ROM correction • Clock output function 3 MB90495G Series s PRODUCT LINEUP Part Number Paarmeter Feature Classification ROM Size RAM Size Process Package Operating Power Emulator power supply* Number of instructions Instruction bit length Instruction length Data bit length  : 351 : 8-bit, 16-bit : 1 to 7 bytes : 1 bit, 8-bit, 16-bit MB90F497G FLASH ROM MB90497G Mask ROM 2 Kbytes CMOS LQFP64 (width 0.65 mm) , QFP64 (width 1.0 mm) 4.5 V to 5.5 V None PGA256 MB90F498G FLASH ROM 128 Kbytes MB90V495G Product Evaluated  6 Kbytes 64 Kbytes CPU Functions Minimum execution time : 62.5 ns (with 16-MHz machine clock) Interrupt processing time : minimum 1.5 µs (with 16-MHz machine clock) Low-power consumption (Standby) Mode I/O Ports Time-base timer Sleep mode/watch mode/time-base timer mode/stop mode / CPU intermittent mode General-purpose I/O ports (CMOS output) : 49 18-bit free-run counter Interrupt interval : 1.024 ms, 4.096 ms, 16.834 ms, 131.072 ms (with 4-MHz oscillation clock) Reset generation intervals : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (with 4-MHz oscillation clock) 16-bit Number of channels : 1 free-run timer Interrupts from overflow generation Input capture Number of channels : 4 Maintenance of free-run timer value through pin input (rising, falling or both edges) Number of channels : 2 16-bit reload timer operation Count clock interval : 0.25 µs, 0.5 µs, 2.0 µs (with 16-MHz machine clock) External event count enabled 15-bit free-run counter Interrupt intervals : 31.25 ms, 62.5 ms, 12 ms, 250 ms, 500 ms, 1.0 s, 2.0 s (with 8.192-kHz subclock) Number of channels : 2 (two 8-bit channels can be used) Two 8-bit or one 16-bit channel PPG operation possible Free interval, free duty pulse output possible Count clock : 62.5 ns to 1 µs (with 16-MHz machine clock) Watchdog timer 16-bit I/O Timer 16-bit reload timer Watch timer 8/16-bit PPG timer * : The S2 dipswitch setting when using the MB2145-507 emulation baud. For details, see the MB2145-507 hardware manual (2.7 Emulator Power Pin) . (Continued) 4 MB90495G Series (Continued) Part Number Parameter Delayed interrupt generation module DTP/external interrupt circuit MB90F497G MB90497G MB90F498G MB90V495G Module for delayed interrupt generation switching tasks Used in real-time OS Number of inputs : 8 Starting by rising edge, falling edge, “H” level input, or “L” level input, external interrupts or extended intelligent I/O service (EI2OS) can be used Number of channels : 8 Resolution : set 10-bit or 8-bit Conversion time : 6.13 µs (with 16-MHz machine clock, including sampling time) Continuous conversion of multiple linked channels possible (up to 8 channels can be set) One-shot conversion mode : converts selected channel only once Continuous conversion mode : converts selected channel continuously Stop conversion mode : converts selected channel and suspends operation repeatedly Number of channels : 1 Clock-synchronous forwarding : 62.5 Kbps to 2 Mbps Clock-asynchronous forwarding : 1,202 bps to 62,500 bps Transmission can be performed by two-way serial transmission or by master/ slave connection Number of channels : 1 Clock-synchronous forwarding : 62.5 Kbps to 2 Mbps Clock-asynchronous forwarding : 9,615 bps to 500 Kbps Transmission can be performed by two-way serial transmission or by master/ slave connection Compliant with CAN specification versions 2.0A and 2.0B Send/receive message buffers : 8 Forwarding bit rate : 10 Kbps to 1 Mbps (with 16-MHz machine clock) 8/10-bit A/D converter UART0 (SCI) UART1 (SCI) CAN s PACKAGES AND CORRESPONDING PRODUCTS Package FPT-64P-M06 FPT-64P-M09 : available × : not available Note : See “Package Dimensions” for details. MB90F497G MB90497G MB90F498G s PRODUCT COMPARISON Memory Size When evaluating with evaluation chips and other means, take careful note of the different between the evaluation chip and the chip actually used. Take particular note of the following. • While the MB90V495G does not feature an on-chip ROM, the dedicated development tool can be used to achieve operation equivalent to a product with built-in ROM. Therefore, the ROM size is configured by the development tool. • On the MB90V495G, the FF4000H to FFFFFFH image is only visible in the 00 bank, and the FE0000H to FF3FFFH is only visible in the FE and FF banks (configurable on development tool) . • On the MB90F497G/F498G/497G, the FF4000H to FFFFFFH image is visible in the 00 bank, and the FF0000H to FF3FFFH is visible only in the FF bank. 5 6 • FPT-64P-M06 s PIN ASSIGNMENTS P31/SCK0/RD P32/SIN0/WRL P33/WRH P34/HRQ P35/HAK VCC C P36/FRCK/RDY P37/ADTG/CLK P40/SIN1 P41/SCK1 P42/SOT1 P43/TX 64 1 51 10 42 58 52 MB90495G Series (TOP VIEW) (FPT-64P-M06) 19 20 26 32 33 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VSS X1 X0 MD2 MD1 RST P44/RX P61/INT1 P62/INT2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT0 X0A X1A P63/INT3 MD0 P30/SOT0/ALE VSS P27/INT7/A23 P26/INT6/A22 P25/INT5/A21 P24/INT4/A20 P23/TOT1/A19 P22/TIN1/A18 P21/TOT0/A17 P20/TIN0/A16 P17/PPG3/AD15 P16/PPG2/AD14 P15/PPG1/AD13 P14/PPG0/AD12 P13/IN3/AD11 P12/IN2/AD10 P11/IN1/AD09 P10/IN0/AD08 P07/AD07 • FPT-64P-M09 VSS P30/SOT0/ALE P31/SCK0/RD P32/SIN0/WRL P33/WRH P34/HRQ P35/HAK VCC C P36/FRCK/RDY P37/ADTG/CLK P40/SIN1 P41/SCK1 P42/SOT1 P43/TX P44/RX 64 1 48 8 40 57 49 (TOP VIEW) (FPT-64P-M09) 16 17 24 P61/INT1 P62/INT2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P60/INT0 X0A X1A 33 32 P27/INT7/A23 P26/INT6/A22 P25/INT5/A21 P24/INT4/A20 P23/TOT1/A19 P22/TIN1/A18 P21/TOT0/A17 P20/TIN0/A16 P17/PPG3/AD15 P16/PPG2/AD14 P15/PPG1/AD13 P14/PPG0/AD12 P13/IN3/AD11 P12/IN2/AD10 P11/IN1/AD09 P10/IN0/AD08 MB90495G Series P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VSS X1 X0 MD2 MD1 RST MD0 P63/INT3 7 MB90495G Series s PIN DESCRIPTION Pin No. M06 2 3 M09 1 2 Pin Name P61 INT1 P62 INT2 P50 to P57 4 to 11 3 to 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 to 33 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 to 32 AN0 to AN7 AVCC AVR AVSS P60 INT0 X0A X1A P63 INT3 MD0 RST MD1 MD2 X0 X1 VSS P00 to P07 AD00 to AD07 P10 to P13 34 to 37 33 to 36 IN0 to IN3 AD08 to AD11 D D E    D A A D C B C F A A  Circuit Type Description General-purpose I/O port Functions as external interrupt input pin. Set this to input port. General-purpose I/O port Functions as external interrupt input pin. Set this to input port. General-purpose I/O port Functions as analog input port of A/D converter. This is enabled if analog input configuration is permitted. VCC power input pin of A/D converter. Reference voltage (+) input pin for the A/D converter.This voltage must not exceed VCC and AVCC. Reference voltage (−) is fixed to AVSS. VSS power input pin of A/D converter. General-purpose I/O port Functions as external interrupt input pin. Set this to input port. Low-speed oscillation pin. Perform pull-down processing if not connected to an oscillator. Low-speed oscillation pin. Set to open if not connected to an oscillator. General-purpose I/O port Functions as external interrupt input pin. Set this to input port. Input pin for specifying operation mode. External reset input pin. Input pin for specifying operation mode. Input pin for specifying operation mode. High-speed oscillation pin. High-speed oscillation pin. Power supply (0 V) input pin. General-purpose I/O port Only enabled in single-chip mode. I/O pin for the lower 8-bit of the external address data bus. Only enabled during external bus mode. General-purpose I/O port. Only enabled in single-chip mode. Functions as trigger input pin for input capture channels 0 to 3. Set this to input port. I/O pin for upper 4-bit of external address data bus. Only enabled during external bus mode. D D (Continued) 8 MB90495G Series (Continued) Pin No. M06 M09 Pin Name P14 to P17 Circuit Type Description General-purpose I/O port. Only enabled in single-chip mode. 38 to 41 37 to 40 PPG0 to PPG3 AD12 to AD15 P20 D Functions as output pin of PPG timer 01, 23. Only valid if output configuration is enabled. I/O pin for upper 4-bit of external address data bus. Only enabled during external bus mode. General-purpose I/O port. When the bits of high address control register (HACR) are set to “1” in external bus mode, these pins function as general purpose I/O ports. 42 41 TIN0 D Functions as event input pin of TIN0 reload timer 0. Set this to input port. Output pin of external address bus (A16) . Only valid when the bits of high address control register (HACR) are set to “0” in external bus mode. General-purpose I/O port. When the bits of high address control register (HACR) are set to “1” in external bus mode, these pins function as general purpose I/O ports. A16 P21 43 42 TOT0 D Functions as event output pin of TOT0 reload timer 0. Only valid if output configuration enabled. Output pin of external address bus (A17) . Only valid when the bits of high address control register (HACR) are set to “0” in external bus mode. General-purpose I/O port. When the bits of high address control register (HACR) are set to “1” in external bus mode, these pins function as general purpose I/O ports. A17 P22 44 43 TIN1 D Functions as event input pin of TIN1 reload timer 1. Set this to input port. Output pin of external address bus (A18) . Only valid when the bits of high address control register (HACR) are set to “0” in external bus mode. General-purpose I/O port. When the bits of high address control register (HACR) are set to “1” in external bus mode, these pins function as general purpose I/O ports. A18 P23 45 44 TOT1 D Functions as event output pin for TOT1 reload timer 1. Only valid if output configuration enabled. Output pin for external address bus (A19) . Only valid when the bits of high address control register (HACR) are set to “0” in external bus mode. (Continued) A19 9 MB90495G Series (Continued) Pin No. M06 M09 Pin Name Circuit Type Description General-purpose I/O port. When the bits of high address control register (HACR) are set to “1” in external bus mode, these pins function as general purpose I/O ports. P24 to P27 46 to 49 45 to 48 INT4 to INT7 D Functions as external interrupt input pin. Set this to input port. Output pin for external address bus (A20 to A23) . Only valid when the bits of high address control register (HACR) are set to “0” in external bus mode. A20 to A23 50 49 VSS P30 51 50 SOT0 ALE P31 52 51 SCK0 RD P32 53 52 SIN0 WRL P33 54 53 WRH P34 55 54 HRQ P35 56 57 58 55 56 57 HAK VCC C D   D D D D D  Power supply (0 V) input pin. General-purpose I/O port. Only enabled in single-chip mode. UART0 serial data output pin. Only valid if UART0 serial data output configuration is enabled. Address latch authorization output pin. Only enabled during external bus mode. General-purpose I/O port. Only enabled in single-chip mode. UART0 serial clock I/O pin. Only valid if UART0 serial clock I/O configuration is enabled. Lead strobe output pin. Only enabled during external bus mode. General-purpose I/O port. UART0 serial data input pin. Set this to input port. Write strobe output pin for lower 8-bit of data bus. Only valid if WRL pin output is enabled, in external bus mode. General-purpose I/O port. Write strobe output pin for upper 8-bit of data bus. Only valid if external bus mode/16-bit bus mode/WRH pin output enabled. General-purpose I/O port. Hold request input pin. Only valid if hold input is enabled, in external bus mode. General-purpose I/O port. Hold addressing output pin. Only valid if hold input is enabled, in external bus mode. Power supply (5 V) input pin. Capacity pin for power stabilization. Please connect to an approximately 0.1 µF ceramic capacitor. (Continued) 10 MB90495G Series (Continued) Pin No. M06 M09 Pin Name P36 Circuit Type Description General-purpose I/O port. 59 58 FRCK RDY P37 D Functions as an external clock input pin for a FRCK 16-bit free-run timer. Set this to input port. External ready input pin. Only valid if external ready input is enabled, in external bus mode. General-purpose I/O port. Functions as A/D converter external trigger input pin. Set this to input port. External clock output pin. Only valid if external clock output is enabled, in external bus mode. General-purpose I/O port. 60 59 ADTG CLK P40 D 61 60 SIN1 P41 D UART1 serial data input pin. Set this to input port. General-purpose I/O port. UART1 serial clock I/O pin. Only valid if UART1 clock I/O configuration is enabled. General-purpose I/O port. UART1 serial data output pin. Only valid if UART1 serial data output configuration is enabled. General-purpose I/O port. CAN transmission output pin. Only valid if output configuration enabled. General-purpose I/O port. CAN reception input pin. Set this to input port. 62 61 SCK1 P42 D 63 62 SOT1 P43 D 64 63 TX P44 D 1 64 RX D 11 MB90495G Series s I/O CIRCUIT TYPE Type X1 Clock input X1A Circuit Remarks • High speed oscillation feedback resistor : 1 MΩ approx. • Low speed oscillation feedback resistor : 10 MΩ approx. A X0 X0A Standby control signal VCC • Hysteresis input with pull-up • Pull-up Resistor : 50 kΩ approx. R Hysteresis input B R • Hysteresis input C R Hysteresis input VCC Pch Digital output • CMOS hysteresis input • CMOS level output • Standby control available D R IOL = 4 mA Nch VSS Digital output Hysteresis input Standby control VCC Pch Digital output • • • • CMOS hysteresis input CMOS level output Doubles as analog input pin Standby control available E IOL = 4 mA R Nch VSS Digital output Hysteresis input Standby control Analog input (Continued) 12 MB90495G Series (Continued) Type R Hysteresis input Circuit Remarks • Hysteresis input with pull-down • Pull-down Resistor : 50 kΩ approx. (except FLASH device) F R VSS 13 MB90495G Series s HANDLING DEVICES • Make sure you do not exceed the maximum rated values (in order to prevent latch-up) . • CMOS IC chips may suffer latch-up if a voltage higher than VCC or lower than VSS is applied to an input or output pin with other than mid or high current resistance; or voltage exceeding the rating is applied across VCC and VSS. • Latch-ups can dramatically increase the power supply current, causing thermal breakdown of the device. Make sure that you do not exceed the maximum rated value of your device, in order to prevent a latch-up. • When turning the analog power supply on or off, make sure that the analog power voltage (AVCC, AVR) and analog input voltages do not exceed the digital voltage (VCC) . • Handling Unused Pins Leaving unused input pins open may cause malfunctions and latch-ups, permanently damaging the device. Prevent this by connecting it to a pull-up or pull-down resistor of no less than 2 kΩ. Leave unused output pins open in output mode, or if in input mode, handle them in the same as input pins. • Notes on Using External Clock When using the external clock, drive pin X0 only, and leave pin X1 unconnected. See below for an example of external clock use. Example External Clock Use X0 Open X1 MB90495G Series • Notes on Not Using Subclock If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the X1A pin open. • Power Supply Pins • If your product has multiple VCC or VSS pins, pins of the same potential are internally connected in the device in order to avoid abnormal operation, including latch-up. However, you should make sure to connect the pins’ external power and ground lines, in order to lower unneeded emissions, prevent abnormal operation of strobe signals due to a rise in ground levels, and maintain total output current within rated levels. • Take care to connect the VCC and VSS pins of MB90495G Series devices to power lines via the lowest possible impedance. • It is recommended that you connect a bypass capacitor of approximately 0.1 µF between VCC and VSS near MB90495G Series device pins. • Crystal Oscillator Circuit • Noise in the vicinity of X0 and X1 pins could cause abnormal operations in MB90495G Series devices. Make sure to provide bypass capacitors via the shortest possible distance from X0 and X1 pins, crystal oscillators (or ceramic resonators) , and ground lines. In addition, design your printed circuit boards so as to keep X0 and X1 wiring from crossing other wiring, if at all possible. • It is strongly recommended that you provide printed circuit board artwork surrounding X0 and X1 pins within a grand area, as this should stabilize operation. 14 MB90495G Series • A/D Converter Power-up and Analog Input Initiation Sequence • Make sure to power up the A/D converter and analog input (pins AN0 to AN7) after turning on digital power (VCC) . • Turn off digital power after turning off the A/D converter power supply and analog inputs. In this case, make sure that the voltage of AVR does not exceed AVCC (it is permissible to turn off analog and digital power simultaneously) . • Connecting Unused A/D Converter Pins If you are not using the A/D converter, set unused pins to AVCC = AVR = VCC, AVSS = VSS. • Notes for Powering Up Ensure that the voltage step-up time (between 0.2 V and 2.7 V) at power-up is no less than 50 µs, in order to prevent malfunction in the built-in step-down circuit. • Initialization The device contains built-in registers which are only initialized by a power-on reset. Cycle the power supply to initialize these registers. • Stabilizing the Power Supply Make sure that the VCC power supply voltage is stable. Even at the rated operating VCC power supply voltage, large, sudden changes in the voltage could cause malfunctions. As a standard for stable power supply, keep VCC ripples (peak-to-peak value) at commercial power frequencies (50 Hz to 60 Hz) to no more than 10% of the power supply voltage, and momentary surges caused by switching the power supply and other events to more than 0.1 V/ms. • If Output from Ports 0/1 Becomes Undefined After power is turned on, if the RST pin is set to “H” during step-down circuit stabilization standby (during poweron reset) , ports 0 and 1 output will be undefined. If the RST pin is set to “L”, ports 0 and 1 will go into a high impedance state. Take careful note of the timing of events outlined in figures 1 and 2. 15 MB90495G Series • Figure 1 - Timing Chart of Undefined Output from Ports 0/1 (with RST pin set to “H”) Time in standby for oscillation to stabilize*2 Time in standby for stepdown circuit to stabilize*1 VCC (power supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operating clock A) signal KB (internal operating clock B) signal PORT (port output) signal Time of undefined output *1 : Step-down circuit stabilization standby time : 217/oscillation clock frequency (with 16-MHz oscillation clock frequency, about 8.19 ms) *2 : Oscillation stabilization standby time : 218/oscillation clock frequency (with 16-MHz oscillation clock frequency, about 16.36 ms) • Figure 2 - Timing Chart of High Impedance State for Ports 0/1 (when RST pin is “L”) Time in standby for oscillation to stabilize*2 Step-down circuit stabilization standby time*1 VCC (power supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operating clock B) signal PORT (port output) signal High impedance *1 : Step-down circuit stabilization standby time : 217/oscillation clock frequency (with 16-MHz oscillation clock frequency, about 8.19 ms) *2 : Oscillation stabilization standby time : 218/oscillation clock frequency (with 16-MHz oscillation clock frequency, about 16.38 ms) 16 MB90495G Series • Caution on Operations during PLL Clock Mode If the PLL clock mode is selected in the microcontroller, it may attempt to continue the operation using the freerunning frequency of the automatic oscillating circuit in the PLL circuitry even if the oscillator is out of place or the clock input is stopped. Performance of this operation, however, cannot be guaranteed. • Support for +125 °C If used exceeding TA = +105 °C, be sure to contact us for reliability limitations. 17 MB90495G Series s BLOCK DIAGRAM X0, X1 RST X0A, X1A Clock control circuit Watch timer Time-base timer CPU F2MC-16LX Core 16 bit free-run timer Input capture (4 ch) FRCK IN0 to IN3 RAM Internal data bus ROM/FLASH 16-bit PPG timer (2 ch) PPG0 to PPG3 Prescaler SOT1 SCK1 SIN1 CAN RX TX UART1 DTP/external interrupt circuit Prescaler INT0 to INT7 SOT0 SCK0 SIN0 UART0 16 bits reload timer (2 ch) TIN0, TIN1 TOT0, TOT1 AVCC AVSS AN0 to AN7 AVR ADTG 8/10 bit A/D converter (8 ch) External bus AD00 to AD15 A16 to A23 ALE RD WRL WRH HRQ HAK RDY CLK 18 MB90495G Series s MEMORY MAP The memory access modes of the MB90495G Series can be set to single chip mode, internal ROM - external bus mode, and external ROM - external bus mode. 1. Memory Allocation of the MB90495G The MB90495G Series has 24-bit internal address bus and 24-bit external address bus output, enabling it to access up to 16 Mbytes of external access memory. The enable/disable time of the ROM mirror function is shown graphically in the memory map. 2. Memory Map Single chip mode (ROM mirror function available) 000000H 0000C0H 000100H Address #1 002000H 003800H 003900H Address #2 Periphery RAM space Register Internal ROM External bus mode Periphery RAM space Register External ROM External bus mode Periphery RAM space Register 010000H Address #3 Extention IO space ROM space (image of bank FF) Extention IO space ROM space (image of bank FF) Extention IO space ROM space ROM space FFFFFFH Internal access memory External access memory Access prohibited Product MB90V495G MB90F497G MB90497G MB90F498G Address #1* 001900H 000900H 000900H 000900H Address #2 004000H 004000H 004000H 004000H Address #3* (FC0000H) FF0000H FF0000H FE0000H * : Addresses #1 and #3 are product-specific. Note : When the internal ROM is operational, the ROM data in the upper address of bank 00 of the F2MC-16LX is visible in an image. This is called the ROM mirror function, and takes advantage of the small C compiler model. With the F2MC-16LX, the lower 16-bit address of bank FF and the lower 16-bit address of bank 00 are set identical to one another. This allows the ROM-internal table to be referenced without specifying a far pointer. For example, say the address “00C000H” is accessed. In actuality, the “FFC000H ” address inside ROM will be accessed. However, as the ROM space in bank FF exceeds 48 Kbytes, the entire space cannot be viewed on bank 00’s image. And so, since “FF4000H” to “FFFFFFH” ROM data will be visible on the “004000H” to “00FFFFH” image, save the ROM data table in the “FF4000H” to “FFFFFFH” space. 19 MB90495G Series s I/O MAP Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H to 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H to 00001AH 00001BH 00001CH to 00001FH 000020H 000021H 000022H 000023H 000024H 000025H 000026H 000027H 000028H SMR0 SCR0 SIDR0/ SODR0 SSR0 CDCR0 SES0 SMR1 SCR1 SIDR1/ SODR1 Serial mode register 0 Serial control register 0 Serial input data register 0/ Serial output data register 0 Serial status register 0 Communication prescaler control register 0 Serial edge selection register 0 Serial mode register 1 Serial control register 1 Serial input data register 1/ Serial output data register 1 ADER DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 Register Abbreviation PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 Register Name Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Access R/W R/W R/W R/W R/W R/W R/W (system-reserved area) * Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXX 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXX 0 0 0 0B Resource Name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Initial Value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (system-reserved area) * Analog input enable register R/W 8/10-bit A/D converter 1 1 1 1 1 1 1 1B (system-reserved area) * R/W R/W R/W R/W R/W R/W R/W R/W R/W UART1 UART0 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B XXXXXXXXB 0 0 0 0 1 X 0 0B 0 XXX 1 1 1 1B XXXXXXX 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B XXXXXXXXB (Continued) 20 MB90495G Series (Continued) Address 000029H 00002AH 00002BH 00002CH to 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H to 00003FH 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H to 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H IPCP0 IPCP1 ICS01 ICS23 TCDT PPGC2 PPGC3 PPG23 PPGC0 PPGC1 PPG01 ENIR EIRR ELVR ADCS ADCR CDCR1 Register Abbreviation SSR1 Register Name Serial status register 1 Communication prescaler control register 1 Access R/W (system-reserved area) * R/W UART1 0 XXX 0 0 0 0B Resource Name UART1 Initial Value 0 0 0 0 1 0 0 0B (system-reserved area) * DTP/external interrupt enable register DTP/external interrupt condition register Detection level configuration register A/D control status register A/D data register R/W R/W R/W R/W R/W R/W R R/W (system-reserved area) * 0 0 0 0 0 0 0 0B DTP/external interrupt XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 8/10-bit A/D converter 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 1 0 1 XXXB PPG0 operation mode control register PPG1 operation mode control register PPG0/1 count clock selection register PPG2 operation mode control register PPG3 operation mode control register PPG2/3 count clock selection register R/W R/W R/W R/W R/W R/W 8/16-bit PPG timer 2/3 8/16-bit PPG timer 0/1 0 X 0 0 0 XX 1B 0 X 0 0 0 0 0 1B 0 0 0 0 0 0 XXB 0 X 0 0 0 XX 1B 0 X 0 0 0 0 0 1B 0 0 0 0 0 0 XXB (system-reserved area) * (system-reserved area) * XXXXXXXXB XXXXXXXXB XXXXXXXXB 16-bit I/O timer Input capture control status register Timer counter data register R/W R/W XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (Continued) 21 Input capture data register 0 Input capture data register 1 R R MB90495G Series (Continued) Address 000058H 000059H 00005AH 00005BH 00005CH 00005DH 00005EH to 000065H 000066H 000067H 000068H 000069H 00006AH to 00006EH 00006FH 000070H to 00007FH 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH RIER ROVRR RRTRR RCR TCR TCANR Send cancel register Send complete register Reception complete register Reception RTR register Reception overrun register Reception complete interrupt enable register TREQR Send request register BVALR ROMM TMCSR0 Timer control status register TMCSR1 Register Abbreviation TCCS IPCP2 IPCP3 Register Name Timer counter control status register Input capture data register 2 Input capture data register 3 Access R/W R R 16-bit I/O timer Resource Name Initial Value 0 0 0 0 0 0 0 0B 0 XXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (system-reserved area) * R/W R/W R/W R/W (system-reserved area) * ROM mirror function selection module 0 0 0 0 0 0 0 0B XXXX0 0 0 0B 0 0 0 0 0 0 0 0B XXXX0 0 0 0B 16-bit reload timer 0 16-bit reload timer 1 ROM mirror function selection register W XXXXXXX 1B (system-reserved area) * Message buffer valid register R/W R/W (system-reserved area) * W (system-reserved area) * R/W R/W R/W R/W CAN controller CAN controller CAN controller CAN controller 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (system-reserved area) * (system-reserved area) * (system-reserved area) * (system-reserved area) * R/W CAN controller 0 0 0 0 0 0 0 0B CAN controller 0 0 0 0 0 0 0 0B CAN controller CAN controller 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (system-reserved area) * (Continued) 22 MB90495G Series (Continued) Address 00008FH to 00009DH 00009EH 00009FH 0000A0H 0000A1H 0000A2H to 0000A4H 0000A5H 0000A6H 0000A7H 0000A8H 0000A9H 0000AAH 0000ABH to 0000ADH 0000AEH 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 FMCS ARSR HACR ECSR WDTC TBTC WTC PACSR DIRR LPMCR CKSCR Register Abbreviation Register Name Access Resource Name Initial Value (system-reserved area) * ROM correction function Delayed interrupt generation module Address detection control register Delayed interrupt request generate/ cancel register Low power consumption mode control register Clock selection register R/W R/W R/W R/W 0 0 0 0 0 0 0 0B XXXXXXX 0B Low-power 0 0 0 1 1 0 0 0B consumption modes Clock 1 1 1 1 1 1 0 0B (system-reserved area) * Auto ready function selection register High address control register Bus control signal selection register Watchdog timer control register Time-base timer control register Watch timer control register W W External access W R/W R/W R/W Watchdog timer Time-base timer Watch timer 0 0 1 1 XX 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 XB or 0 0 0 0 1 0 0 XB XXXXX 1 1 1B 1 XX 0 0 1 0 0B 1 0 0 0 1 0 0 0B (system-reserved area) * 512-Kbit flash memory Flash memory control status register R/W 0 0 0 X 0 0 0 0B (system-reserved area) * Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B (Continued) 23 MB90495G Series (Continued) Address 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H to 0000FFH 001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H 003900H 003901H 003902H 003903H 003904H to 00390FH 003910H 003911H 003912H 003913H 003914H 003915H 003916H 003917H 003918H to 003BFFH 003C00H to 003C0FH 24 TMR0/ TMRLR0 TMR1/ TMRLR1 PADR1 PADR0 Register Abbreviation ICR11 ICR12 ICR13 ICR14 ICR15 Register Name Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 Access R/W R/W R/W R/W R/W Interrupt controller Resource Name Initial Value 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B (system-reserved area) * Detection address configuration register 0 (lower) Detection address configuration register 0 (mid) Detection address configuration register 0 (upper) Detection address configuration register 1 (lower) Detection address configuration register 1 (mid) Detection address configuration register 1 (upper) 16-bit timer register 0/ 16-bit reload register 0 16-bit timer register 1/ 16-bit reload register 1 R/W R/W R/W R/W R/W R/W R/W R/W 16-bit reload timer 0 16-bit reload timer 1 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ROM correction function (system-reserved area) * PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 PPG0 reload register L PPG0 reload register H PPG1 reload register L PPG1 reload register H PPG2 reload register L PPG2 reload register H PPG3 reload register L PPG3 reload register H R/W R/W R/W R/W R/W R/W R/W R/W 8/16-bit PPG timer XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (system-reserved area) * RAM (general-purpose RAM) (Continued) MB90495G Series (Continued) Address 003C10H to 003C13H 003C14H to 003C17H 003C18H to 003C1BH 003C1CH to 003C1FH 003C20H to 003C23H 003C24H to 003C27H 003C28H to 003C2BH 003C2CH to 003C2FH 003C30H 003C31H 003C32H 003C33H 003C34H 003C35H 003C36H 003C37H 003C38H 003C39H 003C3AH 003C3BH 003C3CH 003C3DH 003C3EH 003C3FH 003C40H to 003C47H Register Abbreviation IDR0 Register Name Access Resource Name Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB CAN controller XXXXXXXXB to XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB to XXXXXXXXB (Continued) 25 ID register 0 R/W IDR1 ID register 1 R/W IDR2 ID register 2 R/W IDR3 ID register 3 R/W IDR4 ID register 4 R/W IDR5 ID register 5 R/W IDR6 ID register 6 R/W IDR7 ID register 7 R/W DLCR0 DLCR1 DLCR2 DLCR3 DLCR4 DLCR5 DLCR6 DLCR7 DLC register 0 DLC register 1 DLC register 2 DLC register 3 DLC register 4 DLC register 5 DLC register 6 DLC register 7 R/W R/W R/W R/W R/W R/W R/W R/W DTR0 Data register 0 R/W MB90495G Series (Continued) Address 003C48H to 003C4FH 003C50H to 003C57H 003C58H to 003C5FH 003C60H to 003C67H 003C68H to 003C6FH 003C70H to 003C77H 003C78H to 003C7FH 003C80H to 003CFFH 003D00H 003D01H 003D02H 003D03H 003D04H 003D05H 003D06H 003D07H 003D08H 003D09H 003D0AH 003D0BH 003D0CH 003D0DH 003D0EH TIER RFWTR TRTRR Transmit RTR register Remote frame reception standby register Transmit complete interrupt enable register RTEC BTR IDER CSR LEIR Control status register Display last event register Register Abbreviation DTR1 Register Name Access Resource Name Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB CAN controller XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB Data register 1 R/W DTR2 Data register 2 R/W DTR3 Data register 3 R/W DTR4 Data register 4 R/W DTR5 Data register 5 R/W DTR6 Data register 6 R/W DTR7 Data register 7 R/W (system-reserved area) * R/W R/W CAN controller 0 XXXX 0 0 1B 0 0 XXX 0 0 0B 0 0 0 XX 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (system-reserved area) * Receive/transmit error counter Bit timing register IDE register R R/W R/W (system-reserved area) * R/W (system-reserved area) * R/W CAN controller XXXXXXXXB CAN controller 0 0 0 0 0 0 0 0B CAN controller 1 1 1 1 1 1 1 1B X 1 1 1 1 1 1 1B XXXXXXXXB (system-reserved area) * R/W CAN controller 0 0 0 0 0 0 0 0B (Continued) 26 MB90495G Series (Continued) Address 003D0FH 003D10H 003D11H 003D12H 003D13H 003D14H to 003D17H 003D18H to 003D1BH 003D1CH to 003FFFH Explanation of reset values 0 : The reset value of this bit is 0. 1 : The reset value of this bit is 1. X : The reset value of this bit is undefined. * : System-reserved area contains system-internal addresses, and cannot be used. AMR0 AMSR Register Abbreviation Register Name Access Resource Name Initial Value (system-reserved area) * Acceptance mask selection register R/W CAN controller XXXXXXXXB XXXXXXXXB (system-reserved area) * XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB Acceptance mask register 0 R/W CAN controller AMR1 Acceptance mask register 1 R/W (system-reserved area) * 27 MB90495G Series s INTERRUPT CONDITIONS AND INTERRUPT VECTOR/REGISTER Interrupt Condition Reset INT 9 instruction Exception processing Can controller reception complete (RX) Can controller reception complete (TX) /Node status transition (NS) Reserved Reserved External interrupt (INT0/INT1) Time-base timer 16-bit reload timer 0 8/10-bit A/D converter 16-bit free-run timer overflow External interrupt (INT2/INT3) Reserved PPG timer ch0, ch1 underflow Input capture 0 load External interrupt (INT4/INT5) Input capture 1 load PPG timer ch2, ch3 underflow External interrupt (INT6/INT7) Watch timer Reserved Input capture 2 load Input capture 3 load Reserved Reserved Reserved Reserved Reserved 16-bit reload timer 1 UART1 reception complete UART1 transmission complete × × × × × × × × × × × EI2OS Compatible × × × × × × × Interrupt Vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H ICR09 0000B9H (*1) ICR00 0000B0H (*1) Interrupt Register ICR    Address    Priority *3 Highest ↑ ICR01 0000B1H ICR02 0000B2H (*1) ICR03 0000B3H (*1) ICR04 0000B4H (*1) ICR05 0000B5H (*2) ICR06 0000B6H (*1) ICR07 0000B7H (*1) ICR08 0000B8H (*1) ICR10 0000BAH (*1) ICR11 0000BBH (*1) ICR12 0000BCH (*1) ICR13 0000BDH (*1) (Continued) 28 MB90495G Series (Continued) Interrupt Condition UART0 reception complete UART0 transmission complete Flash memory Delayed interrupt generation module × × EI2OS Compatible Interrupt Vector Number #39 #40 #41 #42 27H 28H 29H 2AH Address FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt Register ICR Address Priority *3 ICR14 0000BEH (*1) ICR15 0000BFH (*1) ↓ Lowest : Available × : Not available : Available, EI2OS halt function supplied : Available for interrupt conditions not shared by ICR *1 : • The interrupt level is the same for peripheral devices sharing the ICR register. • Peripheral devices that share the ICR register and use the extended intelligent I/O service only utilize one set. • If one side of a peripheral device sharing the ICR register is set to extended intelligent I/O service, the other side cannot use interrupts. *2 : Only the 16-bit reload timer is compatible with EI2OS. Since PPG does not support EI2OS, if you use EI2OS with the 16-bit reload timer, prohibit interrupts by PPG. *3 : Priority if two or more interrupts with the same level are generated simultaneously. 29 MB90495G Series s PERIPHERAL RESOURCES 1. I/O Port (1) Overview General-purpose (parallel) I/O ports can be used as the I/O ports. The MB90495G Series has 7 ports (49) . Each port doubles as a peripheral device I/O pin. • I/O Port Features I/O ports output data to I/O pins and load signals input to them, by means of the port data register (PDR) . Additionally, the port direction register (DDR) sets the I/O direction of the I/O pins at the bit level. Below is a description of each pin’s function, and the peripheral device that shares it. • Port 0 : general-purpose I/O port/doubles as external address data bus pin • Port 1 : general-purpose I/O port/doubles as PPG timer output, input capture input, and external address data bus pin • Port 2 : general-purpose I/O port/doubles as reload timer I/O, external interrupt input pin, and external address bus pin • Port 3 : general-purpose I/O port/doubles as UART0 I/O, free-run timer, and A/D converter startup trigger pin • Port 4 : general-purpose I/O port/doubles as UART1 I/O, and CAN controller transmit/receive pin • Port 5 : general-purpose I/O port/doubles as analog input pin • Port 6 : general-purpose I/O port/doubles as external interrupt input pin 30 MB90495G Series • Pin Block Diagram for Port 0 (single chip mode) PDR (port data register) PDR read Internal data bus Output latch PDR write DDR (port direction register) Direction latch DDR write Standby control (SPL = 1) DDR read Nch Pin Pch Standby control : control stop mode (SPL = 1) , time-base timer mode (SPL = 1) and watch mode (SPL = 1) • Port 0 register (single chip mode) • The port 0 register contains the port 0 data register (PDR0) and the port 0 direction register (DDR0) . • The bits making up the register are in a one-to-one relation to the port 0 pin. Compatibility between port 0 register and pin Port Name Related register bit and corresponding pin Port 0 PDR0, DDR0 Corresponding pin bit7 P07 bit6 P06 bit5 P05 bit4 P04 bit3 P03 bit2 P02 bit1 P01 bit0 P00 31 MB90495G Series • Block Diagram for Pins of Ports 1, 2, 3 and 4 (single-chip mode) Peripheral device input Port data register (PDR) Peripheral device output Peripheral device output enabled PDR read Internal data bus Output latch PDR write Port direction register (DDR) Direction latch DDR write Standby control (SPL = 1) Nch Pch Pin DDR read Standby control : control stop mode (SPL = 1) , time-base timer mode (SPL = 1) and watch mode (SPL = 1) • Port 1 register (single-chip mode) • The port1 register contains the port 1 data register (PDR1) and the port 1 direction register (DDR1) . • The bits making up the register are in a one-to-one relationship with the port 1 pins. Port 1 Register and Corresponding Pins Port Name Related register bit and corresponding pin Port 1 PDR1, DDR1 Corresponding pin bit7 P17 bit6 P16 bit5 P15 bit4 P14 bit3 P13 bit2 P12 bit1 P11 bit0 P10 32 MB90495G Series • Port 2 register • The port2 register contains the port 2 data register (PDR2) , the port 2 direction register (DDR2) and the high address control register (HACR). • The high address control register (HACR) enables or disables the output of external addresses (A16 to A23). When the register enables the output of the external addresses, the port can not be used as a peripheral device and a general-purpose I/O port. • The bits making up the register are in a one-to-one relationship with the port 2 pins. Port 2 Register and Corresponding Pins Port Name Related register bit and corresponding pin Port 2 PDR2, DDR2, HACR Corresponding pin bit7 P27 bit6 P26 bit5 P25 bit4 P24 bit3 P23 bit2 P22 bit1 P21 bit0 P20 • Port 3 register • The port3 register contains the port 3 data register (PDR3) and the port 3 direction register (DDR3) . • The bus control signal selection register (ECSR) enables or disables the input and output of external bus control signals (WRL / WRH, HRQ / HAK, RDY, CLK). When the register enables the input and output of the external bus control signals, the port can not be used as a peripheral device and a general-purpose I/O port. • The bits making up the register are in a one-to-one relationship with the port 3 pins. Port 3 Register and Corresponding Pins Port Name Related register bit and corresponding pin PDR3, DDR3 Port 3 ECSR Corresponding pin bit7 CKE P37 bit6 RYE P36 P35 bit5 HDE P34 bit4 bit3 WRE P33 P32 P31 bit2 bit1  P30 bit0 • Port 4 register • The port4 register contains the port 4 data register (PDR4) and the port 4 direction register (DDR4) . • The bits making up the register are in a one-to-one relationship with the port 4 pins. Port 4 Register and Corresponding Pins Port Name Related register bit and corresponding pin Port 4 PDR4, DDR4 Corresponding pin       bit4 P44 bit3 P43 bit2 P42 bit1 P41 bit0 P40 33 MB90495G Series • Block Diagram of Port 5 Pins ADER Port data register (PDR) Analog input Internal data bus PDR read Output latch PDR write Port direction register (DDR) Direction latch DDR write Nch Pin Pch DDR read Standby control (SPL = 1) Standby control : control stop mode (SPL = 1) , time-base timer mode (SPL = 1) , and watch mode (SPL = 1) • Port 5 register • The port 5 register contains the port 5 data register (PDR5) , the port 5 direction register (DDR5) and the analog input enable register (ADER) . • The analog data enable register (ADER) enables or disables the input of analog signals by the analog input pin. • The bits making up the register are in a one-to-one correspondence with the pins of port 5. Port 5 Register and Corresponding Pins Port Name Related register bit and corresponding pin PDR5, DDR5 Port 5 ADER Corresponding pin bit7 ADE7 P57 bit6 ADE6 P56 bit5 ADE5 P55 bit4 ADE4 P54 bit3 ADE3 P53 bit2 ADE2 P52 bit1 ADE1 P51 bit0 ADE0 P50 34 MB90495G Series • Block Diagram of Port 6 Pins Peripheral device input Port data register (PDR) PDR read Internal data bus Output latch PDR write Port direction register (DDR) Direction latch DDR write Standby control (SPL = 1) DDR read Nch Pin Pch Standby control : control stop mode (SPL = 1) , time-base timer mode (SPL = 1) , and watch mode (SPL = 1) • Port 6 register • The port 6 register contains the port 6 data register (PDR6) and the port 6 direction register (DDR6) . • The bits making up the register are in a one-to-one relationship with the port 6 pins. Port 6 Register and Corresponding Pins Port Name Related register bit and corresponding pin Port 6 PDR6, DDR6 Corresponding pin bit7  bit6  bit5  bit4  bit3 P63 bit2 P62 bit1 P61 bit0 P60 35 MB90495G Series 2. Time-base Timer The time-base timer is an 18-bit free-run counter (time-base counter) for counting up in synchronization with the main clock (1/2 main oscillation clock) . • Four interval times are available, and interrupt requests can be generated for each interval time. • The time-base timer also has a function for supplying timers for oscillation stabilize standby time and operating clocks for peripheral devices. • Interval timer feature • When the time-base timer counter reaches the interval set by the interval time selection bits (TBTC : TBC1, TBC0) , it generates an overflow (TBTC : TBOF = 1) and interrupt request. • If the interrupts due to overflow generation are enabled (TBTC : TBIE = 1) , when an overflow is generated (TBTC : TBOF = 1) , an interrupt is generated. • Select from the following 4 time-base timer intervals : Time-base timer interval times Count Clock Interval Time 212/HCLK (approx. 1.0 ms) 2/HCLK (0.5 µs) 214/HCLK (approx. 4.1 ms) 216/HCLK (approx. 16.4 ms) 219/HCLK (approx. 131.1 ms) HCLK : oscillation clock The number in parentheses ( ) for 4-MHz oscillation clock operation • Time-base Timer Block Diagram To PPG timer Time-base timer counter 21/HCLK × 21 × 22 × 23 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 OF OF OF OF To clock controller oscillation stabilize standby time selector Clear counter circuit Clear TBOF Time-base timer control register (TBTC) Time-base timer interrupt signal Reserved Interval Timer selector Set TBOF To watchdog timer Power-on Reset Stop Mode CKSCR : MCS = 1 → 0*1 CKSCR : SCS = 0 → 1*2   TBIE TBOF TBR TBC1 TBC0 OF HCLK *1 *2 : overflow : oscillation clock : Switch machine clock from main clock to PLL clock : Switch machine clock from subclock to main clock See below for the actual interrupt request number of the time-base timer : Interrupt request number : #16 (10H) 36 MB90495G Series 3. Watchdog Timer The watchdog timer is a 2-bit timer used as a count clock for the timer-based or watch timer. If the counter is not cleared within the interval time, it resets the CPU. • Watchdog Timer Function • The watchdog timer is a timer counter used to deal with runaway programs. Once the watchdog timer is launched, it is necessary to keep clearing its counter within the specified interval. If the specified interval passes without the watchdog timer counter being cleared, the CPU will be reset. This feature is called the watchdog timer. • The watchdog timer interval traces back to the clock interval input as the count clock. A watchdog reset is generated for the smallest to largest times. • The clock source output destination is set by the watchdog clock selection bit of the watch timer control register (WTC : WDCS) . • The watchdog timer interval is set time-base timer output selection bit/watch timer output selection bit of the watchdog timer control register (WDTC : WT1, WT0) . Watchdog Timer Intervals Minimum Maximum Approx. 3.58 ms Approx. 14.33 ms Approx. 57.23 ms Approx. 4.61 ms Approx. 18.3 ms Approx. 73.73 ms Clock Interval 214 ± 211 /HCLK 216 ± 213 /HCLK 218 ± 215 /HCLK Minimum Approx. 0.457 s Approx. 3.584 s Approx. 7.168 s Maximum Approx. 0.576 s Approx. 4.608 s Approx. 9.216 s Clock Interval 212 ± 29 /SCLK 215 ± 212 /SCLK 216 ± 213 /SCLK 217 ± 214 /SCLK 221 ± 218 Approx. 14.336 s Approx. 18.432 s /HCLK HCLK : oscillation clock (4 MHz) ; SCLK : Subclock (8.192 kHz) Approx. 458.75 ms Approx. 589.82 ms Notes: • If the count clock of the watchdog timer is set to time-base timer output (overflow signal) , then clearing the time-base timer could make it take longer to reset the watchdog. • If you are using a subclock as the machine clock, make sure to select watch timer output by setting the watchdog timer clock source selection bit (WDCS) of the watch timer control register (WTC) to 0. 37 MB90495G Series • Watchdog Timer Block Diagram Watchdog timer control register (WDTC) PONR  WRST ERST SRST WTE WT1 WT0 Watch timer control register (WTC) WDCS Watchdog timer 2 Launch Reset generation Go to sleep mode Go to time-base timer mode Go to watch mode Go to stop mode Counter clearcontrol circuit Counter clock selector 2-bit counter Clear Watchdog reset generation circuit To internal reset generation circuit 4 4 (Time-base timer counter) Main clock (1/2 HCLK) × 21 × 22 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 (Clock counter) Subclock SCLK × 21 × 22 × 25 × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 HCLK : Oscillation clock SCLK : Subclock 38 MB90495G Series 4. 16-bit I/O Timer The 16-bit I/O timer is a complex module comprising one 16-bit free-run timer, and two input capture units (4 input pins) . Clock interval input signals and pulse widths can be measured based on the 16-bit free-run timer. • 16-bit I/O Timer Configuration The 16-bit I/O timer is made up of the following modules : • One 16-bit free-run timer • Two input capture units (each unit having 2 input pins) • 16-bit I/O Timer Function (1) 16-bit free-run timer function The 16-bit free-run timer consists of a 16-bit up counter, a time counter control status register, and prescaler. The 16-bit up counter counts up in synchronization with a fraction of the machine clock. • The count clock can be set to one of eight fractions of the machine clock. The external clock signals input to the 16-bit free-run timer clock input pin (FRCK) can be used as the count clock. • Interrupts can be generated in response to counter value overflows. • Interrupts launch the extended intelligent I/O service (EI2OS) . • The count value of the 16-bit free-run timer can be cleared to “0000H” by either a reset, or software clear via the timer count clear bit (TCCS : CLR) . • The count value of the 16-bit free-run timer is output to the input capture, and used as the base time for capture operation. (2) Input Capture Function When the input capture detects that an external signal edge has been input to an input pin, it stores the count value of the 16-bit free-run timer in the input capture data register, for the point at which the edge was detected. The input capture consists of an input capture register corresponding to four I/O pins, an input capture control status register, and an edge detection circuit. • When an edge is detected, either rising, falling, or both can be selected. • An interrupt request can be generated to the CPU when an input signal edge is detected. • Interrupts launch the extended intelligent I/O service (EI2OS) . • Since the input capture has four pairs of input pins and input capture data registers, it can measure up to 4 phenomena. • Block Diagram of 16-bit I/O Timer Internal data bus Input capture Dedicated bus 16-bit free-run timer 16-bit free-run timer: The counter value of the 16-bit free-run timer is used as the base time of the input capture. Input capture: Input capture detects rising, falling and both edges for external signals input to input pins, and stores the counter value of the 16-bit free-run timer. Interrupts can be generated in response to input signal edge detection. 39 MB90495G Series • Block Diagram of 16-bit Free-run Timer Timer counter data register (TCDT) Pin FRCK OF CLK 16-bit free-run timer STOP CLR Internal data bus Free-run timer interrupt request Output count value to input capture φ Prescaler 2 Timer counter control status register (TCCS) IVF IVFE STOP Re- CLR CLK2 CLK1 CLK0 served φ OF : Machine clock : overflow Note: The 16-bit I/O timer contains one 16-bit free-run timer. The interrupt request number of the 16-bit free-run timer is as follows : Interrupt request number : 19 (13H) Prescaler: Takes a fraction of the machine clock, and supplies a count clock to the 16-bit up-counter. One of four machine clock fractions can be selected by setting the timer counter control status register (TCCS) . Timer Counter Register (TCDT) : This is a 16-bit up-counter. It is possible to read the current counter value of the 16-bit free-run timer by reading this counter. The counter can be set to an arbitrary value by writing to it while stopped. Timer Counter Control Status Register (TCCS) : TCCS selects the divide ratio of a machine clock, executes software clear of counter values. and enables or disables counter operation. Also TCCS confirms and clears an overflow generation flag, and enables or disables interruption. 40 MB90495G Series • Input Capture Block Diagram 16-bit free-run timer Edge detection circuit IN3 Pin Input capture data register 3 (IPCP3) IN2 Pin 2 2 Input capture data register 2 (IPCP2) Input capture control status register ICP1 ICP0 ICE1 ICE0 EG11EG10EG01EG00 (ICS23) Internal data bus Input capture interrupt request Input capture control status register (ICS01) ICP1 ICP0 ICE1 ICE0 EG11EG10EG01EG00 2 IN1 Pin 2 Input capture data register 1 (IPCP1) IN0 Pin Edge detection circuit Input capture data register 0 (IPCP0) 41 MB90495G Series 5. 16-bit Reload Timer The functions of the 16-bit reload timer are as follows : • Choose one of three internal clocks or an external event clock as the count clock. • Choose a software or external launch trigger. • An interrupt can be sent to the CPU in response to an underflow generated by the 16-bit timer register. Interrupts can be used to utilize the timer as an interval timer. • When an underflow is generated by the 16-bit timer register (TMR) , select one-shot mode, where TMR counter operation is halted, or reload mode, where the 16-bit reload register value is reloaded, and TMR count operation continues. • Supports extended intelligent I/O service (EI2OS) . • The MB90495G Series features two on-chip 16-bit reload timer channels. • 16-bit Reload Timer Operation Mode Count Clock Launch Trigger Internal clock mode Event count mode Software trigger External trigger Software trigger Operation in Case of Underflow One-shot mode Reload mode One-shot mode Reload mode • Internal Clock Mode • Set the count clock selection bits of the timer control status register (TMCSR : CSL1, CSL0) to “00B”, “01B” or “10B” to set the 16-bit reload timer to internal clock mode. • In internal clock mode, the timer counts down in synchronization with the internal clock. • Set the count clock selection bits of the timer control status register (TMCSR : CSL1, CSL0) to select one of three count clock intervals. • Select software-triggered or externally triggered (edge detection) launch. 42 MB90495G Series • 16-bit Reload Timer Block Diagram Internal data bus TMRLR 16-bit reload register Reload signal TMR 16-bit timer register CLK Count clock generation circuit Gate input Valid clock determination circuit Reload control circuit UF Machine clock φ Prescaler 3 Wait signal Output to on-chip peripheral functions Clear Internal clock Pin TIN 3 Select function I/O control circuit External clock 2 CLK Clock selector Select signal Output control circuit Output signal generation circuit EN Pin TOT Operation control circuit     CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG Timer control status register (TMCSR) Output interrupt request 43 MB90495G Series 6. Watch Timer The watch timer is a 15-bit free-run counter that counts up in synchronization with the subclock. • Eight different intervals can be selected, and interrupt requests generated for each interval time. • Supplies a timer for subclock oscillation stabilization standby, and an operational clock for the watchdog timer. • The subclock is always the count clock, regardless of the clock selection register (CKSCR) setting. • Interval timer feature • When the interval time set by the interval time selection bits (WTC : WTC2 to WTC0) is reached, the clock timer generates an overflow in the bits corresponding to the interval time of the watch timer counter, and sets the overflow flag bit (WTC : WTOF = 1) . • Interrupts arising from overflows are enabled (WTC : WTIE = 1) , an interrupt request is generated when the overflow flag bit is set (WTC : WTOF = 1) . • Select from one of the following 8 watch timer intervals : Clock Timer Interval Times Subclock Frequency 8 Interval Time 2 /SCLK (31.25 ms) 29/SCLK (62.5 ms) 210/SCLK (125 ms) 211/SCLK (250 ms) 212/SCLK (500 ms) 213/SCLK (1.0 s) 214/SCLK (2.0 s) 215/SCLK (4.0 s) SCLK (122 µs) SCLK : Subclock frequency Figures in parentheses ( ) are a sample calculation with the subclock running at 8.192 kHz. 44 MB90495G Series • Watch Timer Block Diagram To watchdog timer Watch timer counter SCLK × 21 × 22 × 23 × 24 × 25 × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 OF OF OF OF OF OF OF Power-on reset Go to hardware standby Go to stop mode Interval timer selector Counter clear circuit To subclock oscillation stabilization standby time OF Watch timer interrupt WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 Watch timer control register (WTC) OF : Overflow SCLK : Subclock Notes: The actual interrupt request number generated by the watch timer is as follows : Interrupt request number : #28 (1CH) Watch timer counter: 15-bit up counter using the subclock (SCLK) as its count clock. Counter clear circuit: This circuit clears the watch timer counter. 45 MB90495G Series 7. 8/16-Bit PPG The 8/16-bit PPG timer is a 2-channel reload timer module (PPG0, PPG1) capable of arbitrary synchronization and pulse output of duty ratio. Combining the 2 channel module can yield the following behavior : • 8-bit PPG output, 2-channel independent operation mode • 16-bit PPG output operation mode • 8 + 8-bit PPG output operation mode The MB90495G Series features two on-chip, 8/16-bit PPG timers. This section describes the functions of PPG0/ 1. PPG2/3 has the same functions as PPG0/1. • 8/16-bit PPG Timer Functions The 8/16-bit PPG timer is made up of four 8-bit reload registers (PRLH0/PRLL0, PRLH1/PRLL1) , and two PPG down counters (PNT0, PCNT1) . • Since you can set each output pulse to “H” or “L” width independently, the interval and duty ratio of each pulse can be set to an arbitrary value. • Select one of 6 internal clocks as the count clock. • Interrupt requests can be generated for each interval time, allowing the timer to be used as an interval timer. • The use of an external circuit allows the timer to be used as a D/A converter. 46 MB90495G Series • Block Diagram of 8/16-Bit PPG Timer 0 "H" level side data bus "L" level side data bus PPG0 reload register PRLH0 ("H" level side) PRLL0 ("L" level side) PEN0  PE0 PPG0 operation mode control register (PPGC0) PIE0 PUF0   Reserved PPG0 temporary buffer 0 (PRLBH0) R S 2 Q Output interrupt request* Reload register L/H selector Initial count value Select signal Operation mode control signal PPG0 underflow PPG1 underflow (to PPG1) Reload Underflow Clear Pulse selector PPG0 down counter (PCNT0) CLK Invert Time-base timer output (512/HCLK) Peripheral clock (1/φ) Peripheral clock (2/φ) Peripheral clock (4/φ) Peripheral clock (8/φ) Peripheral clock (16/φ) 3 PPG0 output latch Pin PPG0 PPG output control circuit Count clock selector Select signal PCS2 PCS1 PCS0 PCM2 PCM1 PCM0   PPG0/1 count clock selection register (PPG01)  Reserved HCLK φ * : Undefined : Reserved bit : Oscillation clock frequency : Machine clock frequency : Interrupt output from 8/16-bit PPG timer 0 is merged with interrupt request output from PPG timer 1 into a single interrupt via an OR circuit. 47 MB90495G Series • Block Diagram of 8/16-Bit PPG Timer1 "H" level side data bus "L" level side data bus PPG1 operation mode control register (PPGC1) PPG1 reload register Operation mode control signal PPG1 temporary buffer (PRLBH1) PRLH1 ("H" side) PRLL1 ("L" side) PEN1  2 Output interrupt request* Q PE10 PIE1 PUF1 MD1 MD0 Reserved R S Reload selector L/H selector Initial count value Reload Underflow Select signal Clear PPG1 output latch PPG1 down counter (PCNT1) PPG1 underflow (to PPG0) CLK Invert Pin PPG1 PPG output control circuit MD0 PPG0 underflow (from PPG0) Time-base timer output (512/HCLK) Peripheral clock (1/φ) Peripheral clock (2/φ) Peripheral clock (4/φ) Peripheral clock (8/φ) Peripheral clock (16/φ) Counter clock selector 3 Select signal   PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PPG0/1 count clock selection register (PPG01)  Reserved HCLK φ * : Undefined : Reserved bit : Oscillation clock frequency : Machine clock frequency : Interrupt output from 8/16-bit PPG timer 1 is merged with interrupt request output from PPG timer 0 into a single interrupt via an OR circuit. 48 MB90495G Series 8. Delayed Interrupt Generation Module The delayed interrupt generation module generates interrupts for switching tasks. This module can be used to generate hardware interrupts from the software. • Overview of the Delayed Interrupt Generation Module Use the delayed interrupt generation module to generate or cancel hardware interrupts from the software. Overview of the Delayed Interrupt Generation Module Functions and Control When the R0 bit of the delayed interrupt request generation/cancel register is set to 1 (DIRR : R0 = 1) : Generate interrupt request When the R0 bit of the delayed interrupt request generation/cancel register is set to 0 (DIRR : R0 = 0) : Cancel interrupt request #42 (2AH) There is no enable setting from the register Stored in bit DIRR : R0 Does not support extended intelligent I/O service Interrupt Condition Interrupt number Interrupt control Interrupt flag EI OS 2 • Delayed Interrupt/Generation Module Block Diagram Internal data bus        R0 Delayed interrupt request generation/cancel register (DIRR) S Interrupt R request latch Interrupt request signal  : Undefined Interrupt request latch:This latch stores the delayed interrupt request generation/cancel register setting (generates/cancels delayed interrupt requests) . Delayed interrupt request generation/cancel register (DIRR) : Generates or cancels delayed interrupt requests. • Interrupt number Below is the interrupt number used by the delayed interrupt generation module. Interrupt number : #42 (2AH) 49 MB90495G Series 9. DTP/External Interrupts The DTP/external interrupt transmits interrupt requests or data transfer requests generated by peripheral devices to the CPU, generates external interrupt request, and starts the extended intelligent I/O service (EI2OS) . • DTP/External Interrupt Functions Outputs interrupt requests from external peripheral devices to the CPU using the same procedure as for peripheral functions, and generates external interrupts, or starts the extended intelligent I/O service (EI2OS) . If the interrupt control register is configured to prohibit the extended intelligent I/O service (EI2OS) (ICR : ISE = 0) , then the external interrupt feature becomes valid, and the process branches into interrupt processing. If the EI2OS is enabled (ICR : ISE = 1) , then the DTP function becomes valid, and the EI2OS automatically transmits data, and after transmitting data a specified number of times, branches into interrupt processing. Overview of DTP/External Interrupts External interrupt Input pins Interrupt condition Interrupt numbers Interrupt control Interrupt flag Process selection Processing 8 (INT0 to INT7) Each pin sets individually in the detection level configuration register (ELVR) “H” / “L” level/rising edge/falling edge input “H” / “L” level input #15 (0FH) , #20 (14H) , #24 (18H) , #27 (1BH) The DTP/external interrupt enable register (ENIR) enables or prohibits interrupt request output Interrupt conditions stored by DTP/external interrupt condition register (EIRR) Set EI2OS to prohibited (ICR : ISE = 0) Branch to external interrupt process Set EI2OS to enabled (ICR : ISE = 1) After the EI2OS conducts automated data forwarding the specified number of times, branches to interrupt processing. DTP functions 50 MB90495G Series • DTP/External Interrupt Block Diagram Detection level configuration register (ELVR) LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 Pin INT7 Level/ edge selector Pin INT3 Level/ edge selector Pin INT6 Level/ edge selector Pin INT2 Level/ edge selector Internal data bus Pin INT5 Level/ edge selector Pin INT1 Level/ edge selector Pin INT4 Level/ edge selector Pin INT0 Level/ edge selector DTP/external interrupt input detection circuit ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 DTP/external interrupt condition register (EIRR) Interrupt request signal Interrupt request signal EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 DTP/external interrupt enable register (ENIR) 51 MB90495G Series 10. 8/10-bit A/D Converter The 8/10-bit A/D converter converts analog voltage to 8 or 10-bit digital values, by means of RC successive approximation conversion. • The input signal can be selected from an 8-channel analog input pin set. • Select a software trigger, internal timer output, or external trigger as the start trigger. • Functions of the 8/10 A/D Converter Converts analog voltage (input voltage) input to the analog input pins to 8-bit or 10-bit digital values. (A/D conversion) The 8/10-bit A/D converter has the following features : • Single-channel A/D conversion time is a minimum of 6.12 µs, including sampling time.* • Single-channel sampling time is a minimum of 2.0 µs.* • RC-type successive approximation with sampling and hold circuits is used for conversion. • Select 8 or 10-bit resolution. • Analog input pins can use up to 8 channels. • A/D conversion results are stored in the A/D data register, allowing them to be used to generate interrupts. • Interrupt requests launch the EI2OS. Use the EI2OS to prevent dropped data even with continuous A/D conversion. • Select software, internal timer output, or external trigger (falling edge) as the start trigger. * : With machine clock operating at 16 MHz • Conversion Modes of the 8/10-bit A/D Converter Conversion Mode Single conversion mode Description Conducts A/D conversion for each channel in turn, from the start channel to the end channel. When A/D conversion of the end channel is completed, the A/D conversion function halts. Conducts A/D conversion for each channel in turn, from the start channel to the end channel. When A/D conversion of the end channel is completed, the function returns to the start channel and continues A/D conversion. Suspends each channel and conducts A/D conversion, one at a time. When A/D conversion of the end channel is completed, the function returns to the start channel and repeats the A/D conversion and channel stop. Continuous conversion mode Stop conversion mode 52 MB90495G Series • 8/10-bit A/D Converter Block Diagram Output interrupt request A/D control status register ReBUSY INT INTE PAUS STS1 STS0 STAT served MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 (ADCS) 2 6 ADTG TO Launch Selector 2 Decoder φ Comparator AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 Sample and hold circuit Analog channel selector AVR AVCC AVSS 2 2 A/D data register S10 ST1 ST0 CT1 CT0  (ADCR) D/A converter Control circuit D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TO  Reserved φ : Internal timer output : Undefined : Make sure this is always set to “01” : Machine clock Internal data bus 53 MB90495G Series 11. UART0/1 The UART is a general-purpose serial data communications interface for synchronous or asynchronous communication with external devices. • The UART has a clock-synchronous/clock-asynchronous two-way communications feature . • Also supplies a master/slave communications feature (multi-processor mode) . (It can be used only master side.) • Interrupts can be generated upon send complete, receive complete, or reception error detection. • Supports extended intelligent I/O service (EI2OS) . • UART0/1 Functions Functions Data Buffer Transfer mode Full-duplex double buffer • Clock-synchronous (no start, stop, or parity bit) • Clock-asynchronous (start-stop synchronization) • Select from 8 dedicated baud rate generators • External clock input possible • Clock supplied from internal timer (16-bit reload timer) available • 7-bit (asynchronous normal mode only) • 8-bit Non Return to Zero (NRZ) • Framing error • Overrun error • Parity error (not available in operation mode 1 (multi processor mode) ) • Receive interrupt (reception complete, reception error detected) • Send interrupt (send complete) • Both send and receive support extended intelligent I/O service (EI2OS) 1-to-n (master to slave) communication available (can only be used as master) Baud Rate Data length Signal method Reception Error Detection Interrupt Requests Master/Slave Communications Function (In multiprocessor mode) Note : During clock-synchronous forwarding, just the data is forwarded, with no stop or start bit appended. 54 MB90495G Series • UART0 Block Diagram Control bus Reception interrupt request output Send clock Clock selector Send interrupt request output Dedicated baud rate generator 16-bit reload timer0 Reception clock Pin SCK0 Reception control circuit Send control circuit Send start circuit Send bit counter Send parity counter Pin SOT0 Start bit detection circuit Reception bit counter Reception parity counter Pin SIN0 Reception shift register Reception end Send shift register Send start Serial output data register0 EI2OS receive error generation signal (to CPU) Reception status determination circuit Serial input data register0 Internal data bus Serial edge selection register NEG Communications prescaler control register MD DIV3 DIV2 DIV1 DIV0 Serial mode register0 MD1 MD0 CS2 CS1 CS0 SCKE SOE Serial control register0 PEN P SBL CL A/D REC RXE TXE Serial status register0 PE ORE FRE RDRF TDRE RIE TIE 55 MB90495G Series • UART1 Block Diagram Control bus Reception interrupt request output Send clock Clock selector Send interrupt request output Dedicated baud rate generator 16-bit reload timer1 Reception clock Pin SCK1 Reception control circuit Send control circuit Send start circuit Send bit counter Send parity counter Pin SOT1 Start bit detection circuit Reception bit counter Reception parity counter Pin SIN1 Reception shift register Reception end Send shift register Send start Serial output data register1 EI2OS receive error generation signal (to CPU) Reception status determination circuit Serial input data register1 Internal data bus Communications prescaler control register MD DIV2 DIV1 DIV0 Serial mode register1 MD1 MD0 CS2 CS1 CS0 RST SCKE SOE Serial control register1 PEN P SBL CL A/D REC RXE TXE Serial status register1 PE ORE FRE RDRF TDRE BDS RIE TIE 56 MB90495G Series 12. CAN Controller CAN (Controller Area Network) is a serial communications protocol conforming to CAN version 2.0 A and B. Sending and receiving is available in standard and extended frame format. • • • • • Can Controller Features The CAN controller format conforms to CAN versions 2.0 A and B. Sending and receiving is available in standard and extended frame format. Supports automated data frame formatting through remote frame reception. Baud rate : 10 Kbps to 1 Mbps. When using at 1 Mbps, the machine clock must be operated at 8 MHz or more. Baud rate (Max) 1 Mbps 1 Mbps 1 Mbps 500 Kbps Data Transmission Baud Rates Machine clock 16 MHz 12 MHz 8 MHz 4 MHz • • • • • 2 MHz 250 Kbps Supplies 8 send/receive message buffers. Sending and receiving available in standard frame format (ID 11-bit) , and extended frame format (ID 29-bit) . Message data can be set to 0 to 8 bytes. Possible to configure a multi-level message buffer. The CAN controller has two built-in acceptance masks, each of which can be set to a different mask for reception message IDs. • The two acceptance masks can receive in standard or extended frame format. • Configure four types of partial masks with full-bit compare, full-bit mask, and acceptance mask register 0/1. 57 MB90495G Series • CAN Controller Block Diagram EI2OS -16LX Bus CPU operation clock PSC TS1 BTR TS2 RSJ TOE TS RS CSR HALT NIE NT NS1,0 RTEC BVALR TREQR Clear send buffer Send buffer determination circuit Prescaler (1:1 to 1:64) Bit timing generation circuit Operation clock (TQ) Sink segment Timer segment 1 Timer segment 2 Node status transition interrupt generation circuit Node status transition interrupt signal Error control circuit Bus status determination circuit Idle/ interrupt/ suspend/ send/ receive/ error/ overload Send/receive sequence Send buffer Acceptance Data filter control counter circuit Send ReID DLC ception selection DLC Bit error/ Staff error/ CRC error/ Frame error/ ACK error Error frame generation circuit Overload frame generation circuit Arbitration lost Send buffer TCANR TRTRR RFWTR TCR TIER RCR RIER RRTRR ROVRR AMSR AMR0 AMR1 IDR0 to IDR7 DLCR0 to DLCR7 DTR0 to DTR7 RAM Output driver Pin TX Send shift register Set/clear send buffer Send complete interrupt generation circuit Set reception buffer Reception complete interrupt generation circuit Reception buffer Set/clear send buffer Set reception Select ID buffer Send complete interrupt signal Reception complete interrupt signal Send DLC Staffing ACK CRC generation generation circuit circuit CRC error Receive CRC generation DLC circuit/error check Reception shift register Staff error Destaffing/ staffing error check 0 1 Acceptance filter Reception buffer determination circuit Reception buffer Arbitration lost Bit error Arbitration check Bit error check Acknowledgement error check Form error check Input latch Pin RX RAM address generation circuit IDER LEIR Reception buffer/ Send buffer/ Receive DLC/Send DLC/ Select ID ACK error Frame error 58 MB90495G Series 13. ROM Correction Function In the case that the address of the instruction after the one that a program is currently processing matches the address configured in the detection address configuration register, the program forces the next instruction to be processed into an INT9 instruction, and branches to the interrupt process program. Since processing can be conducted using INT9 interrupts, programs can be repaired using batch processing. • Overview of the ROM Correction Function • The address of the instruction after the one that a program is currently processing is always stored in an address latch via the internal data bus. ROM correction constantly compares the address stored in the address latch with the one configured in the detection address configuration register. If the two compared addresses match, the CPU forcibly changes this instruction into an INT9 instruction, and executes an interrupt processing program. • There are two detection address configuration registers : PADR0 and PADR1. Each register provides an interrupt enable bit. This allows you to individually configure each register to enable/prohibit the generation of interrupts when the address stored in the address latch matches the one configured in the detection address configuration register. • ROM Correction Block Diagram Address latch Comparator INT9 instruction (INT9 interrupt generation) Internal data bus PADR0 (24 bit) Detection address configuration register 0 PADR1 (24 bit) Detection address configuration register 1 PACSR Reserved Reserved Reserved Reserved AD1E Reserved AD0E Reserved Address detection control register (PACSR) Reserved : Make sure this is always set to “01” • Address latch Stores value of address output to internal data bus. • Address detection control register (PACSR) Set this register to enable/prohibit interrupt output when an address match is detected. • Detection address configuration register (PADR0, PADR1) Configure an address with which to compare the address latch value. 59 MB90495G Series 14. ROM Mirror Function Selection Module The ROM mirror function selection module configures ROM-internal data arrayed inside bank FF to be readable by accessing bank 00. • ROM Mirror Function Selection Module Block Diagram ROM mirror function selection register (ROMM) Reserved Reserved Reserved Reserved Reserved Reserved Reserved MI Address Internal data bus Address area Bank FF Bank 00 Data ROM • Accessing Bank FF through ROM Mirror Function 004000H 00FFFFH Bank 00 ROM mirror area FC0000H FE0000H FEFFFFH FF0000H MB90F498G FF4000H Bank FF (Area corresponding to ROM mirror) MB90F497G MB90497G MB90V495G FFFFFFH 60 MB90495G Series 15. 512-K/1-M bit Flash Memory • Overview There are three methods available for writing/deleting data to/from flash memory : 1. Parallel writer 2. Serial dedicated writer 3. Program runtime write/delete • Overview of 512-K/1-M bit flash memory 512-Kbit flash memory is arrayed in bank FFH on the CPU memory map, 1-Mbit flash memory is arrayed in bank FEH to FFH on the CPU memory map. The flash memory interface circuit provides read and program access from the CPU. Since instructions from the CPU are carried out via the flash memory interface circuit, flash memory can be overwritten at the implementation level. This allows you to efficiently improve programs and data. • Features of 512-K/1-M bit Flash Memory • 512-Kbit flash memory : 64 KWords × 8-bit/32 KWords × 16-bit (16 Kbyte + 8 Kbyte + 8 Kbyte + 32 Kbyte) sector architecture • 1-Mbit flash memory : 128 KWords × 8-bit/64 KWords × 16-bit (16 Kbyte + 8 Kbyte + 8 Kbyte + 32 Kbyte + 64 Kbyte) sector architecture • Auto program algorithm (Embedded AlgorithmTM : same as MBM29LV200) • On-chip delete suspend/delete resume functions • Data polling, write/delete completion detection through toggle bit • Write/delete completion detection from CPU overwrite • Sector-specific deletion available (sectors can be combined as desired) • Write/delete iterations (minimum) : 10,000 Embedded AlgorithmTM is a trademark of Advanced Micro Device. Notes : There is no function to read the manufacture or device code. These codes also cannot be accessed through commands. • Flash memory write/delete • It is not possible to simultaneously write to and read from flash memory. • When writing to or deleting from flash memory, first copy the program residing in flash memory into RAM, then execute the program copied into RAM. This will allow you to write to flash memory. 61 MB90495G Series • List of Flash Memory Registers and Reset Values Flash memory control status register (FMCS) × : Undefined bit 7 0 6 0 5 0 4 X 3 0 2 0 1 0 0 0 • Sector Architecture of 512-K/1-M bit Flash memory • Sector architecture 512-Kbit flash memory : When accessing from the CPU, SA0 to SA3 are arrayed in the Bank FF register. 1-Mbit flash memory : When accessing from the CPU, SA0 is arrayed in the Bank FE register, SA1 to SA4 are arrayed in the Bank FF register. Sector Architecture of 512-K/1-M bit Flash Memory 512-Kbit Flash Memory CPU Addresses FF0000H Writer Address* 70000H 77FFFH 78000H 79FFFH 7A000H 7BFFFH 7C000H 7FFFFH SA0 (32 Kbytes) FF7FFFH FF8000H SA1 (8 Kbytes) FF9FFFH FFA000H SA2 (8 Kbytes) FFBFFFH FFC000H SA3 (16 Kbytes) FFFFFFH 1-Mbit Flash Memory CPU Addresses FE0000H Writer Address* 60000H 6FFFFH 70000H 77FFFH 78000H 79FFFH 7A000H 7BFFFH 7C000H 7FFFFH SA0 (64 Kbytes) FEFFFFH FF0000H SA1 (32 Kbytes) FF7FFFH FF8000H SA2 (8 Kbytes) FF9FFFH FFA000H SA3 (8 Kbytes) FFBFFFH FFC000H SA4 (16 Kbytes) FFFFFFH * : If a parallel write is writing data to Flash memory, the write address corresponds to the CPU address. If a general-purpose writer is used to write/delete, this address is written to/over. 62 MB90495G Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol VCC Power supply voltage Input voltage Output voltage Maximum clamp current Total maximum clamp current “L” level maximum output current “L” level average output current “L” level maximum total output current “L” level average total output current “H” level maximum output current “H” level average output current “H” level maximum total output current “H” level average total output current Power consumption Operating temperature Storage temperature AVCC AVR VI VO ICLAMP Σ| ICLAMP | IOL IOLAV ΣIOL ΣIOLAV IOH IOHAV ΣIOH ΣIOHAV PD TA Tstg Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 − 2.0           −40 −40 −55 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 + 2.0 20 15 4 100 50 −15 −4 −100 −50 315 +105 +125 +150 Unit V V V V V mA mA mA mA mA mA mA mA mA mA mW °C °C °C *7 *5 *5 *3 *4 VCC = AVCC AVCC ≥ AVR *1 *1 *2 *2 *6 *6 *3 *4 (VSS = AVSS = 0 V) Remarks *1 : AVCC and AVR shall never exceed VCC. Also, AVR shall never exceed AVCC. *2 : VI and VO shall never exceed VCC + 0.3 V. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *3 : The rating for the maximum output current is the peak value of one of the corresponding pins. *4 : The standard for computing average output current is the average current output from one of the corresponding pins over a period of 100 ms (the average value is taken by multiplying operating current by operational rate) . *5 : The standard for computing average total output current is the average current output from all of the corresponding pins over a period of 100 ms (the average value is taken by multiplying operating current by operational rate) . *6 : • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P44, P50 to P57, P60 to P63 • Use within recommended operating conditions. • Use at DC voltage (current) • The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. (Continued) 63 MB90495G Series (Continued) • Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the +B input pin open. • Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. • Sample recommended circuits: Protective diode VCC Limiting resistance +B input (0 V to 16 V) P-ch N-ch R *7 : If used exceeding TA = +105 °C, be sure to contact us for reliability limitations. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 64 MB90495G Series 2. Recommended Operating Conditions Value Min 4.5 Power supply voltage VCC, AVCC 4.75 3.0 Smoothing capacitor Operating temperature CS TA 0.022 −40 −40 Typ 5.0 5.0  0.1   Max 5.5 5.25 5.5 1.0 +105 +125 (VSS = AVSS = 0.0 V) Unit V V V µF °C °C *2 Remarks During normal operation, TA = −40 °C to +105 °C During normal operation, +105 °C < TA ≤ +125 °C Maintaining stop operation state *1 Parameter Symbol *1 : Use a ceramic capacitor, or one with approximately the same frequency characteristics. The bypass capacitor of the VCC pin should have a greater capacity than CS. See the figure below for details about connecting a smooth capacitor to the CS. *2 : If used exceeding TA = +105 °C, be sure to contact us for reliability limitations. • C Pin Connection Diagram C CS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 65 MB90495G Series 3. DC Characteristics (VCC = 5.0 V ± 5%, VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C) (VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Condition Value Min 0.8 VCC VCC − 0.3 VSS − 0.3 VSS − 0.3 VCC − 0.5 VCC − 0.5 Parameter “H” level input voltage “L” level input voltage “H” level output voltage “L” level output voltage Symbol VIHS Pin Name CMOS hysteresis input pin CMOS hysteresis input pin MD input pin All output pins All output pins Typ           Max VCC + 0.3 VCC + 0.3 Unit Remarks     VCC = 4.5 V, IOH = −4.0 mA VCC = 4.75 V VCC = 4.5 V, IOL = 4.0 mA VCC = 4.75 V VCC = 5.5 V, VSS < VI < VCC VCC = 5.25 V, VSS < VI < VCC VCC = 5.0 V Internal 16-MHz operation, Normal mode VCC = 5.0 V Internal 16-MHz operation, Flash memory write mode VCC = 5.0 V Internal 16-MHz operation, Flash memory delete mode VCC = 5.0 V Internal 16-MHz operation, Sleep mode V V V V V V V V TA = −40 °C to +105 °C +105 °C < TA ≤ +125 °C TA = −40 °C to +105 °C +105 °C < TA ≤ +125 °C VIHM MD input pin VILS VILM VOH 0.2 VCC VSS + 0.3   0.4 0.4 5 5 VOL   −5 −5 Input leakage current IIL All output pins µA TA = −40 °C to +105 °C µA +105 °C < TA ≤ +125 °C MB90497G mA MB90F497G MB90F498G  30 40 ICC Power supply current* VCC  45 50 mA MB90F497G MB90F498G  45 50 mA MB90F497G MB90F498G ICCS  11 18 MB90497G mA MB90F497G MB90F498G (Continued) 66 MB90495G Series (Continued) (VCC = 5.0 V ± 5%, VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C) (VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) SymPin Name bol ICTS Condition VCC = 5.0 V Internal 2-MHz operation, Timer mode VCC = 5.0 V Internal 8-kHz operation, Subclock operation mode TA = + 25 °C VCC ICCLS VCC = 5.0 V Internal 8-kHz operation, Subclock sleep mode TA = + 25 °C VCC = 5.0 V Internal 8-kHz operation, Clock mode TA = + 25 °C VCC Other than AVCC, AVSS, AVR, C, VCC, or VSS RST VCC = 5.0 V Stop mode, TA = + 25 °C Value Min    Typ 0.6 30 300 Max 1.2 50 500 Unit Remarks Parameter MB90497G mA MB90F497G MB90F498G µA MB90497G µA MB90F497G MB90F498G ICCL Power supply current*  10 30 MB90497G µA MB90F497G MB90F498G MB90497G µA MB90F497G MB90F498G MB90497G µA MB90F497G MB90F498G ICCT  8 25 Power supply current* ICCH  5 20 Input Capacity CIN   5 15 pF Pull up Resistor Pull down Resistor RUP   25 25 50 50 100 100 kΩ kΩ RDOWN MD2 * : This is when using the external clock as the power supply current test condition. 67 MB90495G Series 4. AC Characteristics (1) Clock Timing (VCC = 5.0 V ± 5%, VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C) (VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Symbol fC fCL tHCYL tLCYL PWH, PWL PWLH, PWLL Input clock rising/falling time Internal operation clock frequency Internal operation clock cycle time tCR, tCF fCP fLCP tCP tLCP Pin Name X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0     Value Min 3  62.5  10   1.5  62.5  Typ  32.768  30.5  15.2   8.192  122.1 Max 16  333    5 16  666  Unit MHz kHz ns µs ns µs ns MHz kHz ns µs When external clock used When oscillation circuit used When subclock used When using oscillation circuit When subclock used Duty ratio should be around 30 % to 70 % Remarks Parameter Clock frequency Clock Cycle Time Input clock pulse width • X0/X1 Clock Timing tHCYL X0 PWH tCF tLCYL PWL tCR 0.8 VCC 0.2 VCC X0A PWLH tCF PWLL tCR 0.8 VCC 0.2 VCC 68 MB90495G Series • PLL guaranteed operation range Relationship between internal operating clock frequency and power supply voltage MB90F497G/MB90F498G/MB90497G guaranteed operation range (TA = −40°C to +105°C) 5.5 5.25 4.75 4.5 MB90F497G/MB90F498G/MB90497G guaranteed operation range ( = +105°C < TA ≤ +125°C) Power supply voltage VCC (V) PLL guaranteed operation range 3.3 3.0 1.5 3 8 Internal clock fCP (MHz) 12 16 Relationship between external clock frequency and internal operation clock frequency ×4 ×3 ×2 ×1 16 Internal clock fCP (MHz) 12 9 8 ×1/2 (no multiplication) 4 3 4 8 External clock fC (MHz) 16 AC characteristics are specified by the following reference voltage values. • Input Signal Waveform Hysteresis Input Pin 0.8 VCC 0.2 VCC • Output Signal Waveform Output Pin 2.4 V 0.8 V 69 MB90495G Series (2) Clock Output Timing (VCC = 5.0 V ± 5%, VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C) (VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Symbol tCYC tCHCL Pin Name CLK Condition  Value Min 62.5 20 Max   Unit ns ns Remarks Parameter Cycle time CLK ↑ → CLK ↓ tCYC tCHCL 2.4 V 0.8 V 2.4 V CLK (3) Reset Input Timing Parameter Symbol Pin Condition Name Value Min 16 tCP Reset input time tRSTL RST  Oscillator oscillation time* + 16 tCP Max   Unit ns Remarks Normal mode Stop mode, Watch mode, Subclock mode, Subsleep mode ms * : Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to several dozen ms; for a FAR/ceramic oscillator, this is several hundred µs to a few ms, and for an external clock this is 0 ms. • Stop mode, Watch mode, Subclock mode, Subsleep mode tRSTL RST 0.2 VCC 90% of amplitude 0.2 VCC X0 Internal operation clock Oscillator oscillation time 16 tCP Oscillation stabilize standby time Instruction execution Internal reset 70 MB90495G Series (4) Power-on Reset (VCC = 5.0 V ± 5%, VSS = AVSS = 0.0 V, TA = −40 °C to +125 °C) (VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Symbol tR tOFF Pin Name VCC VCC Condition  Value Min 0.05 1 Max 30  Unit ms ms Due to repeated operations Remarks Parameter Power supply rising time Power supply cutoff time tR 2.7 V 0.2 V 0.2 V tOFF 0.2 V VCC Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended that you raise the voltage at a steady rate, in order to suppress fluctuations (see figure below). In this case, perform this operation when the PLL clock is not being used. If, however, the voltage falling speed is no more than 1 V/s, it is permissible to perform this operation while using the PLL clock. VCC 3V VSS RAM data hold period It is recommended that you keep the rising speed to no more than 50 mV/ms. 71 MB90495G Series (5) Bus Read Timing (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +105 °C) Symbol tLHLL tAVLL tLLAX tAVRL tAVDV tRLRH tRLDV tRHDX tRHLH tRHAX tAVCH tRLCH tLLRL Pin Name ALE ALE, A23 to A16, AD15 to AD00 ALE, AD15 to AD00 A23 to A16, AD15 to AD00, RD A23 to A16, AD15 to AD00 RD RD, AD15 to AD00 RD, AD15 to AD00 RD, ALE RD, A23 to A16 A23 to A16, AD15 to AD00, CLK RD, CLK ALE, RD Value Min tCP/2 − 20 tCP/2 − 20 tCP/2 − 15 tCP − 15  3 tCP/2 − 20  0 tCP/2 − 15 tCP/2 − 10 tCP/2 − 20 tCP/2 − 20 tCP/2 − 15 Max     5 tCP/2 − 60  3 tCP/2 − 60       Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks Parameter ALE pulse width Valid address → ALE ↓ time ALE ↓ → address valid time Valid address → RD ↓ time Valid address → Valid data input RD pulse width RD ↓ → valid data input RD ↑ → data hold time RD ↓ → ALE ↑ time RD ↑ → address valid time Valid address → CLK ↑ time RD ↓ → CLK ↑ time ALE ↓ → RD ↓ time 72 MB90495G Series • Bus read timing tAVCH 2.4 V tRLCH 2.4 V CLK tAVLL tLLAX 2.4 V tLHLL tAVRL 0.8 V tRLRH 2.4 V 0.8 V tLLRL tRHAX 2.4 V 2.4 V 0.8 V tAVDV tRLDV tRHDX 2.4 V Address 0.8 V 0.8 V 0.2 VCC 0.8 VCC Read data 0.2 VCC 0.8 VCC tRHLH 2.4 V ALE 2.4 V RD A23 to A16 0.8 V AD15 to AD00 2.4 V 73 MB90495G Series (6) Bus Write Timing (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +105 °C) Symbol tAVWL tWLWH tDVWH tWHDX tWHAX tWHLH tWLCH Pin Name A23 to A16, AD15 to AD00, WR WR AD15 to AD00, WR A23 to A16, WR WR, ALE WR, CLK Value Min tCP − 15 3 tCP/2 − 20 20 tCP/2 − 10 tCP/2 − 15 tCP/2 − 20 Max        Unit ns ns ns ns ns ns ns Remarks Parameter Valid Address → WR ↓ time WR pulse width Valid data output → WR ↑ time WR ↑ → data hold time WR ↑ → address valid time WR ↑ → ALE ↑ time WR ↑ → CLK ↑ time AD15 to AD00, WR 3 tCP/2 − 20 tWLCH 2.4 V CLK tWHLH 2.4 V ALE tAVWL tWLWH 2.4 V 0.8 V WR (WRL, WRH) tWHAX 2.4 V 2.4 V 0.8 V tDVWH tWHDX 2.4 V Write data 0.8 V 0.8 V A23 to A16 0.8 V AD15 to AD00 2.4 V Address 0.8 V 2.4 V 74 MB90495G Series (7) Ready Input Timing (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +105 °C) Symbol tRYHS tRYHH Pin Name RDY RDY Value Min 45 0 Max   Unit ns ns Remarks Parameter RDY setup time RDY hold time Note : Use the automatic ready function if the setup time for the falling edge of the RDY signal is not sufficient. • Ready Input timing 2.4 V CLK ALE RD/WR tRYHS tRYHH 0.8 VCC RDY Unweighted RDY Weighted (1 cycle) 0.8 VCC 0.2 VCC (8) Hold Timing (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +105 °C) Symbol Pin Name tXHAL tHAHV HAK HAK Value Min 30 tCP Max tCP 2 tCP Unit ns ns Remarks Parameter Pin in floating status → HAK ↓ time HAK ↑ → pin valid time Note : It will take at least 1 cycle from the time the HRQ pin is loaded until the HAK changes. • Hold Timing HAK 0.8 V tXHAL tHAHV 2.4 V High-Z 0.8 V 2.4 V Each pin 2.4 V 0.8 V 75 MB90495G Series (9) UART Timing (VCC = 5.0 V±5%, VSS = 0.0 V, TA = −40 °C to +125 °C) (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +105 °C) Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin Name SCK1 SCK1, SOT1 Internal shift clock mode output pin : SCK1, SIN1 CL = 80 pF + 1 TTL SCK1, SIN1 SCK1 Eternal shift clock SCK1, SOT1 mode outputpin : CL = 80 pF + 1 TTL SCK1, SIN1 SCK1, SIN1 SCK1 Condition Value Min 8 tCP* −80 100 60 4 tCP 4 tCP  60 60 Max  80     150   Unit ns ns ns ns ns ns ns ns ns Remarks Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time * : See “ (1) Clock Timing” for details about tCP (internal operating clock cycle time) . Notes : • AC ratings are for CLK synchronous mode. • CL is the load capacitor value connected to pins while testing. 76 MB90495G Series • Internal shift clock mode SCK 0.8 V tSLOV 2.4 V tSCYC 2.4 V 0.8 V SOT 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC SIN 0.2 VCC • External shift clock mode SCK 0.2 VCC tSLOV 2.4 V tSLSH 0.2 VCC tSHSL 0.8 VCC 0.8 VCC SOT 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC SIN 0.2 VCC 77 MB90495G Series (10) Timer Input Timing (VCC = 5.0 V±5%, VSS = 0.0 V, TA = −40 °C to +125 °C) (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +105 °C) Symbol tTIWH tTIWL Pin Name TIN0, TIN1, FRCK IN0 to IN3, FRCK Condition  Value Min 4 tCP Max  Unit ns Remarks Parameter Input pulse width • Timer Input Timing TIN0, TIN1, IN0 to IN3, FRCK 0.8 VCC 0.8 VCC 0.2 VCC tTIWH tTIWL 0.2 VCC (11) Timer Output Timing (VCC = 5.0 V±5%, VSS = 0.0 V, TA = −40 °C to +125 °C) (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +105 °C) Symbol tTO Pin Name TOT0, TOT1, PPG0 to PPG3 Condition  Value Min 30 Max  Unit Remarks ns Parameter CLK ↑ → TOUT change time • Timer Output Timing CLK 2.4 V TOT0, TOT1, PPG0 to PPG3 tTO 2.4 V 0.8 V (12) Trigger Input Timing (VCC = 5.0 V±5%, VSS = 0.0 V, TA = −40 °C to +125 °C) (VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40 °C to +105 °C) Pin Name INT0 to INT7, ADTG Condition  Value Min 5 tCP 1 Max   Unit ns µs Remarks Normal mode Stop mode Parameter Input pulse width Symbol tTRGH tTRGL • Trigger Input Timing INT0 to INT7, ADTG 0.8 VCC 0.8 VCC 0.2 VCC tTRGH tTRGL 0.2 VCC 78 MB90495G Series 5. A/D Converter (VCC = AVCC = 5.0 V±5%, VSS = AVSS = 0.0 V, 3.0 V ≤ AVR − AVSS, TA = −40 °C to +125 °C) (VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, 3.0 V ≤ AVR − AVSS, TA = −40 °C to +105 °C) Symbol     VOT VFST   IAIN VAIN  IA IAH IR IRH  Pin Name     AN0 to AN7 AN0 to AN7   AN0 to AN7 AN0 to AN7 AVR AVCC AVCC AVR AVR AN0 to AN7 Value Min     AVSS − 3.5 LSB AVR − 6.5 LSB 66 tCP 32 tCP  AVSS AVSS + 3.0         AVSS + 0.5 LSB AVR − 1.5 LSB      2  0.9   Typ Max 10 ±5.0 ±2.5 ±1.9 AVSS + 4.5 LSB AVR + 1.5 LSB   10 AVR AVCC 7 5 1.3 5 4 Unit bit LSB LSB LSB V V ns ns µA V V mA µA mA µA LSB * * 1 LSB = AVR / 1024 Machine clock of 16 MHz Parameter Resolution Total error Nonlinearity error Differential linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling period Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Inter-channel variation Remarks * : Current (VCC = AVCC = AVR = 5.0 V) when A/D converter is not operating and CPU is halted. 79 MB90495G Series 6. A/D Converter Glossary Resolution Linearity error : Analog changes that are identifiable with the A/D converter : The deviation of the straight line connecting the zero transition point ( “00 0000 0000” ←→ “00 0000 0001” ) with the full-scale transition point ( “11 1111 1110” ←→ “11 1111 1111” ) from actual conversion characteristics. Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the ideal value. Total error : The difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error, linearity error, and differential linearity error. Total error 3FF 3FE 3FD Digital output {1 LSB × (N − 1) + 0.5 LSB} Actual conversion characteristics 1.5 LSB 004 003 002 001 0.5 LSB AVSS Analog input VNT (actual measurement) Actual conversion characteristics Ideal characteristics AVR Total error of digital output N = 1 LSB = (ideal value) VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVR − AVSS [V] 1024 [LSB] VOT (ideal value) = AVSS + 0.5 LSB [V] VFST (ideal value) = AVR − 1.5 LSB [V] VNT : The voltage to transition digital output from N − 1 to N. (Continued) 80 MB90495G Series (Continued) Linearity error 3FF 3FE 3FD Digital output Actual conversion characteristics {1 LSB × (N − 1) + VOT } N+1 VFST (actual measurement) VNT (actual measurement) Actual conversion characteristics Actual conversion characteristics Differential linearity error Ideal characteristics Digital output N 004 003 002 N−1 V (N + 1) T (actual measurement) VNT (actual measurement) Actual conversion characteristics AVR Analog input Ideal characteristics 001 VOT (actual measurement) AVSS Analog input AVR N−2 AVSS Linearity error of digital output N = Differential linearity error of digital output N = 1 LSB = VNT − {1 LSB × (N − 1) + VOT} 1 LSB V (N + 1) T − VNT 1 LSB VFST − VOT 1022 − 1 LSB [LSB] [V] [LSB] VOT : Voltage for transition from digital output 000H to 001H. VFST : Voltage for transition from digital output 3FEH to 3FFH. 7. Notes on Using A/D Converter Select the output impedance value for the external circuit of analog input according to the following conditions : External circuit output impedance values of about 5 kΩ or lower are recommended. If external capacitors are used, a capacitance of several thousand times the internal capacitor value is recommended in order to minimize the effect of voltage distribution between the external and internal capacitor. If the output impedance of the external circuit is too high, the sampling time for analog voltages may not be sufficient (sampling period = 2.00 µs @ machine clock of 16 MHz) . • Model Analog Input Circuit Comparator Analog input R C MB90F497G, MB90F498G, MB90V495G R 3.2 kΩ, C 30 pF MB90497G R 2.6 kΩ, C 28 pF Note : The figures given here are the suggested values. • About Error The smaller the absolute value of | AVR - AVSS |, the greater the relative error. 81 MB90495G Series 8. Flash Memory Program/Erase Characteristics Parameter Sector erase time Chip erare time Word (16-bit width) programming time Erase/Program cycle  TA = + 25 °C VCC = 5.0 V Condition Value Min    10,000 Typ 1 5 16  Max 15  3,600  Unit s s µs cycle Remarks Excludes 00H programming prior erasure Excludes 00H programming prior erasure Excludes system-level overhead 82 MB90495G Series s EXAMPLE CHARACTERISTICS • MB90F497G/F498G ICC − VCC TA = 25 °C, external clock operation f = internal operation frequency 45 40 35 30 ICC (mA) 25 20 15 10 5 0 3.0 4.0 5.0 VCC (V) f = 4 MHz f = 2 MHz f = 10 MHz f = 8 MHz f = 16 MHz 6.0 7.0 ICCS − VCC TA = 25 °C, external clock operation f = internal operation frequency 16 14 12 10 ICCS (mA) 8 6 4 2 0 3.0 f = 10 MHz f = 8 MHz f = 16 MHz f = 4 MHz f = 2 MHz 4.0 5.0 VCC (V) 6.0 7.0 (Continued) 83 MB90495G Series (Continued) ICCL − VCC TA = 25 °C, external clock operation f = internal operation frequency 180 160 140 120 ICCL (µA) 100 80 60 40 20 0 3.0 4.0 5.0 VCC (V) 6.0 7.0 f = 8 kHz ICCLS − VCC TA = 25 °C, external clock operation f = internal operation frequency 10 9 8 7 ICCLS (µA) 6 5 4 3 2 1 0 3.0 4.0 5.0 VCC (V) 6.0 7.0 f = 8 kHz (Continued) 84 MB90495G Series (Continued) ICCT − VCC TA = 25 °C, external clock operation f = internal operation frequency 7 6 5 ICCT (µA) 4 3 2 1 0 3.0 f = 8 kHz 4.0 5.0 VCC (V) 6.0 7.0 (VCC − VOH) − IOH TA = 25 °C, VCC = 4.5 V 1000 900 800 VCC - VOH (mV) 700 VOL (V) 600 500 400 300 200 100 0 0 1 2 3 4 567 IOH (mA) 8 9 10 11 12 1000 900 800 700 600 500 400 300 200 100 0 0 1 2 VOL − IOL TA = 25 °C, VCC = 4.5 V 3 4 567 IOL (mA) 8 9 10 11 12 85 MB90495G Series • MB90497G ICC − VCC TA = 25 °C, external clock operation f = internal operation frequency 45 40 35 30 ICC (mA) 25 20 15 10 5 0 3.0 4.0 5.0 VCC (V) f = 4 MHz f = 2 MHz 6.0 7.0 f = 10 MHz f = 8 MHz f = 16 MHz ICCS − VCC TA = 25 °C, external clock operation f = internal operation frequency 16 14 12 10 ICCS (mA) f = 10 MHz 8 f = 8 MHz 6 4 2 0 3.0 f = 4 MHz f = 2 MHz 4.0 5.0 VCC (V) 6.0 7.0 f = 16 MHz (Continued) 86 MB90495G Series (Continued) ICCL − VCC TA = 25 °C, external clock operation f = internal operation frequency 25 20 f = 8 kHz ICCL (µA) 15 10 5 0 3.0 4.0 5.0 VCC (V) 6.0 7.0 ICCLS − VCC TA = 25 °C, external clock operation f = internal operation frequency 10 9 8 7 ICCLS (µA) 6 5 4 3 2 1 0 3.0 4.0 5.0 VCC (V) 6.0 7.0 f = 8 kHz (Continued) 87 MB90495G Series (Continued) ICCT − VCC TA = 25 °C, external clock operation f = internal operation frequency 7 f = 8 kHz 6 5 ICCT (µA) 4 3 2 1 0 3.0 4.0 5.0 VCC (V) 6.0 7.0 (VCC − VOH) − IOH TA = 25 °C, VCC = 4.5 V 1000 900 800 VCC - VOH (mV) 700 VOL (V) 600 500 400 300 200 100 0 0 1 2 3 4 567 IOH (mA) 8 9 10 11 12 1000 900 800 700 600 500 400 300 200 100 0 0 1 2 VOL − IOL TA = 25 °C, VCC = 4.5 V 3 4 567 IOL (mA) 8 9 10 11 12 88 MB90495G Series s ORDERING INFORMATION Part Number MB90F497GPF MB90497GPF MB90F498GPF MB90F497GPFM MB90497GPFM MB90F498GPFM Package 64-pin plastic QFP (FPT-64P-M06) 64-pin plastic LQFP (FPT-64P-M09) Remarks 89 MB90495G Series s PACKAGE DIMENSIONS 64-pin plastic QFP (FPT-64P-M06) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 24.70±0.40(.972±.016) * 20.00±0.20(.787±.008) 51 33 0.17±0.06 (.007±.002) 52 32 18.70±0.40 (.736±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 3.00 –0.20 .118 –.008 +0.35 +.014 (Mounting height) 64 20 0~8˚ 1 19 1.00(.039) 0.42±0.08 (.017±.003) 0.20(.008) M 0.25 –0.20 1.20±0.20 (.047±.008) +0.15 +.006 .010 –.008 (Stand off) "A" 0.10(.004) C 2003 FUJITSU LIMITED F64013S-c-5-5 Dimensions in mm (inches) Note : The values in parentheses are reference values. (Continued) 90 MB90495G Series (Continued) 64-pin plastic LQFP (FPT-64P-M09) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 14.00±0.20(.551±.008)SQ * 12.00±0.10(.472±.004)SQ 48 33 0.145±0.055 (.0057±.0022) 49 32 0.10(.004) Details of "A" part 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) 0.25(.010) INDEX 0~8˚ 64 17 1 16 "A" 0.65(.026) 0.32±0.05 (.013±.002) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.10 (.004±.004) (Stand off) 0.13(.005) M C 2003 FUJITSU LIMITED F64018S-c-3-5 Dimensions in mm (inches) Note : The values in parentheses are reference values. 91 MB90495G Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0306 © FUJITSU LIMITED Printed in Japan