MB90884SPMC

FUJITSU SEMICONDUCTOR DATA SHEET DS07-13743-2E 16-Bit Proprietary Microcontroller CMOS F2MC-16LX MB90880 Series MB90F882(S)/F883(S)/F883A(S)/F884(S)/F884A(S) MB90882(S)/883(S)/884(S)/V880(A)-101/-102 ■ DESCRIPTION The MB90880 series is a general-purpose 16-bit microcontroller, designed by Fujitsu, for process control of devices such as consumer appliances, which require high-speed real-time processing capabilities. The instruction set of the F2MC-16LX CPU core retains the same AT architecture as the F2MC*1 family, with further refinements including high-level language instructions, an expanded addressing mode, enhanced multiplierdivider instructions and bit processing. In addition, a 32-bit accumulator is built in to enable long word processing. As its peripheral resources, the MB90880 series has a 16-bit PPG, multi-function serial interface (software switch over enabled for SIO, UART and I2C*2) , 10-bit A/D converter, 16-bit I/O timer, 8/16-bit up-down counter, base timer (software switch over enabled for 16-bit reload timer, PWC timer, PPG timer and PWM timer) , DTP / external interrupt and chip select pins. *1 : F2MC is the abbreviation of FUJITSU Flexible Microcontroller. *2 : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. Copyright©2006-2007 FUJITSU LIMITED All rights reserved MB90880 Series ■ FEATURES • Clock Minimum instruction execution time : 30.3 ns / 4.125 MHz source oscillation × eight times (in internal operation : 33 MHz/3.3 V ± 0.3 V) PLL clock multiplication system • Maximum memory space 16 Mbytes • Instruction set optimized for control applications Supported data types : bit, byte, word and long word Standard addressing modes : 23 types Enhanced high-precision calculation realized by 32-bit accumulator Signed multiplication/division instructions and extended RETI instruction functions • Instruction set supporting high-level language (C language) and multi-task operations Introduction of system stack pointer Symmetrical instruction set and barrel shift instructions • Improved execution speed 4-byte queue • Powerful interrupt functions Eight priority levels programmable; External interrupts : 24 • Data transfer functions (µDMAC) Up to 16 channels • Built-in ROM Flash ROM : 256, 384 and 512 Kbytes; MASK ROM : 256, 384 and 512 Kbytes • Built-in RAM Flash RAM : 16, 24 and 30 Kbytes; MASK RAM : 16, 24 and 30 Kbytes • General-purpose ports Dual clock product : up to 81 channels; Single clock product : up to 83 channels • A/D converter RC successive approximation conversion type : 20 channels (Resolution : 8 or 10 bits) • Multi-function serial interface 7 channels (software switchable between for SIO, UART and I2C) • 16-bit PPG 8 channels • 8/16-bit up-down counter/timer Event input pins : 6 8-bit up-down counters : 2 8-bit reload/compare registers : 2 • Base timer 4 channels (software switchable between 16-bit reload timer, PWC timer, PPG timer, and PWM timer) • 16-bit I/O timer Input capture × 2 channels, output compare × 6 channels, free run timer × 1 channel • Built-in dual clock generator • Low power consumption modes Stop mode, sleep mode, CPU intermittent operation mode, watch timer, time base timer mode • Package QFP-100/LQFP-100 • Process CMOS technology • Power supply voltage 3V : Single power supply operation 2 MB90880 Series ■ PRODUCT LINEUP Item Name Class ROM size RAM size MB90882 (S) MB90883 (S) MB90884 (S) MB90F882 (S) MASK ROM product 256 Kbytes 16 Kbytes 384 Kbytes 24 Kbytes 512 Kbytes 30 Kbytes 256 Kbytes 16 Kbytes MB90F883 (S) / MB90F884 (S) / MB90F883A (S) MB90F884A (S) Flash memory product 384 Kbytes 24 Kbytes 512 Kbytes 30 Kbytes CPU functions Number of instructions Instruction bit length Instruction length Data bit length Minimum execution time : 351 : 8 bits, 16 bits : 1 to 7 bytes : 1 bit, 8 bits, 16 bits : 30.3 ns (machine clock : 33 MHz) The maximum operating frequency of MB90F883(S) and MB90F884(S) is 25 MHz. Ports Multi-function serial interface 16-bit PPG timer 8/16-bit up-down counter/timer 16-bit free run timer 16-bit I/O timer General-purpose I/O ports : up to 81 for dual clock model, up to 83 for single clock model General-purpose I/O ports (CMOS output) 7 channels (software switchable between SIO, UART & I2C) 8 channels Event input pins : 6, 8-bit up-down counters : 2 8-bit reload/compare registers : 2 Number of channels : 1 Overflow interrupt Output Number of channels : 6 compare Pin input source : Match signal of compare register (OCU) Input capture (ICU) Number of channels : 2 Rewriting register by pin input (rising, falling or both edges) External interrupt pins : 24 channels (edge/level support) 4 channels (software switchable between 16-bit reload timer, PWC timer, PPG timer, and PWM timer) In MB90F883(S) and MB90F884(S), P24/TIO0, P25/TIO1, P26/TIO2, and P27/TIO3 cannot be used as input function. 18-bit counter Interrupt interval : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (source oscillation : 4 MHz) Conversion accuracy : 8 or 10 bits can be switched Single conversion mode (Selected channel converted only once) Scan conversion mode (Multiple successive channels converted) Successive conversion mode (Selected channel converted repeatedly) Stop conversion mode (Selected channel converted and stopped repeatedly) Reset generation interval : 3.58 ms, 14.33 ms, 57.23ms, 458.75 ms (source oscillation : 4 MHz, minimum value) (Continued) DTP/external interrupt circuit Base timer Time base timer A/D converter Watchdog timer 3 MB90880 Series (Continued) Item Name Low power consumption (standby) modes Flash memory Process MB90882 (S) MB90883 (S) MB90884 (S) MB90F882 (S) MB90F883 (S) / MB90F884 (S) / MB90F883A (S) MB90F884A (S) Sleep, stop, CPU intermittent operation, watch timer, time base timer ⎯ Flash security/ write-protect feature (not available in MB90F883(S), MB90F884(S), MB90F883A(S), and MB90F884A(S)) CMOS technology 4 MB90880 Series ■ PIN ASSIGNMENTS (TOP VIEW) P13/AD11/D11/OUT3 P15/AD13/D13/OUT5 P10/AD08/D08/OUT0 P14/AD12/D12/OUT4 P12/AD10/D10/OUT2 P11/AD09/D09/OUT1 P07/AD07/D07/IRQ7 P06/AD06/D06/IRQ6 P05/AD05/D05/IRQ5 82 P04/AD04/D04/IRQ4 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 P17/AD15/D15/IN1 100 P23/A19/PPG3 P16/AD14/D14/IN0 P22/A18/PPG2 P21/A17/PPG1 P20/A16/PPG0 99 98 97 96 95 94 93 92 91 90 VCC VSS X0 X1 89 88 87 86 85 84 P24/A20/TIO0 P25/A21/TIO1 P26/A22/TIO2 P27/A23/TIO3 P30/A00/ZIN0/UI1 P31/A01/AIN0/UO1 P32/A02/BIN0/UCK1 P33/A03/UI2 P34/A04/UO2 P35/A05/ZIN1/UCK2 P36/A06/AIN1/IRQ8 P37/A07/BIN1/IRQ9 P40/A08/X0A* P41/A09/X1A* VCC VSS C P42/A10/UI3 P43/A11/UO3 P44/A12/UCK3 P45/A13/UI4 P46/A14/UO4 P47/A15/UCK4 P90/CS0/AN8 P91/CS1/AN9 P92/CS2/AN10 P93/CS3/AN11 P94/AN12 P95/(UI3)/AN13 P96/(UO3)/AN14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 83 P03/AD03/D03/IRQ3 P02/AD02/D02/IRQ2 P01/AD01/D01/IRQ1 P00/AD00/D00/IRQ0 P57/CLK/PPG7 P56/RDY/PPG6 P55/HAK/PPG5 P54/HRQ/PPG4 P53/WRH/IRQ23 P52/WRL P51/RD P50/ALE PA3/(PPG7)/IRQ22 PA2/(PPG6)/IRQ21 DVSS DVCC PA1/(PPG5)/IRQ20 PA0/(PPG4)/IRQ19 P87/IRQ18/ADTG P86/UCK0 P85/UO0 P84/UI0 P83/IRQ17 P82/IRQ16/UCK6 P81/UO6 P80/IRQ15/UI6 RST MD0 MD1 MD2 QFP-100 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 P75/UO5 P97/(UCK3)/AN15 P72/(UO4)/IRQ11/AN18 P71/(UI4)/IRQ10/AN17 P73/(UCK4)/IRQ12/AN19 P70/AN16 AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 VSS P74/IRQ13/UI5 (FPT-100P-M06) * : dual clock product is sub clock oscillation pin. P76/IRQ14/UCK5 AVCC AVRH 50 5 MB90880 Series (TOP VIEW) P12/AD10/D10/OUT2 P14/AD12/D12/OUT4 P11/AD09/D09/OUT1 P15/AD13/D13/OUT5 P13/AD11/D11/OUT3 P10/AD08/D08/OUT0 P07/AD07/D07/IRQ7 P06/AD06/D06/IRQ6 P05/AD05/D05/IRQ5 P04/AD04/D04/IRQ4 P02/AD02/D02/IRQ2 77 P17/AD15/D15/IN1 P16/AD14/D14/IN0 P01/AD01/D01/IRQ1 76 P03/AD03/D03/IRQ3 78 P21/A17/PPG1 P20/A16/PPG0 P22/A18/PPG2 P23/A19/PPG3 P25/A21/TIO1 P24/A20/TIO0 99 97 96 95 94 92 91 90 88 VCC VSS X0 X1 83 100 79 98 93 89 87 86 85 84 82 81 80 P26/A22/TIO2 P27/A23/TIO3 P30/A00/ZIN0/UI1 P31/A01/AIN0/UO1 P32/A02/BIN0/UCK1 P33/A03/UI2 P34/A04/UO2 P35/A05/ZIN1/UCK2 P36/A06/AIN1/IRQ8 P37/A07/BIN1/IRQ9 P40/A08/X0A* P41/A09/X1A* VCC VSS C P42/A10/UI3 P43/A11/UO3 P44/A12/UCK3 P45/A13/UI4 P46/A14/UO4 P47/A15/UCK4 P90/CS0/AN8 P91/CS1/AN9 P92/CS2/AN10 P93/CS3/AN11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 P00/AD00/D00/IRQ0 P57/CLK/PPG7 P56/RDY/PPG6 P55/HAK/PPG5 P54/HRQ/PPG4 P53/WRH/IRQ23 P52/WRL P51/RD P50/ALE PA3/(PPG7)/IRQ22 PA2/(PPG6)/IRQ21 DVSS DVCC PA1/(PPG5)/IRQ20 PA0/(PPG4)/IRQ19 P87/IRQ18/ADTG P86/UCK0 P85/UO0 P84/UI0 P83/IRQ17 P82/IRQ16/UCK6 P81/UO6 P80/IRQ15/UI6 RST MD0 LQFP-100 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 MD2 P71/(UI4)/IRQ10/AN17 P75/UO5 P73/(UCK4)/IRQ12/AN19 P76/IRQ14/UCK5 AVCC AVRH AVSS P60/AN0 P61/AN1 P97/(UCK3)/AN15 P70/AN16 P62/AN2 P64/AN4 P65/AN5 P66/AN6 P67/AN7 P94/AN12 P63/AN3 P96/(UO3)/AN14 (FPT-100P-M20) * : dual clock product is sub clock oscillation pin. 6 P72/(UO4)/IRQ11/AN18 P95/(UI3)/AN13 P74/IRQ13/UI5 MD1 VSS 50 MB90880 Series ■ PIN DESCRIPTIONS Pin no. LQFP *1 QFP *2 Pin name P26 I/O circuit type*3 General-purpose I/O port In multiplex mode, it serves as higher address output pin (A22) when corresponding bit in external address output control register (HACR) is set to "0". In non-multiplex mode, it serves as higher address output pin (A22) when corresponding bit in external address output control register (HACR) is set to "0". Base timer I/O pin (ch.2) General-purpose I/O port In multiplex mode, it serves as higher address output pin (A23) when corresponding bit in external address output control register (HACR) is set to "0". In non-multiplex mode, it serves as higher address output pin (A23) when corresponding bit in external address output control register (HACR) is set to "0". Base timer I/O pin (ch.3) General-purpose I/O port E Serves as an external address pin in non-multiplex mode. 8/16-bit up-down counter/timer input pin (ch.0) Multi-function serial input pin General-purpose I/O port Serves as an external address pin in non-multiplex mode. E 8/16-bit up-down counter/timer input pin (ch.0) Multi-function serial output pin General-purpose I/O port Serves as an external address pin in non-multiplex mode. E 8/16-bit up-down counter/timer input pin (ch.0) Multi-function serial clock I/O pin General-purpose I/O port E Serves as an external address pin in non-multiplex mode. Multi-function serial input pin General-purpose I/O port E Serves as an external address pin in non-multiplex mode. Multi-function serial output pin (Continued) 7 Function 1 3 A22 D TIO2 P27 2 4 A23 D TIO3 P30 3 5 A00 ZIN0 UI1 P31 A01 4 6 AIN0 UO1/ (SDA1) P32 A02 5 7 BIN0 UCK1/ (SCL1) P33 6 8 A03 UI2 P34 7 9 A04 UO2/ (SDA2) MB90880 Series Pin no. LQFP *1 QFP *2 Pin name P35 A05 I/O circuit type*3 General-purpose I/O port Function Serves as an external address pin in non-multiplex mode. E 8/16-bit up-down counter/timer input pin (ch.1) Multi-function serial clock I/O pin General-purpose I/O port D Serves as an external address pin in non-multiplex mode. 8/16-bit up-down counter/timer input pin (ch.1) External interrupt input pin General-purpose I/O port D Serves as an external address pin in non-multiplex mode. 8/16-bit up-down counter/timer input pin (ch.1) External interrupt input pin General-purpose I/O port A/D Serves as an external address pin in non-multiplex mode. 32 kHz oscillator connecting pin General-purpose I/O port A/D E Serves as an external address pin in non-multiplex mode. 32 kHz oscillator connecting pin Power supply pin Power supply pin (GND) Regulator stabilization capacity connecting pin General-purpose I/O port Serves as an external address pin in non-multiplex mode. Multi-function serial input pin General-purpose I/O port E Serves as an external address pin in non-multiplex mode. Multi-function serial output pin General-purpose I/O port E Serves as an external address pin in non-multiplex mode. Multi-function serial clock I/O pin General-purpose I/O port E Serves as an external address pin in non-multiplex mode. Multi-function serial input pin (Continued) 8 10 ZIN1 UCK2/ (SCL2) P36 A06 AIN1 IRQ8 P37 A07 BIN1 IRQ9 P40 9 11 10 12 11 13 A08 X0A P41 12 13 14 15 16 14 15 16 17 18 A09 X1A VCC VSS C P42 A10 UI3 P43 A11 UO3/ (SDA3) P44 A12 UCK3/ (SCL3) P45 17 19 18 20 19 21 A13 UI4 8 MB90880 Series Pin no. LQFP *1 QFP *2 Pin name P46 I/O circuit type*3 General-purpose I/O port E Function 20 22 A14 UO4/ (SDA4) P47 A15 UCK4/ (SCL4) P90 Serves as an external address pin in non-multiplex mode. Multi-function serial output pin General-purpose I/O port 21 23 E Serves as an external address pin in non-multiplex mode. Multi-function serial clock I/O pin General-purpose I/O port 22 24 CS0 AN8 P91 H Chip select 0 Analog input pin General-purpose I/O port 23 25 CS1 AN9 P92 H Chip select 1 Analog input pin General-purpose I/O port 24 26 CS2 AN10 P93 H Chip select 2 Analog input pin General-purpose I/O port 25 27 CS3 AN11 P94 AN12 P95 AN13 (UI3) P96 AN14 (UO3)/ (SDA3) P97 AN15 (UCK3)/ (SCL3) H Chip select 3 Analog input pin General-purpose I/O port Analog input pin General-purpose I/O port Analog input pin Multi-function serial input pin (when set by P9FSR register) General-purpose I/O port Analog input pin Multi-function serial output pin (when set by P9FSR register) General-purpose I/O port 26 28 H 27 29 K 28 30 K 29 31 K Analog input pin Multi-function serial clock I/O pin (when set by P9FSR register) 30 31 32 32 33 34 AVCC AVRH P70 AN16 H A/D converter power supply pin A/D converter external reference power supply pin General-purpose I/O port Analog input pin (Continued) 9 MB90880 Series Pin no. LQFP *1 33 34 35 36 37 38 39 40 41 42 QFP *2 35 36 37 38 39 40 41 42 43 44 Pin name AVSS P60 AN0 P61 AN1 P62 AN2 P63 AN3 P64 AN4 P65 AN5 P66 AN6 P67 AN7 VSS P71 IRQ10 AN17 (UI4) P72 IRQ11 I/O circuit type*3 H H H H H H H H General-purpose I/O port Analog input pin General-purpose I/O port Analog input pin General-purpose I/O port Analog input pin General-purpose I/O port Analog input pin General-purpose I/O port Analog input pin General-purpose I/O port Analog input pin General-purpose I/O port Analog input pin General-purpose I/O port Analog input pin Power supply pin (GND) General-purpose I/O port K External interrupt input pin Analog input pin Function A/D converter power supply pin 43 45 Multi-function serial input pin (when set by P7FSR register) General-purpose I/O port External interrupt input pin K Analog input pin Multi-function serial output pin (when set by P7FSR register) General-purpose I/O port External interrupt input pin K Analog input pin Multi-function serial clock I/O pin (when set by F7FSR register) General-purpose I/O port G External interrupt input pin Multi-function serial input pin (Continued) 44 46 AN18 (UO4)/ (SDA4) P73 IRQ12 45 47 AN19 (UCK4)/ (SCL4) P74 46 48 IRQ13 UI5 10 MB90880 Series Pin no. LQFP *1 47 QFP *2 49 Pin name P75 UO5/ (SDA5) P76 IRQ14 UCK5/ (SCL5) I/O circuit type*3 General-purpose I/O port G Function Multi-function serial output pin General-purpose I/O port 48 50 G External interrupt input pin Multi-function serial clock I/O pin 49 50 51 52 53 51 52 53 54 55 MD2 MD1 MD0 RST P80 IRQ15 UI6 P81 L L L B G Operation mode specification input pin Operation mode specification input pin Operation mode specification input pin Reset input pin General-purpose I/O port External interrupt input pin Multi-function serial input pin General-purpose I/O port 54 56 UO6/ (SDA6) P82 IRQ16 UCK6/ (SCL6) G Multi-function serial output pin General-purpose I/O port 55 57 G External interrupt input pin Multi-function serial clock I/O pin 56 57 58 59 P83 IRQ17 P84 UI0 P85 UO0/ (SDA0) P86 UCK0/ (SCL0) P87 IRQ18 ADTG PA0 I G General-purpose I/O port External interrupt input pin General-purpose I/O port Multi-function serial input pin General-purpose I/O port 58 60 G Multi-function serial output pin General-purpose I/O port 59 61 G Multi-function serial clock I/O pin General-purpose I/O port 60 62 I External interrupt input pin External trigger input pin, when A/D converter is used. General-purpose I/O port 61 63 IRQ19 (PPG4) J External interrupt input pin PPG timer output pin (when set by PAFSR register) (Continued) 11 MB90880 Series Pin no. LQFP *1 QFP *2 Pin name PA1 I/O circuit type*3 General-purpose I/O port J J External interrupt input pin Function 62 63 64 65 64 65 66 67 IRQ20 (PPG5) DVCC DVSS PA2 IRQ21 (PPG6) PA3 PPG timer output pin (when set by PAFSR register) PA port power supply pin PA port power supply pin (GND) General-purpose I/O port External interrupt input pin PPG timer output pin (when set by PAFSR register) General-purpose I/O port J External interrupt input pin PPG timer output pin (when set by PAFSR register) General-purpose I/O port F Serves as address latch enable signal (ALE) pin in external bus mode. General-purpose I/O port Serves as read strobe output (RD) pin in external bus mode. General-purpose I/O port F Serves as lower data write strobe output (WRL) pin in external bus mode, and serves as a general-purpose I/O port when WRE bit in EPCR register is "0". General-purpose I/O port F Serves as higher data write strobe output (WRH) pin in external bus mode with 16-bit bus width, and serves as a general-purpose I/O port when WRE bit in EPCR register is "0". External interrupt input pin General-purpose I/O port F Serves as hold request input (HRQ) pin in external bus mode, and serves as a general-purpose I/O port when HDE bit in EPCR register is "0". PPG timer output pin General-purpose I/O port F Serves as hold acknowledge output (HAK) pin in external bus mode, and serves as a general-purpose I/O port when HDE bit in EPCR register is "0". PPG timer output pin (Continued) 66 68 IRQ22 (PPG7) P50 67 69 ALE P51 RD P52 68 70 F 69 71 WRL P53 70 72 WRH IRQ23 P54 71 73 HRQ PPG4 P55 72 74 HAK PPG5 12 MB90880 Series Pin no. LQFP *1 QFP *2 Pin name P56 I/O circuit type*3 General-purpose I/O port F Function 73 75 RDY PPG6 P57 Serves as external ready input (RDY) pin in external bus mode, and serves as a general-purpose I/O port when RYE bit in EPCR register is "0". PPG timer output pin General-purpose I/O port Serves as machine cycle clock output (CLK) pin in external bus mode, and serves as a general-purpose I/O port when CKE bit in EPCR register is "0". PPG timer output pin General-purpose I/O port In multiplex mode, it serves as lower external address/data bus I/O pin. Serves as lower external data bus output pin in non-multiplex mode. External interrupt input pin General-purpose I/O port Serves as an external address/lower data bus I/O pin in multiplex mode. Serves as a lower external data bus output pin in non-multiplex mode. External interrupt input pin General-purpose I/O port Serves as an external address/lower data bus I/O pin in multiplex mode. Serves as a lower external data bus output pin in non-multiplex mode. External interrupt input pin General-purpose I/O port Serves as an external address/lower data bus I/O pin in multiplex mode. Serves as a lower external data bus output pin in non-multiplex mode. External interrupt input pin General-purpose I/O port In multiplex mode, it serves as lower external address/data bus I/O pin. Serves as a lower external data bus output pin in non-multiplex mode. External interrupt input pin (Continued) 13 74 76 CLK PPG7 P00 F 75 77 AD00/ D00 IRQ0 P01 AD01/ D01 IRQ1 P02 AD02/ D02 IRQ2 P03 AD03/ D03 IRQ3 P04 AD04/ D04 IRQ4 C 76 78 C 77 79 C 78 80 C 79 81 C MB90880 Series Pin no. LQFP *1 QFP *2 Pin name P05 AD05/ D05 IRQ5 P06 AD06/ D06 IRQ6 P07 AD07/ D07 IRQ7 P10 I/O circuit type*3 General-purpose I/O port Function 80 82 C In multiplex mode, it serves as lower external address/data bus I/O pin. Serves as a lower external data bus output pin in non-multiplex mode. External interrupt input pin General-purpose I/O port In multiplex mode, it serves as lower external address/data bus I/O pin. Serves as a lower external data bus output pin in non-multiplex mode. External interrupt input pin General-purpose I/O port In multiplex mode, it serves as lower external address/data bus I/O pin. Serves as a lower external data bus output pin in non-multiplex mode. External interrupt input pin General-purpose I/O port In multiplex mode, it serves as higher external address/data bus I/O pin. In non-multiplex mode, it serves as higher external data output pin. Output compare event output pin General-purpose I/O port In multiplex mode, it serves as higher external address/data bus I/O pin. In non-multiplex mode, it serves as higher external data output pin. Output compare event output pin General-purpose I/O port In multiplex mode, it serves as higher external address/data bus I/O pin. In non-multiplex mode, it serves as higher external data output pin. Output compare event output pin General-purpose I/O port In multiplex mode, it serves as higher external address/data bus I/O pin. In non-multiplex mode, it serves as higher external data output pin. Output compare event output pin (Continued) 81 83 C 82 84 C 83 85 AD08/ D08 OUT0 P11 C 84 86 AD09/ D09 OUT1 P12 C 85 87 AD10/ D10 OUT2 P13 C 86 88 AD11/ D11 OUT3 C 14 MB90880 Series Pin no. LQFP *1 QFP *2 Pin name P14 I/O circuit type*3 General-purpose I/O port C Function 87 89 AD12/ D12 OUT4 VCC VSS X1 X0 P15 In non-multiplex mode, it serves as higher external data output pin. Output compare event output pin 88 89 90 91 90 91 92 93 A A Power supply pin Power supply pin (GND) Main oscillator connecting pin Main oscillator connecting pin General-purpose I/O port In multiplex mode, it serves as higher external address/data bus I/O pin. In non-multiplex mode, it serves as higher external data output pin. Output compare event output pin General-purpose I/O port In multiplex mode, it serves as higher external address/data bus I/O pin. In non-multiplex mode, it serves as higher external data output pin. Trigger input pin for input capture ch.0 General-purpose I/O port In multiplex mode, it serves as higher external address/data bus I/O pin. In non-multiplex mode, it serves as higher external data output pin. Trigger input pin for input capture ch.1 General-purpose I/O port In multiplex mode, it serves as higher address output pin (A16) when corresponding bit in external address output control register (HACR) is set to "0". In non-multiplex mode, it serves as higher address output pin (A16) when corresponding bit in external address output control register (HACR) is set to "0". PPG timer output pin General-purpose I/O port In multiplex mode, it serves as higher address output pin (A17) when corresponding bit in external address output control register (HACR) is set to "0". In non-multiplex mode, it serves as higher address output pin (A17) when corresponding bit in external address output control register (HACR) is set to "0". PPG timer output pin (Continued) 15 92 94 AD13/ D13 OUT5 P16 C 93 95 AD14/ D14 IN0 P17 C 94 96 AD15/ D15 IN1 P20 C 95 97 A16 D PPG0 P21 96 98 A17 D PPG1 MB90880 Series (Continued) Pin no. LQFP *1 QFP *2 Pin name P22 I/O circuit type*3 General-purpose I/O port Function 97 99 A18 D In multiplex mode, it serves as higher address output pin (A18) when corresponding bit in external address output control register (HACR) is set to "0". In non-multiplex mode, it serves as higher address output pin (A18) when corresponding bit in external address output control register (HACR) is set to "0". PPG timer output pin General-purpose I/O port In multiplex mode, it serves as higher address output pin (A19) when corresponding bit in external address output control register (HACR) is set to "0". In non-multiplex mode, it serves as higher address output pin (A19) when corresponding bit in external address output control register (HACR) is set to "0". PPG timer output pin General-purpose I/O port In multiplex mode, it serves as higher address output pin (A20) when corresponding bit in external address output control register (HACR) is set to "0". In non-multiplex mode, it serves as higher address output pin (A20) when corresponding bit in external address output control register (HACR) is set to "0". Base timer I/O pin (ch.0) General-purpose I/O port In multiplex mode, it serves as higher address output pin (A21) when corresponding bit in external address output control register (HACR) is set to "0". In non-multiplex mode, it serves as higher address output pin (A21) when corresponding bit in external address output control register (HACR) is set to "0". Base timer I/O pin (ch.1) PPG2 P23 98 100 A19 D PPG3 P24 99 1 A20 D TIO0 P25 100 2 A21 D TIO1 *1 : LQFP : FPT-100P-M20 *2 : QFP : FPT-100P-M06 *3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”. 16 MB90880 Series ■ I/O CIRCUIT TYPE Type X1, X1A Circuit Remarks • Oscillation feedback resistance X1, X0 : approx. 1 MΩ X1A, X0A : approx. 10 MΩ • Standby control provided Standby control signal Hysteresis input with pull-up resistor P-ch N-ch Xout A X0, X0A B R R Hysteresis input Pull-up control signal P-ch P-ch N-ch • • • • Input pull-up resistor control provided CMOS level output Hysteresis input CMOS input (in external bus mode) C R CMOS input Hysteresis input Standby control for input shutdown P-ch • CMOS level output • Hysteresis input N-ch D R Hysteresis input Standby control for input shutdown P-ch • CMOS level output • Hysteresis input • I2C level hysteresis input N-ch E R Hysteresis input I2C level hysteresis input Standby control for input shutdown (Continued) 17 MB90880 Series Type P-ch Circuit Remarks • CMOS level output • Hysteresis input • CMOS input (in external bus mode) N-ch F R CMOS input Hysteresis input Standby control for input shutdown P-ch Open-drain control signal N-ch • CMOS level output (Open-drain control provided) • 5V tolerant • Hysteresis input • I2C level hysteresis input G R Hysteresis input I2C level hysteresis input Standby control for input shutdown P-ch • CMOS level output • Hysteresis input • Analog input N-ch H R Hysteresis input Standby control for input shutdown Analog input • CMOS level output (Open-drain control provided) • 5V tolerant • Hysteresis input P-ch Open-drain control signal N-ch I R Hysteresis input Standby control for input shutdown (Continued) 18 MB90880 Series (Continued) Type P-ch Circuit Remarks • CMOS/level output (high-current type) • Hysteresis input N-ch J R Hysteresis input Standby control for input shutdown • • • • CMOS level output Hysteresis input Analog input I2C level hysteresis input P-ch N-ch K R Hysteresis input I2C level Hysteresis input Standby control for input shutdown Analog input Flash memory product N-ch N-ch Flash memory product • CMOS level input • High-voltage control for flash test provided Control signal L N-ch N-ch R Mode input MASK ROM product Hysteresis input Hysteresis input Diffused resistor MASK ROM product R 19 MB90880 Series ■ HANDLING DEVICES 1. Maximum rated voltages for the prevention of latch-up Be cautious not to exceed the absolute maximum rating. CMOS ICs may cause latch-up, when a voltage higher than VCC or lower than VSS is applied to input or output pins other than medium-to-high resistant pins, or when a voltage exceeding the rating is applied between VCC and VSS pins. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Take the utmost care not to let it occur. Likewise, care must be taken not to allow the analog power supply (AVCC, AVRH) and analog input to exceed the digital power supply (VCC) when turning on or off any analog system. 2. Handling unused pins Leaving unused input pins open may cause a malfunction or latch-up which leads to fatal damage to the device. Therefore, they must be pulled up or down through at least 2 kΩ resistance. Also, any unused I/O pin should be left open in the output state, or set to the input state and handled in the same way as an unused input pin. 3. Notes on using external clock Even when an external clock is being used, oscillation stabilization wait time is required for a power-on reset or release from sub clock mode or stop mode. Note that 25 MHz is the upper limit on the external clock that can be used. The following diagram shows an example of using an external clock. X0 Open X1 4. Handling power supply pins (VCC/VSS) When multiple VCC and VSS pins supply pins are used, all the power supply pins must be connected to external power and ground lines due to the device design, to reduce latch-up and unwanted radiation, prevent abnormal operation of strobe signals caused by the rise in the ground level and to conform to the total output current rating. Make sure to connect the VCC and VSS pins of this device via lowest impedance to power lines. It is recommended that a bypass capacitor of around 0.1 µF be placed between the VCC and VSS pins near the device. 5. Crystal oscillator circuit Noises around X0/X1 or X0A/X1A pins may cause abnormal operations. It is strongly recommended to provide bypass capacitors via shortest distance from X0/X1, X0A/X1A pins, crystal oscillator (or ceramic oscillator) and ground lines and also not to allow the lines of the oscillation circuit to cross the lines of other circuits. This will ensure stable operations of the printed circuit boards. Please ask each crystal maker to evaluate the oscillational characteristics of the crystal and this device. 6. Notes on PLL clock mode operation If an oscillator comes off or clock input stops during PLL clock mode operation, this microcontroller may continue its operation using a free-running frequency from a self-excited oscillation circuit within PLL. This is not a guaranteed operation. 20 MB90880 Series 7. Power-on and power-off sequence of A/D converter and analog input Turn on the A/D converters (AVCC, AVRH) and analog inputs (AN0 to AN19) after turning on the digital power supply (VCC) . During power-off, turn off the digital power supply (VCC) after turning off the A/D converters and analog inputs (AN0 to AN19) . In this case, make sure that AVRH does not exceed AVCC during the power-on/power-off procedure. Also make sure that the input voltage does not exceed AVCC when a pin which is also used as an analog input is used as an input port. 8. Handling power supply pins on A/D converter-mounted models Make sure to achieve "AVCC = AVRH = VCC" and "AVSS = VSS" in connecting the circuits, even when not using the A/D converter function. 9. Note on power-up To prevent the internal regulator from malfunctioning, maintain the voltage rise time at 50 µs (between 0.2V and 2.7V) or more during power-up. 10. Stabilization of power supply Even when the VCC power supply voltage is within the specified operating range, it may still cause the device to malfunction, if the power supply changes rapidly. For stabilization reference, it is recommended to control the supply voltage so that VCC ripple variations (P-P values) at commercial frequencies (50/60 Hz) fall below 10% of the standard VCC supply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching. 11. Writing to Flash memory For serial writing to Flash memory, always make sure that the operating voltage VCC is between 3.13V and 3.6V. For normal writing to Flash memory, always make sure that the operating voltage VCC is between 3.0V and 3.6V. 12. P90/CS0 pins P90/CS0 pins output “L” during writing Flash serial. Do not input from external. 13. Note of MB90F883 (S) , MB90F884 (S) • Maximum operating frequency is 25 MHz. • The base timer cannot use P24/TIO0, P25/TIO1, P26/TIO2, and P27/TIO3 as input function. • MB90F883(S) and MB90F884(S) do not contain the flash security feature and write-protect feature. 21 MB90880 Series ■ BLOCK DIAGRAM X0, X1, RST X0A, X1A MD0 to MD2 Clock control circuit RAM CPU F2MC-16LX series core Interrupt controller ROM µDMAC 16-bit PPG PPG0 to PPG7 SIO/UART/I2C mode switching enabled F2MC-16LX bus UI0 to UI6 UO0 to UO6 UCK0 to UCK6 Multifunction serial 8/16-bit up-down counter/timer AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 I/O timer AVCC AVRH AVSS ADTG AN0 to AN19 16-bit input capture × 2 channels IN0, IN1 OUT0 to OUT5 10-bit A/D converter 16-bit output compare × 6 channels 16-bit free-run timer 24 IRQ0 to IRQ23 External interrupt 16-bit base timer Reload timer/PWM/PWC mode switching enabled TIO0 to TIO3 I/O port 8 P00 to P07 8 P10 to P17 8 P20 to P27 8 P30 to P37 8 P40 to P47 8 P50 to P57 8 P60 to P67 7 P70 to P76 8 P80 to P87 8 P90 to P97 4 PA0 to PA3 Note : The I/O ports shown in the diagram above are shared by other built-in function blocks. They cannot be used as I/O ports when used as pins for a built-in module. 22 MB90880 Series ■ MEMORY MAP Single chip mode FFFFFFH Internal ROM external bus External ROM external bus ROM area Address #1 ROM area 010000H ROM area Address #2 007900H ROM area Image of FF bank Image of FF bank Peripheral area Peripheral area Peripheral area Address #3 RAM 000100H 0000F0H 000000H Register RAM Register RAM Register Peripheral area : Internal Peripheral area : External Peripheral area : Access prohibited Parts No. MB90882 (S) MB90F882 (S) MB90883 (S) MB90F883 (S) / MB90F883A (S) MB90884 (S) MB90F884 (S) / MB90F884A (S) MB90V880 (S) Address #1 FC0000H FC0000H FA0000H FA0000H F80000H F80000H (F80000H) Address #2 Address #3 004100H 004100H 006100H 008000H, fixed 006100H 007900H 007900H 007900H Note : The image of the ROM data in the FF band appears at the top of the 00 bank in order to enable efficient use of the C compiler small memory model. The lower 16-bit address for the FF bank will be assigned to the same address, so that tables in ROM can be referenced without declaring a "far" indication with the pointer. For example, when accessing the address 00C000H, the actual access is to address FFC000H in ROM. Here the FF bank ROM area exceeds 32 Kbytes, it is not possible to see the entire area in the 00 bank image. Therefore, the ROM data in FF8000H to FFFFFFH can be seen in the 00 bank image, while the data in FF0000H to FF7FFFH can only be seen in the FF bank. 23 MB90880 Series ■ F2MC-16L CPU PROGRAMMING MODEL • Dedicated register AH AL USP SSP PS PC DPR PCB DTB USB SSB ADB 8 bits 16 bits 32 bits Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register • General-purpose register MSB 000180H + RP × 10H RW0 RL0 RW1 RW2 RL1 RW3 R1 R3 R5 R7 R0 R2 R4 R6 RW4 RL2 RW5 RW6 RL3 RW7 16 bits LSB • Processor status bit 15 PS ILM bit 13 bit 12 RP bit 8 bit 7 CCR bit 0 24 MB90880 Series ■ I/O MAP Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH 00000CH 00000DH 00000EH 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H 00001AH 00001BH 00001CH 00001DH 00001EH 00001FH DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA ADER0 ADER1 ADER2 RDR0 RDR1 Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register Analog input enable register 0 Analog input enable register 1 Analog input enable register 2 Port 0 input resistance register Port 1 input resistance register Register abbreviation PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA UDER ILSR0 ILSR1 ILSR2 Register name Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Up-down timer input enable register Serial input level selection register 0 Serial input level selection register 1 Serial input level selection register 2 Disabled R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 6, A/D Port 9, A/D Port 7, A/D Port 0 (pull-up resistance control) Port 1 (pull-up resistance control) 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B -0000000B 00000000B 00000000B ----0000B 11111111B 11111111B ----1111B 00000000B 00000000B (Continued) 25 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Multi-function serial control Resource Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Up-down timer input control Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XX000000B 00000000B 00000000B ---00000B MB90880 Series Address 000020H Register abbreviation SMR0 Register name Serial bus mode register ch.0 SCR0/IBCR0 serial bus control register/I2C bus control register ch.0 Extended communication control register/I2C bus status register ch.0 Serial status register ch.0 Transmission/reception data register 0 ch.0 Transmission/reception data register 1 ch.0 Baud rate generator register 0 ch.0 Baud rate generator register 1 ch.0 7-bit slave address register ch.0 7-bit slave address mask register ch.0 Serial bus mode register ch.1 Serial bus control register / I2C bus control register ch.1 Extended communication control register / I2C bus status register ch.1 Serial status register ch.1 Transmission/reception data register 0 ch.1 Transmission/reception data register 1 ch.1 Baud rate generator register 0 ch.1 Baud rate generator register 1 ch.1 7-bit slave address register ch.1 7-bit slave address mask register ch.1 Lower A/D control status register Higher A/D control status register Lower A/D data register Higher A/D data register Lower A/D conversion channel setting register Higher A/D conversion channel setting register Reserved R/W R/W R/W R/W R/W R,W R,W R/W R/W R/W R/W R/W R/W R/W R/W R,W R,W R/W R/W R/W R/W R/W R/W R R R/W R/W Resource Initial value $$$$$$$$B $$$$$$$$B $$$$$$$$B $$$$$$$$B 000021H SCR0/IBCR0 000022H 000023H 000024H 000025H 000026H 000027H 000028H 000029H 00002AH ESCR0/ IBSR0 SSR0 RDR00/ TDR00 RDR10/ TDR10 BGR00 BGR10 ISBA0 ISMK0 SMR1 Multi-function serial ch.0 $$$$$$$$B $$$$$$$$B $$$$$$$$B $$$$$$$$B 00000000B 01111111B $$$$$$$$B $$$$$$$$B $$$$$$$$B $$$$$$$$B 00002BH SCR1/IBCR1 00002CH 00002DH 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH ESCR1/ IBSR1 SSR1 RDR01/ TDR01 RDR11/ TDR11 BGR01 BGR11 ISBA1 ISMK1 ADCSL ADCSH ADCRL ADCRH ADSRL ADSRH Multi-function serial ch.1 $$$$$$$$B $$$$$$$$B $$$$$$$$B $$$$$$$$B 00000000B 01111111B 00011110B 00000000B XXXXXXXXB 111111XXB 00000000B 00000000B A/D Converter (Continued) 26 MB90880 Series Address 00003BH 00003CH 00003DH 00003EH Register abbreviation PACSR1 OLSR0 OLSR1 SMR2 Register name Address detection control status register 1 Output level selection register 0 Output level selection register 1 Serial bus mode register ch.2 Serial bus control register / I C bus control register ch.2 Extended communication control register / I2C bus status register ch.2 Serial status register ch.2 Transmission/reception data register 0 ch.2 Transmission/reception data register 1 ch.2 Baud rate generator register 0 ch.2 Baud rate generator register 1 ch.2 7-bit slave address register ch.2 7-bit slave address mask register ch.2 Serial bus mode register ch.3 Serial bus control register / I2C bus control register ch.3 Extended communication control register / I2C bus status register ch.3 Serial status register ch.3 Transmission/reception data register 0 ch.3 Transmission/reception data register 1 ch.3 Baud rate generator register 0 ch.3 Baud rate generator register 1 ch.3 7-bit slave address register ch.3 7-bit slave address mask register ch.3 Serial bus mode register ch.4 Serial bus control register / I C bus control register ch.4 2 2 R/W R/W R/W R/W R/W R/W R/W R/W R,W R,W R/W R/W R/W R/W R/W R/W R/W R/W R,W R,W R/W R/W R/W R/W R/W R/W Resource Address match detection function Port 7 (N-ch open-drain control) Port 8 (N-ch open-drain control) Initial value 00000000B -000----B 00000000B $$$$$$$$B $$$$$$$$B $$$$$$$$B $$$$$$$$B 00003FH SCR2/IBCR2 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H 000048H ESCR2/ IBSR2 SSR2 RDR02/ TDR02 RDR12/ TDR12 BGR02 BGR12 ISBA2 ISMK2 SMR3 Multi-function serial ch.2 $$$$$$$$B $$$$$$$$B $$$$$$$$B $$$$$$$$B 00000000B 01111111B $$$$$$$$B $$$$$$$$B $$$$$$$$B $$$$$$$$B 000049H SCR3/IBCR3 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H ESCR3/ IBSR3 SSR3 RDR03/ TDR03 RDR13/ TDR13 BGR03 BGR13 ISBA3 ISMK3 SMR4 Multi-function serial ch.3 $$$$$$$$B $$$$$$$$B $$$$$$$$B $$$$$$$$B 00000000B 01111111B $$$$$$$$B 000053H SCR4/IBCR4 Multi-function serial ch.4 $$$$$$$$B (Continued) 27 MB90880 Series Address 000054H 000055H 000056H 000057H 000058H 000059H 00005AH 00005BH 00005CH Register abbreviation ESCR4/ IBSR4 SSR4 RDR04/ TDR04 RDR14/ TDR14 BGR04 BGR14 ISBA4 ISMK4 SMR5 Register name Extended communication control register / I2C bus status register ch.4 Serial status register ch.4 Transmission/reception data register 0 ch.4 Transmission/reception data register 1 ch.4 Baud rate generator register 0 ch.4 Baud rate generator register 1 ch.4 7-bit slave address register ch.4 7-bit slave address mask register ch.4 Serial bus mode register ch.5 Serial bus control register / I C bus control register ch.5 Extended communication control register / I2C bus status register ch.5 Serial status register ch.5 Transmission/reception data register 0 ch.5 Transmission/reception data register 1 ch.5 Baud rate generator register 0 ch.5 Baud rate generator register 1 ch.5 7-bit slave address register ch.5 7-bit slave address mask register ch.5 Lower output compare register (ch.0) Higher output compare register (ch.0) Lower output compare register (ch.1) Higher output compare register (ch.1) Lower output compare register (ch.2) Higher output compare register (ch.2) Lower output compare register (ch.3) Higher output compare register (ch.3) Reserved ROM mirror function selection register 2 R/W R/W R/W R,W R,W R/W R/W R/W R/W R/W R/W R/W R/W R,W R,W R/W R/W R/W R/W R/W R/W R/W R/W Resource Initial value $$$$$$$$B $$$$$$$$B $$$$$$$$B Multi-function serial ch.4 $$$$$$$$B $$$$$$$$B $$$$$$$$B 00000000B 01111111B $$$$$$$$B $$$$$$$$B $$$$$$$$B $$$$$$$$B 00005DH SCR5/IBCR5 00005EH 00005FH 000060H 000061H 000062H 000063H 000064H 000065H 000066H 000067H 000068H 000069H 00006AH 00006BH 00006CH 00006DH 00006EH 00006FH ROMM ESCR5/ IBSR5 SSR5 RDR05/ TDR05 RDR15/ TDR15 BGR05 BGR15 ISBA5 ISMK5 OCCP0 OCCP1 OCCP2 OCCP3 Multi-function serial ch.5 $$$$$$$$B $$$$$$$$B $$$$$$$$B $$$$$$$$B 00000000B 01111111B 00000000B 00000000B 00000000B 16-bit I/O timer output compare (ch.0 to ch.5) 00000000B 00000000B 00000000B 00000000B 00000000B R/W ROM mirror function -------1B (Continued) 28 MB90880 Series Address 000070H 000071H 000072H 000073H 000074H Register abbreviation OCCP4 OCCP5 Register name Lower output compare register (ch.4) Higher output compare register (ch.4) Lower output compare register (ch.5) Higher output compare register (ch.5) Lower output compare control register (ch.0, ch.1) Higher output compare control register (ch.0, ch.1) Lower output compare control register (ch.2, ch.3) Higher output compare control register (ch.2, ch.3) Lower output compare control register (ch.4, ch.5) Higher output compare control register (ch.4, ch.5) Lower input capture data register (ch.0) Higher input capture data register (ch.0) Lower input capture data register (ch.1) Higher input capture data register (ch.1) Input capture control status register Input capture edge register Lower timer counter data register Higher timer counter data register Timer control status register Timer control status register Lower compare clear register Higher compare clear register Reserved R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R R/W R/W R/W R/W R/W Resource Initial value 00000000B 00000000B 00000000B 00000000B 0000--00B OCS01 000075H 000076H OCS23 000077H 000078H OCS45 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH 000080H 000081H 000082H 000083H 000084H 000085H 000086H to 00009AH 00009BH 00009CH 00009DH DCSR DSRL DSRH IPCP1 ICS01 ICE01 TCDT TCDT TCCS TCCS CPCLR IPCP0 16-bit I/O timer output compare (ch.0 to ch.5) ---00000B 0000--00B ---00000B 0000--00B ---00000B XXXXXXXXB XXXXXXXXB 6-bit I/O timer input capture (ch.0, ch.1) XXXXXXXXB XXXXXXXXB 00000000B ------XXB 00000000B 00000000B 00000000B XX-00000B XXXXXXXXB XXXXXXXXB 16-bit I/O timer free-run timer DMAC descriptor channel specification register DMAC lower status register DMAC higher status register R/W R/W R/W DMAC DMAC DMAC 00000000B 00000000B 00000000B (Continued) 29 MB90880 Series Address 00009EH 00009FH 0000A0H 0000A1H 0000A2H, 0000A3H 0000A4H 0000A5H 0000A6H 0000A7H 0000A8H 0000A9H 0000AAH 0000ABH 0000ACH 0000ADH 0000AEH 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH Register abbreviation PACSR0 DIRR LPMCR CKSCR Register name Address detection control status register 0 Delayed interrupt source generation/ release register Low power consumption mode control register Clock selection register Reserved R/W R/W R/W W, R/W R, R/W Resource Address match detection function Delayed interrupt generation module Low power consumption Initial value 00000000B -------0B 00011000B 11111100B DSSR ARSR HACR EPCR WDTC TBTC WTC DERL DERH FMCS ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 DMAC stop status register Auto ready function selection register External address output control register Bus control signal selection register Watchdog timer control register Time base timer control register Watch timer control register Reserved DMAC lower enable register DMAC higher enable register Flash memory control status register Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Prohibited R/W W W W R, W W, R/W R, R/W R/W R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W W, R/W DMAC External pin Watchdog timer Time base timer Watch timer 00000000B 0011--00B ********B 1000*10-B XXXXX111B 1XX00100B 10001000B 00000000B 00000000B 000X0000B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B (Continued) DMAC Flash memory I/F Interrupt control 30 MB90880 Series Address 0000BEH 0000BFH 0000C0H 0000C1H 0000C2H 0000C3H 0000C4H 0000C5H 0000C6H 0000C7H 0000C8H 0000C9H 0000CAH to 0000CEH 0000CFH 0000D0H 0000D1H 0000D2H 0000D3H 0000D4H 0000D5H 0000D6H 0000D7H 0000D8H to 0000DFH 0000E0H 0000E1H 0000E2H 0000E3H 0000E4H 0000E5H 0000E6H 0000E7H Register abbreviation ICR14 ICR15 CMR0 CAR0 CMR1 CAR1 CMR2 CAR2 CMR3 CAR3 CSCR CALR Register name Interrupt control register 14 Interrupt control register 15 Chip select area MASK register 0 Chip select area register 0 Chip select area MASK register 1 Chip select area register 1 Chip select area MASK register 2 Chip select area register 2 Chip select area MASK register 3 Chip select area register 3 Chip select control register Chip select active level register Reserved R/W W, R/W W, R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource Interrupt control Chip select function Initial value 00000111B 00000111B 00001111B 11111111B 00001111B 11111111B 00001111B Interrupt control 11111111B 00001111B 11111111B ----000*B ----0000B PLLOS BAPL BAPM BAPH MACS IOAL IOAH DCTL DCTH PLL output selection register DMA buffer address pointer (low) DMA buffer address pointer (middle) DMA buffer address pointer (high) DMA control register DMAI/O register address pointer (low) DMAI/O register address pointer (high) DMA data counter (low) DMA data counter (high) Reserved W R/W R/W R/W R/W R/W R/W R/W R/W PLL ------X0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB DMAC ENIR0 EIRR0 ELVR0 ENIR1 EIRR1 ELVR1 Interrupt/DTP enable register 0 Interrupt/DTP source register 0 Request level setting register 0 Request level setting register 0 Interrupt/DTP enable register 1 Interrupt/DTP source register 1 Request level setting register 1 Request level setting register 1 R/W R/W R/W R/W R/W R/W R/W R/W DTP / external interrupt DTP / external interrupt 00000000B XXXXXXXXB 00000000B 00000000B 00000000B XXXXXXXXB 00000000B 00000000B (Continued) 31 MB90880 Series Address 0000E8H 0000E9H 0000EAH 0000EBH 0000ECH to 0000EFH 0000F0H to 0000FFH 000100H to #H* 007900H 007901H 007902H 007903H 007904H 007905H 007906H 007907H 007908H 007909H 00790AH 00790BH 00790CH 00790DH 00790EH 00790FH 007910H 007911H 007912H 007913H 007914H 007915H Register abbreviation ENIR2 EIRR2 ELVR2 Register name Interrupt/DTP enable register 2 Interrupt/DTP source register 2 Request level setting register 2 Request level setting register 2 Reserved R/W R/W R/W R/W R/W Resource Initial value XXXX0000B DTP / external interrupt XXXXXXXXB 00000000B 00000000B External area RAM area PCNTL0 PCNTH0 PCNTL1 PCNTH1 PCNTL2 PCNTH2 PCNTL3 PCNTH3 PCNTL4 PCNTH4 PCNTL5 PCNTH5 PCNTL6 PCNTH6 PCNTL7 PCNTH7 PPGDIV PDCRL0 PDCRH0 PCSRL0 PCSRH0 PPG0 lower control status register PPG0 higher control status register PPG1 lower control status register PPG1 higher control status register PPG2 lower control status register PPG2 higher control status register PPG3 lower control status register PPG3 higher control status register PPG4 lower control status register PPG4 higher control status register PPG5 lower control status register PPG5 higher control status register PPG6 lower control status register PPG6 higher control status register PPG7 lower control status register PPG7 higher control status register PPG0 output division setting register Reserved PPG0 down counter register PPG0 period setting register R 16-bit PPG0 W 11111111B 11111111B 11111111B 11111111B (Continued) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00000000B 00000001B 00000000B 00000001B 00000000B 00000001B 00000000B 00000001B 00000000B 00000001B 00000000B 00000001B 00000000B 00000001B 00000000B 00000001B 11111100B 16-bit PPG0 16-bit PPG1 16-bit PPG2 16-bit PPG3 16-bit PPG4 16-bit PPG5 16-bit PPG6 16-bit PPG7 16-bit PPG0 32 MB90880 Series Address 007916H 007917H 007918H 007919H 00791AH 00791BH 00791CH 00791DH 00791EH 00791FH 007920H 007921H 007922H 007923H 007924H 007925H 007926H 007927H 007928H 007929H 00792AH 00792BH 00792CH 00792DH 00792EH 00792FH 007930H 007931H 007932H 007933H 007934H 007935H 007936H 007937H Register abbreviation PUDUTL0 PUDUTH0 Register name PPG0 duty setting register Disabled Disabled R/W W Resource 16-bit PPG0 Initial value 00000000B 00000000B PDCRL1 PDCRH1 PCSRL1 PCSRH1 PUDUTL1 PUDUTH1 PPG1 down counter register PPG1 period setting register PPG1 duty setting register Disabled Disabled R W W 16-bit PPG1 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B PDCRL2 PDCRH2 PCSRL2 PCSRH2 PUDUTL2 PUDUTH2 PPG2 down counter register PPG2 period setting register PPG2 duty setting register Disabled Disabled R W W 16-bit PPG2 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B PDCRL3 PDCRH3 PCSRL3 PCSRH3 PUDUTL3 PUDUTH3 PPG3 down counter register PPG3 period setting register PPG3 duty setting register Disabled Disabled R W W 16-bit PPG3 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B PDCRL4 PDCRH4 PCSRL4 PCSRH4 PUDUTL4 PUDUTH4 PPG4 down counter register PPG4 period setting register PPG4 duty setting register R W W 16-bit PPG4 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B (Continued) 33 MB90880 Series Address 007938H 007939H 00793AH 00793BH 00793CH 00793DH 00793EH 00793FH 007940H 007941H 007942H 007943H 007944H 007945H 007946H 007947H 007948H 007949H 00794AH 00794BH 00794CH 00794DH 00794EH 00794FH 007950H 007951H 007952H 007953H 007954H 007955H 007956H Register abbreviation Register name Disabled Disabled R/W Resource Initial value PDCRL5 PDCRH5 PCSRL5 PCSRH5 PUDUTL5 PUDUTH5 PPG5 down counter register PPG5 period setting register PPG5 duty setting register Disabled Disabled R W W 16-bit PPG5 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B PDCRL6 PDCRH6 PCSRL6 PCSRH6 PUDUTL6 PUDUTH6 PPG6 down counter register PPG6 period setting register PPG6 duty setting register Disabled Disabled R W W 16-bit PPG6 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B PDCRL7 PDCRH7 PCSRL7 PCSRH7 PUDUTL7 PUDUTH7 PPG7 down counter register PPG7 period setting register PPG7 duty setting register Disabled Disabled R W W 16-bit PPG7 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B TMCR0 STC0 Timer control register ch.0 Status control register ch.0 Disabled R/W R/W 00000000B Base timer ch.0 00000000B 00000000B 00000000B/ XXXXXXXXB 00000000B/ XXXXXXXXB (Continued) TMR0 007957H Timer register ch.0 R/W Base timer ch.0 34 MB90880 Series Address 007958H 007959H 00795AH 00795BH 00795CH 00795DH 00795EH 00795FH 007960H Register abbreviation PCSR0/ PRLL0 PDUT0/ PRLH0/ DTBF0 TMCR1 STC1 Register name Period/L-width setting register ch.0 R/W R/W Resource Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB/ 00000000B XXXXXXXXB/ 00000000B 00000000B Base timer ch.0 Duty/H-width/data buffer register ch.0 R/W Timer control register ch.1 Status control register ch.1 Disabled R/W R/W Base timer ch.1 00000000B 00000000B 00000000B/ XXXXXXXXB 00000000B/ XXXXXXXXB TMR1 007961H 007962H 007963H 007964H 007965H 007966H 007967H 007968H 007969H 00796AH TMR2 00796BH 00796CH 00796DH 00796EH 00796FH 007970H 007971H 007972H PCSR2/ PRLL2 PDUT2/ PRLH2/ DTBF2 TMCR3 STC3 PCSR1/ PRLL1 PDUT1/ PRLH1/ DTBF1 TMCR2 STC2 Timer register ch.1 R/W Period/L-width setting register ch.1 R/W Base timer ch.1 XXXXXXXXB XXXXXXXXB XXXXXXXXB/ 00000000B XXXXXXXXB/ 00000000B 00000000B Duty/H-width/data buffer register ch.1 R/W Timer control register ch.2 Status control register ch.2 Disabled R/W R/W Base timer ch.2 00000000B 00000000B 00000000B/ XXXXXXXXB 00000000B/ XXXXXXXXB Timer register ch.2 R/W Period/L-width setting register ch.2 R/W Base timer ch.2 XXXXXXXXB XXXXXXXXB XXXXXXXXB/ 00000000B XXXXXXXXB/ 00000000B 00000000B Duty/H-width/data buffer register ch.2 R/W Timer control register ch.3 Status control register ch.3 R/W R/W Base timer ch.3 00000000B 00000000B (Continued) 35 MB90880 Series Address 007973H 007974H Register abbreviation Register name Disabled R/W Resource Initial value TMR3 007975H 007976H 007977H 007978H 007979H 00797AH 00797BH 00797CH 00797DH 00797EH 00797FH 007980H 007981H 007982H 007983H 007984H 007985H to 00798FH 007990H SMR6 CSR1 PCSR3/ PRLL3 PDUT3/ PRLH3/ DTBF3 UDCR0 UDCR1 RCR0 RCR1 CCRL0 CCRH0 CCRL1 CCRH1 CSR0 Timer register ch.3 R/W 00000000B/ XXXXXXXXB 00000000B/ XXXXXXXXB Base timer ch.3 XXXXXXXXB XXXXXXXXB XXXXXXXXB/ 00000000B XXXXXXXXB/ 00000000B 00000000B 00000000B 00000000B 00000000B 8/16-bit up-down counter/timer XX00X000B 00000000B XX00X000B -0000000B 00000000B 8/16-bit up-down counter/timer Period/L-width setting register ch.3 R/W Duty/H-width/data buffer register ch.3 R/W Up-down count register (ch.0) Up-down count register (ch.1) Reload/compare register (ch.0) Reload/compare register (ch.1) Lower counter control register (ch.0) Higher counter control register (ch.0) Lower counter control register (ch.1) Higher counter control register (ch.1) Counter status register (ch.0) Reserved Counter status register (ch.1) Reserved Serial bus mode register ch.6 Serial bus control register / I2C bus control register ch.6 Extended communication control register / I2C bus status register ch.6 Serial status register ch.6 Transmission/reception data register 0 ch.6 Transmission/reception data register 1 ch.6 Baud rate generator register 0 ch.6 Baud rate generator register 1 ch.6 R R W W W, R/W R/W W, R/W R/W R, R/W R, R/W 00000000B R/W R/W R/W R/W R,W R,W R/W R/W Multi-function serial ch.6 $$$$$$$$B $$$$$$$$B $$$$$$$$B $$$$$$$$B $$$$$$$$B $$$$$$$$B $$$$$$$$B $$$$$$$$B (Continued) 007991H SCR6/IBCR6 007992H 007993H 007994H 007995H 007996H 007997H ESCR6/ IBSR6 SSR6 RDR06/ TDR06 RDR16/ TDR16 BGR06 BGR16 36 MB90880 Series Address 007998H 007999H 00799AH 00799BH 00799CH 00799DH 00799CH to 0079A1H 0079A2H 0079A3H 0079A4H, 0079A5H 0079A6H 0079A7H 0079A8H to 0079DFH 0079E0H 0079E1H 0079E2H 0079E3H 0079E4H 0079E5H 0079E6H 0079E7H 0079E8H 0079E9H to 0079EFH 0079F0H 0079F1H 0079F2H Register abbreviation ISBA6 ISMK6 PAFSR PMSSR Register name 7-bit slave address register ch.6 7-bit slave address mask register ch.6 PPG pin assignment switching register PPG multi-channel start register Reserved R/W R/W R/W R/W R/W Resource Multi-function serial ch.6 PPG pin switching control PPG multi-start control Multi-function serial pin control Initial value 00000000B 01111111B ----0000B 00000000B P9FSR Serial pin switching register 1 Reserved R/W -----000B P7FSR LSYNS Serial pin switching register 0 LIN SYNCH FIELD switching register Reserved R/W R/W Multi-function serial pin control Input capture input control ----000XB 10001000B FWR0 FWR1 Flash memory write control register 0 Flash memory write control register 1 Reserved Detection address register 0 (low) R/W R/W Flash memory I/F 00000000B 00000000B XXXXXXXXB R/W Address match detection function XXXXXXXXB XXXXXXXXB XXXXXXXXB R/W Address match detection function XXXXXXXXB XXXXXXXXB XXXXXXXXB R/W Address match detection function XXXXXXXXB XXXXXXXXB PADR0 Detection address register 0 (middle) Detection address register 0 (high) Detection address register 1 (low) PADR1 Detection address register 1 (middle) Detection address register 1 (high) Detection address register 2 (low) PADR2 Detection address register 2 (middle) Detection address register 2 (high) Reserved Detection address register 3 (low) XXXXXXXXB R/W Address match detection function XXXXXXXXB XXXXXXXXB (Continued) PADR3 Detection address register 3 (middle) Detection address register 3 (high) 37 MB90880 Series (Continued) Address 0079F3H 0079F4H 0079F5H 0079F6H 0079F7H 0079F8H 0079F9H to 007FFFH Explanation on R/W R/W : Readable/Writable R : Read only W : Write only Explanation on initial value 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. : This bit is not used. * : The initial value of this bit is “1” or “0”. It varies depending on the mode pin (MD2, MD1 or MD0 pin) . + : The initial value of this bit is “1” or “0”. $ : The initial value of this bit varies depending on the operation mode of the resource. #H* : Varies depending on the RAM area of the device. PADR5 PADR4 Register abbreviation Register name Detection address register 4 (low) Detection address register 4 (middle) Detection address register 4 (high) Detection address register 5 (low) Detection address register 5 (middle) Detection address register 5 (high) Reserved R/W Address match detection function R/W Address match detection function R/W Resource Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 38 MB90880 Series ■ INTERRUPT SOURCES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTERS Interrupt source Reset INT9 instruction Exception INT0 (IRQ0/1) INT0 (IRQ2 to IRQ7) INT0 (IRQ8 to IRQ15) INT0 (IRQ16 to IRQ23) Base timer ch.0 (source 0,1) Base timer ch.1 (source 0,1) Base timer ch.2 (source 0,1) Base timer ch.3 (source 0,1) PPG0/PPG4 counter borrow PPG1/PPG5 counter borrow PPG2/PPG6 counter borrow PPG3/PPG7 counter borrow 8/16-bit up-down counter/timer (ch.0/1) compare / underflow / overflow / up-down inversion Input capture retrieval (ch.0/1) Output compare (ch.0/1/2) match Output compare (ch.3/4/5) match A/D converter Overflow in 16-bit free-run timer / compare clear / multi-function serial ch.4/5/6 status Multi-function serial ch.4 reception Multi-function serial ch.4 transition Multi-function serial ch.5 reception Multi-function serial ch.5 transition Multi-function serial ch.6 reception Multi-function serial ch.6 transition Multi-function serial ch.0/1 reception / status Multi-function serial ch.0/1 transmission Multi-function serial ch.2 reception / status Multi-function serial ch.2 transmission × × µDMAC Clearing channel of EI2OS no. × × × ⎯ ⎯ ⎯ 0 × × × 1 2 3 4 5 6 7 8 × × × × × 9 10 11 12 13 14 15 × × × × Interrupt vector No. #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H ICR08 0000B8H ICR07 0000B7H Interrupt control register No. ⎯ ⎯ ⎯ ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 Address ⎯ ⎯ ⎯ 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H ICR06 0000B6H ICR09 ICR10 ICR11 ICR12 ICR13 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH (Continued) 39 MB90880 Series (Continued) Interrupt source Multi-function serial ch.3 reception / status Multi-function serial ch.3 transmission Flash writing/deletion, time base timer, watch timer* Delayed interrupt generation module × × × µDMAC Clearing channel 2OS of EI no. × × × × Interrupt vector No. #39 #40 #41 #42 Address FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register No. ICR14 Address 0000BEH ICR15 0000BFH : The interrupt request flag is not cleared by the interrupt clear signal. : The interrupt request flag is cleared by the interrupt clear signal. : The interrupt request flag is cleared by the interrupt clear signal. Stop request function provided at receiving only. * : Flash writing/deletion, the time base timer and watch timer cannot be used simultaneously. Note : If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are cleared by the EI2OS/µDMAC interrupt clear signal. Therefore, when either of the two sources for the EI2OS/ µDMAC function is used, the other interrupt function can not be used. In this case, set the interrupt request enable bit to “0” in the appropriate resource and take measures by software polling. 40 MB90880 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute maximum ratings Parameter Symbol VCC Power supply voltage*1 DVCC AVCC AVRH Input voltage*1 Output voltage*1 Maximum clamp current Total maximum clamp current “L” level maximum output current “L” level average output current “L” level maximum total output current “L” level average total output current “H” level maximum output current “H” level average output current “H” level maximum total output current “H” level average total output current Power consumption Operating temperature Storage temperature VI VO ICLAMP Σ⏐ICLAMP⏐ IOL1 IOL2 IOLAV1 IOLAV2 ΣIOL1 ΣIOL2 ΣIOLAV1 ΣIOLAV2 IOH1 IOH2 IOHAV1 IOHAV2 ΣIOH1 ΣIOH2 ΣIOHAV1 ΣIOHAV2 PD TA Tstg Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 − 2.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ −40 −55 Max VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 7.0 VSS + 4.0 VSS + 7.0 +2.0 20 10 20 3 10 60 80 30 40 −10 −20 −3 −10 −60 −80 −30 −40 320 +85 +150 Unit V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mW °C °C PA0 to PA3 *6 PA0 to PA3*6 PA0 to PA3 *6 PA0 to PA3*6 *4 PA0 to PA3*4 *5 PA0 to PA3*5 DVcc = Vcc*2 *2 *2 *3 *3, *8 *3 *3, *8 *7 *7 *4 PA0 to PA3*4 *5 PA0 to PA3*5 Remarks *1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V. *2 : Set AVCC, DVCC and AVRH to the same voltage. AVCC and DVCC must not exceed VCC. Also, AVRH must not exceed AVCC. *3 : VI and VO must not exceed 0.3V. When the maximum current to/from an input is limited by using an external component, the ICLAMP rating supersedes the VI rating. *4 : The maximum output current is defined as the peak value of the current of any one of the corresponding pins. (Continued) 41 MB90880 Series (Continued) *5 : The average output current is defined as the value of the average current flowing over 100 ms at any one of the corresponding pins. *6 : The average total output current is defined as the value of the average current flowing over 100 ms at all of the corresponding pins. *7 : • Relevant pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P76, P80 to P87, P90 to P97, PA0 to PA3 • Use within recommended operating conditions. • Use with DC voltage (current) . • The + B signal should always be applied with a limiting resistance placed between the + B signal and the microcontroller. • Set the limiting resistor value, whether instantaneous or stationary, so that the current to be input to the microcontroller pin does not exceed the rating during the input of the + B signal. • Note that when the microcontroller drive current is low, such as in the power saving modes, the + B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a + B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the + B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the + B input pin open. • Note that analog system input/output pins (LCD drive pins, comparator input pins, etc.) cannot accept + B signal input. • Sample recommended circuit : • Input/Output equivalent circuit Protective diode VCC Limiting resistance + B input (0V to 16V) P-ch N-ch R *8 : P74 to P76 and P80 to P87 can be used as 5V I/F pins. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed any of these ratings. 42 MB90880 Series 2. Recommended operating conditions (VSS = AVSS = 0.0 V) Parameter Power supply voltage Symbol VCC DVcc VIH VIH2 VIHS “H” level input voltage VIHS2 VIHS3 VIHM VIHX VIL VILS “L” level input voltage VILS2 VILS3 VILM VILX Value Min 2.7 1.8 0.7 VCC 0.7 VCC 0.8 VCC 0.7 VCC 0.7 VCC VCC − 0.3 0.8 VCC VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 Max 3.6 3.6 VCC + 0.3 VSS + 5.8 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.3 VCC 0.2 VCC 0.3 VCC 0.3 VCC VSS + 0.3 0.1 Unit V V V V V V V V V V V V V V V Remarks In normal operation Hold stop status All pins other than VIH2, VIHS, VIHM and VIHX P74 to P76, P80 to P87 Hysteresis input pins Hysteresis input pins (multi-function serial pins) CMOS input pins (external bus mode input pins) MD pin input X0A and X1A pins All pins other than VILS, VILM and VIHX Hysteresis input pins Hysteresis input pins (multi-function serial pins) CMOS input pins (external bus mode pins) MD pin input X0A and X1A pins Use a ceramic capacitor or comparable capacitor of the AC characteristics. Bypass capacitor at the VCC pin should be greater than this capacitor. Smoothing capacitor CS 0.1 1.0 µF Operating temperature • C Pin Connection Diagram TA −40 +85 °C C CS 43 MB90880 Series WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 44 MB90880 Series 3. DC characteristics (VCC = 2.7V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name All pins except P74 to P76, P80 to P87 and PA0 to PA3 P74 to P76, P80 to P87 PA0 to PA3 All pins except P74 to P76, P80 to P87 and PA0 to PA3 P74 to P76, P80 to P87 PA0 to PA3 Input leak current IIL All input pins Conditions Value Min Typ Max Unit Remarks VCC = 3.0 V, IOH = −4.0 mA VCC − 0.5 ⎯ ⎯ V “H” level output voltage VOH VCC = 3.0 V, IOH = −2.0 mA DVCC = 3.0 V, IOH = −10.0 mA VCC − 0.5 DVCC − 0.6 ⎯ ⎯ ⎯ ⎯ V V VCC = 3.0 V, IOL = 4.0 mA ⎯ ⎯ 0.4 V “L” level output voltage VOL VCC = 3.0 V, IOH = −2.0 mA DVCC = 3.0 V, IOL = 10.0 mA VCC = 3.3 V, VSS < VI < VCC ⎯ ⎯ −10 25 ⎯ ⎯ ⎯ 50 0.4 0.5 +10 100 V V µA kΩ Evaluation version Flash memory version / MASK ROM version Pull-up resistance RPULL ⎯ ⎯ 15 33 66 kΩ Open-drain output current Ileak P31, P32, P34, P35, P43, P44, P46, P47, P72 to P76, P80 to P87, P96, P97 ⎯ ⎯ 0.1 10 µA (Continued) 45 MB90880 Series (Continued) (VCC = 2.7V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Conditions VCC = 3.3V; Normal internal 25 MHz operation VCC = 3.3V; Normal internal 33 MHz operation VCC = 3.3V; Internal 25 MHz operation; flash write VCC = 3.3V; Internal 33 MHz operation; flash write VCC = 3.3V; Internal 25 MHz operation; sleep mode VCC = 3.3V; Internal 33 MHz operation; sleep mode VCC = 3.3 V; Internal 2 MHz, operation; Time-base timer VCC = 3.3V; External 32 kHz & internal 8 kHz operation; sub-operation (TA = + 25 °C) VCC = 3.3 V; External 32 MHz, Internal 8 MHz operation; sub sleep mode (TA = +25 °C) VCC = 3.3V; External 32 kHz & internal 8 kHz operation; watch operation (TA = + 25 °C) TA = + 25 °C; Stop mode; VCC = 3.3V AVCC, AVSS, VCC, DVCC, VSS, DVSS Value Min ⎯ Typ 20 Max 28 Unit mA ⎯ 28 38 mA ICC ⎯ ⎯ 30 40 mA ⎯ 40 52 mA ⎯ 6 12 mA ICCS ⎯ ⎯ 10 20 mA Supply current ICTS ⎯ ⎯ 0.25 0.9 mA ICCL ⎯ ⎯ 80 200 µA ICCLS ⎯ ⎯ 50 160 µA ICCT ⎯ ⎯ 20 110 µA ICCH ⎯ All pins except AVCC, AVSS, VCC, DVCC, VSS, DVSS ⎯ 15 100 µA Input capacitance CIN ⎯ 5 15 pF Note : P74 to P76 and P80 to P87 are N-ch open-drain pins with controls and normally used at the CMOS level. 46 MB90880 Series 4. AC characteristics (1) Clock timing ratings (VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Conditions ⎯ ⎯ ⎯ Clock frequency FCH X0, X1 ⎯ ⎯ ⎯ ⎯ ⎯ FCL Clock cycle time tC tCL PWH PWL PWLH PWLL tcr tcf fCP fCPL tCP tCPL X0A, X1A X0, X1 X0A, X1A X0 X0A X0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Value Min 3 3 4 3 3 3 3 3 ⎯ 15.15 ⎯ 5 ⎯ ⎯ 1.5 ⎯ 30.3 ⎯ Typ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 32.768 ⎯ 30.5 ⎯ 15.2 ⎯ ⎯ 8.192 ⎯ 122.1 Max 25 50 25 12.5 6.66 6.25 5.5 4.125 ⎯ 333 ⎯ ⎯ ⎯ 5 33 ⎯ 666 ⎯ kHz ns µs ns µs ns *2 External clock in use *1 Unit Remarks External crystal oscillation External clock input PLL1 multiplication MHz PLL2 multiplication PLL3 multiplication PLL4 multiplication PLL6 multiplication PLL8 multiplication Input clock pulse width Input clock rise/fall time Internal operating clock frequency Internal operating clock cycle time MHz *1 kHz ns µs *1 *1 : Observe the operating voltage with care. The maximum operating frequency is 25 MHz in MB90F883(S) and MB90F884(S). *2 : Input it at a duty ratio of 50% ±3%. • X0, X1 clock timing tC X0 PWH tcf PWL tcr 0.8 VCC 0.2 VCC 47 MB90880 Series • X0A, X1A clock timing tCL X0A PWLH tcf PWLL tcr 0.8 VCC 0.1 VCC 48 MB90880 Series • PLL warranted operating range Internal operating clock frequency vs. Supply voltage 3.6 Supply voltage VCC (V) PLL warranted operating range 3.0 2.7 Normal operating range 1.5 4 16 33 Internal clock fCP (MHz) *4 Notes: • Use the fCP at 4 MHz or higher only for PLL1 multiplication. • For A/D operating frequencies, refer to “5. A/D Converter electrical characteristics”. Source oscillator frequency vs. Internal operating clock frequency 33 8 Multiplication*3 3 Multiplication*1 25 24 Internal clock fCP (MHz) *4 20 18 16 12 9 8 6 4 1.5 6 Multiplication*3 2 Multiplication*1, *2 4 Multiplication *1, *2 1 Multiplication*1 No multiplication 3 4 5 6 8 10 12.5 16 20 25 32 40 50 Source oscillator clock FCH (MHz) *1 : When using the internal clock at “20 MHz < fCP ≤ 25 MHz” in PLL1, 2, 3 or 4 multiplication setting, set both of the DIV2 and PLL2 bits to “1” in the PLLOS register. Example : When the source oscillator frequency is 24 MHz in PLL1 multiplication : CKSCR register : CS1 = “0”, CS0 = “0” PLLOS register : DIV2 = “1”, PLL2 = “1” Example : When the source oscillator frequency is 6 MHz in PLL3 multiplication : CKSCR register : CS1 = “1”, CS0 = “0” PLLOS register : DIV2 = “1”, PLL2 = “1” When using the internal clock at “20 MHz < fCP ≤ 25 MHz” in PLL 2 or 4 multiplication setting, the following settings can also be used. PLL2 multiplication : CKSCR register : CS1 = “0”, CS0 = “0” PLLOS register : DIV2 = “0”, PLL2 = “1” PLL4 multiplication CKSCR register : CS1 = “0”, CS0 = “1” PLLOS register : DIV2 = “0”, PLL2 = “1” When using the PLL6 or 8 multiplication setting, set DIV2 to “0” and PLL2 to “1” in the PLLOS register. Example : When the source oscillator frequency is 4 MHz in PLL6 multiplication : CKSCR register : CS1 = “1”, CS0 = “0” PLLOS register : DIV2 = “0”, PLL2 = “1” Example : When the source oscillator frequency is 3 MHz in PLL8 multiplication : CKSCR register : CS1 = “1”, CS0 = “1” PLLOS register : DIV2 = “0”, PLL2 = “1” The maximum operating frequency of MB90F883(S) and MB90F884(S) is 25 MHz. *2 : *3 : *4 : 49 MB90880 Series AC characteristics are determined using the following measurement reference voltage values. • Input signal waveform Hysteresis input pins 0.8 VCC 0.2 VCC • Output signal waveform Output pins 2.4 V 0.8 V Pins other than hysteresis input/MD input pins 0.7 VCC 0.3 VCC 50 MB90880 Series (2) Clock output timing (VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Cycle time CLK↑ → CLK↓ Symbol tCYC tCHCL Pin name CLK CLK Conditions ⎯ Value Min tCP* Max ⎯ Unit ns ns ns ns fCP = 25 MHz fCP = 16 MHz fCP = 5 MHz Remarks VCC = 3.0 V to 3.6 V tCP* / 2 − 15 tCP* / 2 + 15 VCC = 2.7 V to 3.3 V tCP* / 2 − 20 tCP* / 2 + 20 VCC = 2.7 V to 3.3 V tCP* / 2 − 64 tCP* / 2 + 64 * : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”. tCYC tCHCL 2.4 V 2.4 V 0.8 V CLK 51 MB90880 Series (3) Reset input ratings (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Conditions Value Min 16 tCP*1 Max ⎯ Unit ns Remarks In normal operation In sub clock, sub-sleep, watch and stop modes In time base timer mode Reset input time tRSTL RST ⎯ Oscillator oscillation time *2 + 100 µs + 16 tCP*1 ⎯ ms 100 ⎯ µs *1 : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”. *2 : Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to several tens of ms; for a ceramic oscillator, this is several hundred ms to a few ms, and for an external clock this is 0 ms. • In sub clock, sub-sleep, watch and stop modes tRSTL RST 0.2 VCC 0.2 VCC 90% of amplitude X0 Internal operation clock 100 µs + 16 tCP Oscillator oscillation time Internal reset Oscillation stabilization wait time Execution of instruction • Measurement conditions for AC ratings Pin CL : Load capacitance applied to pin during testing CLK, ALE : CL = 30 pF AD15 to AD00 (Address, data bus) , RD, WR, A23 to A00/D15 to D00 : CL = 30 pF CL 52 MB90880 Series (4) Power-on ratings (Power-on reset) (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Power rise time Power cutoff time Symbol Pin name tR tOFF VCC VCC ⎯ Conditions Value Min 0.05 1 Max 30 ⎯ Unit ms ms * For continuous operation Remarks * : During the power rise time, VCC must be less than 0.2V. Notes : • The above ratings are values used for power-on reset. • A power-on reset should be applied by restarting the power supply inside the device. tR VCC 2.7 V 0.2 V 0.2 V tOFF 0.2 V A sudden change in the supply voltage may activate a power-on reset. As shown in the following figure, it is recommended to apply a smooth voltage rise with suppressed fluctuation when changing the supply voltage during operation. Main power voltage VCC Sub supply voltage VSS RAM data held A rise slope of 50mV/ms or less is recommended. 53 MB90880 Series (5) Bus read timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C) Parameter Symbol Pin name Conditions Value Min tCP* / 2 − 15 ALE pulse width tLHLL ALE ⎯ tCP* / 2 − 20 tCP* / 2 − 35 Valid address → ALE↓ time ALE ↓ → valid address time valid address → RD↓ Time Valid address → valid data input tAVLL tLLAX tAVRL tAVDV Address, ALE ALE, address RD, address Address / data ⎯ ⎯ ⎯ ⎯ tCP* / 2 − 17 tCP* / 2 − 40 tCP* / 2 − 15 tCP* − 25 ⎯ ⎯ 3 tCP* / 2 − 25 RD pulse width tRLRH RD ⎯ 3 tCP* / 2 − 20 RD↓ → valid data input RD↑→ data hold time RD↑ → ALE↑ time RD↑ → valid address time Valid address → CLK↑ time RD↓ → CLK↑ time ALE↓ → RD↓ time tRLDV tRHDX tRHLH tRHAX tAVCH tRLCH tLLRL RD, data RD, data RD, ALE Address, RD Address, CLK RD, CLK RD, ALE ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 tCP* / 2 − 15 tCP* / 2 − 10 tCP* / 2 − 17 tCP* / 2 − 17 tCP* / 2 − 15 ⎯ 3 tCP* / 2 − 55 3 tCP* / 2 − 80 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns ns ns ns ns ns ns ns ns fCP ≤ 8 MHz Max ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 5 tCP* / 2 − 55 5 tCP* / 2 − 80 ⎯ Unit ns ns ns ns ns ns ns ns ns ns fCP ≤ 8 MHz 16 MHz < fCP ≤ 25 MHz 8 MHz < fCP ≤ 16 MHz fCP ≤ 8 MHz Remarks 16 MHz < fCP ≤ 25 MHz 8 MHz < fCP ≤ 16 MHz fCP ≤ 8 MHz * : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”. 54 MB90880 Series tAVCH 2.4 V tRLCH 2.4 V CLK tRHLH ALE 2.4 V tLHLL 2.4 V 0.8 V tRLRH 2.4 V RD 2.4 V tAVLL tLLAX tLLRL 0.8 V Multiplex mode tAVRL 2.4 V 0.8 V tAVDV 2.4 V 2.4 V tRLDV tRHAX 2.4 V 0.8 V A23 to A16 tRHDX 0.7 VCC 0.7 VCC AD15 to AD00 0.8 V Address 0.8 V 0.3 VCC Read data 0.3 VCC tRHAX Non-multiplex mode A23 to A00 2.4 V 0.8 V tRLDV tAVDV 0.7 VCC 2.4 V 0.8 V tRHDX 0.7 VCC D15 to D00 0.3 VCC Read data 0.3 VCC 55 MB90880 Series (6) Bus write timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C) Parameter Valid address → WR ↓ time Symbol tAVWL Pin name Address, WR Conditions ⎯ ⎯ WR pulse width tWLWH WRL, WRH ⎯ Valid data output → WR↑ time tDVWH Data, WR ⎯ ⎯ WR↑ → data hold time tWHDX WR, data ⎯ ⎯ WR↑ → valid address time WR↑ → ALE↑ time WR↓ → CLK↑ time tWHAX tWHLH tWLCH WR, address WR, ALE WR, CLK ⎯ ⎯ ⎯ 3 tCP* / 2 − 20 3 tCP* / 2 − 15 10 20 30 tCP* / 2 − 10 tCP* / 2 − 15 tCP* / 2 − 17 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ns ns ns ns ns ns ns ns 16 MHz < fCP ≤ 25 MHz 8 MHz < fCP ≤ 16 MHz fCP ≤ 8 MHz Value Min tCP* − 15 3 tCP* / 2 − 25 Max ⎯ ⎯ Unit ns ns 16 MHz < fCP ≤ 25 MHz 8 MHz < fCP ≤ 16 MHz Remarks * : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”. 56 MB90880 Series tWLCH 2.4 V CLK tWHLH ALE tWLWH 2.4 V 2.4 V WR (WRL, WRH) Multiplex mode tAVWL 2.4 V 0.8 V 0.8 V tWHAX 2.4 V 0.8 V tDVWH tWHDX 2.4 V A23 to A16 2.4 V AD15 to AD00 0.8 V Address 2.4 V 0.8 V Write data 0.8 V tWHAX Non-multiplex mode A23 to A00 2.4 V 0.8 V tDVWH 2.4 V 0.8 V tWHDX 2.4 V D15 to D00 2.4 V 0.8 V Write data 0.8 V 57 MB90880 Series (7) Ready input timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C) Parameter RDY setup time RDY hold time Symbol tRYHS tRYHH Pin name Conditions ⎯ RDY ⎯ ⎯ Value Min 35 70 0 Max ⎯ ⎯ ⎯ Unit ns ns ns fCP = 8 MHz Remarks 2.4 V 2.4 V CLK ALE RD/WR tRYHS tRYHH When RDY wait is not applied When RDY wait is applied (1 cycle) 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tRYHS 58 MB90880 Series (8) Hold timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C) Parameter Pin floating → HAK↓ time HAK↓ → valid pin time Symbol tXHAL tHAHV Pin name HAK HAK Conditions Value Min 30 tCP* Max tCP* 2 tCP* Unit ns ns ⎯ * : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”. Note : It takes one or more cycles from when the HRQ pin is read to when HAK changes. HAK 0.8 V tXHAL 2.4 V 0.8 V 2.4 V tHAHV High-Z Pins 2.4 V 0.8 V 59 MB90880 Series (9) Multi-function serial timing (UART, SIO) (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Serial clock cycle time UCK↓ → UO delay time Valid UI → UCK↑ UCK↑ → valid UI hold time Serial clock “H” pulse width Serial clock “L” pulse width UCK↓ → UO delay time Valid UI → UCK↑ UCK↑ → valid UI hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ External shift clock mode output pin : CL*1 = 80 pF + 1 TTL Internal shift clock mode output pin : CL*1 = 80 pF + 1 TTL Conditions Value Min 8 tCP*2 −50 50 0 4 tCP*2 4 tCP*2 ⎯ 50 50 Max ⎯ +50 ⎯ ⎯ ⎯ ⎯ 50 ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns *1 : CL is the load capacitance applied to pins during testing. *2 : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”. Note : The above AC characteristics are for CLK synchronous mode operation. • Internal shift clock mode tSCYC UCK 0.8 V tSLOV 2.4 V 2.4 V 0.8 V UO 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC UI 0.2 VCC • External shift clock mode tSLSH tSHSL 0.8 VCC 0.2 VCC tSLOV 2.4 V 0.2 VCC 0.8 VCC UCK UO 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC UI 0.2 VCC 60 MB90880 Series (10) Multi-function serial timing (I2C) a. Master mode operation (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter SCL clock frequency SCL clock “L” width SCL clock “H” width Bus-free time between “stop” condition and “start” condition Repeat “start” condition setup time SCL↑ → SDA↓ (Repeat) “start” condition hold time SDA↓ → SCL↓ “Stop” condition setup time SCL↑ → SDA↑ Data hold time SCL↓ → SDA↓↑ Data setup time SDA↓↑ → SCL↑ Symbol fSCL tLOW tHIGH tBUS tSUSTA tHDSTA tSUSTO tHDDAT tSUDAT Conditions Standard mode Min 0 4.7 4.0 4.7 4.7 Max 100 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ High-speed mode*3 Min 0 4.7 4.0 1.3 0.6 0.6 0.6 2tcp*1 100*2 Max 400 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Unit kHz µs µs µs µs µs µs µs ns R=1kΩ C=50pF*4 4.0 4.0 2tcp*1 250 61 MB90880 Series b. Slave mode operation (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter SCL clock frequency SCL clock “L” width SCL clock “H” width Bus-free time between “stop” condition and “start” condition Repeat “start” condition setup time SCL↑ → SDA↓ (Repeat) “start” condition hold time SDA↓ → SCL↓ “Stop” condition setup time SCL↑ → SDA↑ Data hold time SCL↓ → SDA↓↑ Data setup time SDA↓↑ → SCL↑ Symbol fSCL tLOW tHIGH tBUS tSUSTA tHDSTA tSUSTO tHDDAT tSUDAT Conditions Standard mode Min 0 4.7 4.0 4.7 4.7 Max 100 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ High-speed mode *3 Min 0 1.3 0.6 1.3 0.6 0.6 0.6 2tcp*1 100*2 Max 400 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Unit kHz µs µs µs µs µs µs µs ns R=1kΩ C=50pF*4 4.0 4.0 2tcp*1 250 *1 : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”. *2 : The high-speed mode I2C bus device can be used in a standard mode I2C bus system. However, the device must satisfy the required condition “tSUDAT ≥ 250 ns”. If the device does not extend the “L” period of the SCL signal, the succeeding data must be output to the SDA line before a period of 1250 ns (the maximum time of SDA/SCL rise + tSUDAT) in which the SCL line is open. *3 : Set the internal operation clock to 6MHz or higher when using this over 100kHz. *4 : “R” and “C” are the pull-up resistance and load capacitance of the SCL/SDA lines. 62 MB90880 Series • Note on SDA/SCL setup time SDA Input data setup time SCL 6 tcp Note: The specification for the input data setup time of the device which is connected to the bus may not be satisfied, depending on the load capacitance and pull-up resistance. If the specification of the input data setup time can not be satisfied, adjust the pull-up resistance of SDA and SCL. • Timing definition SDA tBUS tLOW SCL tHDSTA tHIGH tHDDAT fSCL tSUSTA tSUSTO tSUDAT tHDSTA 63 MB90880 Series (11) Timer input timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Input pulse width Symbol tTIWH tTIWL Pin name IN0, IN1, TIO0 to TIO3 Conditions ⎯ Value Min 4 tCP* Max ⎯ Unit ns *: tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”. IN0, IN1 TIO0 to TIO3 0.8 VCC 0.8 VCC 0.2 VCC tTIWH tTIWL 0.2 VCC (12) Timer output timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter CLK↑ → change time PPG0 to PPG5 change time OUT0 to OUT5 change time Symbol Pin name Conditions Value Min Max Unit tTO PPG0 to PPG7, OUT0 to OUT5, TIO0 to TIO3 Load condition : 80 pF 30 ⎯ ns CLK 0.7 VCC PPG0 to PPG7 OUT0 to OUT5 TIO0 to TIO3 0.7 VCC 0.3 VCC tTO 64 MB90880 Series (13) Trigger input timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Input pulse width Symbol tTRGH tTRGL Pin name ADTG, IRQ0 to IRQ7 Conditions ⎯ Value Min 5 tCP* 1 Max ⎯ ⎯ Unit ns µs Remarks In normal operation In stop mode *: tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”. IRQ0 to IRQ7 ADTG 0.8 VCC 0.8 VCC 0.2 VCC tTRGH tTRGL 0.2 VCC 65 MB90880 Series (14) Chip select output timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Chip select output valid time → RD↓ Chip select output valid time → WR↓ RD↑ → Chip select output valid time WR↑ → Chip select output valid time Symbol tSVRL tSVWL tRHSV tWHSV Pin name CS0 to CS3, RD CS0 to CS3, WRH, WRL RD, CS0 to CS3 WRH, WRL, CS0 to CS3 Conditions ⎯ ⎯ ⎯ ⎯ Value Min tCP* / 2 − 7 tCP* / 2 − 7 tCP* / 2 − 17 tCP* / 2 − 17 Max ⎯ ⎯ ⎯ ⎯ Unit ns ns ns ns *: tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”. tSVRL 2.4 V RD 0.8 V tRHSV 2.4 V 0.8 V A23 to A16 CS0 to CS3 D15 to D00 2.4 V Read data 0.8 V tSVWL tWHSV 2.4 V 0.8 V WRH, WRL D15 to D00 Undefined Write data Note : The chip select output signal changes simultaneously due to the internal bus configuration; therefore, this may generate a bus wait. AC cannot be warranted between the ALE output signal and the chip select output signal. 66 MB90880 Series 5. A/D converter electrical characteristics (VCC = AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, 2.7 V ≤ AVRH, TA = −40 °C to +85 °C) Parameter Resolution Total error Linear error Differential linear error Zero transition voltage Full-scale transition voltage Sampling time Compare time Conversion time Analog port input current Analog input voltage Reference voltage Supply current Reference voltage supply current Inter-channel variation *1 : Time per channel *2 : Current when the A/D converter is not in operation and the CPU is stopped (VCC = AVCC = AVRH = 3.0 V ) Symbol ⎯ ⎯ ⎯ ⎯ VOT VFST tSMP tCMP tCNV IAIN VAIN ⎯ IA IAH IR IRH ⎯ Pin name ⎯ ⎯ ⎯ ⎯ AN0 to AN7 Value Min ⎯ ⎯ ⎯ ⎯ AVSS − 1.5 LSB Standard ⎯ ⎯ ⎯ ⎯ AVSS + 0.5 LSB Max 10 ±3.0 ±2.5 ±1.9 AVSS + 2.5 LSB Unit Remarks bit LSB LSB LSB V V µs µs µs µA V V mA µA µA µA LSB *1 *1 *1 AN0 to AN7 AVRH − 3.5 LSB AVRH − 1.5 LSB AVRH + 0.5 LSB ⎯ ⎯ ⎯ AN0 to AN7 AN0 to AN7 AVRH AVCC AVCC AVRH AVRH AN0 to AN7 1.2 1.8 3.0 − 3.0 AVSS AVSS + 2.2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 1.9 ⎯ 520 ⎯ ⎯ ⎯ ⎯ ⎯ + 3.0 AVRH AVCC 3.7 5*2 720 5 *2 4 67 MB90880 Series • External impedance and sampling time for analog input This is an A/D converter with a sample hold function. If high external impedance is preventing it from securing sufficient sampling time, a sufficient analog voltage will not be charged in the internal sample hold capacitor, affecting the accuracy of the A/D conversion. In order to satisfy the A/D conversion accuracy specifications, adjust the register values and operating frequency or decrease the external impedance so that the sampling time becomes longer than the minimum value, based on the relationship between the external impedance and the minimum sampling time. If a sufficient sampling time cannot be secured, connect a capacitor with a capacitance of approximately 0.1 µF to the analog input pin. Model diagram of analog input circuit R Analog input Comparator C Turned on during sampling ON R 12.2kΩ (Max) C 8.5pF (Max) Note : These are reference values. • Relation between external impedance and minimum sampling time [External impedance = 0 kΩ to 100 kΩ] Flash memory device MASK ROM device 100 90 20 18 [External impedance = 0 kΩ to 20 kΩ] Flash memory device MASK ROM device External impedance [kΩ] External impedance [kΩ] 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 Minimum sampling time [µs] Minimum sampling time [µs] • Errors : As | AVRH⎯AVSS | decreases, the absolute error increases. 68 MB90880 Series 6. Definition of A/D Converter Terms Resolution Non linearity error Differential linearity error Total error : Analog variation that is recognized by an A/D converter. : Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” ) and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion characteristics. : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. : Difference between an actual value and a theoretical value. A total error includes zero transition error, full-scale transition error, and linear error. Total error 3FFH 3FEH 3FDH Actual conversion characteristics 1.5 LSB Digital output {1 LSB × (N − 1) + 0.5 LSB} 004H 003H 002H 001H 0.5 LSB AVSS VNT (Actual measurement value) Actual conversion characteristics Ideal characteristics AVRH Analog input Total error of digital output “N” = VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVRH − AVSS 1 LSB (Ideal value) = [V] 1024 [LSB] VOT (Ideal value) = AVSS + 0.5 LSB [V] VFST (Ideal value) = AVRH − 1.5 LSB [V] VNT : A voltage at which digital output transits from (N − 1) H, NH. (Continued) 69 MB90880 Series (Continued) Linearity error Differential linearity error Ideal characteristics (N + 1)H VFST (actual measurement value) VNT (actual measurement value) Actual conversion characteristics Actual conversion characteristics 3FFH 3FEH 3FDH Actual conversion characteristics {1 LSB × (N − 1) + VOT } Digital output Digital output NH 004H 003H 002H 001H AVSS (N − 1)H V (N + 1) T (actual measurement value) VNT (actual measurement value) Actual conversion characteristics AVRH Ideal characteristics VOT (actual measurement value) AVRH (N − 2)H AVSS Analog input Non linearity error of digital output N = Differential linearity error of digital output N = 1 LSB = Analog input VNT − {1 LSB × (N − 1) + VOT} 1 LSB V (N+1) T − VNT 1 LSB VFST − VOT 1022 −1 LSB [LSB] [V] [LSB] VOT : Voltage at which digital output transits from “000H” to “001H.” VFST : Voltage at which digital output transits from “3FEH” to “3FFH.” • Flash memory write/erase characteristics Parameter Sector erase time Chip erase time Byte (16-bit width) write time Number of write/erase cycles Flash memory data hold time ⎯ Average TA = +85 °C TA = +25 °C, VCC = 3.0 V Conditions Value Min ⎯ ⎯ ⎯ 10000 100000 Standard 0.9 6.2 23 ⎯ ⎯ Max 3.6 ⎯ ⎯ ⎯ ⎯ Unit s s µs cycle h * Remarks Excludes internal write time before erase operation. Excludes internal write time before erase operation. Excludes overhead time at system level. * : Value converted from the evaluation result of technology reliability (The Arrhenius equation is used to convert the high-temperature high-speed test result into the average temperature + 85 °C.) 70 MB90880 Series ■ ORDERING INFORMATION Part number MB90F882PF MB90F883PF MB90F883APF MB90F884PF MB90F884APF MB90882PF MB90883PF MB90884PF MB90F882SPF MB90F883SPF MB90F883ASPF MB90F884SPF MB90F884ASPF MB90882SPF MB90883SPF MB90884SPF MB90F882PMC MB90F883PMC MB90F883APMC MB90F884PMC MB90F884APMC MB90882PMC MB90883PMC MB90884PMC MB90F882SPMC MB90F883SPMC MB90F883ASPMC MB90F884SPMC MB90F884ASPMC MB90882SPMC MB90883SPMC MB90884SPMC MB90V880-101CR-ES MB90V880-102CR-ES MB90V880A-101CR-ES MB90V880A-102CR-ES Package Remarks 100-pin plastic QFP (FPT-100P-M06) With S : Single clock product (without sub clock) Without S : Dual clock product (with sub clock) 100-pin plastic LQFP (FPT-100P-M20) 299-pin ceramic PGA (PGA-299C-A01) Evaluation product 101 : Single clock product (without sub clock) 102 : Dual clock product (with sub clock) 71 MB90880 Series ■ PACKAGE DIMENSIONS 100-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight 0.50 mm 14.0 mm × 14.0 mm Gullwing Plastic mold 1.70 mm Max 0.65 g P-LFQFP100-14×14-0.50 (FPT-100P-M20) Code (Reference) 100-pin plastic LQFP (FPT-100P-M20) 16.00±0.20(.630±.008)SQ Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. * 14.00±0.10(.551±.004)SQ 75 51 76 50 0.08(.003) Details of "A" part INDEX 1.50 –0.10 .059 –.004 (Mounting height) 26 +0.20 +.008 100 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) 0˚~8˚ "A" (0.50(.020)) 0.60±0.15 (.024±.006) 1 25 0.50(.020) 0.20±0.05 (.008±.002) 0.08(.003) M 0.145±0.055 (.0057±.0022) C 2005 FUJITSU LIMITED F100031S-c-2-1 Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html (Continued) 72 MB90880 Series (Continued) 100-pin plastic QFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Code (Reference) 0.65 mm 14.00 × 20.00 mm Gullwing Plastic mold 3.35 mm MAX P-QFP100-14×20-0.65 (FPT-100P-M06) 100-pin plastic QFP (FPT-100P-M06) 23.90±0.40(.941±.016) * 20.00±0.20(.787±.008) 80 51 Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 81 50 0.10(.004) 17.90±0.40 (.705±.016) *14.00±0.20 (.551±.008) INDEX Details of "A" part 100 31 1 30 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8˚ 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off) 0.65(.026) 0.32±0.05 (.013±.002) 0.13(.005) M "A" C 2002 FUJITSU LIMITED F100008S-c-5-5 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 73 MB90880 Series ■ MAIN CHANGES IN THIS EDITION Page ⎯ 3 Section ⎯ ■ PRODUCT LINEUP Change Results Added the following part numbers: MB90F883A (S), MB90F884A (S) Added the following details to the CPU functions: “Maximum operating frequency is 25 MHz in MB90F883 (S) , MB90F884 (S)” Added the following details to the base timer: “In MB90F883(S) and MB90F884(S), P24/TIO0, P25/TIO1, P26/TIO2, and P27/TIO3 cannot be used as input function.” 4 21 43 46 ■ HANDLING DEVICES Added the "Flash memory" item Added "13. Note of MB90F883 (S), MB90F884 (S)" ■ ELECTRICAL CHARACTERISTICS Added the "Smoothing capacitor" item 2. Recommended operating conditions Added the "• C Pin Connection Diagram" ■ ELECTRICAL CHARACTERISTICS 3. DC characteristics Added the "ICTS" and "ICCLS" items to the supply current Changed supply current ratings: ICCS Internal 25 MHz operation; Typ 9 → 6, Max 16 → 12 ICCS Internal 33 MHz operation; Typ 12 → 10, Max 22 → 20 ICCL Typ 70 → 80 ICCT Typ 15 → 20 ICCH Typ 10 → 15 Added the following details to footnote 1 of the table: “The maximum operating frequency is 25 MHz in MB90F883(S) and MB90F884(S).” Added the following part numbers: MB90F883APF, MB90F884APF, MB90F883ASPF, MB90F884ASPF, MB90F883APMC, MB90F884APMC, MB90F883ASPMC, MB90F884ASPMC Added the following details to the remarks: With S : Single clock product (without sub clock) Without S : Dual clock product (with sub clock) Added the MB90V880 item The vertical lines marked in the left side of the page show the changes. 47 ■ELECTRICAL CHARACTERISTICS 4. AC characteristics (1) Clock timing ratings ■ ORDERING INFORMATION 71 74 MB90880 Series The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. 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Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept. F0702