FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13744-2E
16-bit Proprietary Microcontrollers
CMOS
F2MC-16LX MB90350E Series
MB90F351E (S) , MB90F351TE (S) , MB90F352E (S) , MB90F352TE (S) , MB90351E (S) , MB90351TE (S) , MB90352E (S) , MB90352TE (S) , MB90F356E (S) , MB90F356TE (S) , MB90F357E (S) , MB90F357TE (S) , MB90356E (S) , MB90356TE (S) , MB90357E (S) , MB90357TE(S) , MB90V340E-101/102/103/104
■ DESCRIPTION
The MB90350E series, loaded 1 channel FULL-CAN* interface and Flash ROM, is general-purpose FUJITSU 16-bit microcontroller designing for automotive and industrial applications. Its main feature is the on-board CAN interface, which conforms to CAN standard Version2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN approach. With the new 0.35 µm CMOS technology, Fujitsu now offers on-chip Flash ROM program memory up to 128 Kbytes. The power supply (3 V) is supplied to the MCU core from an internal regulator circuit. This creates a major advantage in terms of EMI and power consumption. The PLL clock multiplication circuit provides an internal 42 ns instruction execution time from an external 4 MHz clock. Also, the clock supervisor function can monitor main clock and sub clock independently. As the peripheral resources, the unit features a 4-channel Output Compare Unit, 6-channel Input Capture Unit, 2 separate 16-bit free-run timers, 2-channel UART and 15-channel 8/10-bit A/D converter built-in. * : Controller Area Network (CAN) - License of Robert Bosch GmbH Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Copyright©2006-2007 FUJITSU LIMITED All rights reserved
MB90350E Series
■ FEATURES
• Clock • Built-in PLL clock frequency multiplication circuit • Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz). • Operation by sub clock (up to 50 kHz : 100 kHz oscillation clock divided by two) is allowed (devices without S-suffix only) . • Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time multiplied PLL clock). • Built-in clock modulation circuit • 16 Mbytes CPU memory space 24-bit internal addressing • Instruction system best suited to controller • Wide choice of data types (bit, byte, word, and long word) • Wide choice of addressing modes (23 types) • Enhanced multiply-divide instructions with sign and RETI instructions • Clock supervisor (MB90x356x and MB90x357x only) • Main clock or sub clock is monitored independently. • Internal CR oscillation clock (100 kHz typical) can be used as sub clock. • Enhanced high-precision computing with 32-bit accumulator • Instruction system compatible with high-level language (C language) and multitask • Employing system stack pointer • Enhanced various pointer indirect instructions • Barrel shift instructions • Increased processing speed 4-byte instruction queue • Powerful interrupt function • Powerful 8-level, 34-condition interrupt feature • Up to 8 channels external interrupts are supported. • Automatic data transfer function independent of CPU • Extended intelligent I/O service function (EI2OS) : up to 16 channels • DMA : up to 16 channels • Low power consumption (standby) mode • Sleep mode (a mode that stops CPU operating clock) • Main timer mode (a timebase timer mode switched from the main clock mode) • PLL timer mode (a timebase timer mode switched from the PLL clock mode) • Watch mode (a mode that operates sub clock and watch timer only) • Stop mode (a mode that stops oscillation clock and sub clock) • CPU intermittent operation mode • Process CMOS technology • I/O port • General-purpose input/output port (CMOS output) - 49 ports (devices without S-suffix : devices that correspond to sub clock) - 51 ports (devices with S-suffix : devices that do not correspond to sub clock) (Continued) 2
MB90350E Series
• Sub clock pin (X0A, X1A) • Yes (using the external oscillation) : devices without S-suffix • No (using the sub clock mode at internal CR oscillation) : devices with S-suffix • Timer • Timebase timer, watch timer, watchdog timer : 1 channel • 8/16-bit PPG timer : 8-bit × 10 channels or 16-bit × 6 channels • 16-bit reload timer : 2 channels (only Evaluation products has 4 channels) • 16- bit input/output timer - 16-bit free-run timer : 2 channels (FRT0 : ICU0/1, FRT1 : ICU4/5/6/7, OCU4/5/6/7) - 16- bit input capture: (ICU) : 6 channels - 16-bit output compare : (OCU) : 4 channels • FULL-CAN interface : 1 channel • Compliant with CAN standard Version2.0 Part A and Part B • 16 message buffers are built-in • CAN wake-up function • UART (LIN/SCI) : 2 channels • Equipped with full-duplex double buffer • Clock-asynchronous or clock-synchronous serial transmission is available. • I2C interface*1 : 1 channel Up to 400 kbps transfer rate • DTP/External interrupt : 8 channels, CAN wakeup : 1 channel Module for activation of extended intelligent I/O service (EI2OS), DMA, and generation of external interrupt by external input. • Delay interrupt generator module Generates interrupt request for task switching. • 8/10-bit A/D converter : 15 channels • Resolution is selectable between 8-bit and 10-bit. • Activation by external trigger input is allowed. • Conversion time : 3 µs (at 24-MHz machine clock, including sampling time) • Program patch function • Address matching detection for 6 address pointers. • Capable of changing input voltage level for port • Automotive/CMOS-Schmitt (initial level is Automotive in single chip mode) • TTL level (corresponds to external bus pins only, initial level of these pins is TTL in external bus mode) • Low voltage/CPU operation detection reset (devices with T-suffix) • Detects low voltage (4.0 V ± 0.3 V) and resets automatically • Resets automatically when program is runaway and counter is not cleared within interval time (approx. 262 ms : external 4 MHz) • Dual operation Flash memory • Erase/write and read can be executed in the different bank (Upper Bank/Lower Bank) at the same time. • Supported TA = + 125 °C The maximum operating frequency is 24 MHz*2 : (at TA = +125 °C) . (Continued)
3
MB90350E Series
(Continued) • Flash security function • Protects the content of Flash memory (MB90F352x, MB90F357x only) • External bus interface • 4 Mbytes external memory space MB90F351E(S), MB90F351TE(S), MB90F352E(S), MB90F352TE(S) : External bus Interface can not be used in internal vector mode. It can be used only in external vector mode. *1 : I2C license : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. *2 : If used exceeding TA = + 105 °C, be sure to contact Fujitsu for reliability limitations.
4
MB90350E Series
■ PRODUCT LINEUP1 (Without Clock supervisor function)
• Flash memory products Part Number Parameter Type CPU System clock ROM RAM Emulator-specific power supply*1 Sub clock pin (X0A, X1A) (Max 100 kHz) Clock supervisor Low voltage/CPU operation detection reset Operating voltage Operating temperature Package No Yes Yes No No Yes
MB90F351E, MB90F352E MB90F351TE, MB90F352TE MB90F351ES, MB90F352ES MB90F351TES, MB90F352TES
Flash memory products F2MC-16LX CPU PLL clock multiplication circuit (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops) Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6) 64 Kbytes Flash memory : MB90F351E(S), MB90F351TE(S) 128 Kbytes Dual operation Flash memory (Erase/write and read can be operated at the same time) : MB90F352E(S), MB90F352TE(S) 4 Kbytes ⎯ No
3.5 V to 5.5 V : at normal operating (not using A/D converter) 4.0 V to 5.5 V : at using A/D converter/Flash programming 4.5 V to 5.5 V : at using external bus −40 °C to +125 °C LQFP-64 2 channels Wide range of baud rate settings using a dedicated reload timer Special synchronous options for adapting to different synchronous serial protocols LIN functionality working either as master or slave LIN device 1 channel 15 channels 10-bit or 8-bit resolution Conversion time : Min 3 µs includes sample time (per one channel) Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency) Supports External Event Count function. I/O Timer 0 (clock input FRCK0) corresponds to ICU0/1. I/O Timer 1 (clock input FRCK1) corresponds to ICU4/5/6/7, OCU4/5/6/7.
UART
I2C (400 kbps) A/D converter 16-bit reload timer (2 channels)
16-bit I/O timer (2 channels)
Signals an interrupt when overflowing. Supports Timer Clear when it matches Output Compare (ch.0, ch.4) . Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27 (fsys = Machine clock frequency) 4 channels Signals an interrupt when 16-bit I/O Timer matches with output compare registers. A pair of compare registers can be used to generate an output signal. (Continued) 5
16-bit output compare
MB90350E Series
(Continued) Part Number Parameter 16-bit Input capture
MB90F351E, MB90F352E
MB90F351TE, MB90F352TE
MB90F351ES, MB90F352ES
MB90F351TES, MB90F352TES
6 channels Retains free-run timer value by (rising edge, falling edge or rising & falling edge) , signals an interrupt. 6 channels (16-bit)/10 channels (8-bit) 8-bit reload counters × 12 8-bit reload registers for L pulse width × 12 8-bit reload registers for H pulse width × 12
8/16-bit programmable pulse Supports 8-bit and 16-bit operation modes. generator A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler + 8-bit reload counter. Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz (fsys = Machine clock frequency, fosc = Oscillation clock frequency) 1 channel Compliant with CAN standard Version2.0 Part A and Part B. Automatic re-transmission in case of error Automatic transmission responding to Remote Frame 16 prioritized message buffers for data and ID Supports multiple messages. Flexible configuration of acceptance filtering : Full bit compare/Full bit mask/Two partial bit masks Supports up to 1 Mbps. 8 channels External interrupt D/A converter Can be used rising edge, falling edge, starting up by “H”/“L” level input, external interrupt, extended intelligent I/O services (EI2OS) and DMA. ⎯ Virtually all external pins can be used as general purpose I/O port. All push-pull outputs Bit-wise settable as input/output or peripheral signal Settable as CMOS schmitt trigger/ automotive inputs TTL input level settable for external bus (only for external bus pin) Supports automatic programming, Embedded AlgorithmTM*2 Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of erase cycles : 10000 times Data retention time : 20 years Boot block configuration Erase can be performed on each block. Block protection with external programming voltage Flash Security Feature for protecting the content of the Flash (MB90F352E(S) and MB90F352TE(S) only) MB90V340E-102 MB90V340E-101
CAN interface
I/O ports
Flash memory
Corresponding evaluation name
*1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the Emulator hardware manual about details. *2 : Embedded Algorithm is a trademark of Advanced Micro Devices Inc. 6
MB90350E Series
• MASK ROM products/Evaluation products Part Number Parameter Type CPU System clock ROM RAM Emulator-specific power supply* Sub clock pin (X0A, X1A) (Max 100 kHz) Clock supervisor Low voltage/CPU operation detection reset Operating voltage range Operating temperature range Package No Yes No Yes
MB90351E, MB90352E
MB90351TE, MB90352TE
MB90351ES, MB90352ES
MB90351TES, MB90352TES
MB90V340E101
MB90V340E102
MASK ROM products F2MC-16LX CPU
Evaluation products
PLL clock multiplication circuit (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops) Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6) MASK ROM 64 Kbytes : MB90351E(S), MB90351TE(S) 128 Kbytes : MB90352E(S), MB90352TE(S) 4 Kbytes ⎯ No No Yes No No External 30 Kbytes Yes Yes
3.5 V to 5.5 V : at normal operating (not using A/D converter) 4.0 V to 5.5 V : at using A/D converter 4.5 V to 5.5 V : at using external bus −40 °C to +125 °C LQFP-64 2 channels
5 V ± 10% ⎯ PGA-299 5 channels
UART
Wide range of baud rate settings using a dedicated reload timer Special synchronous options for adapting to different synchronous serial protocols LIN functionality working either as master or slave LIN device 1 channel 15 channels 10-bit or 8-bit resolution Conversion time : Min 3 µs includes sample time (per one channel) 2 channels 4 channels Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency) Supports External Event Count function. I/O Timer 0 (clock input FRCK0) corresponds to ICU0/1. I/O Timer 1 (clock input FRCK1) corresponds to ICU4/5/6/7, OCU4/5/6/7. I/O Timer 0 corresponds to ICU0/1/2/3, OCU0/1/2/3. I/O Timer 1 corresponds to ICU4/5/6/7, OCU4/5/6/7. 2 channels 24 channels
I2C (400 kbps) A/D converter
16-bit reload timer
16-bit I/O timer (2 channels)
Signals an interrupt when overflowing. Supports Timer Clear when it matches Output Compare (ch.0, ch.4) . Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27 (fsys = Machine clock frequency) (Continued) 7
MB90350E Series
(Continued) Part Number Parameter 16-bit output compare
MB90351E, MB90352E
MB90351TE, MB90352TE
MB90351ES, MB90352ES
MB90351TES, MB90352TES
MB90V340E101
MB90V340E102
4 channels
8 channels
Signals an interrupt when 16-bit I/O Timer matches output compare registers. A pair of compare registers can be used to generate an output signal. 6 channels 8 channels Retains free-run timer value by (rising edge, falling edge, or the both edges), signals an interrupt. 8 channels (16-bit)/ 16 channels (8-bit) 8-bit reload counters × 16 8-bit reload registers for L pulse width × 16 8-bit reload registers for H pulse width × 16
16-bit input capture
8/16-bit programmable pulse generator
6 channels (16-bit)/10 channels (8-bit) 8-bit reload counters × 12 8-bit reload registers for L pulse width × 12 8-bit reload registers for H pulse width × 12
Supports 8-bit and 16-bit operation modes. A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler + 8-bit reload counter. Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz (fsys = Machine clock frequency, fosc = Oscillation clock frequency) 1 channel Compliant with CAN standard Version 2.0 Part A and Part B. Automatic re-transmission in case of error Automatic transmission responding to Remote Frame 16 prioritized message buffers for data and ID Supports multiple messages. Flexible configuration of acceptance filtering : Full bit compare/Full bit mask/Two partial bit masks Supports up to 1 Mbps. 8 channels 16 channels Can be used rising edge, falling edge, starting up by “H”/“L” level input, external interrupt, extended intelligent I/O services (EI2OS) and DMA. ⎯ Virtually all external pins can be used as general purpose I/O port. All push-pull outputs Bit-wise settable as input/output or peripheral signal Settable as CMOS schmitt trigger/ automotive inputs TTL input level settable for external bus (only for external bus pin) ⎯ MB90V340E-102 MB90V340E-101 ⎯ 2 channels 3 channels
CAN interface
External interrupt D/A converter
I/O ports
Flash memory Corresponding evaluation name
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the Emulator hardware manual about details.
8
MB90350E Series
■ PRODUCT LINEUP 2 (With Clock supervisor function)
• Flash memory products Part Number Parameter Type CPU System clock ROM RAM Emulator-specific power supply*1 Sub clock pin (X0A, X1A) Clock supervisor Low voltage/CPU operation detection reset Operating voltage range Operating temperature range Package No Yes Yes Yes No Yes
MB90F356E, MB90F357E MB90F356TE, MB90F357TE MB90F356ES, MB90F357ES MB90F356TES, MB90F357TES
Flash memory products F2MC-16LX CPU On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops) Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6) Dual operation flash memory 64 Kbytes : MB90F356E(S), MB90F356TE(S) 128 Kbytes : MB90F357E(S), MB90F357TE(S) 4 Kbytes ⎯ No (internal CR oscillation can be used as sub clock)
3.5 V to 5.5 V : at normal operating (not using A/D converter) 3.5 V to 5.5 V : at using A/D converter/Flash programming 3.5 V to 5.5 V : at using external bus −40 °C to +125 °C LQFP-64 2 channels Wide range of baud rate settings using a dedicated reload timer Special synchronous options for adapting to different synchronous serial protocols LIN functionality working either as master or slave LIN device 1 channel 15 channels 10-bit or 8-bit resolution Conversion time : Min 3 µs includes sample time (per one channel) Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency) Supports External Event Count function. I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1. I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7.
UART
I2C (400 kbps) A/D Converter 16-bit Reload Timer (4 channels)
16-bit I/O Timer (2 channels)
Signals an interrupt when overflowing. Supports Timer Clear when a match with Output Compare (Channel 0, 4) . Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27 (fsys = Machine clock frequency) 4 channels Signals an interrupt when 16-bit I/O Timer matches with output compare registers. A pair of compare registers can be used to generate an output signal. (Continued) 9
16-bit Output Compare
MB90350E Series
(Continued) Part Number Parameter 16-bit Input Capture
MB90F356E, MB90F357E
MB90F356TE, MB90F357TE
MB90F356ES, MB90F357ES
MB90F356TES, MB90F357TES
6 channels Retains free-run timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt. 6 channels (16-bit)/10 channels (8-bit) 8-bit reload counters × 12 8-bit reload registers for L pulse width × 12 8-bit reload registers for H pulse width × 12
8/16-bit Programmable Pulse Supports 8-bit and 16-bit operation modes. Generator A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler + 8-bit reload counter. Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz (fsys = Machine clock frequency, fosc = Oscillation clock frequency) 1 channel Conforms to CAN Specification Version 2.0 Part A and B. Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 message buffers for data and ID Supports multiple messages. Flexible configuration of acceptance filtering : Full bit compare/Full bit mask/Two partial bit masks Supports up to 1 Mbps. 8 channels External Interrupt D/A converter Can be used rising edge, falling edge, starting up by H/L level input, external interrupt, extended intelligent I/O services (EI2OS) and DMA. ⎯ Virtually all external pins can be used as general purpose I/O port. All push-pull outputs Bit-wise settable as input/output or peripheral module signal Settable as CMOS schmitt trigger/ automotive inputs TTL input level settable for external bus (only for external bus pin) Supports automatic programming, Embedded AlgorithmTM*2 Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of erase cycles : 10000 times Data retention time : 10 years Boot block configuration Erase can be performed on each block. Block protection with external programming voltage Flash Security Feature for protecting the content of the Flash (MB90F357x only) MB90V340E-104 MB90V340E-103
CAN Interface
I/O Ports
Flash Memory
Corresponding EVA name
*1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the Emulator hardware manual about details. *2 : Embedded Algorithm is a trademark of Advanced Micro Devices Inc. 10
MB90350E Series
• MASK ROM products/Evaluation products Part Number Parameter CPU System clock ROM RAM Emulator-specific power supply* Sub clock pin (X0A, X1A) Clock supervisor Low voltage/CPU operation detection reset Operating voltage range Operating temperature range Package No Yes No
MB90356E, MB90357E
MB90356TE, MB90357TE
MB90356ES, MB90357ES
MB90356TES, MB90357TES
MB90V340E103
MB90V340E104
F2MC-16LX CPU On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops) Minimum instruction execution time : 42 ns (oscillation clock 4 MHz, PLL × 6) MASK ROM 64 Kbytes :MB90356E(S), MB90356TE(S) 128 Kbytes :MB90357E(S), MB90357TE(S) 4 Kbytes ⎯ No (internal CR oscillation can be used as sub clock) Yes Yes No External 30 Kbytes Yes No (internal CR oscillation can be used as sub clock)
Yes
Yes
3.5 V to 5.5 V : at normal operating (not using A/D converter) 4.0 V to 5.5 V : at using A/D converter 4.5 V to 5.5 V : at using external bus −40 °C to +125 °C LQFP-64 2 channels
5 V ± 10% ⎯ PGA-299 5 channels
UART
Wide range of baud rate settings using a dedicated reload timer Special synchronous options for adapting to different synchronous serial protocols LIN functionality working either as master or slave LIN device 1 channel 15 channels 10-bit or 8-bit resolution Conversion time : Min 3 µs includes sample time (per one channel) Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = Machine clock frequency) Supports External Event Count function. I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1. I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7. I/O Timer 0 corresponds to ICU 0/1/2/3, OCU 0/1/2/3. I/O Timer 1 corresponds to ICU 4/5/6/7, OCU 4/5/6/7. 2 channels 24 channels
I2C (400 kbps) A/D Converter 16-bit Reload Timer (4 channels)
16-bit I/O Timer (2 channels)
Signals an interrupt when overflowing. Supports Timer Clear when a match with Output Compare (Channel 0, 4) . Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27 (fsys = Machine clock frequency) (Continued)
11
MB90350E Series
(Continued) Part Number Parameter 16-bit Output Compare
MB90356E, MB90357E
MB90356TE, MB90357TE
MB90356ES, MB90357ES
MB90356TES, MB90357TES
MB90V340E103
MB90V340E104
4 channels
8 channels
Signals an interrupt when 16-bit I/O Timer matches with output compare registers. A pair of compare registers can be used to generate an output signal. 6 channels 8 channels Retains free-run timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt. 8 channels (16-bit)/ 16 channels (8-bit) 8-bit reload counters × 16 8-bit reload registers for L pulse width × 16 8-bit reload registers for H pulse width × 16
16-bit Input Capture
8/16-bit Programmable Pulse Generator
6 channels (16-bit)/10 channels (8-bit) 8-bit reload counters × 12 8-bit reload registers for L pulse width × 12 8-bit reload registers for H pulse width × 12
Supports 8-bit and 16-bit operation modes. A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler + 8-bit reload counter. Operation clock frequency : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz (fsys = Machine clock frequency, fosc = Oscillation clock frequency) 1 channel Conforms to CAN Specification Version 2.0 Part A and B. Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 message buffers for data and ID Supports multiple messages. Flexible configuration of acceptance filtering : Full bit compare/Full bit mask/Two partial bit masks Supports up to 1 Mbps. 8 channels 16 channels Can be used rising edge, falling edge, starting up by H/L level input, external interrupt, extended intelligent I/O services (EI2OS) and DMA. ⎯ Virtually all external pins can be used as general purpose I/O port. All push-pull outputs Bit-wise settable as input/output or peripheral module signal Settable as CMOS schmitt trigger/ automotive inputs TTL input level settable for external bus (only for external bus pin) ⎯ MB90V340E-104 MB90V340E-103 ⎯ 2 channels 3 channels
CAN Interface
External Interrupt D/A converter
I/O Ports
Flash Memory Corresponding EVA name *:
It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the Emulator hardware manual about details.
12
MB90350E Series
■ PACKAGES AND PRODUCT CORRESPONDENCE
MB90F351E (S) , MB90F351TE (S) MB90F352E (S) , MB90F352TE (S) MB90F356E (S) , MB90F356TE (S) MB90F357E (S) , MB90F357TE (S) MB90351E (S) , MB90351TE (S) MB90352E (S) , MB90352TE (S) MB90356E (S) , MB90356TE (S) MB90357E (S) , MB90357TE (S) × × ×
Package
MB90V340E-101, MB90V340E-102, MB90V340E-103, MB90V340E-104
PGA-299C-A01 FPT-64P-M23 (12.0 mm , 0.65 mm pitch) FPT-64P-M24 (10.0 mm , 0.50 mm pitch) : Yes, × : No Note : Refer to “■ PACKAGE DIMENSIONS” for detail of each package.
13
MB90350E Series
■ PIN ASSIGNMENTS
• MB90F351E(S), MB90F351TE(S), MB90F352E(S), MB90F352TE(S),MB90F356E(S), MB90F356TE(S), MB90F357E(S), MB90F357TE(S), MB90351E(S), MB90351TE(S), MB90352E(S), MB90352TE(S), MB90356E(S), MB90356TE(S), MB90357E(S), MB90357TE(S) (TOP VIEW)
P14/AD12/SCK3
P12/AD10/SIN3/INT11R
P22/A18/PPGD(C)
P21/A17/PPGB(A)
P23/A19/PPGF(E)
P20/A16/PPG9(8)
P13/AD11/SOT3
P16/AD14
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Vcc C P25/A21/IN1/ADTG P44/SDA0/FRCK0 P45/SCL0/FRCK1 P30/ALE/IN4 P31/RD/IN5 P32/WRL/WR/INT10R P33/WRH P34/HRQ/OUT4 P35/HAK/OUT5 P36/RDY/OUT6 P37/CLK/OUT7 P60/AN0 P61/AN1 AVcc
P15/AD13
P11/AD09/TOT1
P24/A20/IN0
P17/AD15
RST
Vss
X0
X1
49 50 51 52 53 54 55
56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
P65/AN5/PPGA(B) P67/AN7/PPGE(F) P66/AN6/PPGC(D) P62/AN2/PPG4(5) P63/AN3/PPG6(7) P64/AN4/PPG8(9) P52/AN10/SCK2 AVRH P50/AN8/SIN2 P42/IN6/RX1/INT9R
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
P10/AD08/TIN1 P07/AD07/INT15 P06/AD06/INT14 P05/AD05/INT13 P04/AD04/INT12 P03/AD03/INT11 P02/AD02/INT10 P01/AD01/INT9 P00/AD00/INT8 MD0 MD1 MD2 P41/X1A* P40/X0A* Vss P43/IN7/TX1
P53/AN11/TIN3
P54/AN12/TOT3
P55/AN13
(FPT-64P-M23, FPT-64P-M24) * : Devices without S-suffix : X0A, X1A Devices with S-suffix : P40, P41
14
P51/AN9/SOT2
P56/AN14
AVss
MB90350E Series
■ PIN DESCRIPTION
Pin No. 46 47 45 Pin name X1 X0 RST P62 to P67 AN2 to AN7 3 to 8 PPG4 (5) , 6 (7) , 8 (9) , A (B) , C (D) , E (F) P50 9 AN8 SIN2 P51 10 AN9 SOT2 P52 11 AN10 SCK2 P53 12 AN11 TIN3 P54 13 AN12 TOT3 14, 15 P55, P56 AN13, AN14 P42 16 IN6 RX1 INT9R P43 17 IN7 TX1 P40, P41 19, 20 X0A, X1A B F F F I I I I I O I Output pins for PPGs General purpose I/O port Analog input pin for A/D converter Serial data input pin for UART2 General purpose I/O port Analog input pin for A/D converter Serial data output pin for UART2 General purpose I/O port Analog input pin for A/D converter Serial clock I/O pin for UART2 General purpose I/O port Analog input pin for A/D converter Event input pin for reload timer3 General purpose I/O port Analog input pin for A/D converter Output pin for reload timer3 General purpose I/O ports Analog input pins for A/D converter General purpose I/O port Data sample input pin for input capture ICU6 RX input pin for CAN1 External interrupt request input pin for INT9 General purpose I/O port Data sample input pin for input capture ICU7 TX output pin for CAN1 General purpose I/O ports (devices with S-suffix and MB90V340E-101/103) X0A : Oscillation input pins for sub clock X1A : Oscillation output pins for sub clock (devices without S-suffix and MB90V340E-102/104) (Continued) 15 I/O Circuit type* A E Oscillation output pin Oscillation input pin Reset input pin General purpose I/O ports Analog input pins for A/D converter Function
MB90350E Series
Pin No.
Pin name P00 to P07
I/O Circuit type*
Function General purpose I/O ports. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode.
24 to 31
AD00 to AD07 INT8 to INT15 P10
G
Input/output pins of external address data bus lower 8 bits. This function is enabled when the external bus is enabled. External interrupt request input pins for INT8 to INT15 General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode.
32
AD08 TIN1 P11
G
Input/output pin for external bus address data bus bit 8. This function is enabled when external bus is enabled. Event input pin for reload timer1 General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode.
33
AD09 TOT1 P12
G
Input/output pin for external bus address data bus bit 9. This function is enabled when external bus is enabled. Output pin for reload timer1 General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode.
34
AD10 SIN3 INT11R P13
N
Input/output pin for external bus address data bus bit 10. This function is enabled when external bus is enabled. Serial data input pin for UART3 External interrupt request input pin for INT11 General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode.
35
AD11 SOT3 P14
G
Input/output pin for external bus address data bus bit 11. This function is enabled when external bus is enabled. Serial data output pin for UART3 General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode.
36
AD12 SCK3 P15
G
Input/output pin for external bus address data bus bit 12. This function is enabled when external bus is enabled. Clock input/output pin for UART3 General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. Input/output pin for external bus address data bus bit 13. This function is enabled when external bus is enabled. General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. Input/output pin for external bus address data bus bit 14. This function is enabled when external bus is enabled. (Continued)
37 AD13 P16 38 AD14
N
G
16
MB90350E Series
Pin No.
Pin name P17
I/O Circuit type*
Function General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. Input/output pin for external bus address data bus bit 15. This function is enabled when external bus is enabled. General purpose I/O ports. The register can be set to select whether to use a pull-up resistor. In external bus mode, the pins are enabled as a generalpurpose I/O port when the corresponding bit in the external address output control register (HACR) is 1.
39 AD15
G
P20 to P23
40 to 43
A16 to A19 PPG9 (8) , PPGB (A) , PPGD (C) , PPGF (E)
G
Output pins for A16 to A19 of the external address data bus. When the corresponding bit in the external address output control register (HACR) is 0, the pins are enabled as high address output pins A16 to A19.
Output pins for PPGs
P24 44 A20 IN0 G
General purpose I/O port. The register can be set to select whether to use a pull-up resistor. In external bus mode, the pin is enabled as a generalpurpose I/O port when the corresponding bit in the external address output control register (HACR) is 1. Output pin for A20 of the external address data bus. When the corresponding bit in the external address output control register (HACR) is 0, the pin is enabled as high address output pin A20. Data sample input pin for input capture ICU0 General purpose I/O port. The register can be set to select whether to use a pull-up resistor. In external bus mode, the pin is enabled as a generalpurpose I/O port when the corresponding bit in the external address output control register (HACR) is 1. G Output pin for A21 of the external address data bus. When the corresponding bit in the external address output control register (HACR) is 0, the pin is enabled as high address output pin A21. Data sample input pin for input capture ICU1 Trigger input pin for A/D converter General purpose I/O port H Serial data I/O pin for I2C 0 Input pin for the 16-bit I/O Timer 0 General purpose I/O port H Serial clock I/O pin for I2C 0 Input pin for the 16-bit I/O Timer 1 (Continued)
P25
51 A21 IN1 ADTG P44 52 SDA0 FRCK0 P45 53 SCL0 FRCK1
17
MB90350E Series
Pin No.
Pin name P30
I/O Circuit type*
Function General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode.
54
ALE IN4 P31
G
Address latch enable output pin. This function is enabled when external bus is enabled. Data sample input pin for input capture ICU4 General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode.
55
RD IN5 P32
G
Read strobe output pin for data bus. This function is enabled when external bus is enabled. Data sample input pin for input capture ICU5 General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the WR/WRL pin output disabled.
56 WR/WRL INT10R P33 57 WRH
G
Write strobe output pin for the data bus. This function is enabled when both the external bus and the WR/WRL pin output are enabled. WRL is used to write-strobe 8 lower bits of the data bus in 16-bit access. WR is used to write-strobe 8 bits of the data bus in 8-bit access. External interrupt request input pin for INT10 General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode, in external bus 8-bit mode or with the WRH pin output disabled. Write strobe output pin for the 8 higher bits of the data bus. This function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the WRH output pin is enabled. General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the hold function disabled.
G
P34 58 HRQ OUT4 P35 59 HAK OUT5 P36 60 RDY OUT6 G G G
Hold request input pin. This function is enabled when both the external bus and the hold function are enabled. Wave form output pin for output compare OCU4 General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the hold function disabled. Hold acknowledge output pin. This function is enabled when both the external bus and the hold function are enabled. Wave form output pin for output compare OCU5 General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the external ready function disabled. Ready input pin. This function is enabled when both the external bus and the external ready function are enabled. Wave form output pin for output compare OCU6 (Continued)
18
MB90350E Series
(Continued) Pin No. Pin name I/O Circuit type* Function General purpose I/O port. The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or with the CLK output disabled. G CLK OUT7 62, 63 64 2 1 22, 23 21 49 18, 48 50 P60, P61 AN0, AN1 AVCC AVRH AVSS MD1, MD0 MD2 VCC VSS C I K L K C D ⎯ ⎯ K CLK output pin. This function is enabled when both the external bus and CLK output are enabled. Wave form output pin for output compare OCU7 General purpose I/O ports Analog input pins for A/D converter VCC power input pin for analog circuits Reference voltage input for the A/D converter. This power supply must be turned on or off while a voltage higher than or equal to AVRH is applied to AVCC. VSS power input pin for analog circuits Input pins for specifying the operating mode Input pin for specifying the operating mode Power (3.5 V to 5.5 V) input pin Power (0 V) input pins This is the power supply stabilization capacitor pin. It should be connected to a higher than or equal to 0.1 µF ceramic capacitor.
P37 61
* : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
19
MB90350E Series
■ I/O CIRCUIT TYPE
Type Circuit Remarks Oscillation circuit High-speed oscillation feedback resistor = approx. 1 MΩ
X1
Xout
A
X0
Standby control signal
X1A
Xout
Oscillation circuit Low-speed oscillation feedback resistor = approx. 10 MΩ
B
X0A
Standby control signal
R
C
CMOS hysteresis inputs
• MASK ROM device CMOS hysteresis input pin • Flash memory device CMOS input pin • MASK ROM device CMOS hysteresis input pin Pull-down resistor value: approx. 50 kΩ • Flash memory device CMOS input pin No Pull-down
R
D
CMOS hysteresis inputs
Pull-down resistor
CMOS hysteresis input pin Pull-up resistor value: approx. 50 kΩ E
Pull-up resistor R CMOS hysteresis inputs
(Continued)
20
MB90350E Series
Type
P-ch
Circuit
Remarks • CMOS level output (IOL = 4 mA, IOH = −4 mA) • CMOS hysteresis inputs (With input shutdown function when is standby) • Automotive input (With the standby-time input shutdown function)
Pout N-ch Nout
F
R CMOS hysteresis inputs Automotive inputs Standby control for input shutdown Pull-up control Pull-up resistor P-ch P-ch Pout N-ch Nout
G
R CMOS hysteresis inputs Automotive inputs
• CMOS level output (IOL = 4 mA, IOH = −4 mA) • CMOS hysteresis inputs (With the standby-time input shutdown function) • Automotive input (With the standby-time input shutdown function) • TTL input (With the standby-time input shutdown function) • Programmable pull-up resistor: approx. 50 kΩ
TTL input Standby control for input shutdown
P-ch Pout N-ch Nout
H
• CMOS level output (IOL = 3 mA, IOH = −3 mA) • CMOS hysteresis inputs (With the standby-time input shutdown function) • Automotive input (With the standby-time input shutdown function)
R CMOS hysteresis inputs Automotive inputs Standby control for input shutdown
(Continued)
21
MB90350E Series
Type
P-ch
Circuit
Remarks • CMOS level output (IOL = 4 mA, IOH = −4 mA) • CMOS hysteresis inputs (With the standby-time input shutdown function) • Automotive input (With the standby-time input shutdown function) • Analog input for A/D converter
Pout N-ch Nout R
I
CMOS hysteresis inputs Automotive inputs Standby control for input shutdown Analog input
Protection circuit for power supply input
K
P-ch N-ch
ANE
L
P-ch N-ch
AVR ANE
• With the protection circuit of A/D converter reference voltage power input pin • Flash memory devices do not have a protection circuit against VCC for pin AVRH. (Continued)
22
MB90350E Series
(Continued) Type
Circuit
Pull-up control
Remarks • CMOS level output (IOL = 4 mA, IOH = −4 mA) • CMOS inputs (With the standby-time input shutdown function) • Automotive input (With the standby-time input shutdown function) • TTL input (With the standby-time input shutdown function) • Programmable pull-up resistor: approx. 50 kΩ
Pull-up resistor
P-ch
P-ch Pout N-ch Nout
N
R CMOS inputs
Automotive inputs
TTL input Standby control for input shutdown
P-ch Pout N-ch Nout R
O
• CMOS level output (IOL = 4 mA, IOH = −4 mA) • CMOS inputs (With the standby-time input shutdown function) • Automotive input (With the standby-time input shutdown function) • Analog input for A/D converter
CMOS inputs
Automotive inputs Standby control for input shutdown Analog input
23
MB90350E Series
■ HANDLING DEVICES
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions : • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between VCC and VSS pins. • The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage (VCC) .
2. Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 kΩ. Unused I/O pins should be set to the output state and can be left open, or the input state with the above described connection.
3. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open. MB90350E Series X0 Open X1
4. Precautions for when not using a sub clock signal
X0A and X1A are oscillation pins for sub clock. If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the X1A pin open.
5. Notes on during operation of PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
24
MB90350E Series
6. Treatment of Power Supply Pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected inside of the device to prevent malfunction such as latch-up. To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally. Connect VCC and VSS pins to the device from the current supply source at a possibly low impedance. • As a measure against power supply noise, it is recommended to connect a capacitor of about 0.1 µF as a bypass capacitor between VCC and VSS pins in the vicinity of VCC and VSS pins of the device.
Vcc Vss
Vcc Vss Vcc
Vss
MB90350E Series
Vcc Vss
Vss
Vcc
7. Pull-up/down resistors
The MB90350E series does not support internal pull-up/down resistors (Port 0 to Port 3: built-in pull-up resistors). Use external components where needed.
8. Crystal oscillator circuit
Noise around the X0/X1, or X0A/X1A pins may cause this device to operate abnormally. In the interest of stable operation it is strongly recommended that printed circuit artwork places ground bypass capacitors as close as possible to the X0/X1, X0A/X1A and crystal oscillator (or ceramic oscillator) and that oscillator lines do not cross the lines of other circuits. Please ask each crystal maker to evaluate the oscillational characteristics of the crystal and this device.
9. Turning-on sequence of power supply to A/D converter and analog inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH) and analog inputs (AN0 to AN14) after turning-on the digital power supply (VCC) .Turn-off the digital power after turning off the A/D converter power supply and analog inputs. In this case, make sure that the voltage does not exceed AVRH or AVCC (turning on/ off the analog and digital power supplies simultaneously is acceptable).
10. Connection of unused pins of A/D converter if A/D converter is not used
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS.
11. Notes on energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 µs or more (0.2 V to 2.7 V) .
25
MB90350E Series
12. Stabilization of power supply voltage
A sudden change in the power supply voltage may cause the device to malfunction even within the specified power supply voltage VCC operating range. Therefore, the power supply voltage VCC should be stabilized. For reference, the power supply voltage should be controlled so that VCC ripple variations (peak-to-peak value) at commercial frequencies (50 Hz/60 Hz) fall below 10% of the standard power supply voltage VCC and the coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
13. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers, turn on the power again.
14. Port 0 to port 3 output during power-on (External-bus mode)
As shown below, when power is turned on in external-bus mode, there is a possibility that output signal of Port 0 to Port 3 might be unstable regardless of reset inputs.
1/2 VCC VCC
Port 0 to Port 3
Port 0 to Port 3 outputs Port 0 to Port 3 outputs = Hi-Z might be unstable.
15. Setting using CAN function
To use CAN function, please set “1” to DIRECT bit of CAN direct mode register (CDMR). If DIRECT bit is set to “0” (initial value), wait states will be performed when accessing CAN registers. Note : Please refer to section “23.12 CAN Direct Mode Register” in Hardware Manual of MB90350E series for detail of CAN direct mode register.
16. Flash security function
The security byte is located in the area of the Flash memory. If protection code 01H is written in the security byte, the Flash memory is in the protected state by security. Therefore please do not write 01H in this address if you do not use the security function. Please refer to following table for the address of the security byte. Product name MB90F352E(S) MB90F352TE(S) MB90F357E(S) MB90F357TE(S) Flash memory size Address for security bit
Embedded 1 Mbit Flash memory
FE0001H
17. Operation with TA = +105 °C or more
If used exceeding TA = +105 °C, please contact Fujitsu sales representatives for reliability limitations.
26
MB90350E Series
18. Low voltage/CPU operation reset circuit
The low voltage detection reset circuit is a function that monitors power supply voltage in order to detect when a voltage drops below a given voltage level. When a low voltage condition is detected, an internal reset signal is generated. The CPU operation detection reset circuit is a 20-bit counter that uses oscillation as a count clock and generates an internal reset signal if not cleared within a given time after startup. (1) Low voltage detection reset circuit Detection voltage 4.0 V ± 0.3 V When a low voltage condition is detected, the low voltage detection flag (LVRC : LVRF) is set to “1” and an internal reset signal is output. Because the low voltage detection reset circuit continues to operate even in stop mode, detection of a low voltage condition generates an internal reset and releases stop mode. During an internal RAM write cycle, low voltage reset is generated after the completion of writing. During the output of this internal reset, the reset output from the low voltage detection reset circuit is suppressed. (2) CPU operation detection reset circuit The CPU operation detection reset circuit is a counter that prevents program runaway. The counter starts automatically after a power-on reset, and must be continually and regularly cleared within a given time. If the given time interval elapses and the counter has not been cleared, a cause such as infinite program looping is assumed and an internal reset signal is generated. The internal reset generated from the CPU operation detection circuit has a width of 5 machine cycles. Interval time 220/FC (approx. 262 ms*) * : This value assumes the interval time at an oscillation clock frequency of 4 MHz. During recovery from standby mode, the detection period is the maximum interval plus 20 µs. This circuit does not operate in modes where CPU operation is stopped. The CPU operation detection reset circuit counter is cleared under any of the following conditions. • “0” writing to CL bit of LVRC register • Internal reset • Main oscillation clock stop • Transit to sleep mode • Transit to timebase timer mode and watch mode
19. Internal CR oscillation circuit
Value Min 50 ⎯ Typ 100 ⎯ Max 200 100
Parameter Oscillation frequency Oscillation stabilization wait time
Symbol fRC tstab
Unit kHz µs
27
MB90350E Series
■ BLOCK DIAGRAMS
• MB90V340E-101/102
X0 X0A* RST X1 X1A*
Clock controller
F2MC-16LX CPU
RAM 30 Kbytes
I/O Timer 0 Input Capture 8 channels Output Compare 8 channels
FRCK0
IN7 to IN0
OUT7 to OUT0
Prescaler 5 channels
SOT4 to SOT0 SCK4 to SCK0 SIN4 to SIN0
I/O Timer 1
FRCK1
F2MC-16LX Bus
UART 5 channels
CAN Controller 3 channels 16-bit Reload Timer 4 channels
RX2 to RX0 TX2 to TX0
AVCC AVSS AN23 to AN0 AVRH AVRL ADTG
TIN3 to TIN0 TOT3 to TOT0
8/10-bit A/D Converter 24 channels
AD15 to AD00 A21 to A16 ALE
DA00,DA01
10-bit D/A Converter 2 channels 8/16-bit PPG 16 channels I2C interface 2 channels
RD
External Bus Interface
WR/WRL WRH HRQ HAK RDY CLK
PPGF to PPG0
SDA0,SDA1 SCL0,SCL1
DTP/ External Interrupt Clock Monitor
INT7 to INT0 INT15 to INT8 (INT11R to INT9R)
DMAC
CKOT
* : MB90V340E-102 only
28
MB90350E Series
• MB90V340E-103/104
X0 X0A* RST X1 X1A*
Clock controller/ Monitor
F2MC-16LX CPU I/O Timer 0 Input Capture 8 channels Output Compare 8 channels I/O Timer 1 CAN Controller 3 channels 16-bit Reload Timer 4 channels
CR oscillation circuit RAM 30 Kbytes Prescaler 5 channels
SOT4 to SOT0 SCK4 to SCK0 SIN4 to SIN0 AVCC AVSS AN23 to AN0 AVRH AVRL ADTG
FRCK0 IN7 to IN0
OUT7 to OUT0 FRCK1
UART 5 channels
RX2 to RX0 TX2 to TX0
F2MC-16LX Bus
8/10-bit A/D Converter 24 channels 10-bit D/A Converter 2 channels 8/16-bit PPG 16 channels I2C interface 2 channels
DMA
TIN3 to TIN0 TOT3 to TOT0 AD15 to AD00 A23 to A16 ALE RD WRL WRH HRQ HAK RDY CLK INT15 to INT8 (INT15R to INT8R) INT7 to INT0 CKOT
DA01, DA00
External Bus Interface
PPGF to PPG0 SDA1, SDA0 SCL1, SCL0
DTP/External Interrupt
Clock Monitor
* : MB90V340E-104 only
29
MB90350E Series
• MB90F352E (S) , MB90F352TE (S) , MB90F351E (S) , MB90F351TE (S) , MB90352E (S) , MB90352TE (S) , MB90351E (S) , MB90351TE (S)
X0 X0A *1 RST X1 X1A*1
Clock controller
F2MC-16LX CPU
Low voltage/ CPU operation detection reset*2
I/O Timer 0 Input Capture 6 channels Output Compare 4 channels I/O Timer 1
FRCK0
RAM 4 Kbytes ROM/Flash 128 Kbytes/ 64 Kbytes Prescaler 2 channels
SOT3, SOT2 SCK3, SCK2 SIN3, SIN2
IN7 to IN4, IN1, IN0 OUT7 to OUT4
FRCK1
F2MC-16LX Bus
UART 2 channels
CAN Controller 1 channel 16-bit Reload Timer 2 channels
RX1 TX1
AVCC AVSS AN14 to AN0 AVRH ADTG
TIN3, TIN1 TOT3, TOT1
8/10-bit A/D Converter 15 channels
AD15 to AD00 A21 to A16 ALE RD
PPGF to PPG8 PPG6, PPG4
8/16-bit PPG 10/6 channels I2C interface 1 channel
External Bus Interface
WR/WRL WRH HRQ HAK RDY CLK
SDA0 SCL0
DTP/ External Interrupt
DMAC
INT15 to INT8 (INT11R to INT9R)
*1 : Only for devices without “S”-suffix *2 : Only for devices with “T”-suffix 30
MB90350E Series
• MB90F357E (S) , MB90F357TE (S) , MB90F356E (S) , MB90F356TE (S) , MB90357E (S) , MB90357TE (S) , MB90356E (S) , MB90356TE (S)
X0 X0A*1 RST X1 X1A*1
Clock controller/ Monitor CR oscillation circuit
Low voltage/ CPU operation detector reset*2
F2MC-16LX CPU
I/O Timer 0 Input Capture 6 channels Output Compare 4 channels I/O Timer 1
FRCK0
IN7 to IN4, IN1, IN0 OUT7 to OUT4
RAM 4 Kbytes ROM/Flash 128 Kbytes/ 64 Kbytes Prescaler 2 channels
SOT3, SOT2 SCK3, SCK2 SIN3, SIN2 AVCC AVSS AN14 to AN0 AVRH ADTG PPGF to PPG8 PPG6, PPG4
FRCK1
F2MC-16LX Bus
CAN Controller 1 channel 16-bit Reload Timer 4 channels
RX1 TX1
UART 2 channels
TIN3, TIN1 TOT3, TOT1
AD15 to AD00
8/10-bit A/D Converter 15 channels
A21 to A16 ALE RD WR/WRL WRH HRQ HAK RDY CLK
External Bus Interface
8/16-bit PPG 10/6 channels I2C interface 1 channel
SDA0 SCL0
External Interrupt
INT15 to INT8 (INT11R to INT9R)
DMAC
*1 : Only for devices without “S”-suffix *2 : Only for devices with “T”-suffix
31
MB90350E Series
■ MEMORY MAP
MB90352E (S) MB90352TE (S) MB90F352E (S) MB90F352TE (S) MB90357E (S) MB90357TE (S) MB90F357E (S) MB90F357TE (S)
FFFFFFH FFFFFFH
MB90V340E-101 MB90V340E-102 MB90V340E-103 MB90V340E-104
FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH F80000H 00FFFFH
MB90351E (S) MB90351TE (S) MB90F351E (S) MB90F351TE (S) MB90356E (S) MB90356TE (S) MB90F356E (S) MB90F356TE (S)
ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) ROM (F8 bank)
External access area
ROM (FF bank)
FF0000H FEFFFFH FF0000H
ROM (FF bank)
ROM (FE bank)
FE0000H FDFFFFH FDFFFFH
External access area
C00100H C00100H
External access area
00FFFFH 008000H 007FFFH 007900H
ROM (image of FF bank)
00FFFFH
ROM
ROM
008000H (image of FF bank) 007FFFH
008000H (image of FF bank) 007FFFH 007900H 0078FFH
Peripheral
007900H
Peripheral
Peripheral
RAM 30 Kbytes
001100H 0010FFH 000100H
External access area
RAM 4 Kbytes
External access area
001100H 0010FFH 000100H
RAM 4 Kbytes
External access area
000100H
0000EFH 000000H
Peripheral
0000EFH 000000H
Peripheral
0000EFH 000000H
Peripheral
: No access
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without using the far specification in the pointer declaration. For example, an attempt to access 00C000H practically accesses the value at FFC000H in ROM. The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00. The image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF7FFFH is visible only in bank FF.
32
MB90350E Series
■ I/O MAP
Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H to 00000AH 00000BH 00000DH 00000EH 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H to 000019H 00001AH 00001BH 00001CH Port 0 Pull-up Control Register 00001DH Port 1 Pull-up Control Register 00001EH 00001FH 000020H to 000037H Port 2 Pull-up Control Register Port 3 Pull-up Control Register SIN input Level Setting Register Input Level Select Register 0 Input Level Select Register 1 Port 0 Direction Register Port 1 Direction Register Port 2 Direction Register Port 3 Direction Register Port 4 Direction Register Port 5 Direction Register Port 6 Direction Register Port 5 Analog Input Enable Register 00000CH Port 6 Analog Input Enable Register Register Port 0 Data Register Port 1 Data Register Port 2 Data Register Port 3 Data Register Port 4 Data Register Port 5 Data Register Port 6 Data Register Abbreviation Access PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 Reserved ADER5 ADER6 Reserved ILSR0 ILSR1 DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 Reserved DDRA Reserved PUCR0 PUCR1 PUCR2 PUCR3 Reserved (Continued) R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 00000000B 00000000B 00000000B 00000000B W UART2, UART3 X00XXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W Ports Ports Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 00000000B 00000000B 00000000B 00000000B XX000000B 00000000B XX000000B X0000000B 00000000B R/W R/W Port 5, A/D Port 6, A/D 11111111B 11111111B R/W R/W R/W R/W R/W R/W R/W Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
33
MB90350E Series
Address
Register
Abbreviation Access PPGC4 PPGC5 PPG45 PACSR1 PPGC6 PPGC7 PPG67 Reserved PPGC8 PPGC9 PPG89 Reserved PPGCA PPGCB PPGAB Reserved PPGCC PPGCD PPGCD Reserved PPGCE PPGCF PPGEF Reserved W,R/W W,R/W W, R/W W, R/W W, R/W
Resource name
Initial value 0X000XX1B 0X000001B 000000X0B 00000000B 0X000XX1B 0X000001B 000000X0B 0X000XX1B 0X000001B 000000X0B 0X000XX1B 0X000001B 000000X0B 0X000XX1B 0X000001B 000000X0B 0X000XX1B 0X000001B 000000X0B
000038H PPG 4 Operation Mode Control Register 000039H PPG 5 Operation Mode Control Register 00003AH PPG 4/5 Count Clock Select Register 00003BH Address Detect Control Register 1 00003CH PPG 6 Operation Mode Control Register 00003DH PPG 7 Operation Mode Control Register 00003EH PPG 6/7 Count Clock Select Register 00003FH 000040H PPG 8 Operation Mode Control Register 000041H PPG 9 Operation Mode Control Register 000042H PPG 8/9 Count Clock Select Register 000043H 000044H PPG A Operation Mode Control Register 000045H PPG B Operation Mode Control Register 000046H PPG A/B Count Clock Select Register 000047H 000048H PPG C Operation Mode Control Register 000049H PPG D Operation Mode Control Register 00004AH PPG C/D Count Clock Select Register 00004BH 00004CH PPG E Operation Mode Control Register 00004DH PPG F Operation Mode Control Register 00004EH PPG E/F Count Clock Select Register 00004FH 000050H Input Capture Control Status Register 0/1
16-bit Programmable W, R/W Pulse Generator 4/5 R/W R/W W, R/W 16-bit Programmable W, R/W Pulse Generator 6/7 R/W Address Match Detection 1
16-bit Programmable W, R/W Pulse Generator 8/9 R/W
16-bit Programmable W, R/W Pulse Generator A/B R/W
16-bit Programmable W,R/W Pulse Generator C/D R/W
16-bit Programmable W,R/W Pulse Generator E/F R/W
ICS01 ICE01 Reserved
R/W R/W, R
Input Capture 0/1
00000000B XXX0X0XXB
000051H Input Capture Edge Register 0/1 000052H, 000053H 000054H Input Capture Control Status Register 4/5 Input Capture Control Status Register 6/7
ICS45 ICE45 ICS67 ICE67
R/W R R/W R/W, R
Input Capture 4/5
00000000B XXXXXXXXB
000055H Input Capture Edge Register 4/5 000056H
Input Capture 6/7
00000000B XXX000XXB (Continued)
000057H Input Capture Edge Register 6/7
34
MB90350E Series
Address 000058H to 00005BH 00005CH 00005DH 00005EH 00005FH
Register
Abbreviation Access Reserved
Resource name
Initial value
Output Compare Control Status Register 4 Output Compare Control Status Register 5 Output Compare Control Status Register 6 Output Compare Control Status Register 7
OCS4 OCS5 OCS6 OCS7 TMCSR0 TMCSR0 TMCSR1 TMCSR1 TMCSR2 TMCSR2 TMCSR3 TMCSR3 ADCS0 ADCS1 ADCR0 ADCR1 ADSR0 ADSR1 LVRC ROMM Reserved
R/W Output Compare 4/5 R/W R/W Output Compare 6/7 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W Low Voltage/CPU R/W, W Operation Detection Reset W ROM Mirror A/D Converter 16-bit Reload Timer 0 16-bit Reload Timer 1 16-bit Reload Timer 2 16-bit Reload Timer 3
0000XX00B 0XX00000B 0000XX00B 0XX00000B 00000000B XXXX0000B 00000000B XXXX0000B 00000000B XXXX0000B 00000000B XXXX0000B 000XXXX0B 0000000XB 00000000B XXXXXX00B 00000000B 00000000B 00111000B XXXXXXX1B
000060H Timer Control Status Register 0 000061H Timer Control Status Register 0 000062H Timer Control Status Register 1 000063H Timer Control Status Register 1 000064H Timer Control Status Register 2 000065H Timer Control Status Register 2 000066H Timer Control Status Register 3 000067H Timer Control Status Register 3 000068H A/D Control Status Register 0 000069H A/D Control Status Register 1 00006AH A/D Data Register 0 00006BH A/D Data Register 1 00006CH ADC Setting Register 0 00006DH ADC Setting Register 1 00006EH Low Voltage/CPU Operation Detection Reset Control Register
00006FH ROM Mirror Function Select Register 000070H to 00007FH
000080H to Reserved for CAN controller 1. Refer to “■ CAN CONTROLLERS” 00008FH 000090H to 00009AH Reserved (Continued)
35
MB90350E Series
Address 00009BH
Register DMA Descriptor Channel Specification Register
Abbreviation DCSR DSRL DSRH PACSR0 DIRR LPMCR
Access Resource name Initial value R/W R/W R/W R/W R/W W,R/W Address Match Detection 0
Low Power Consumption Control Circuit Low Power Consumption Control Circuit
00000000B DMA 00000000B 00000000B 00000000B
00009CH DMA Status Register L Register 00009DH DMA Status Register H Register 00009EH Address Detect Control Register 0 00009FH Delayed Interrupt/Release Register 0000A0H Low-power Consumption Mode Control Register
Delayed Interrupt XXXXXXX0B 00011000B
0000A1H Clock Selection Register 0000A2H, 0000A3H 0000A4H DMA Stop Status Register 0000A5H Automatic Ready Function Selection Register
CKSCR
R,R/W
11111100B
Reserved DSSR ARSR HACR ECSR WDTC TBTC WTC Reserved DERL DERH FMCS Reserved ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W Interrupt Control 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B (Continued) R/W R/W R,R/W DMA 00000000B 00000000B 000X0000B R/W W W W R,W W,R/W R,R/W Timebase timer Watch Timer External Memory Access DMA 00000000B 0011XX00B 00000000B 0000000XB Watchdog Timer XXXXX111B 1XX00100B 1X001000B
0000A6H External Address Output Control Register 0000A7H Bus Control Signal Selection Register 0000A8H Watchdog Control Register 0000A9H Timebase Timer Control Register 0000AAH Watch Timer Control Register 0000ABH 0000ACH DMA Enable Register L Register 0000ADH DMA Enable Register H Register Flash Control Status Register 0000AEH (Flash Devices only. Otherwise reserved) 0000AFH 0000B0H Interrupt Control Register 00 0000B1H Interrupt Control Register 01 0000B2H Interrupt Control Register 02 0000B3H Interrupt Control Register 03 0000B4H Interrupt Control Register 04 0000B5H Interrupt Control Register 05 0000B6H Interrupt Control Register 06 0000B7H Interrupt Control Register 07 0000B8H Interrupt Control Register 08
Flash memory
36
MB90350E Series
Address
Register
Abbreviation ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Reserved ENIR1 EIRR1 ELVR1 ELVR1 EISSR PSCCR BAPL BAPM BAPH DMACS IOAL IOAH DCTL DCTH SMR2 SCR2 RDR2/TDR2 SSR2 ECCR2 ESCR2 BGR20
Access W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W W,R/W
Resource name
Initial value 00000111B 00000111B 00000111B
0000B9H Interrupt Control Register 09 0000BAH Interrupt Control Register 10 0000BBH Interrupt Control Register 11 0000BCH Interrupt Control Register 12 0000BDH Interrupt Control Register 13 0000BEH Interrupt Control Register 14 0000BFH Interrupt Control Register 15 0000C0H to 0000C9H 0000CAH External Interrupt Enable Register 1 0000CBH External Interrupt Source Register 1 0000CCH External Interrupt Level Register 1 0000CDH External Interrupt Level Register 1 0000CEH External Interrupt Source Select Register DMA Buffer Address Pointer L Register DMA Buffer Address Pointer M Register DMA Buffer Address Pointer H Register I/O Register Address Pointer L Register I/O Register Address Pointer H Register
Interrupt Control
00000111B 00000111B 00000111B 00000111B
R/W R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W W,R/W W,R/W R/W R,R/W R,W, R/W R/W R/W UART2 DMA PLL External Interrupt 1
00000000B XXXXXXXXB 00000000B 00000000B 00000000B XXXX0000B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00000000B 00001000B 000000XXB 00000100B 00000000B (Continued) 37
0000CFH PLL/Sub clock Control register 0000D0H 0000D1H 0000D2H
0000D3H DMA Control Register 0000D4H 0000D5H
0000D6H Data Counter L Register 0000D7H Data Counter H Register 0000D8H Serial Mode Register 2 0000D9H Serial Control Register 2 0000DAH Reception/Transmission Data Register 2 Extended Communication Control Register 2
0000DBH Serial Status Register 2 0000DCH
0000DDH Extended Status/Control Register 2 0000DEH Baud Rate Generator Register 20
MB90350E Series
Address 0000E0H to 0000EFH 0000F0H to 0000FFH 007900H to 007907H 007908H 007909H
Register
Abbreviation BGR21 Reserved
Access R/W
Resource name UART2
Initial value 00000000B
0000DFH Baud Rate Generator Register 21
External area
Reserved Reload Register L4 Reload Register H4 PRLL4 PRLH4 PRLL5 PRLH5 PRLL6 PRLH6 PRLL7 PRLH7 PRLL8 PRLH8 PRLL9 PRLH9 PRLLA PRLHA PRLLB PRLHB PRLLC PRLHC PRLLD PRLHD PRLLE PRLHE PRLLF PRLHF IPCP0 IPCP0 IPCP1 IPCP1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R Input Capture 0/1 XXXXXXXXB 16-bit Programmable XXXXXXXXB Pulse XXXXXXXXB Generator 4/5 XXXXXXXXB XXXXXXXXB 16-bit Programmable XXXXXXXXB Pulse XXXXXXXXB Generator 6/7 XXXXXXXXB XXXXXXXXB 16-bit Programmable XXXXXXXXB Pulse XXXXXXXXB Generator 8/9 XXXXXXXXB XXXXXXXXB 16-bit Programmable XXXXXXXXB Pulse XXXXXXXXB Generator A/B XXXXXXXXB XXXXXXXXB 16-bit Programmable XXXXXXXXB Pulse XXXXXXXXB Generator C/D XXXXXXXXB XXXXXXXXB 16-bit Programmable XXXXXXXXB Pulse XXXXXXXXB Generator E/F XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued)
00790AH Reload Register L5 00790BH Reload Register H5 00790CH Reload Register L6 00790DH Reload Register H6 00790EH Reload Register L7 00790FH Reload Register H7 007910H 007911H 007912H 007913H 007914H 007915H 007916H 007917H 007918H 007919H Reload Register L8 Reload Register H8 Reload Register L9 Reload Register H9 Reload Register LA Reload Register HA Reload Register LB Reload Register HB Reload Register LC Reload Register HC
00791AH Reload Register LD 00791BH Reload Register HD 00791CH Reload Register LE 00791DH Reload Register HE 00791EH Reload Register LF 00791FH Reload Register HF 007920H 007921H 007922H 007923H Input Capture Register 0 Input Capture Register 0 Input Capture Register 1 Input Capture Register 1
38
MB90350E Series
Address 007924H to 007927H 007928H 007929H 00792AH 00792BH 00792CH 00792DH 00792EH 00792FH 007930H to 007937H 007938H 007939H 00793AH 00793BH 00793CH 00793DH 00793EH 00793FH 007940H 007941H 007942H 007943H 007944H 007945H 007946H 007947H 007948H 007949H 00794AH 00794BH 00794CH 00794DH 00794EH 00794FH
Register
Abbreviation
Access
Resource name
Initial value
Reserved Input Capture Register 4 Input Capture Register 4 Input Capture Register 5 Input Capture Register 5 Input Capture Register 6 Input Capture Register 6 Input Capture Register 7 Input Capture Register 7 IPCP4 IPCP4 IPCP5 IPCP5 IPCP6 IPCP6 IPCP7 IPCP7 Reserved Output Compare Register 4 Output Compare Register 4 Output Compare Register 5 Output Compare Register 5 Output Compare Register 6 Output Compare Register 6 Output Compare Register 7 Output Compare Register 7 Timer Data Register 0 Timer Data Register 0 Timer Control Status Register 0 Timer Control Status Register 0 Timer Data Register 1 Timer Data Register 1 Timer Control Status Register 1 Timer Control Status Register 1 Timer Register 0/Reload Register 0 Timer Register 1/Reload Register 1 Timer Register 2/Reload Register 2 Timer Register 3/Reload Register 3 OCCP4 OCCP4 OCCP5 OCCP5 OCCP6 OCCP6 OCCP7 OCCP7 TCDT0 TCDT0 TCCSL0 TCCSH0 TCDT1 TCDT1 TCCSL1 TCCSH1 TMR0/ TMRLR0 TMR1/ TMRLR1 TMR2/ TMRLR2 TMR3/ TMRLR3 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 16-bit Reload Timer 0 16-bit Reload Timer 1 16-bit Reload Timer 2 16-bit Reload Timer 3 I/O Timer 1 I/O Timer 0 Output Compare 6/7 Output Compare 4/5 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00000000B 0XXXXXXXB 00000000B 00000000B 00000000B 0XXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) 39 R R R R R R R R Input Capture 6/7 Input Capture 4/5 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
MB90350E Series
Address
Register
Abbreviation Access SMR3 SCR3 RDR3/TDR3 SSR3 ECCR3 ESCR3 BGR30 BGR31 Reserved CSVCR Reserved CDMR Reserved IBSR0 IBCR0 ITBAL0 ITBAH0 ITMKL0 ITMKH0 ISBA0 ISMK0 IDAR0 Reserved ICCR0 Reserved FWR0 FWR1 SSR0 Reserved Setting Prohibited R/W R/W R/W R/W R/W R W,R/W R/W R/W R/W R/W R/W R/W R/W R, R/W W, R/W W, R/W R/W R,R/W R,W, R/W R/W R/W R/W
Resource name
Initial value 00000000B 00000000B 00000000B
007950H Serial Mode Register 3 007951H Serial Control Register 3 007952H Reception/Transmission Data Register 3 Extended Communication Control Register 3
007953H Serial Status Register 3 007954H
UART3
00001000B 000000XXB 00000100B 00000000B 00000000B
007955H Extended Status Control Register 3 007956H Baud Rate Generator Register 30 007957H Baud Rate Generator Register 31 007958H, 007959H 007960H Clock supervisor Control Register 007961H to 00796DH 00796EH CAN Direct Mode Register 00796FH 007970H I C Bus Status Register 0 007971H I C Bus Control Register 0 007972H 007973H I2C 10-bit Slave Address Register 0
2 2
Clock supervisor
00011100B
CAN Clock Sync
XXXXXXX0B 00000000B 00000000B 00000000B 00000000B
007974H I2C 10-bit Slave Address Mask 007975H Register 0 007976H I C 7-bit Slave Address Register 0 007977H I C 7-bit Slave Address Mask Register 0 007978H I C data register 0 007979H, 00797AH 00797BH I2C Clock Control Register 0 00797CH to 0079A1H 0079A2H Flash Write Control Register 0 0079A3H Flash Write Control Register 1 0079A4H Sector Change Setting Register 0 0079A5H to 0079C1H 0079C2H
2 2 2
I C Interface 0
2
11111111B 00111111B 00000000B 01111111B 00000000B
I2C Interface 0
00011111B
00000000B Dual Operation Flash 00000000B 00XXXXX0B
(Continued) 40
MB90350E Series
(Continued) Address 0079C3H to 0079DFH 0079E0H 0079E1H 0079E2H 0079E3H 0079E4H 0079E5H 0079E6H 0079E7H 0079E8H 0079E9H to 0079EFH 0079F0H 0079F1H 0079F2H 0079F3H 0079F4H 0079F5H 0079F6H 0079F7H 0079F8H 0079F9H to 007BFFH 007C00H to 007DFFH 007E00H to 007FFFH Detect Address Setting Register 3 Detect Address Setting Register 3 Detect Address Setting Register 3 Detect Address Setting Register 4 Detect Address Setting Register 4 Detect Address Setting Register 4 Detect Address Setting Register 5 Detect Address Setting Register 5 Detect Address Setting Register 5 Detect Address Setting Register 0 Detect Address Setting Register 0 Detect Address Setting Register 0 Detect Address Setting Register 1 Detect Address Setting Register 1 Detect Address Setting Register 1 Detect Address Setting Register 2 Detect Address Setting Register 2 Detect Address Setting Register 2
Register
Abbreviation
Access
Resource name
Initial value
Reserved PADR0 PADR0 PADR0 PADR1 PADR1 PADR1 PADR2 PADR2 PADR2 Reserved PADR3 PADR3 PADR3 PADR4 PADR4 PADR4 PADR5 PADR5 PADR5 Reserved R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Match Detection 1 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W Address Match Detection 0 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
Reserved for CAN controller 1. Refer to “■ CAN CONTROLLERS”
Reserved
Notes : • Initial value of “X” represents unknown value. • Any write access to reserved addresses in I/O map should not be performed. A read access to reserved addresses results reading unknown value.
41
MB90350E Series
■ CAN CONTROLLERS
• Compliant with CAN standard Version2.0 Part A and Part B - Supports transmission/reception in standard frame and extended frame formats • Supports transmitting of data frames by receiving remote frames • 16 transmitting/receiving message buffers - 29-bit ID and 8-byte data - Multi-level message buffer configuration • Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as ID acceptance mask - Two acceptance mask registers in either standard frame format or extended frame formats • Bit rate programmable from 10 kbps to 2 Mbps (when input clock is at 16 MHz) List of Control Registers Address CAN1 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH Register Message buffer enable register Transmit request register Transmit cancel register Transmission complete register Receive complete register Remote request receiving register Receive overrun register Reception interrupt enable register Abbreviation BVALR TREQR TCANR TCR RCR RRTRR ROVRR RIER Access R/W R/W W R/W R/W R/W R/W R/W Initial Value 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued)
42
MB90350E Series
(Continued) Address CAN1 007D00H 007D01H 007D02H 007D03H 007D04H 007D05H 007D06H 007D07H 007D08H 007D09H 007D0AH 007D0BH 007D0CH 007D0DH 007D0EH 007D0FH 007D10H 007D11H 007D12H 007D13H 007D14H 007D15H 007D16H 007D17H 007D18H 007D19H 007D1AH 007D1BH Acceptance mask register 1 AMR1 R/W XXXXXXXXB XXXXXXXXB Acceptance mask register 0 AMR0 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Acceptance mask select register AMSR R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
Register Control status register Last event indicator register Receive/transmit error counter Bit timing register IDE register Transmit RTR register Remote frame receive waiting register Transmit interrupt enable register
Abbreviation CSR LEIR RTEC BTR IDER TRTRR RFWTR TIER
Access R/W, W R/W, R R/W R R/W R/W R/W R/W R/W
Initial Value 0XXXX0X1B 00XXX000B 000X0000B XXXXXXXXB 00000000B 00000000B 11111111B X1111111B XXXXXXXXB XXXXXXXXB 00000000B 00000000B XXXXXXXXB XXXXXXXXB 00000000B 00000000B XXXXXXXXB XXXXXXXXB
43
MB90350E Series
List of Message Buffers (ID Registers) Address CAN1 007C00H to 007C1FH 007C20H 007C21H 007C22H 007C23H 007C24H 007C25H 007C26H 007C27H 007C28H 007C29H 007C2AH 007C2BH 007C2CH 007C2DH 007C2EH 007C2FH 007C30H 007C31H 007C32H 007C33H 007C34H 007C35H 007C36H 007C37H 007C38H 007C39H 007C3AH 007C3BH 007C3CH 007C3DH 007C3EH 007C3FH ID register 7 IDR7 R/W XXXXXXXXB XXXXXXXXB (Continued) 44 ID register 6 IDR6 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 5 IDR5 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 4 IDR4 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 3 IDR3 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 2 IDR2 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 1 IDR1 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 0 IDR0 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Register Abbreviation Access Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXXB XXXXXXXXB
General-purpose RAM
⎯
R/W
MB90350E Series
(Continued) Address CAN1 007C40H 007C41H 007C42H 007C43H 007C44H 007C45H 007C46H 007C47H 007C48H 007C49H 007C4AH 007C4BH 007C4CH 007C4DH 007C4EH 007C4FH 007C50H 007C51H 007C52H 007C53H 007C54H 007C55H 007C56H 007C57H 007C58H 007C59H 007C5AH 007C5BH 007C5CH 007C5DH 007C5EH 007C5FH ID register 15 IDR15 R/W XXXXXXXXB XXXXXXXXB ID register 14 IDR14 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 13 IDR13 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 12 IDR12 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 11 IDR11 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 10 IDR10 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 9 IDR9 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID register 8 IDR8 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
Register
Abbreviation
Access
Initial Value XXXXXXXXB XXXXXXXXB
45
MB90350E Series
List of Message Buffers (DLC Registers and Data Registers) Address CAN1 007C60H 007C61H 007C62H 007C63H 007C64H 007C65H 007C66H 007C67H 007C68H 007C69H 007C6AH 007C6BH 007C6CH 007C6DH 007C6EH 007C6FH 007C70H 007C71H 007C72H 007C73H 007C74H 007C75H 007C76H 007C77H 007C78H 007C79H 007C7AH 007C7BH 007C7CH 007C7DH 007C7EH 007C7FH Register DLC register 0 DLC register 1 DLC register 2 DLC register 3 DLC register 4 DLC register 5 DLC register 6 DLC register 7 DLC register 8 DLC register 9 DLC register 10 DLC register 11 DLC register 12 DLC register 13 DLC register 14 DLC register 15 Abbreviation DLCR0 DLCR1 DLCR2 DLCR3 DLCR4 DLCR5 DLCR6 DLCR7 DLCR8 DLCR9 DLCR10 DLCR11 DLCR12 DLCR13 DLCR14 DLCR15 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued)
46
MB90350E Series
Address CAN1 007C80H to 007C87H 007C88H to 007C8FH 007C90H to 007C97H 007C98H to 007C9FH 007CA0H to 007CA7H 007CA8H to 007CAFH 007CB0H to 007CB7H 007CB8H to 007CBFH 007CC0H to 007CC7H 007CC8H to 007CCFH 007CD0H to 007CD7H 007CD8H to 007CDFH 007CE0H to 007CE7H 007CE8H to 007CEFH
Register Data register 0 (8 bytes) Data register 1 (8 bytes) Data register 2 (8 bytes) Data register 3 (8 bytes) Data register 4 (8 bytes) Data register 5 (8 bytes) Data register 6 (8 bytes) Data register 7 (8 bytes) Data register 8 (8 bytes) Data register 9 (8 bytes) Data register 10 (8 bytes) Data register 11 (8 bytes) Data register 12 (8 bytes) Data register 13 (8 bytes)
Abbreviation
Access
Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB (Continued)
DTR0
R/W
DTR1
R/W
DTR2
R/W
DTR3
R/W
DTR4
R/W
DTR5
R/W
DTR6
R/W
DTR7
R/W
DTR8
R/W
DTR9
R/W
DTR10
R/W
DTR11
R/W
DTR12
R/W
DTR13
R/W
47
MB90350E Series
(Continued) Address CAN1 007CF0H to 007CF7H 007CF8H to 007CFFH
Register Data register 14 (8 bytes) Data register 15 (8 bytes)
Abbreviation
Access
Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB
DTR14
R/W
DTR15
R/W
48
MB90350E Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt cause Reset INT9 instruction Exception Reserved Reserved CAN 1 RX / Input Capture 6 CAN 1 TX/NS / Input Capture 7 I2C Reserved 16-bit Reload Timer 0 16-bit Reload Timer 1 16-bit Reload Timer 2 16-bit Reload Timer 3 PPG 4/5 PPG 6/7 PPG 8/9/C/D PPG A/B/E/F Timebase Timer External Interrupt 8 to 11 Watch Timer External Interrupt 12 to 15 A/D Converter I/O Timer 0 / I/O Timer 1 Input Capture 4/5 Output Compare 4/5 Input Capture 0/1 Output Compare 6/7 Reserved Reserved UART 3 RX UART 3 TX EI2OS corresponding N N N N N Y1 Y1 N N Y1 Y1 Y1 Y1 N N N N N Y1 N Y1 Y1 N Y1 Y1 Y1 Y1 N N Y2 Y1 DMA ch number ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 1 2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 3 ⎯ 4 5 ⎯ 6 7 8 9 10 11 12 13 Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H Interrupt control register Number ⎯ ⎯ ⎯ ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 Address ⎯ ⎯ ⎯ 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH (Continued)
49
MB90350E Series
(Continued) Interrupt cause UART 2 RX UART 2 TX Flash memory Delayed interrupt Y1 : Usable Y2 : Usable, with EI2OS stop function N : Unusable Notes : • The peripheral resources sharing the ICR register have the same interrupt level. • When the peripheral resources sharing the ICR register use extended intelligent I/O service, only one can use EI2OS at a time. • When either of the two peripheral resources sharing the ICR register specifies EI2OS, the other one cannot use interrupts. EI2OS corresponding Y2 Y1 N N DMA ch number 14 15 ⎯ ⎯ Interrupt vector Number #39 #40 #41 #42 Address FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register Number ICR14 ICR15 Address 0000BEH 0000BFH
50
MB90350E Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol VCC Power supply voltage* Input voltage*1 Output voltage*
1 1
Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 −4.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ −40 −40 −55 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 +4.0 40 15 4 100 50 −15 −4 −100 −50 320 +105 +125 +150
Unit V V V V V mA mA mA mA mA mA mA mA mA mA mW °C °C °C *6
Remarks
AVCC AVRH VI VO ICLAMP Σ|ICLAMP| IOL IOLAV ΣIOL ΣIOLAV IOH IOHAV ΣIOH ΣIOHAV PD TA TSTG
VCC = AVCC*2 AVCC ≥ AVRH*2 *3 *3 *5 *5 *4 *4 *4 *4 *4 *4 *4 *4
Maximum Clamp Current Total Maximum Clamp Current “L” level maximum output current “L” level average output current “L” level maximum overall output current “L” level average overall output current “H” level maximum output current “H” level average output current “H” level maximum overall output current “H” level average overall output current Power consumption Operating temperature Storage temperature
(Continued)
51
MB90350E Series
(Continued) *1: This parameter is based on VSS = AVSS = 0 V *2: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on. *3: VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4: Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45, P50 to P56, P60 to P67 *5: • Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45, P50 to P56 (for evaluation device : P50 to P55) , P60 to P67 • Use within recommended operating conditions. • Use at DC voltage (current) • The +B signal should always be applied a connecting limit resistance between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the +B input pin open. • Recommended circuit sample: • Input/output equivalent circuits Protective diode
VCC
Limiting resistance +B input (0 V to 16 V)
P-ch
N-ch
R
*6 : If used exceeding TA = +105 °C, be sure to contact Fujitsu for reliability limitations. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
52
MB90350E Series
2. Recommended Operating Conditions
Parameter Symbol Value Min 4.0 Power supply voltage VCC, AVCC 3.5 4.5 3.0 Smoothing capacitor Operating temperature CS TA 0.1 −40 Typ 5.0 5.0 5.0 ⎯ ⎯ ⎯ Max 5.5 5.5 5.5 5.5 1.0 +125 Unit V V V V µF Remarks Under normal operation Under normal operation, when not using the A/D converter and not Flash programming. When External bus is used. Maintains RAM data in stop mode Use a ceramic capacitor or comparable capacitor of the AC characteristics. Bypass capacitor at the VCC pin should be greater than this capacitor.
(VSS = AVSS = 0 V)
°C *
* : If used exceeding TA = +105 °C, be sure to contact Fujitsu for reliability limitations. • C Pin Connection Diagram
C CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
53
MB90350E Series
3. DC Characteristics
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Symbol Pin Condition Value Min Typ ⎯ Max VCC + 0.3 Unit Remarks Pin inputs if CMOS hysteresis input levels are selected (except P12, P15, P44, P45, P50) Pin inputs if Automotive input levels are selected Pin inputs if TTL input levels are selected P12, P15, P50 inputs if CMOS input levels are selected P44, P45 inputs if CMOS hysteresis input levels are selected RST input pin (CMOS hysteresis) MD input pin Pin inputs if CMOS hysteresis input levels are selected (except P12, P15, P44, P45, P50) Pin inputs if Automotive input levels are selected Pin inputs if TTL input levels are selected P12, P15, P50 inputs if CMOS input levels are selected P44, P45 inputs if CMOS hysteresis input levels are selected RST input pin (CMOS hysteresis) MD input pin
VIHS
⎯
⎯
0.8 VCC
V
VIHA “H” level input voltage (At VCC = 5 V ± 10%)
⎯ ⎯ ⎯
⎯ ⎯ ⎯
0.8 VCC
⎯ ⎯ ⎯
VCC + 0.3 VCC + 0.3 VCC + 0.3
V
VIHT
2.0
V
VIHS
0.7 VCC
V
VIHI
⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯
0.7 VCC
⎯ ⎯ ⎯ ⎯
VCC + 0.3 VCC + 0.3 VCC + 0.3 0.2 VCC
V
VIHR VIHM
0.8 VCC VCC − 0.3 VSS − 0.3
V V
VILS
V
VILA “L” level input voltage (At VCC = 5 V ± 10%)
⎯ ⎯ ⎯
⎯ ⎯ ⎯
VSS − 0.3 VSS − 0.3 VSS − 0.3
⎯ ⎯ ⎯
0.5 VCC
V
VILT
0.8
V
VILS
0.3 VCC
V
VILI
⎯ ⎯ ⎯ Normal outputs
⎯ ⎯ ⎯
VSS − 0.3 VSS − 0.3 VSS − 0.3
⎯ ⎯ ⎯ ⎯ ⎯
0.3 VCC
V
VILR VILM Output “H” voltage Output “H” voltage VOH VOHI
0.2 VCC VSS + 0.3 ⎯ ⎯
V V V V
VCC = 4.5 V, VCC − 0.5 IOH = −4.0 mA
I2C current VCC = 4.5 V, VCC − 0.5 outputs IOH = −3.0 mA
(Continued)
54
MB90350E Series
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Output “L” voltage Output “L” voltage Input leak current Pull-up resistance Pull-down resistance Symbol VOL VOLI IIL Pin Normal outputs I2C current outputs ⎯ P00 to P07, P10 to P17, P20 to P25, P30 to P37, RST MD2 Condition VCC = 4.5 V, IOL = 4.0 mA VCC = 4.5 V, IOL = 3.0 mA VCC = 5.5 V, VSS < VI < VCC Value Min ⎯ ⎯ −1 Typ ⎯ ⎯ ⎯ Max 0.4 0.4 +1 Unit V V µA Remarks
RUP
⎯
25
50
100
kΩ
RDOWN
⎯ VCC = 5.0 V, Internal frequency : 24 MHz, At normal operation.
25 ⎯
50 48
100 60
kΩ mA
Except Flash memory devices
ICC
VCC = 5.0 V, Internal frequency : 24 MHz, At writing Flash memory. VCC = 5.0 V, Internal frequency : 24 MHz, At erasing Flash memory.
⎯
53
65
mA
Flash memory devices Flash memory devices
⎯
58
70
mA
Power supply current
ICCS
VCC
VCC = 5.0 V, Internal frequency : 24 MHz, At Sleep mode. VCC = 5.0 V, Internal frequency : 2 MHz, At Main Timer mode VCC = 5.0 V, Internal frequency : 24 MHz, At PLL Timer mode, external frequency = 4 MHz
⎯
25
35
mA Devices mA without “T”-suffix mA Devices with “T”-suffix
⎯ ⎯
0.3 0.4
0.8 1.0
ICTS
ICTSPLL6
⎯
4
7
mA (Continued)
55
MB90350E Series
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Symbol Pin Condition VCC = 5.0 V, Internal frequency: 8 kHz, During stopping clock supervisor, At sub clock operation TA = +25°C VCC = 5.0 V, Internal frequency: 8 kHz, During operating clock supervisor, At sub clock operation TA = +25°C VCC = 5.0 V, Internal CR oscillation/ 4 division, At sub clock operation TA = +25°C ICCL VCC VCC = 5.0 V, Internal frequency: 8 kHz, During stopping clock supervisor, At sub clock operation TA = +25°C VCC = 5.0 V, Internal frequency: 8 kHz, During operating clock supervisor, At sub clock operation TA = +25°C VCC = 5.0 V, Internal CR oscillation/ 4 division, At sub clock operation TA = +25°C Value Min Typ Max Unit Remarks MB90F351E MB90F352E MB90351E MB90352E MB90F356E MB90F357E MB90356E MB90357E MB90F356E MB90F357E MB90356E MB90357E
⎯
70
140
µA
⎯
100
200
µA
⎯
100
200
µA
MB90F356ES MB90F357ES MB90356ES MB90357ES MB90F351TE MB90F352TE MB90351TE MB90352TE MB90F356TE MB90F357TE MB90356TE MB90357TE MB90F356TE MB90F357TE MB90356TE MB90357TE
Power supply current
⎯
120
240
µA
⎯
150
300
µA
⎯
150
300
µA
MB90F356TES MB90F357TES MB90356TES MB90357TES (Continued)
56
MB90350E Series
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Symbol Pin Condition VCC = 5.0 V, Internal frequency: 8 kHz, During stopping clock supervisor, At sub sleep TA = +25°C VCC = 5.0 V, Internal frequency: 8 kHz, During operating clock supervisor, At sub sleep TA = +25°C VCC = 5.0 V, Internal CR oscillation/ 4 division, At sub sleep TA = +25°C ICCLS VCC VCC = 5.0 V, Internal frequency: 8 kHz, At sub sleep TA = +25°C Value Min Typ Max Unit Remarks MB90F351E MB90F352E MB90351E MB90352E MB90F356E MB90F357E MB90356E MB90357E MB90F356E MB90F357E MB90356E MB90357E
⎯
20
50
µA
⎯
60
200
µA
⎯
60
200
µA
MB90F356ES MB90F357ES MB90356ES MB90357ES MB90F351TE MB90F352TE MB90351TE MB90352TE MB90F356TE MB90F357TE MB90356TE MB90357TE MB90F356TE MB90F357TE MB90356TE MB90357TE
Power supply current
⎯
70
150
µA
VCC = 5.0 V, Internal frequency: 8 kHz, During operating clock supervisor, At sub sleep TA = +25°C VCC = 5.0 V, Internal CR oscillation/ 4 division, At sub sleep TA = +25°C
⎯
110
300
µA
⎯
110
300
µA
MB90F356TES MB90F357TES MB90356TES MB90357TES (Continued)
57
MB90350E Series
(Continued) Symbol (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Pin Condition VCC = 5.0 V, Internal frequency: 8 kHz, During stopping clock supervisor, At watch mode TA = +25°C VCC = 5.0 V, Internal frequency: 8 kHz, During operating clock supervisor, At watch mode TA = +25°C VCC = 5.0 V, Internal CR oscillation/ 4 division, At watch mode TA = +25°C ICCT Power supply current VCC VCC = 5.0 V, Internal frequency: 8 kHz, During stopping clock supervisor, At watch mode TA = +25°C VCC = 5.0 V, Internal frequency: 8 kHz, During operating clock supervisor, At watch mode TA = +25°C VCC = 5.0 V, Internal CR oscillation/ 4 division, At watch mode TA = +25°C VCC = 5.0 V, At stop mode, TA = +25°C Other than C, AVCC, AVSS, AVRH, VCC, VSS Value Min Typ Max Unit Remarks MB90F351E MB90F352E MB90351E MB90352E MB90F356E MB90F357E MB90356E MB90357E MB90F356E MB90F357E MB90356E MB90357E MB90F356ES MB90F357ES MB90356ES MB90357ES MB90F351TE MB90F352TE MB90351TE MB90352TE MB90F356TE MB90F357TE MB90356TE MB90357TE MB90F356TE MB90F357TE MB90356TE MB90357TE MB90F356TES MB90F357TES MB90356TES MB90357TES Devices without “T”-suffix Devices with “T”-suffix
Parameter
⎯
10
35
µA
⎯
25
150
µA
⎯
25
150
µA
⎯
60
140
µA
⎯
80
250
µA
⎯
80
250
µA
⎯ ⎯
7 60
25 130
µA µA
ICCH
Input capacity
CIN
⎯
⎯
5
15
pF
58
MB90350E Series
4. AC Characteristics
(1) Clock Timing (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Symbol Pin Value Min 3 4 4 X0, X1 4 4 ⎯ Clock frequency fC 3 4 4 X0 4 4 ⎯ fCL Clock cycle time tCYL tCYLL Input clock pulse width Input clock rise and fall time PWH, PWL PWHL, PWLL tCR, tCF X0A, X1A X0, X1 X0 X0A, X1A X0 X0A X0 — 62.5 41.67 10 10 5 ⎯ ⎯ ⎯ ⎯ 32.768 ⎯ ⎯ 30.5 ⎯ 15.2 ⎯ 8 6 4 100 333 333 — ⎯ ⎯ 5 MHz MHz MHz kHz ns ns µs ns µs ns Duty ratio should be about 30% to 70%. When using an external clock (Continued) ⎯ ⎯ ⎯ 24 24 12 MHz MHz MHz ⎯ ⎯ ⎯ 8 6 4 MHz MHz MHz Typ ⎯ ⎯ ⎯ Max 16 16 12 Unit MHz MHz MHz Remarks 1/2 (at PLL stop) When using an oscillation circuit 1 multiplied PLL When using an oscillation circuit 2 multiplied PLL When using an oscillation circuit 3 multiplied PLL When using an oscillation circuit 4 multiplied PLL When using an oscillation circuit 6 multiplied PLL When using an oscillation circuit 1/2 (at PLL stop), When using an external clock 1 multiplied PLL When using an external clock 2 multiplied PLL When using an external clock 3 multiplied PLL When using an external clock 4 multiplied PLL When using an external clock 6 multiplied PLL When using an external clock When using sub clock When using an oscillation circuit When using an external clock
59
MB90350E Series
(Continued) (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Symbol fCP fCPL tCP tCPL Pin ⎯ ⎯ ⎯ ⎯ Value Min 1.5 ⎯ 41.67 20 Typ ⎯ 8.192 ⎯ 122.1 Max 24 50 666 ⎯ Unit MHz kHz ns µs Remarks When using main clock When using sub clock When using main clock When using sub clock
Parameter Internal operating clock frequency (machine clock) Internal operating clock cycle time (machine clock) • Clock Timing
tCYL
X0
PWH tCF PWL tCR
0.8 VCC 0.2 VCC
tCYLL
X0A
PWHL tCF PWLL tCR
0.8 VCC 0.2 VCC
60
MB90350E Series
• PLL guaranteed operation range
Guaranteed operation range
Power supply voltage VCC (V)
5.5 4.0 3.5
Guaranteed A/D converter operation range
Guaranteed PLL operation range
1.5
4
24
Main clock fCP (MHz) Guaranteed operation range of MB90350E series
Guaranteed A/D converter operation range
24 ×6 ×4 ×3 ×2 ×1
Internal clock fCP (MHz)
16 12 8 4.0 1.5 34 8 12 16 24 × 1/2 (PLL off)
External clock fC (MHz) * * : When using crystal oscillator or ceramic oscillator, the maximum clock frequency is 16 MHz. External clock frequency and internal operation clock frequency
61
MB90350E Series
(2) Reset Standby Input (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Symbol Pin Value Min 500 Reset input time Oscillation time of oscillator* + 100 µs 100 Max ⎯ ⎯ ⎯ Unit ns µs µs Remarks Under normal operation In Stop mode, Sub Clock mode, Sub Sleep mode and Watch mode In Main timer mode and PLL timer mode
tRSTL
RST
* : Oscillation time of oscillator is the time that the amplitude reaches 90%. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In ceramic oscillators, the oscillation time is between hundreds of µs to several ms. With an external clock, the oscillation time is 0 ms.
Under normal operation: tRSTL RST
0.2 VCC
0.2 VCC
In Stop mode, Sub Clock mode, Sub Sleep mode and, Watch mode:
tRSTL
RST
0.2 VCC 90% of amplitude 0.2 VCC
X0
Internal operation clock
Oscillation time of oscillator
100 µs Oscillation stabilization waiting time Instruction execution
Internal reset
62
MB90350E Series
(3) Power On Reset (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Power on rise time Power off time Symbol tR tOFF Pin VCC VCC Condition ⎯ Value Min 0.05 1 Max 30 ⎯ Unit ms ms Waiting time until power-on Remarks
tR 2.7 V 0.2 V 0.2 V tOFF 0.2 V
VCC
Note : If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you start up smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within 1 V/s, you can operate while using the PLL clock.
VCC 3V VSS
Holds RAM data We recommend the slope for a rise of 50 mV/ms maximum.
(4) Clock Output Timing (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, fCP ≤ 24 MHz) Parameter Cycle time CLK ↑ → CLK ↓ Symbol tCYC tCHCL Pin CLK CLK Condition ⎯ ⎯ Value Min 62.5 41.76 20 13 Max ⎯ ⎯ ⎯ ⎯ Unit ns ns ns ns Remarks fCP = 16 MHz fCP = 24 MHz fCP = 16 MHz fCP = 24 MHz
tCYC tCHCL
CLK
2.4 V 0.8 V
2.4 V
63
MB90350E Series
(5) Bus Timing (Read) (TA = –40°C to +105°C, VCC = 5.0 V ± 10 %, VSS = 0.0 V, fCP ≤ 24 MHz) Parameter ALE pulse width Valid address → ALE ↓ time ALE ↓ → Address valid time Valid address → RD ↓ time Valid address → Valid data input RD pulse width RD ↓ → Valid data input RD ↑ → Data hold time RD ↑ → ALE ↑ time RD ↑ → Address valid time Valid address → CLK ↑ time RD ↓ → CLK ↑ time ALE ↓ → RD ↓ time * : Number of ready cycles Symbol tLHLL tAVLL tLLAX tAVRL tAVDV tRLRH tRLDV tRHDX tRHLH tRHAX tAVCH tRLCH tLLRL ALE ALE, A21 to A16, AD15 to AD00 ALE, AD15 to AD00 A21 to A16, AD15 to AD00, RD A21 to A16, AD15 to AD00 RD RD, AD15 to AD00 RD, AD15 to AD00 RD, ALE RD, A21 to A16 A21 to A16, AD15 to AD00, CLK RD, CLK ALE, RD ⎯ Pin Condition Value Min tCP/2 − 10 tCP/2 − 20 tCP/2 − 15 tCP − 15 ⎯
(n*+3/2) tCP − 20
Max ⎯ ⎯ ⎯ ⎯ 5 tCP/2 − 60 ⎯
(n*+3/2) tCP − 50
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
⎯ 0 tCP/2 − 15 tCP/2 − 10 tCP/2 − 16 tCP/2 − 15 tCP/2 − 15
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
64
MB90350E Series
For 1 cycle of auto-ready CLK
tAVCH 2.4 V
tRLCH 2.4 V
tAVLL
tLLAX 2.4 V
tRHLH 2.4 V
ALE
2.4 V tLHLL tAVRL
0.8 V tRLRH 2.4 V 0.8 V tLLRL tRHAX
RD
A21 to A16
2.4 V 0.8 V tRLDV tAVDV 2.4 V 0.8 V 2.4 V Address 0.8 V VIH VIL
2.4 V 0.8 V tRHDX VIH Read data VIL
AD15 to AD00
65
MB90350E Series
(6) Bus Timing (Write) (TA = –40°C to +105°C, VCC = 5.0 V ± 10 %, VSS = 0.0 V, fCP ≤ 24 MHz) Parameter Symbol Pin A21 to A16, AD15 to AD00, WR WR AD15 to AD00, WR AD15 to AD00, WR A21 to A16, WR WR, ALE WR, CLK Condition Value Min tCP−15
(n*+3/2)tCP − 20 (n*+3/2)tCP − 20
Max ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Unit
Valid address → WR ↓ time WR pulse width Valid data output → WR ↑ time WR ↑ → Data hold time WR ↑ → Address valid time WR ↑ → ALE ↑ time WR ↓ → CLK ↑ time * : Number of ready cycles
tAVWL tWLWH tDVWH tWHDX tWHAX tWHLH tWLCH
ns ns ns ns ns ns ns
⎯ 15 tCP/2 − 10 tCP/2 − 15 tCP/2 − 15
For 1 cycle of auto-ready
tWLCH 2.4 V
CLK
tWHLH
ALE
tAVWL tWLWH 2.4 V 0.8 V
2.4 V
WR (WRL, WRH)
tWHAX
A21 to A16
2.4 V 0.8 V tDVWH
2.4 V 0.8 V tWHDX 2.4 V Write data 0.8 V
AD15 to AD00
2.4 V 0.8 V
2.4 V Address 0.8 V
66
MB90350E Series
(7) Ready Input Timing (TA = –40°C to +105°C, VCC = 5.0 V ± 10 %, VSS = 0.0 V, fCP ≤ 24 MHz) Parameter RDY set-up time RDY hold time Symbol tRYHS tRYHH Pin RDY RDY Condition Value Min 45 ⎯ 32 0 Max ⎯ ⎯ ⎯ Units ns ns ns Remarks fCP = 16 MHz fCP = 24 MHz
Note : If the RDY set-up time is insufficient, use the auto-ready function.
CLK
2.4 V
ALE
RD/WR
tRYHS tRYHH VIH
RDY (When WAIT is not used.)
VIH
RDY (When WAIT is used.)
VIL
67
MB90350E Series
(8) Hold Timing (TA = –40°C to +105°C, VCC = 5.0 V ± 10 %, VSS = 0.0 V, fCP ≤ 24 MHz) Parameter Pin floating → HAK ↓ time HAK ↑ time → Pin valid time Symbol tXHAL tHAHV Pin HAK ⎯ HAK tCP 2 tCP ns Condition Value Min 30 Max tCP Units ns
Note : There is more than 1 machine cycle from when HRQ pin reads in until the HAK is changed.
HAK 0.8 V tXHAL Each pin 2.4 V 0.8 V Hi-Z
2.4 V
tHAHV 2.4 V 0.8 V
68
MB90350E Series
(9) UART 2/3 (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin SCK2, SCK3 SCK2, SCK3, SOT2, SOT3 SCK2, SCK3, SIN2, SIN3 SCK2, SCK3, SIN2, SIN3 SCK2, SCK3 SCK2, SCK3 SCK2, SCK3, SOT2, SOT3 SCK2, SCK3, SIN2, SIN3 SCK2, SCK3, SIN2, SIN3 External shift clock mode output pins are CL = 80 pF + 1 TTL Condition Value Min 8 tCP* −80 Internal shift clock mode output pins are CL = 80 pF + 1 TTL 100 60 4 tCP 4 tCP ⎯ 60 60 Max ⎯ +80 ⎯ ⎯ ⎯ ⎯ 150 ⎯ ⎯ Unit ns ns ns ns ns ns ns ns ns
* : Refer to “ (1) Clock timing” rating for tCP (internal operating clock cycle time). Notes : • AC characteristic in CLK synchronous mode. • CL is load capacity value of pins when testing.
• Internal Shift Clock Mode
tSCYC SCK 2.4 V 0.8 V tSLOV SOT 2.4 V 0.8 V tIVSH SIN VIH VIL tSHIX VIH VIL 0.8 V
69
MB90350E Series
• External Shift Clock Mode
tSLSH SCK VIL tSLOV SOT 2.4 V 0.8 V tIVSH SIN VIH VIL tSHIX VIH VIL VIL VIH tSHSL VIH
(10) Trigger Input Timing (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Value Pin Condition Unit Min Max INT8 to INT15, INT9R to INT11R, ADTG ⎯ 5 tCP ⎯ ns
Parameter Input pulse width
Symbol tTRGH tTRGL
VIH
VIH VIL tTRGH tTRGL VIL
INT8 to INT15, INT9R to INT11R, ADTG
70
MB90350E Series
(11) Timer Related Resource Input Timing (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Value Parameter Symbol Pin Condition Unit Min Max Input pulse width tTIWH tTIWL TIN1, TIN3,IN0, IN1, IN4 to IN7 ⎯ 4 tCP ⎯ ns
VIH
VIH VIL tTIWH tTIWL VIL
TIN1, TIN3, IN0, IN1, IN4 to IN7
(12) Timer Related Resource Output Timing (TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Value Parameter Symbol Pin Condition Unit Min Max CLK ↑ → TOUT change time tTO TOT1, TOT3, PPG4, PPG6, PPG8 to PPGF ⎯ 30 ⎯ ns
CLK
2.4 V
TOT1, TOT3, PPG4, PPG6 PPG8 to PPGF
tTO
2.4 V 0.8 V
71
MB90350E Series
(13) I2C Timing (TA = −40 °C to +125 °C, VCC = AVCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Standard-mode Fast-mode*4 Parameter Symbol Condition Unit Min Max Min Max SCL clock frequency Hold time for (repeated) START condition SDA ↓ → SCL ↓ “L” width of the SCL clock “H” width of the SCL clock Set-up time for a repeated START condition SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data set-up time SDA ↓ ↑ → SCL ↑ Set-up time for STOP condition SCL ↑ → SDA ↑ Bus free time between STOP condition and START condition fSCL tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tSUSTO tBUS R = 1.7 kΩ, C = 50 pF*1 0 4.0 4.7 4.0 4.7 0 250*5 4.0 4.7 100 ⎯ ⎯ ⎯ ⎯ 3.45*2 ⎯ ⎯ ⎯ 0 0.6 1.3 0.6 0.6 0 100*5 0.6 1.3 400 ⎯ ⎯ ⎯ ⎯ 0.9*3 ⎯ ⎯ ⎯ kHz µs µs µs µs µs ns µs µs
*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum tHDDAT has to meet at least that the device does not exceed the “L” width (tLOW) of the SCL signal. *3 : A Fast-mode I2C -bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT ≥ 250 ns must be met. *4 : For use at over 100 kHz, set the machine clock to at least 6 MHz. *5 : Refer to “• Note of SDA, SCL set-up time”.
• Note of SDA, SCL set-up time
SDA
Input data set-up time
SCL
6 tCP
72
MB90350E Series
Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on the load capacitance or pull-up resistor. Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be satisfied. • Timing definition
SDA tBUS tLOW SCL tHDSTA tHIGH tHDDAT fSCL tSUSTA tSUSTO tSUDAT tHDSTA
73
MB90350E Series
5. A/D Converter
(TA = −40 °C to +125 °C, 3.0 V ≤ AVRH, VCC = AVCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V) Parameter Resolution Total error Nonlinearity error Differential nonlinearity error Zero reading voltage Full scale reading voltage Compare time Sampling time Analog port input current Analog input voltage range Reference voltage range Power supply current Reference voltage supply current Offset between channels Symbol ⎯ ⎯ ⎯ ⎯ VOT VFST ⎯ ⎯ IAIN VAIN ⎯ IA IAH IR IRH ⎯ Pin ⎯ ⎯ ⎯ ⎯ Value Min ⎯ ⎯ ⎯ ⎯ Typ ⎯ ⎯ ⎯ ⎯ AVSS + 0.5 Max 10 ±3.0 ±2.5 ±1.9 AVSS + 2.5 Unit bit LSB LSB LSB V V µs µs µA V V mA µA µA µA LSB * * 4.5 V ≤ AVCC ≤ 5.5 V 4.0 V ≤ AVCC < 4.5 V 4.5 V ≤ AVCC ≤ 5.5 V 4.0 V ≤ AVCC < 4.5 V Remarks
AN0 to AN14 AVSS − 1.5
AN0 to AN14 AVRH − 3.5 AVRH − 1.5 AVRH + 0.5 ⎯ ⎯ AN0 to AN14 AN0 to AN14 AVRH AVCC AVCC AVRH AVRH AN0 to AN14 1.0 2.0 0.5 1.2 − 0.3 AVSS AVSS + 2.7 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 3.5 ⎯ 600 ⎯ ⎯ 16500
∞
+ 0.3 AVRH AVCC 7.5 5 900 5 4
* : If A/D converter is not operating, a current when CPU is stopped is applicable (VCC = AVCC = AVRH = 5.0 V) .
74
MB90350E Series
Notes on A/D Converter Section • About the external impedance of the analog input and its sampling time A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. Therefore to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
· Analog input equivalence circuit R Analog input C Comparator
ON at sampling
MB90F351E(S), MB90F352E(S), MB90F356E(S), MB90F357E(S), MB90F351TE(S), MB90F352TE(S),MB90F356TE(S), MB90F357TE(S)
R 4.5 V ≤ AVCC ≤ 5.5 V 2.0 kΩ (Max) 4.0 V ≤ AVCC ≤ 4.5 V 8.2 kΩ (Max)
MB90V340E-101/102/103/104, MB90351E(S), MB90352E(S),MB90356E(S), MB90357E(S), MB90351TE(S), MB90352TE(S),MB90356TE(S), MB90357TE(S)
C 16.0 pF (Max) 16.0 pF (Max)
Note : The value is reference value.
4.5 V ≤ AVCC ≤ 5.5 V 4.0 V ≤ AVCC ≤ 4.5 V
R 2.0 kΩ (Max) 8.2 kΩ (Max)
C 14.4 pF (Max) 14.4 pF (Max)
75
MB90350E Series
• Flash memory device
· Relation between External impedance and minimum sampling time (MB90F351E(S), MB90F352E(S), MB90F356E(S), MB90F357E(S), MB90F351TE(S), MB90F352TE(S),MB90F356TE(S), MB90F357TE(S)) [External impedance = 0 kΩ to 100 kΩ]
100 90
[External impedance = 0 kΩ to 20 kΩ]
20 18
4.5 V ≤ AVCC ≤ 5.5 V External impedance [kΩ]
4.5 V ≤ AVCC ≤ 5.5 V
External impedance [kΩ]
80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35
16 14 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8
4.0 V ≤ AVCC ≤ 4.5 V
4.0 V ≤ AVCC ≤ 4.5 V
Minimum sampling time [µs]
• MASK ROM device
Minimum sampling time [µs]
· Relation between External impedance and minimum sampling time (MB90V340E-101/102/103/104, MB90351E(S), MB90352E(S), MB90356E(S), MB90357E(S), MB90351TE(S), MB90352TE(S), MB90356TE(S), MB90357TE(S)) [External impedance = 0 kΩ to 100 kΩ]
100
[External impedance = 0 kΩ to 20kΩ]
20
4.5 V ≤ AVCC ≤ 5.5 V External impedance [kΩ]
4.5 V ≤ AVCC ≤ 5.5 V
External impedance [kΩ]
90 80 70 60 50 40 30 20 10 00 5 10 15 20 25 30 35
18 16 14 12 10 8 6 4 2 00 1 2 3 4 5 6 7 8
4.0 V ≤ AVCC ≤ 4.5 V
4.0 V ≤ AVCC ≤ 4.5 V
Minimum sampling time [µs]
Minimum sampling time [µs]
• About the error Values of relative errors grow larger, as |AVRH − AVSS| becomes smaller.
76
MB90350E Series
6. Definition of A/D Converter Terms
Resolution Non linearity error Differential linearity error Total error : Analog variation that is recognized by an A/D converter. : Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” ) and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion characteristics. : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. : Difference between an actual value and a theoretical value. A total error includes zero transition error, full-scale transition error, and linear error.
Total error
3FFH 3FEH 3FDH Digital output {1 LSB × (N − 1) + 0.5 LSB} Actual conversion characteristics 1.5 LSB
004H 003H 002H 001H 0.5 LSB AVSS Analog input
VNT (Actual measurement value) Actual conversion characteristics Ideal characteristics
AVRH
Total error of digital output “N” =
VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVRH − AVSS 1 LSB (Ideal value) = [V] 1024
[LSB]
N VOT VFST VNT
: A/D converter digital output value (Ideal value) = AVSS + 0.5 LSB [V] (Ideal value) = AVRH − 1.5 LSB [V] : A voltage at which digital output transits from (N − 1) to N.
(Continued)
77
MB90350E Series
(Continued) Non linearity error
3FFH 3FEH 3FDH Digital output Actual conversion characteristics {1 LSB × (N − 1) + VOT } N + 1H VFST (actual measurement value) VNT (actual measurement value) Actual conversion characteristics Actual conversion characteristics
Differential linearity error
Ideal characteristics
Digital output
NH
004H 003H 002H
N − 1H
V (N + 1) T (actual measurement value) VNT (actual measurement value) Actual conversion characteristics AVRH Analog input
Ideal characteristics 001H VOT (actual measurement value) AVSS Analog input AVRH
N − 2H
AVSS
Non linearity error of digital output N = Differential linearity error of digital output N = 1 LSB =
VNT − {1 LSB × (N − 1) + VOT} 1 LSB V (N+1) T − VNT 1 LSB VFST − VOT 1022 −1 LSB [LSB] [V]
[LSB]
N : A/D converter digital output value VOT : Voltage at which digital output transits from “000H” to “001H”. VFST : Voltage at which digital output transits from “3FEH” to “3FFH”.
78
MB90350E Series
7. Flash Memory Program/Erase Characteristics
• Dual Operation Flash Memory Parameter Sector erase time (4 Kbytes sector) Sector erase time (16 Kbytes sector) Chip erase time Word (16-bit width) programming time Program/Erase cycle Flash memory Data Retention Time ⎯ Average TA = +85 °C TA = +25 °C VCC = 5.0 V Conditions Value Min ⎯ ⎯ ⎯ ⎯ 10000 20 Typ 0.2 0.5 4.6 64 ⎯ ⎯ Max 0.5 7.5 ⎯ 3600 ⎯ ⎯ Unit s s s µs cycle year * Remarks Excludes programming prior to erasure Excludes programming prior to erasure Excludes programming prior to erasure Except for the overhead time of the system level
* : Corresponding value comes from the technology reliability evaluation result. (Using Arrhenius equation to translate high temperature measurements test result into normalized value at +85 °C)
79
MB90350E Series
■ ORDERING INFORMATION
Part number MB90F351EPMC MB90F351ESPMC MB90F351TEPMC MB90F351TESPMC MB90F356EPMC MB90F356ESPMC MB90F356TEPMC MB90F356TESPMC MB90F352EPMC MB90F352ESPMC MB90F352TEPMC MB90F352TESPMC MB90F357EPMC MB90F357ESPMC MB90F357TEPMC MB90F357TESPMC MB90351EPMC MB90351ESPMC MB90351TEPMC MB90351TESPMC MB90356EPMC MB90356ESPMC MB90356TEPMC MB90356TESPMC MB90352EPMC MB90352ESPMC MB90352TEPMC MB90352TESPMC MB90357EPMC MB90357ESPMC MB90357TEPMC MB90357TESPMC (Continued) 64-pin plastic LQFP FPT-64P-M23 12.0 mm , 0.65 mm pitch MASK ROM products (128 Kbytes) 64-pin plastic LQFP FPT-64P-M23 12.0 mm , 0.65 mm pitch MASK ROM products (64 Kbytes) 64-pin plastic LQFP FPT-64P-M23 12.0 mm , 0.65 mm pitch Dual operation Flash memory products (128 Kbytes) 64-pin plastic LQFP FPT-64P-M23 12.0 mm , 0.65 mm pitch Dual operation Flash memory products (64 Kbytes) Package Remarks
80
MB90350E Series
(Continued) Part number MB90F351EPMC1 MB90F351ESPMC1 MB90F351TEPMC1 MB90F351TESPMC1 MB90F356EPMC1 MB90F356ESPMC1 MB90F356TEPMC1 MB90F356TESPMC1 MB90F352EPMC1 MB90F352ESPMC1 MB90F352TEPMC1 MB90F352TESPMC1 MB90F357EPMC1 MB90F357ESPMC1 MB90F357TEPMC1 MB90F357TESPMC1 MB90351EPMC1 MB90351ESPMC1 MB90351TEPMC1 MB90351TESPMC1 MB90356EPMC1 MB90356ESPMC1 MB90356TEPMC1 MB90356TESPMC1 MB90352EPMC1 MB90352ESPMC1 MB90352TEPMC1 MB90352TESPMC1 MB90357EPMC1 MB90357ESPMC1 MB90357TEPMC1 MB90357TESPMC1 MB90V340E-101 MB90V340E-102 MB90V340E-103 MB90V340E-104 299-pin ceramic PGA PGA-299C-A01 Device for evaluation 64-pin plastic LQFP FPT-64P-M24 10.0 mm , 0.50 mm pitch MASK ROM products (128 Kbytes) 64-pin plastic LQFP FPT-64P-M24 10.0 mm , 0.50 mm pitch MASK ROM products (64 Kbytes) 64-pin plastic LQFP FPT-64P-M24 10.0 mm , 0.50 mm pitch Dual operation Flash memory products (128 Kbytes) 64-pin plastic LQFP FPT-64P-M24 10.0 mm , 0.50 mm pitch Dual operation Flash memory products (64 Kbytes)
Package
Remarks
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MB90350E Series
■ PACKAGE DIMENSIONS
64-pin plastic LQFP Lead pitch Package width × package length Lead shape Sealing method Mounting height Code (Reference) 0.65 mm 12.0 × 12.0 mm Gullwing Plastic mold 1.70 mm MAX P-LFQFP64-12×12-0.65
(FPT-64P-M23)
64-pin plastic LQFP (FPT-64P-M23)
14.00±0.20(.551±.008)SQ *12.00±0.10(.472±.004)SQ
48 33
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
0.145±0.055 (.0057±.0022)
49
32
0.10(.004) Details of "A" part 1.50 –0.10 .059 –.004
+0.20 +.008
(Mounting height)
0.25(.010) INDEX 0~8˚
64 17
1
16
"A"
0.65(.026)
0.32±0.05 (.013±.002)
0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006)
0.10±0.10 (.004±.004) (Stand off)
0.13(.005)
M
C
2003 FUJITSU LIMITED F64034S-c-1-1
Dimensions in mm (inches). Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html (Continued)
82
MB90350E Series
(Continued)
64-pin plastic LQFP
Lead pitch Package width × package length Lead shape Sealing method Mounting height Weight
0.50 mm 10.0 × 10.0 mm Gullwing Plastic mold 1.70 mm MAX 0.32g P-LFQFP64-10×10-0.50
(FPT-64P-M24)
Code (Reference)
64-pin plastic LQFP (FPT-64P-M24)
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
* 10.00±0.10(.394±.004)SQ
48 33
0.145±0.055 (.006±.002)
49
32
Details of "A" part 0.08(.003) 1.50 –0.10 .059 –.004
+0.20 +.008
(Mounting height)
INDEX
64 17
0˚~8˚ "A" 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006)
0.10±0.10 (.004±.004) (Stand off)
0.25(.010)
LEAD No.
1
16
0.50(.020)
0.20±0.05 (.008±.002)
0.08(.003)
M
C
2005 FUJITSU LIMITED F64036S-c-1-1
Dimensions in mm (inches). Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
83
MB90350E Series
■ MAIN CHANGES IN THIS EDITION
Page ⎯ 1 2 13 ■DESCRIPTION ■FEATURES ■PACKAGES AND PRODUCT CORRESPONDENCE Section ⎯ Change Results Added the following part numbers.
MB90356E(S)/TE(S),MB90F356E(S)/TE(S), MB90357E(S)/TE(S), MB90F357E(S)/TE(S), MB90V340E-103/104)
Added a description of the "Clock supervisor". Added a description of the "Clock supervisor". Changed the description of "FPT-64P-M24" as follows: *→ Removed the table footnote "* : This device is under development."
27 40 56 57 58 81
■HANDLING DEVICES ■ I/O MAP ■ELECTRICAL CHARACTERISTICS 3. DC Characteristics
Added section "19.Internal CR oscillation circuit". Added the “Clock supervisor Control Register”. Added the ratings for the "Clock supervisor" to the "ICCL" section of the power supply current ratings. Added the ratings for the "Clock supervisor" to the "ICCLS" section of the power supply current ratings. Added the ratings for the "Clock supervisor" to the "ICCT" section of the power supply current ratings.
■ORDERING INFORMATION
Removed the footnote asterisks from the "Dual operation Flash memory products*" and "MASK ROM products*" of the "FPT-64P-M24" package. Removed the table footnote "* : This device is under development."
The vertical lines marked in the left side of the page show the changes.
84
MB90350E Series
The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept.
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