MB90F387S

FUJITSU SEMICONDUCTOR DATA SHEET DS07-13717-3E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90385 Series MB90387/387S/F387/F387S/MB90V495G s DESCRIPTION MB90385 series devices are general-purpose high-performance 16-bit micro controllers designed for process control of consumer products, which require high-speed real-time processing. The devices of this series have the built-in full-CAN interface. The system, inheriting the architecture of F2MC* family, employs additional instruction ready for high-level languages, expanded addressing mode, enhanced multiply-divide instructions, and enriched bit-processing instructions. Furthermore, employment of 32-bit accumulator achieves processing of long-word data (32 bits). The peripheral resources of MB90385 series include the following: 8/10-bit A/D converter, UART (SCI), 8/16-bit PPG timer, 16-bit input-output timer (16-bit free-run timer, input capture 0, 1, 2, 3 (ICU)), and CAN controller. *: “F2MC”, an abbreviation for FUJITSU Flexible Microcontroller, is a registered trademark of FUJITSU Ltd. s FEATURES • Clock • Built-in PLL clock frequency multiplication circuit • Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and multiplication of 1 to 4 times of oscillation clock (for 4-MHz oscillation clock, 4 MHz to 16 MHz). • Operation by sub-clock (8.192 kHz) is allowed. • Minimum execution time of instruction: 62.5 ns (when operating with 4-MHz oscillation clock, and 4-time multiplied PLL clock). (Continued) 48-pin plastic-LQFP s PACKAGE (FPT-48P-M26) MB90385 Series • 16 Mbyte CPU memory space • 24-bit internal addressing • Instruction system best suited to controller • Wide choice of data types (bit, byte, word, and long word) • Wide choice of addressing modes (23 types) • Enhanced multiply-divide instructions and RETI instructions • Enhanced high-precision computing with 32-bit accumulator • Instruction system compatible with high-level language (C language) and multitask • Employing system stack pointer • Enhanced various pointer indirect instructions • Barrel shift instructions • Increased processing speed • 4-byte instruction queue • Powerful interrupt function with 8 levels and 34 factors • Automatic data transfer function independent of CPU • Expanded intelligent I/O service function (EI2 OS): Maximum of 16 channels • Low power consumption (standby) mode • Sleep mode (a mode that halts CPU operating clock) • Time-base timer mode (a mode that operates oscillation clock, sub clock, time-base timer and clock timer only) • Clock mode (a mode that operates sub clock and clock timer only) • Stop mode (a mode that stops oscillation clock and sub clock) • CPU blocking operation mode • Process • CMOS technology • I/O port • General-purpose input/output port (CMOS output) : MB90387, MB90F387 : 34 ports (including 4 high-current output ports) MB90387S, MB90F387S : 36 ports (including 4 high-current output ports) • Timer • Time-base timer, clock timer, watchdog timer: 1 channel • 8/16-bit PPG timer: 8-bit x 4 channels, or 16-bit x 2 channels • 16-bit reload timer: 2 channels • 16-bit input/output timer - 16-bit free run timer: 1 channel - 16-bit input capture: (ICU): 4 channels Interrupt request is issued upon latching a count value of 16-bit free run timer by detection of an edge on pin input. • CAN controller: 1 channel • Compliant with Ver2.0A and Ver2.0B CAN specifications • 8 built-in message buffers • Transmission rate of 10 Kbps to 1 Mbps (by 16 MHz machine clock) • CAN wake-up • UART (SCI): 1 channel • Equipped with full-duplex double buffer • Clock-asynchronous or clock-synchronous serial transmission is available. (Continued) 2 MB90385 Series (Continued) • DTP/External interrupt: 4 channels, CAN wakeup: 1channel • Module for activation of expanded intelligent I/O service (EI2OS), and generation of external interrupt. • Delay interrupt generator module • Generates interrupt request for task switching. • 8/10-bit A/D converter: 8 channels • Resolution is selectable between 8-bit and 10-bit. • Activation by external trigger input is allowed. • Conversion time: 6.125 µs (at 16-MHz machine clock, including sampling time) • Program patch function • Address matching detection for 2 address pointers. 3 MB90385 Series s PRODUCT LINEUP Part Number Parameter Classification ROM capacity RAM capacity Process Package Operating power supply voltage Special power supply for emulator*1 3.5 V to 5.5 V  Number of basic instructions Instruction bit length Instruction length Data bit length : 351 instructions : 8 bits and 16 bits : 1 byte to 7 bytes : 1 bit, 8 bits, 16 bits MB90F387/S Flash ROM 64 Kbytes 2 Kbytes CMOS LQFP-48 (0.50 mm width) PGA256 4.5 V to 5.5 V None MB90387/S Mask ROM MB90V495G Evaluation product  6 Kbytes CPU functions Minimum instruction execution time : 62.5 ns (at 16-MHz machine clock) Interrupt processing time : 1.5 µs at minimum (at 16-MHz machine clock) Low power consumption (standby) mode I/O port Sleep mode/Clock mode/Time-base timer mode/ Stop mode/CPU intermittent General-purpose input/output ports (CMOS output) : 34 ports (36 ports*2) including 4 high-current output ports (P14 to P17) 18-bit free-run counter Interrupt cycle : 1.024 ms, 4.096 ms, 16.834 ms, 131.072 ms (with oscillation clock frequency at 4 MHz) Reset generation cycle: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (with oscillation clock frequency at 4 MHz) 16-bit free-run timer Input capture Number of channels: 1 Interrupt upon occurrence of overflow Number of channels: 4 Retaining free-run timer value set by pin input (rising edge, falling edge, and both edges) Number of channels: 2 16-bit reload timer operation Count clock cycle: 0.25 µs, 0.5 µs, 2.0 µs (at 16-MHz machine clock frequency) External event count is allowed. 15-bit free-run counter Interrupt cycle: 31.25 ms, 62.5 ms, 12 ms, 250 ms, 500 ms, 1.0 s, 2.0 s (with 8.192 kHz sub clock) Number of channels: 2 (four 8-bit channels are available also.) PPG operation is allowed with four 8-bit channels or one 16-bit channel. Outputting pulse wave of arbitrary cycle or arbitrary duty is allowed. Count clock: 62.5 ns to 1 µs (with 16 MHz machine clock) Time-base timer Watchdog timer 16-bit input/ output timer 16-bit reload timer Clock timer 8/16-bit PPG timer (Continued) 4 MB90385 Series (Continued) Part Number Parameter Delay interrupt generator module DTP/External interrupt MB90F387/S MB90387/S MB90V495G Interrupt generator module for task switching. Used for realtime OS. Number of inputs: 4 Activated by rising edge, falling edge, “H” level or “L” level input. External interrupt or expanded intelligent I/O service (EI2OS) is available. Number of channels: 8 Resolution: Selectable 10-bit or 8-bit. Conversion time: 6.125 µs (at 16-MHz machine clock, including sampling time) Sequential conversion of two or more successive channels is allowed. (Setting a maximum of 8 channels is allowed.) Single conversion mode : Selected channel is converted only once. Sequential conversion mode: Selected channel is converted repetitively. Halt conversion mode : Conversion of selected channel is stopped and activated alternately. Number of channels: 1 Clock-synchronous transfer: 62.5 Kbps to 2 Mbps Clock-asynchronous transfer: 9,615 bps to 500 Kbps Communication is allowed by bi-directional serial communication function and master/slave type connection. Compliant with Ver 2.0A and Ver 2.0B CAN specifications. 8 built-in message buffers. Transmission rate of 10 Kbps to 1 Mbps (by 16 MHz machine clock) CAN wake-up 8/10-bit A/D converter UART(SCI) CAN *1 : Settings of DIP switch S2 for using emulation pod MB2145-507. For details, see MB2145-507 Hardware Manual (2.7 Power Pin solely for Emulator). *2 : MB90387S, MB90F387S s PACKAGES AND PRODUCT MODELS Package FPT-48P-M26 : Yes × : No Note : Refer to PACKAGE DIMENSION for details of the package. MB90F387/S MB90387/S s PRODUCT COMPARISON Memory space When testing with test product for evaluation, check the differences between the product and a product to be used actually. Pay attention to the following points: • The MB90V495G has no built-in ROM. However, a special-purpose development tool allows the operations as those of one with built-in ROM. ROM capacity depends on settings on a development tool. • On MB90V495G, an image from FF4000H to FFFFFFH is viewed on 00 bank and an image of FE0000H to FF3FFFH is viewed only on FE bank and FF bank. (Modified on settings of a development tool.) • On MB90F387/S/387/S, an image from FF4000H to FFFFFFH is viewed on 00 bank and an image of FE0000H to FF3FFFH is viewed only on FF bank. 5 MB90385 Series s PIN ASSIGNMENT (TOP VIEW) AVSS X1A/P36* X0A/P35* P33 P32 P31 P30 P44/RX P43/TX P42/SOT1 P41/SCK1 P40/SIN1 AVCC AVR P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 P37/ADTG P20/TIN0 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 * : MB90387, MB90F387 : X1A, X0A MB90387S, MB90F387S: P36, P35 6 P21/TOT0 P22/TIN1 P23/TOT1 P24/INT4 P25/INT5 P26/INT6 P27/INT7 MD2 MD1 MD0 RST VCC 13 14 15 16 17 18 19 20 21 22 23 24 P17/PPG3 P16/PPG2 P15/PPG1 P14/PPG0 P13/IN3 P12/IN2 P11/IN1 P10/IN0 X1 X0 C VSS (FPT-48P-M26) MB90385 Series s PIN DESCRIPTION Pin No. 1 2 3 to 10 Pin name AVcc AVR P50 to P57 AN0 to AN7 P37 11 ADTG P20 12 TIN0 P21 13 TOT0 P22 14 TIN1 P23 15 TOT1 P24 to P27 INT4 to INT7 MD2 MD1 MD0 RST Vcc Vss C X0 X1 P10 to P13 29 to 32 IN0 to IN3 D D D D D D E Circuit type   Function Vcc power input pin for A/D converter. Power (Vref+) input pin for A/D converter. Use as input for Vcc or lower. General-purpose input/output ports. Functions as analog input pin for A/D converter. Valid when analog input setting is “enabled.” General-purpose input/output ports. Function as an external trigger input pin for A/D converter. Use the pin by setting as input port. General-purpose input/output ports. Function as an event input pin for reload timer 0. Use the pin by setting as input port. General-purpose input/output ports. Function as an event output pin for reload timer 0. Valid only when output setting is “enabled.” General-purpose input/output ports. Function as an event input pin for reload timer 1. Use the pin by setting as input port. General-purpose input/output ports. Function as an event output pin for reload timer 1. Valid only when output setting is “enabled.” General-purpose input/output ports. Functions as external interrupt input pin. Use the pin by setting as input port. 16 to 19 20 21 22 23 24 25 26 27 28 D F C C B    A A Input pin for specifying operation mode. Connect directly to Vss. Input pin for specifying operation mode. Connect directly to Vcc. Input pin for specifying operation mode. Connect directly to Vcc. External reset input pin. Power source (5 V) input pin. Power source (0 V) input pin. Capacitor pin for stabilizing power source. Connect a ceramic capacitor of approximately 0.1 µF. Pin for high-rate oscillation. Pin for high-rate oscillation. General-purpose input/output ports. Functions as trigger input pins of input capture channels 0 to 3. Use the pins by setting as input ports. (Continued) 7 MB90385 Series (Continued) Pin No. Pin name P14 to P17 33 to 36 PPG0 to PPG3 P40 SIN1 P41 38 SCK1 P42 39 SOT1 P43 40 TX P44 41 42 to 45 46 47 48 RX P30 to P33 X0A* P35* X1A* P36* AVss D D A A  D D D G Circuit type Function General-purpose input/output ports. High-current output ports. Functions as output pin of PPG timers 01 and 23. Valid when output setting is “enabled.” General-purpose input/output port. Serial data input pin for UART. Use the pin by setting as input port. General-purpose input/output port. Serial clock input pin for UART. Valid only when serial clock input/output setting on UART is “enabled.” General-purpose input/output port. Serial data input pin for UART. Valid only when serial data input/output setting on UART is “enabled.” General-purpose input/output port. Transmission output pin for CAN. Valid only when output setting is “enabled.” General-purpose input/output port. Transmission output pin for CAN. Valid only when output setting is “enabled.” General-purpose input/output ports. Pin for low-rate oscillation. General-purpose input/output port. Pin for low-rate oscillation. General-purpose input/output port. Vss power source input pin for A/D converter. 37 D * : MB90387, MB90F387 : X1A, X0A MB90387S, MB90F387S: P36, P35 8 MB90385 Series s I/O CIRCUIT TYPE Type Circuit Remarks • High-rate oscillation feedback resistor, approx.1 MΩ • Low-rate oscillation feedback resistor, approx.10 MΩ X1 A X1A X0 X0A Clock input Standby control signal Vcc B • Hysteresis input with pull-up resistor. • Pull-up resistor, approx.50 kΩ R R Hysteresis input • Hysteresis input C R Hysteresis input • CMOS hysteresis input • CMOS level output • Standby control provided Digital output Digital output Hysteresis input Standby control • • • • CMOS hysteresis input CMOS level output Shared for analog input pin Standby control provided Vcc Pch D R Nch Vss Vcc Pch Digital output Digital output Hysteresis input E R Nch Vss Standby control Analog input (Continued) 9 MB90385 Series (Continued) Type Circuit Remarks • Hysteresis input with pull-down resistor • Pull-down resistor, approx. 50 kΩ • FLASH product is not provided with pull-down resistor. R Hysteresis input F R Vss Vcc Pch High-current output High-current output • CMOS hysteresis input • CMOS level output (high-current output) • Standby control provided G R Nch Vss Hysteresis input Standby control 10 MB90385 Series s HANDLING DEVICES • Do Not Exceed Maximum Rating (preventing “latch up”) • On a CMOS IC, latch-up may occur when applying a voltage higher than Vcc or a voltage lower than Vss to input or output pin, which has no middle or high withstand voltage. Latch-up may also occur when a voltage exceeding maximum rating is applied across Vcc and Vss. • Latch-up causes drastic increase of power current, which may lead to destruction of elements by heat. Extreme caution must be taken not to exceed maximum rating. • When turning on and off analog power source, take extra care not to apply an analog power voltages (AVcc and AVR) and analog input voltage that are higher than digital power voltage (Vcc). • Handling Unused Pins • Leaving unused input pins open may cause permanent destruction by malfunction or latch-up. Apply pull-up or pull-down process to the unused pins using resistors of 2 kΩ or higher. Leave unused input pins open under output status, or process as input pins if they are under input status. • Using External Clock • When using an external clock, drive only X0 pin and leave X1 pin open. An example of using an external clock is shown below. • Using external clock X0 Open X1 MB90385 series • Notes When Using No Sub Clock • If an oscillator is not connected to X0A and X1A pin, apply pull-down resistor to X0A pin and leave X1A pin open. • About Power Supply Pins • If two or more Vcc and Vss exist, the pins that should be at the same potential are connected to each other inside the device. For reducing unwanted emissions and preventing malfunction of strobe signals caused by increase of ground level, however, be sure to connect the Vcc and Vss pins to the power source and the ground externally. • Pay attention to connect a power supply to Vcc and Vss of MB90385 series device in a lowest-possible impedance. • Near pins of MB90385 series device, connecting a bypass capacitor is recommended at 0.1 µF across Vcc and Vss. • Crystal Oscillator Circuit • Noises around X0 and X1 pins cause malfunctions on a MB90385 series device. Design a print circuit so that X0 and X1 pins, an crystal oscillator (or a ceramic oscillator), and bypass capacitor to the ground become as close as possible to each other. Furthermore, avoid wires to X0 and X1 pins crossing each other as much as possible. • Print circuit designing that surrounds X0 and X1 pins with grounding wires, which ensures stable operation, is strongly recommended. • Caution on Operations during PLL Clock Mode • If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. 11 MB90385 Series • Sequence of Turning on Power of A/D Converter and Applying Analog Input • Be sure to turn on digital power (Vcc) before applying signals to the A/D converter and applying analog input signals (AN0 to AN7 pins). • Be sure to turn off the power of A/D converter and analog input before turning off the digital power source. • Be sure not to apply AVR exceeding AVcc when turning on and off. (No problems occur if analog and digital power is turned on and off simultaneously.) • Handling Pins When A/D Converter is Not Used • If the A/D converter is not used, connect the pins under the following conditions: “AVcc=AVR=Vcc,” and “AVss=Vss” • Note on Turning on Power • For preventing malfunctions on built-in step-down circuit, maintain a minimum of 50 µs of voltage rising time (between 0.2 V and 2.7V) when turning on the power. • Stabilization of supply voltage • A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply voltage operating range. Therefore, the VCC supply voltage should be stabilized. For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values) at commercial frequencies (50 Hz to 60 Hz) fall below 10% of the standard VCC supply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching. 12 MB90385 Series s BLOCK DIAGRAM X0,X1 RST X0A,X1A Clock control circuit Clock timer Time-base timer CPU F2MC-16LX core 16-bit free-run timer Input capture (4ch) IN0 to IN3 RAM ROM/FLASH 16-bit PPG timer (2ch) Internal data bus PPG0 to PPG3 Prescaler SOT1 SCK1 SIN1 CAN RX TX UART1 DTP/External interrupt AVcc AVss AN0 to AN7 AVR ADTG INT4 to INT7 8/10-bit A/D converter (8ch) 16-bit reload timer (2ch) TIN0,TIN1 TOT0,TOT1 13 MB90385 Series s MEMORY MAP MB90385 series allows specifying a memory access mode “single chip mode.” 1. Memory allocation of MB90385 MB90385 series model has 24-bit wide internal address bus and up to 24-bit bus of external address bus. A maximum of 16 Mbyte memory space of external access memory is accessible. 2. Memory map (with ROM mirroring function enabled) 000000H 0000C0H 000100H Peripheral RAM area Register Address #1 003800H 004000H 010000H FE0000H Extension IO area ROM area (FF bank image) ROM area* FF0000H FFFFFFH ROM area Model MB90V495G MB90F387/S MB90387/S Address #1 001900 H 000900 H 000900 H : Internal access memory : Access disallowed * : On MB90387/S or MB90F387/S, to read “FE0000H” to “FEFFFFH” is to read out “FF0000H” to “FFFFFFH”. Note : When internal ROM is operating, F2MC-16LX allows viewing ROM data image on FF bank at upper-level of 00 bank. This function is called “mirroring ROM,” which allows effective use of C compiler small model. F2MC-16LX assigns the same low order 16-bit address to FF bank and 00 bank, which allows referencing table in ROM without specifying “far” using pointer. For example, when accessing to “00C000H”, ROM data at “FFC000H” is accessed actually. However, because ROM area of FF bank exceeds 48 Kbytes, viewing all areas is not possible on 00 bank image. Because ROM data of “FF4000H” to “FFFFFFH” is viewed on “004000H” to “00FFFFH” image, store a ROM data table in area “FF4000H” to “FFFFFFH.” 14 MB90385 Series s I/O MAP Register Address abbreviation Register Read/ Write (Reserved area) * R/W R/W R/W R/W R/W (Reserved area) * Resource Initial value 000000H 000001H 000002H 000003H 000004H 000005H 000006H to 000010H 000011H 000012H 000013H 000014H 000015H 000016H to 00001AH 00001BH 00001CH to 000025H 000026H 000027H 000028H 000029H 00002AH 00002BH 00002CH to 00002FH 000030H 000031H 000032H 000033H ENIR EIRR ELVR CDCR1 SMR1 SCR1 SIDR1/ SODR1 SSR1 Serial mode register 1 Serial control register 1 ADER DDR1 DDR2 DDR3 DDR4 DDR5 PDR1 PDR2 PDR3 PDR4 PDR5 Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 1 Port 2 Port 3 Port 4 Port 5 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Port 1 direction data register Port 2 direction data register Port 3 direction data register Port 4 direction data register Port 5 direction data register R/W R/W R/W R/W R/W Port 1 Port 2 Port 3 Port 4 Port 5 00000000B 00000000B 000X0000B XXX00000B 00000000B (Reserved area) * 8/10-bit A/D converter Analog input permission register R/W 11111111B (Reserved area) * R/W R/W, W R, W R, R/W (Reserved area) * Communication prescaler control register 1 R/W UART1 0XXX0000B UART1 00000000B 00000100B XXXXXXXXB 00001000B Serial input data register 1/ Serial output data register 1 Serial status data register 1 (Reserved area) * DTP/External interrupt permission register DTP/External interrupt permission register Detection level setting register R/W R/W R/W R/W DTP/External interrupt 00000000B XXXXXXXXB 00000000B 00000000B (Continued) 15 MB90385 Series Register Address abbreviation Register A/D control status register A/D data register Read/ Write R/W R/W, W W, R R (Reserved area) * Resource Initial value 00000000B 000034H 000035H 000036H 000037H 000038H to 00003FH 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H to 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H 000059H 00005AH 00005BH 00005CH 00005DH ADCS ADCR 8/10-bit A/D converter 00000000B XXXXXXXXB 00101XXXB PPGC0 PPGC1 PPG01 PPG0 operation mode control register PPG1 operation mode control register PPG0/1 count clock selection register PPG2 operation mode control register PPG3 operation mode control register PPG2/3 count clock selection register R/W, W R/W, W R/W 8/16-bit PPG timer 0/1 0X000XX1B 0X000001B 000000XXB (Reserved area) * PPGC2 PPGC3 PPG23 R/W, W R/W, W R/W 8/16-bit PPG timer 2/3 0X000XX1B 0X000001B 000000XXB (Reserved area) * XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 16-bit input/output timer 00000000B 00000000B 00000000B 00000000B 00000000B XXXXXXXXB 16-bit input/output timer IPCP3 Input capture data register 3 R XXXXXXXXB XXXXXXXXB XXXXXXXXB IPCP0 IPCP1 ICS01 ICS23 TCDT TCCS Input capture data register 0 Input capture data register 1 Input capture control status register Timer counter data register Timer counter control status register R R R/W R/W R/W (Reserved area) * IPCP2 Input capture data register 2 R (Continued) 16 MB90385 Series Register Address abbreviation Register Read/ Write (Reserved area) * R/W Resource Initial value 00005EH to 000065H 000066H 000067H 000068H 000069H 00006AH to 00006EH 00006FH 000070H to 00007FH 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH to 00009DH 00009EH 00009FH PACSR DIRR RIER ROVRR Receive overrun register RRTRR Receive RTR register RCR Receive completion register TCR Send completion register TCANR Send cancel register TREQR Send request register BVALR ROMM TMCSR0 Timer control status register TMCSR1 R/W R/W R/W (Reserved area) * 16-bit reload timer 0 16-bit reload timer 1 00000000B XXXX0000B 00000000B XXXX0000B ROM mirroring function selection register W ROM mirroring function selection module XXXXXXX1B (Reserved area) * Message buffer enabling register R/W R/W (Reserved area) * W (Reserved area) * R/W (Reserved area) * R/W (Reserved area) * R/W (Reserved area) * R/W (Reserved area) * Receive completion interrupt permission register R/W CAN controller 00000000B CAN controller 00000000B CAN controller 00000000B CAN controller 00000000B CAN controller 00000000B CAN controller 00000000B CAN controller CAN controller 00000000B 00000000B (Reserved area) * (Reserved area) * Address matching detection function Delay interrupt generation module Address detection control register Delay interrupt request generation/ release register R/W R/W 00000000B XXXXXXX0B (Continued) 17 MB90385 Series Register Address abbreviation Register Lower power consumption mode control register Clock selection register Read/ Write W,R/W R,R/W (Reserved area) * Resource Lower power consumption mode Clock Initial value 00011000B 11111100B 0000A0H 0000A1H 0000A2H to 0000A7H 0000A8H 0000A9H 0000AAH 0000ABH to 0000ADH 0000AEH 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H to 0000FFH LPMCR CKSCR WDTC TBTC WTC Watchdog timer control register Time-base timer control register Clock timer control register R,W R/W,W R,R/W Watchdog timer Time-base timer Clock timer XXXXX111B 1XX00100B 1X001000B (Reserved area) * Flash memory control status register Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 (Reserved area) * R/W Interrupt controller 512k-bit flash memory FMCS R,W,R/W 000X0000B (Reserved area) * ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B (Continued) 18 MB90385 Series Register Address abbreviation Register Detection address setting register 0 (low-order) Read/ Write Resource Initial value XXXXXXXXB 001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H 003900H 003901H 003902H 003903H 003904H to 00390FH 003910H 003911H 003912H 003913H 003914H 003915H 003916H 003917H 003918H to 00392FH 003930H to 003BFFH 003C00H to 003C0FH PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 TMR0/ TMRLR0 TMR1/ TMRLR1 PADR1 PADR0 Detection address setting register 0 (middle-order) Detection address setting register 0 (high-order) Detection address setting register 1 (low-order) Detection address setting register 1 (middle-order) Detection address setting register 1 (high-order) 16-bit timer register 0/16-bit reload register 16-bit timer register 1/16-bit reload register R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Address matching detection function R/W R,W R,W 16-bit reload timer 0 16-bit reload timer 1 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Reserved area) * PPG0 reload register L PPG0 reload register H PPG1 reload register L PPG1 reload register H PPG2 reload register L PPG2 reload register H PPG3 reload register L PPG3 reload register H R/W R/W R/W R/W R/W R/W R/W R/W (Reserved area) * 8/16-bit PPG timer XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Reserved area) * RAM (General-purpose RAM) (Continued) 19 MB90385 Series Register Address abbreviation Register ID register 0 Read/ Write R/W Resource Initial value XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB 003C10H to 003C13H 003C14H to 003C17H 003C18H to 003C1BH 003C1CH to 003C1FH 003C20H to 003C23H 003C24H to 003C27H 003C28H to 003C2BH 003C2CH to 003C2FH 003C30H 003C31H 003C32H 003C33H 003C34H 003C35H 003C36H 003C37H 003C38H 003C39H 003C3AH 003C3BH IDR0 IDR1 ID register 1 R/W IDR2 ID register 2 R/W IDR3 ID register 3 R/W IDR4 ID register 4 R/W IDR5 ID register 5 R/W CAN controller IDR6 ID register 6 R/W XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB IDR7 DLCR0 DLCR1 DLCR2 DLCR3 DLCR4 DLCR5 ID register 7 DLC register 0 DLC register 1 DLC register 2 DLC register 3 DLC register 4 DLC register 5 R/W R/W R/W R/W R/W R/W R/W (Continued) 20 MB90385 Series Address 003C3CH 003C3DH 003C3EH 003C3FH 003C40H to 003C47H 003C48H to 003C4FH 003C50H to 003C57H 003C58H to 003C5FH 003C60H to 003C67H 003C68H to 003C6FH 003C70H to 003C77H 003C78H to 003C7FH 003C80H to 003CFFH 003D00H 003D01H 003D02H 003D03H 003D04H 003D05H 003D06H 003D07H 003D08H 003D09H 003D0AH Register abbreviation Register DLC register 6 DLC register 7 Data register 0 Read/ Write R/W R/W R/W Resource Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB DLCR6 DLCR7 DTR0 DTR1 Data register 1 R/W DTR2 Data register 2 R/W CAN controller DTR3 Data register 3 R/W XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB DTR4 Data register 4 R/W DTR5 Data register 5 R/W DTR6 Data register 6 R/W DTR7 Data register 7 R/W (Reserved area) * CSR LEIR Control status register Last event display register R/W, R R/W (Reserved area) * RTEC BTR IDER TRTRR Send/receive error counter Bit timing register IDE register Send RTR register R R/W R/W (Reserved area) * R/W CAN controller 00000000B CAN controller 00000000B 00000000B 11111111B X1111111B XXXXXXXXB 0XXXX001B 00XXX000B 000XX000B CAN controller (Continued) 21 MB90385 Series (Continued) Register Address abbreviation Register Read/ Write (Reserved area) * R/W Resource Initial value 003D0BH 003D0CH 003D0DH 003D0EH 003D0FH 003D10H 003D11H 003D12H 003D13H 003D14H to 003D17H 003D18H to 003D1BH 003D1CH to 003DFFH 003E00H to 003EFFH 003FF0H to 003FFFH Initial values : 0 : Initial value of this bit is “0.” 1 : Initial value of this bit is “1.” X : Initial value of this bit is undefined. AMR0 Acceptance mask register 0 AMSR TIER Send completion interrupt permission register RFWTR Remote frame receive wait register CAN controller XXXXXXXXB (Reserved area) * R/W (Reserved area) * Acceptance mask selection register R/W CAN controller XXXXXXXXB XXXXXXXXB CAN controller 00000000B (Reserved area) * R/W CAN controller AMR1 Acceptance mask register 1 R/W XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB (Reserved area) * (Reserved area) * (Reserved area) * * : “Reserved area” should not be written anything. Result of reading from “Reserved area” is undefined. 22 MB90385 Series s INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS Interrupt source Reset INT 9 instruction Exceptional treatment CAN controller reception completed (RX) CAN controller transmission completed (TX) / Node status transition (NS) Reserved Reserved CAN wakeup Time-base timer 16-bit reload timer 0 8/10-bit A/D converter 16-bit free-run timer overflow Reserved Reserved PPG timer ch0, ch1 underflow Input capture 0-input External interrupt (INT4/INT5) Input capture 1-input PPG timer ch2, ch3 underflow External interrupt (INT6/INT7) Clock timer Reserved Input capture 2-input Input capture 3-input Reserved Reserved Reserved Reserved Reserved 16-bit reload timer 1 EI2OS readiness Interrupt vector Number #08 #09 #10 #11 08H 09H 0AH 0BH Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H Interrupt control register ICR    Address    Priority*3 High ↑ × × × × × × × ∆ × ∆ ∆ ∆ × × × ∆ ∆ ∆ × ∆ ∆ × × × × × × × ICR00 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH ICR09 0000B0H*1 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 0000B1H 0000B2H*1 0000B3H*1 0000B4H*1 0000B5H*2 0000B6H*1 0000B7H*1 0000B8H*1 0000B9H*1 ICR10 ICR11 ICR12 0000BAH*1 0000BBH*1 0000BCH*1 ↓ Low (Continued) 23 MB90385 Series (Continued) Interrupt source UART1 reception completed UART1 transmission completed Reserved Reserved Flash memory Delay interrupt generation module : Available × : Unavailable : Available El2OS function is provided. ∆ : Available when a cause of interrupt sharing a same ICR is not used. *1 : • Peripheral functions sharing an ICR register have the same interrupt level. • If peripheral functions share an ICR register, only one function is available when using expanded intelligent I/O service. • If peripheral functions share an ICR register, a function using expanded intelligent I/O service does not allow interrupt by another function. *2 : Only 16-bit reload timer is ready for EI2OS. Because PPG is not ready for EI2OS, disable PPG interrupt when using EI2OS with 16-bit reload timer. *3 : Priority when two or more interrupts of a same level occur simultaneously. ∆ × × × × EI2OS readiness Interrupt vector Number #37 #38 #39 #40 #41 #42 25H 26H 27H 28H 29H 2AH Address FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register ICR ICR13 ICR14 Address 0000BDH*1 0000BEH*1 Priority*3 High ↑ ICR15 0000BFH*1 ↓ Low 24 MB90385 Series s PERIPHERAL RESOURCES 1. I/O Ports The I/O ports are used as general-purpose input/output ports (parallel I/O ports). The MB60385 series model is provided with 5 ports (34 inputs). The ports function as input/output pins for peripheral functions also. • I/O port functions An I/O port, using port data resister (PDR), outputs the output data to I/O pin and input a signal input to I/O port. The port direction register (DDR) specifies direction of input/output of I/O pins on a bit-by-bit basis. The following summarizes functions of the ports and sharing peripheral functions : • Port 1 : General-purpose input/output port, used also for PPG timer output and input capture inputs. • Port 2 : General-purpose input/output port, used also for reload timer input/output and external interrupt input. • Port 3 : General-purpose input/output port, used also for A/D converter activation trigger pin. • Port 4 : General-purpose input/output port, used also for UART input/output and CAN controller send/receive pin. • Port 5 : General-purpose input/output port, used also analog input pin. • Port 1 pins block diagram (single-chip mode) Peripheral function input Peripheral function output Port data register (PDR) Peripheral function output permission PDR read Internal data bus Port 1 Output latch PDR write Port direction register (DDR) Direction latch Nch Pch Pin DDR write Standby control (SPL=1) DDR read Standby control : Control among Stop mode (SPL=1), Time-base timer mode (SPL=1), and clock mode (SPL=1). • Port 1 registers (single-chip mode) • Port 1 registers include port 1 data register (PDR1) and port 1 direction register (DDR1). • The bits configuring the register correspond to port 1 pins on a one-to-one basis. Relation between port 1 registers and pins Port name Bits of register and corresponding pins PDR1, DDR1 Corresponding pins bit7 P17 bit6 P16 bit5 P15 bit4 P14 bit3 P13 bit2 P12 bit1 P11 bit0 P10 25 MB90385 Series • Port 2 pins block diagram (general-purpose input/output port) Peripheral function input Peripheral function output Port data register (PDR) Peripheral function output permission PDR read Internal data bus Port 2 Output latch PDR write Port direction register (DDR) Direction latch Nch Pch Pin DDR write Standby control (SPL=1) DDR read Standby control : Control among Stop mode (SPL=1), Time-base timer mode (SPL=1), and clock mode (SPL=1). • Port 2 registers • Port 2 registers include port 2 data register (PDR2) and port 2 direction register (DDR2). • The bits configuring the register correspond to port 2 pins on a one-to-one basis. Relation between port 2 registers and pins Port name Bits of register and corresponding pins PDR2,DDR2 Corresponding pins bit7 P27 bit6 P26 bit5 P25 bit4 P24 bit3 P23 bit2 P22 bit1 P21 bit0 P20 26 MB90385 Series • Port 3 pins block diagram (general-purpose input/output port) Peripheral function input Peripheral function output Port data register (PDR) Peripheral function output permission PDR read Internal data bus Port 3 Output latch PDR write Port direction register (DDR) Direction latch Nch Pch Pin DDR write Standby control (SPL=1) DDR read Standby control : Control among Stop mode (SPL=1), Time-base timer mode (SPL=1), and clock mode (SPL=1). • Port 3 registers • Port 3 registers include port 3 data register (PDR3) and port 3 direction register (DDR3). • The bits configuring the register correspond to port 3 pins on a one-to-one basis. Relation between port 3 registers and pins Port name Bits of register and corresponding pins PDR3, DDR3 Corresponding pins bit7 P37 bit6 P36* bit5 P35* bit4  bit3 P33 bit2 P32 bit1 P31 bit0 P30 * : P35 and P36 do not exist on MB90387and MB90F387. 27 MB90385 Series • Port 4 pins block diagram Peripheral function input Peripheral function output Port data register (PDR) Peripheral function output permission PDR read Internal data bus Port 4 Output latch PDR write Port direction register (DDR) Direction latch Nch Pch Pin DDR write Standby control (SPL=1) DDR read Standby control : Control among Stop mode (SPL=1), Time-base timer mode (SPL=1), and clock mode (SPL=1). • Port 4 registers • Port 4 registers include port 4 data register (PDR4) and port 4 direction register (DDR4). • The bits configuring the register correspond to port 4 pins on a one-to-one basis. Relation between port 4 registers and pins Port name Bits of register and corresponding pins PDR4, DDR4 Corresponding pins       bit4 P44 bit3 P43 bit2 P42 bit1 P41 bit0 P40 28 MB90385 Series • Port 5 pins block diagram ADER Analog input Port data register (PDR) PDR read Internal data bus Output latch PDR write Port direction register (DDR) Direction latch Nch Pch Pin DDR write Standby control (SPL=1) DDR read Standby control: Control among Stop mode (SPL=1), Time-base timer mode (SPL=1), and clock mode (SPL=1). • Port 5 registers • Port 5 registers include port 5 data register (PDR5), port 5 direction register (DDR5), and analog input permission register (ADER). • Analog input permission register (ADER) allows or disallows input of analog signal to the analog input pin. • The bits configuring the register correspond to port 5 pins on a one-to-one basis. Relation between port 5 registers and pins Port name Bits of register and corresponding pins PDR5, DDR5 Port 5 ADER Corresponding pins bit7 ADE7 P57 bit6 ADE6 P56 bit5 ADE5 P55 bit4 ADE4 P54 bit3 ADE3 P53 bit2 ADE2 P52 bit1 ADE1 P51 bit0 ADE0 P50 29 MB90385 Series 2. Time-Base Timer The time-base time is an 18-bit free-run counter (time-base timer counter) that counts up in synchronization with the main clock (dividing main oscillation clock by 2). • Four choices of interval time are selectable, and generation of interrupt request is allowed for each interval time. • Provides operation clock signal to oscillation stabilizing wait timer and peripheral functions. • Interval timer function • When the counter of time-base timer reaches an interval time specified by interval time selection bit (TBTC:TBC1, TBC0), an overflow (carrying-over) occurs (TBTC: TBOF=1) and interrupt request is generated. • If an interrupt by overflow is permitted (TBTC: TBIE=1), an interrupt is generated when overflow occurs (TBTC: TBOF=1). • The following four interval time settings are selectable : Interval time of time-base timer Count clock Interval time 212/HCLK (Approx. 1.0 ms) 2/HCLK (0.5 µs) 214/HCLK (Approx. 4.1 ms) 216/HCLK (Approx. 16.4 ms) 219/HCLK (Approx. 131.1 ms) HCLK: Oscillation clock Values in parentheses “( )” are those under operation of 4-MHz oscillation clock. 30 MB90385 Series • Time-base timer block diagram To PPG timer Time-base timer counter 21/HCLK 21 22 23 · · · ··· 28 29 210 OF 211 212 OF 213 214 215 216 To watchdog timer 217 218 OF OF Power-on reset Stop mode CKSCR : MCS = 1 CKSCR : SCS = 0 0 1 1 2 To clock controller oscillation stabilizing wait time selector Counterclear circuit Interval timer selector TBOF clear TBOF set Time-base timer control register (TBTC) Time-base timer interrupt signal OF : Overflow HCLK : Oscillation clock Reserved TBIE TBOF TBR TBC1 TBC0 *1 : Switch machine clock from main clock to PLL clock. *2 : Switch machine clock from sub clock to main clock. Actual interrupt request number of time-base timer is as follows: Interrupt request number: #16 (10H) 31 MB90385 Series 3. Watchdog Timer The watchdog timer is a 2-bit counter that uses time-base timer or clock timer as count clock. If the counter is not cleared within an interval time, CPU is reset. •Watchdog timer functions • The watchdog timer is a timer counter that prevents runaway of a program. Once a watchdog timer is activated, the counter of watchdog timer must always be cleared within a specified time of interval. If specified interval time elapses without clearing the counter of a watchdog timer, CPU resetting occurs. This is the function of a watchdog timer. • The interval time of a watchdog timer is determined by a clock cycle, which is input as a count clock. Watchdog resetting occurs between a minimum time and a maximum time specified. • The output target of a clock source is specified by the watchdog clock selection bit (WTC: WDCS) in the clock timer control register. • Interval time of a watchdog timer is specified by the time-base timer output selection bit/clock timer output selection bit (WDTC: WT1, WT0) in the watchdog timer control register. Interval timer of watchdog timer Min Max Approx. 3.58 ms Approx. 4.61 ms Clock cycle 2 ±2 /HCLK 14 11 Min Max Clock cycle 212±29 /SCLK 215±212 /SCLK 216±213 /SCLK 217±214 /SCLK Approx. 0.457 s Approx. 0.576 s Approx. 3.584 s Approx. 4.608 s Approx. 7.168 s Approx. 9.216 s Approx. 14.336 s Approx. 18.432 s Approx. 14.33 ms Approx. 18.3 ms Approx. 57.23 ms Approx. 73.73 ms Approx. 458.75 ms Approx. 589.82 ms 216±213 /HCLK 218±215 /HCLK 221±218 /HCLK HCLK: Oscillation clock ( 4 MHz) , CSCLK: Sub clock (8.192 kHz) Notes: • If the time-base timer is cleared when watchdog timer count clock is used as time base timer output (carry-over signal), watchdog reset time may become longer. • When using the sub clock as machine clock, be sure to specify watchdog timer clock source selection bit (WDCS) in clock timer control register (WTC) at “0,” selecting output of clock timer. 32 MB90385 Series • Watchdog timer block diagram Watchdog timer control register(WDTC) PONR WRST ERST SRST WTE WT1 WT0 2 Clock timer control register (WTC) WDCS Watchdog timer Activate Reset occurs Shift to sleep mode Shift to time-base timer mode Shift to clock mode Shift to stop mode Counter clear control circuit Count clock selector 2-bit counter Clear Watchdog reset generation circuit Internal reset generation circuit 4 4 Time-base timer counter Main clock (dividing HCLK by 2) 21 22 28 29 210 211 212 213 214 215 216 217 218 Clock counter Sub clock SCLK HCLK: Oscillation clock SCLK: Sub clock 21 22 25 26 27 28 29 210 211 212 213 214 215 33 MB90385 Series 4. 16-bit Input/Output Timer The 16-bit input/output timer is a compound module composed of 16-bit free-run timer, (1 unit) and input capture (2 units, 4 input pins). The timer, using the 16-bit free-run timer as a basis, enables measurement of clock cycle of an input signal and its pulse width. • Configuration of 16-bit input/output timer The 16-bit input/output timer is composed of the following modules: • 16-bit free-run timer (1 unit) • Input capture (2 units, 2 input pins per unit) • Functions of 16-bit input/output timer (1) Functions of 16-bit free-run timer The 16-bit free-run timer is composed of 16-bit up counter, timer counter control status register, and prescaler. The 16-bit up counter increments in synchronization with dividing ratio of machine clock. • Count clock is set among four types of machine clock dividing rates. • Generation of interrupt is allowed by counter value overflow. • Activation of expanded intelligent I/O service (EI2OS) is allowed by interrupt generation. • Counter value of 16-bit free-run timer is cleared to “0000H” by either resetting or software-clearing with timer count clear bit (TCCS: CLR). • Counter value of 16-bit free-run timer is output to input capture, which is available as base time for capture operation. (2) Functions of input capture The input capture, upon detecting an edge of a signal input to the input pin from external device, stores a counter value of 16-bit free-run timer at the time of detection into the input capture data register. The function includes the input capture data registers corresponding to four input pins, input capture control status register, and edge detection circuit. • Rising edge, falling edge, and both edges are selectable for detection. • Generating interrupt on CPU is allowed by detecting an edge of input signal. • Expanded intelligent I/O service (EI2OS) is activated by interrupt generation. • The four input capture input pins and input capture data registers allows monitoring of a maximum of four events. 34 MB90385 Series • 16-bit input/output timer block diagram Internal data bus Input capture Specialpurpose bus 16-bit free-run timer • 16-bit free-run timer Counter value of 16-bit free-run timer is used as reference time (base time) of input capture. • Input capture Input capture detects rising edge, falling edge or both edges and retains a counter value of 16-bit free-run timer. Detection of edge on input signal is allowed to generate interrupt. • 16-bit free-run timer block diagram Timer counter data register (TCDT) 16-bit free-run timer OF CLK STOP CLR Output counter value to input capture Internal data bus Prescaler 2 Timer counter control status register (TCCS) IVF IVFE STOP Reserved CLR CLK2 CLK1 CLK0 φ : Machine clock OF : Overflow Free-run timer interrupt request 35 MB90385 Series • Detailed pin assignment on block diagram The 16-bit input/output timer includes a 16-bit free-run timer. Interrupt request number of the 16-bit free-run timer is as follows: Interrupt request number: 19 (13H) • Prescaler The prescaler divides a machine clock and provides a counter clock to the 16-bit up counter. Dividing ratio of the machine clock is specified by timer counter control status register (TCCS) among four values. • Timer counter data register (TCDT) The timer counter data register is a 16-bit up counter. A current counter value of the 16-bit free-run timer is read. Writing a value during halt of the counter allows setting an arbitrary counter value. 36 MB90385 Series •Input capture block diagram Edge detection circuit IN3 16-bit free-run timer Pin IN2 Input capture data register 3 (IPCP3) Pin 2 Input capture data register 2 (IPCP2) 2 Input capture control status register (ICS23) ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 Internal data bus Input capture interrupt request Input capture control ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 status register (ICS01) 2 IN1 2 Pin IN0 Input capture data register 1 (IPCP1) Pin Edge detection circuit Input capture data register 0 (IPCP0) 37 MB90385 Series 5. 16-bit Reload Timer The 16-bit reload timer has the following functions: • Count clock is selectable among 3 internal clocks and external event clock. • Activation trigger is selectable between software trigger and external trigger. • Generation of CPU interrupt is allowed upon occurrence of underflow on 16-bit timer register. Available as an interval timer using the interrupt function. • When underflow of 16-bit timer register (TMR) occurs, one of two reload modes is selectable between oneshot mode that halts counting operation of TMR, and reload mode that reloads 16-bit reload register value to TMR, continuing TMR counting operation. • The 16-bit reload timer is ready for expanded intelligent I/O service (EI2OS). • MB90385 series device has 2 channels of built-in 16-bit reload timer. • Operation mode of 16-bit reload timer Count clock Activation trigger Internal clock mode Event count mode Software trigger, external trigger Software trigger Operation upon underflow One-shot mode, reload mode One-shot mode, reload mode • Internal clock mode • The 16-bit reload timer is set to internal clock mode, by setting count clock selection bit (TMCSR: CSL1, CSL0) to “00B”, “01B”, “10B”. • In the internal clock mode, the counter decrements in synchronization with the internal clock. • Three types of count clock cycles are selectable by count clock selection bit (TMCSR: CSL1, CSL0) in timer control status register. • Edge detection of software trigger or external trigger is specified as an activation trigger. 38 MB90385 Series • 16-bit reload timer block diagram Internal data bus TMRLR 16-bit reload register Reload signal TMR Reload control circuit 16-bit timer register UF Count clock generation circuit Machine clock φ Prescaler 3 CLK Gate input Valid clock decision circuit Wait signal Output control circuit Output signal generation circuit EN Clear Internal clock CLK Output to internal peripheral functions Pin TIN Input control circuit 3 Clock selector External clock 2 Select signal Pin TOT Select function Operation control circuit generation circuit CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG Timer control status register (TMCSR) Interrupt request output 39 MB90385 Series 6. Clock Timer Outline The clock timer is a 15-bit free-run counter that increments in synchronization with sub clock. • Interval time is selectable among 7 choices, and generation of interrupt request is allowed for each interval. • Provides operation clock to the subclock oscillation stabilizing wait timer and watchdog timer. • Always uses subclock as a count clock regardless of settings of clock selection register (CKSCR). • Interval timer function • In the clock timer, a bit corresponding to the interval time overflows (carry-over) when an interval time, which is specified by interval time selection bit, is reached. Then overflow flag bit is set (WTC: WTOF=1). • If an interrupt by overflow is permitted (WTC: WTIE=1), an interrupt request is generated upon setting an overflow flag bit. • Interval time of clock timer is selectable among the following seven choices : • Interval time of clock timer Sub clock cycle 2 /SCLK (31.25 ms) 29/SCLK (62.5 ms) 210/SCLK (125 ms) SCLK (122 µs) 211/SCLK (250 ms) 212/SCLK (500 ms) 213/SCLK (1.0 s) 214/SCLK (2.0 s) SCLK: Sub clock frequency Values in parentheses “( )” are calculation when operating with 8.192 kHz clock. 8 Interval time 40 MB90385 Series • Clock timer block diagram To watchdog timer Clock timer counter SCLK 21 22 23 24 25 26 27 28 29 210 211 212 213 214 215 OF OF OF OF OF OF OF Power-on reset Shift to hardware standby Shift to stop mode Counter clear circuit Interval timer selector OF To sub clock oscillation stabilizing wait time Clock time interrupt OF : Overflow SCLK : Sub clock WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 Clock timer control register (WTC) Actual interrupt request number of clock timer is as follows : Interrupt request number : #28 (1CH) • Clock timer counter A 15-bit up counter that uses sub clock (SCLK) as a count clock. • Counter clear circuit A circuit that clears the clock timer counter. 41 MB90385 Series 7. 8/16-bit PPG Timer Outline The 8/16-bit PPG timer is a 2-channel reload timer module (PPG0 and PPG1) that allows outputting pulses of arbitrary cycle and duty cycle. Combination of the two channels allows selection among the following operations: • 8-bit PPG output 2-channel independent operation mode • 16-bit PPG output operation mode • 8-bit and 8-bit PPG output operation mode MB90385 series device has two 8/16-bit built-in PPG timers. This section describes functions of PPG0/1. PPG2/ 3 have the same functions as those of PPG0/1. • Functions of 8/-16-bit PPG timer The 8/-16-bit PPG timer is composed of four 8-bit reload register (PRLH0/PRLL0, PRLH1/PRLL1) and two PPG down counters (PCNT0, PCNT1). • Widths of “H” and “L” in output pulse are specifiable independently. Cycle and duty factor of output pulse is specifiable arbitrarily. • Count clock is selectable among 6 internal clocks. • The timer is usable as an interval timer, by generating interrupt requests for each interval. • The time is usable as a D/A converter, with an external circuit. 42 MB90385 Series • 8/16-bit PPG timer 0 block diagram “H” level side data bus “L” level side data bus PPG0 reload register PPLH0 (“H” level side) PPLL0 (“L” level side) PEN0 PPG0 operation mode control register (PPGC0) PE0 PIE0 PUF0 Reserved PPG0 temporary buffer 0(PRLBH0) Select signal R S 2 Q Interrupt request output* Operation mode control signal PPG1 underflow PPG0 underflow (To PPG1) Reload register L/H selector Count start value Reload Clear Pulse selector PPG0 down counter (PCNT0) CLK Underflow Reversed PPG0 output latch Pin PPG0 Time-base timer output (512/HCLK) Peripheral clock (1/φ) Peripheral clock (2/φ) Peripheral clock (4/φ) Peripheral clock (8/φ) Peripheral clock (16/φ) 3 PPG output control circuit Count clock selector Select signal PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PPG0/1 count clock selection register (PPG01) − : Undefined Reserved : Reserved bit HCLK : Oscillation clock frequency φ : Machine clock frequency * : Interrupt output of 8/16-bit PPG timer 0 is incorporated into one by the OR circuit against interrupt output of 8/16-bit PPG timer 1. 43 MB90385 Series • 8/16-bit PPG timer 1 block diagram “H” level side data bus “L” level side data bus PPG1 reload register Operation (“H” level side) (“L” level side) mode control signal PPG1 temporary buffer 0(PRLBH1) PRLH1 PRLL1 PEN1 2 PPG1 operation mode control register (PPGC1) RePE1 PIE1 PUF1 MD1 MD0 served R S Q Interrupt request output* Reload selector L/H selector Count start value Reload Underflow Select signal Clear PPG1 Re- output latch MD0 PPG1 down counter (PCNT1) PPG1 underflow (To PPG0) CLK Pin PPG1 versed PPG output control circuit PPG0 underflow (From PPG0) Time-base timer output (512/HCLK) Peripheral clock (1/φ) Peripheral clock (2/φ) Peripheral clock (4/φ) Peripheral clock (8/φ) Peripheral clock (16/φ) Count clock selector Select signal 3 PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PPG0/1 count clock selection register (PPG01) − : Undefined Reserved : Reserved bit HCLK : Oscillation clock frequency φ : Machine clock frequency * : Interrupt output of 8/16-bit PPG timer 1 is incorporated into one by the OR circuit against interrupt output of 8/16-bit PPG timer 0. 44 MB90385 Series 8. Delay Interrupt Generation Module Outline The delay interrupt generation module is a module that generates interrupts for switching tasks. Generation of a hardware interrupt request is performed by software. • Delay interrupt generation module outline Using the delay interrupt generation module, hardware interrupt request is generated and released by software. Delay interrupt generation module outline Function and control Set “1” in R0 bit of delay interrupt request generation/release register (DIRR: R0=1), generating an interrupt request. Set “0” in R0 bit of delay interrupt request generation/release register (DIRR: R0=0), releasing an interrupt request. #42 (2AH) No setting of permission register is provided. Retained in DIRR: R0 bit Not ready for expanded intelligent I/O service. Cause of interrupt Interrupt number Interrupt control Interrupt flag EI OS 2 • Delay interrupt generation module block diagram Internal data bus R0 S Interrupt request R Latch Delay interrupt request generation/release register (DIRR) − : Not defined Interrupt request signal • Interrupt request latch A latch that retains settings on delay interrupt request generation/release register (generation or release of delay interrupt request). • Delay interrupt request generation/release register (DIRR) Generates or releases delay interrupt request. • Interrupt number An interrupt number used in delay interrupt generation module is as follows: Interrupt number: #42 (2AH) 45 MB90385 Series 9. DTP/External Interrupt and CAN Wakeup Outline DTP/external interrupt transfers an interrupt request generated by an external peripheral device or a data transmission request to CPU, generating external interrupt request and activating expanded intelligent I/O service. Input RX of CAN controller is used as external interrupt input. • DTP/external interrupt and CAN wakeup function An interrupt request input from external peripheral device to external input pins (INT7 to INT4) and RX pin, just as interrupt request of peripheral device, generates an interrupt request. The interrupt request generates an external interrupt and activates expanded intelligent I/O service (EI2OS). If the expanded intelligent I/O service (EI2OS) has been disabled by interrupt control register (ICR: ISE=0), external interrupt function is enabled and branches to interrupt processing. If the EI2OS has been enabled, (ICR: ISE=1), DTP function is enabled and automatic data transmission is performed by EI2OS. After performing specified number of data transmission processes, the process branches to interrupt processing. DTP/external interrupt and CAN wakeup outline External interrupt Input pin Interrupt cause Interrupt number Interrupt control Interrupt flag Process selection Process 5 pins (RX, and INT4 to INT7) Specify for each pin with detection level setting register (ELVR). Input of “H” level/“L” level/rising edge/falling Input of “H” level/ “L” level edge. #15 (0FH) , #24 (18H) , #27 (1BH) Enabling or disabling output of interrupt request, using DTP/external interrupt permission register (ENIR). Retaining interrupt cause with DTP/external interrupt cause register (EIRR). Disable EI2OS (ICR: ISE=0) Branch to external interrupt process Enable EI2OS (ICR: ISE=1) After automatic data transmission by EI2OS for specified number of times, branch to interrupt process. DTP function 46 MB90385 Series • DTP/External interrupt/CAN wakeup block diagram Detection level setting register (ELVR) LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 Re- Re- Re- Re- Re- Reserved served served served served served LB0 LA0 Pin INT7 Level/edge selector Pin INT6 Level/edge selector Internal data bus Interrupt request signal Pin INT5 Level/edge selector Pin INT4 Level/edge selector Pin RX Level/edge selector DTP/external interrupt input detection circuit ER7 ER6 ER5 ER4 served served served ER0 ReReRe- DTP/external interrupt cause register (EIRR) Interrupt request signal Re- Re- ReEN7 EN6 EN5 EN4 served served served EN0 DTP/external interrupt permission register (ENIR) 47 MB90385 Series 10. 8/10-bit A/D Converter The 8/10-bit A/D converter converts an analog input voltage into 8-bit or 10/bit digital value, using the RC-type successive approximation conversion method. • Input signal is selected among 8 channels of analog input pins. • Activation trigger is selected among software trigger, internal timer output, and external trigger. • Functions of 8/10-bit A/D converter The 8/10-bit A/D converter converts an analog voltage (input voltage) input to analog input pin into an 8-bit or 10-bit digital value (A/D conversion). The 8/10-bit A/D converter has the following functions: • A/D conversion takes a minimum of 6.12 µs* for 1 channel, including sampling time. (A/D conversion) • Sampling of one channel takes a minimum of 2.0 µs*. • RC-type successive approximation conversion method, with sample & hold circuit is used for conversion. • Resolution of either 8 bits or 10 bits is specifiable. • A maximum of 8 channels of analog input pins are allowed for use. • Generation of interrupt request is allowed, by storing A/D conversion result in A/D data register. • Activation of EI2OS is allowed upon occurrence of an interrupt request. With use of EI2OS, data loss is avoided even if A/D conversion is performed successively. • An activation trigger is selectable among software trigger, internal timer output, and external trigger (fall edge). *: When operating with 16-MHz machine clock • 8/10-bit A/D converter conversion mode Conversion mode Singular conversion mode Sequential conversion mode Pausing conversion mode Description The A/D conversion is performed form a start channel to an end channel sequentially. Upon completion of A/D conversion on an end channel, A/D conversion function stops. The A/D conversion is performed form a start channel to an end channel sequentially. Upon completion of A/D conversion on an end channel, A/D conversion function resumes from the start channel. The A/D conversion is performed by pausing at each channel. Upon completion of A/D conversion on an end channel, A/D conversion and pause functions resume from the start channel. 48 MB90385 Series • 8/10-bit A/D converter block diagram A/D control status register (ADCS) Interrupt request output Reserved BUSY INT INTE PAUS STS1 STS0 STRT 2 MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 6 ADTG TO Activation selector 2 Decoder Internal data bus AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 Sample& hold circuit Analog channel selector AVR AVcc AVss 2 2 Comparator Control circuit D/A converter A/D data register (ADCR) S10 ST1 ST0 CT1 CT0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TO : − : Reserved : φ : Internal timer output Not defined Be sure to set to “0” Machine clock 49 MB90385 Series 11. UART Outline UART is a general-purpose serial data communication interface for synchronous and asynchronous communication using external devices. • Provided with bi-directional communication function for both clock-synchronous and clock-asynchronous modes. • Provided with master/slave communication function (multi-processor mode). (Only master side is available.) • Interrupt request is generated upon completion of reception, completion of transmission and detection of reception error. • Ready for expanded intelligent service, EI2OS. UART functions Description Data buffer Transmission mode Full-duplex double buffer Clock synchronous (No start/stop bit, no parity bit) Clock asynchronous (start-stop synchronous) Built-in special-purpose baud-rate generator. Setting is selectable among 8 values. Input of external values is allowed. Use of clock from external timer (16-bit reload timer 0) is allowed. 7 bits (only asynchronous normal mode) 8 bits Non Return to Zero (NRZ) system Framing error Overrun error Parity error (not detectable in operation mode 1 (multi-processor mode)) Receive interrupt (reception completed, reception error detected) Transmission interrupt (transmission completed) Ready for expanded intelligent I/O service (EI2OS) in both transmission and reception Communication between 1 (master) and n (slaves) are available (usable as master only). Baud rate Data length Signaling system Reception error detection Interrupt request Master/slave communication function (asynchronous, multi-processor mode) Note : Start/stop bit is not added upon clock-synchronous transmission. Data only is transmitted. UART operation modes Operation mode 0 1 2 Asynchronous mode (normal mode) Multi processor mode Synchronous mode 8+1*1 8 Data length With parity Without parity Synchronization Asynchronous   Asynchronous Synchronous No Stop bit length 7-bit or 8-bit 1- bit or 2-bit *2  : Disallowed *1 : “+1” is an address/data selection bit used for communication control (bit 11 of SCR1 register: A/D). *2 : Only 1 bit is detected as a stop bit on data reception. 50 MB90385 Series • UART block diagram Control bus Special-purpose baud-rate generator 16-bit reload timer Pin SCK1 Reception interrupt request output Transmission interrupt request output Transmission control circuit Transmission clock Clock Reception Reception selector clock control circuit Start bit detection circuit Reception bit counter Reception parity counter Transmission start circuit Transmission bit counter Transmission parity counter Pin SOT1 Pin SIN1 Shift register for reception Reception Serial input data comregister 1 pleted Shift register for transmission Reception status decision circuit Serial output data register 1 Start transmission Reception error occurrence signal for EI2OS (to CPU) Internal data bus Communication prescaler control register MD DIV2 DIV1 DIV0 Serial mode register 1 MD1 MD0 CS2 CS1 CS0 RST SCKE SOE Serial control register 1 PEN P SBL CL A/D REC RXE TXE Serial status register 1 PE ORE FRE RDRF TDRE BDS RIE TIE 51 MB90385 Series 12. CAN Controller The Controller Area Network (CAN) is a serial communication protocol compliant with CANVer2.0A and Ver2.0B. The protocol allows data transmission and reception in both standard frame format and expanded frame format. • Features of CAN controller • CAN controller format is compliant with CANVer2.0A and Ver2.0B. • The protocol allows data transmission and reception in standard frame format and expanded frame format. • Automatic transmission of data frame by remote frame reception is allowed. • Baud rate ranges from 10 Kbps to 1 Mbps (with 16-MHz machine clock). Data transmission baud rate Machine clock 16 MHz 12 MHz 8 MHz 4 MHz 2 MHz • • • • • Baud rate (Max) 1 Mbps 1 Mbps 1 Mbps 500 Kbps 250 Kbps Provided with 8 transmission/reception message buffers. Transmission/reception is allowed at ID11bit in standard format, and at ID29bit in expanded frame format. Specifying 0 byte to 8 bytes is allowed in message data. Multi-level message buffer configuration is allowed. CAN controller has two built-in acceptance masks. Mask settings are independently allowed for the two acceptance masks on reception IDs. • The two acceptance masks allow reception in standard frame format and expanded frame format. • For types of masking, all-bit comparison, all-bit masking, and partial masking with acceptance mask register 0/1, are specifiable. 52 MB90385 Series • CAN controller block diagram F2MC-16LX bus CPU operation clock PSC TS1 BTR TS2 RSJ TOE TS RS CSR HALT NIE NT NS1,0 RTEC BVALR TREQR Prescaler (dividing by 1 to 64) Bit timing generation circuit Operation clock (TQ) Sync segment Time segment 1 Time segment 2 Node status transition interrupt generation circuit Node status transition interrupt signal Error control circuit Bus status decision circuit Idle, interrupt, suspend, transmit, receive, error, and overload Transmission/ reception sequence Error frame generation circuit Overload frame generation circuit Arbitration lost Output driver Clear transmission buffer Transmission buffer decision circuit Transmission buffer Data Acceptance counter filter control circuit Trans- Recep- ID mission tion selection DLC DLC Transmission buffer TCANR TRTRR RFWTR TCR TIER RCR RIER RRTRR ROVRR AMSR AMR0 AMR1 IDR0 to 7 DLCR0 to 7 DTR0 to 7 RAM IDER LEIR 0 1 Bit error, stuff error, CRC error, frame error, ACK error Transmission shift register Transmission completion interrupt signal Reception completion interrupt signal Pin TX Stuffing CRC ACK generation generation circuit Set and clear transmission buffer Transmission completion interrupt generation circuit Transmission circuit DLC CRC error Set reception buffer Reception completion interrupt generation circuit Reception CRC generation circuit/ DLC error check Reception shift register Stuffing error Set and clear reception buffer and transmission buffer Set reception ID selection buffer Destuffing/stuffing error check Arbitration lost Bit error ACK error Form error Arbitration check Bit error check Acknowledgment error check Form error check Acceptance filter Reception buffer decision circuit Reception buffer Input latch Pin RX RAM address generation circuit Reception buffer, transmission buffer, reception DLC, transmission DLC, ID selection 53 MB90385 Series 13. Address Matching Detection Function Outline The address matching detection function checks if an address of an instruction to be processed next to a currentlyprocessed instruction is identical with an address specified in the detection address register. If the addresses match with each other, an instruction to be processed next in program is forcibly replaced with INT9 instruction, and process branches to the interrupt process program. Using INT9 interrupt, this function is available for correcting program by batch processing. • Address matching detection function outline • An address of an instruction to be processed next to a currently-processed instruction of the program is always retained in an address latch via internal data bus. By the address matching detection function, the address value retained in the address latch is always compared with an address specified in detection address setting register. If the compared address values match with each other, an instruction to be processed next by CPU is forcibly replaced with INT9 instruction, and an interrupt process program is executed. • Two detection address setting registers are provided (PADR0 and PADR1), and each register is provided with interrupt permission bit. Generation of interrupt, which is caused by address matching between the address retained in address latch and the address specified in address setting register, is permitted and prohibited on a register-by-register basis. • Address matching detection function block diagram Address latch Comparator Internal data bus PADR0 24bit Detection address setting register 0 PADR1 24bit INT9 instruction (generate INT9 interrupt) Detection address setting register 1 PACSR Reserved Reserved Reserved Reserved AD1E Reserved AD0E Reserved Address detection control register (PACSR) Reserved: Be sure to set to “0.” • Address latch Retains address value output to internal data bus. • Address detection control register (PACSR) Specifies if interrupt is permitted or prohibited when addresses match with each other. • Detection address setting (PADR0, PADR1) Specifies addresses to be compared with values in address latch. 54 MB90385 Series 14. ROM Mirror Function Selection Module Outline The ROM mirror function selection module sets the data in ROM assigned to FF bank so that the data is read by access to 00 bank. • ROM mirror function selection module block diagram ROM mirror function selection register (ROMM) Reserved Reserved Reserved Reserved Reserved Reserved Reserved MI Address Internal data bus Address area FF bank 00 bank Data ROM • FF bank access by ROM mirror function 004000 H 00 bank ROM mirror area 00FFFFH FBFFFF H FC0000H FEFFFF H FF0000 H MB90V495G MB90F387 MB90387 FF4000 H FFFFFFH FF bank (ROM mirror applicable area) 55 MB90385 Series 15. 512 Kbit Flash Memory Outline The following three methods are provided for data writing and deleting on flash memory: 1. Parallel writer 2. Serial special-purpose writer 3. Writing/deleting by program execution This section describes “3. Writing/deleting by program execution.” • 512 Kbit flash memory outline The 512K-bit flash memory is allocated on FFH bank of CPU memory map. Using the function of flash memory interface circuit, the memory allows read access and program access from CPU. Writing/deleting on flash memory is performed by instruction from CPU via flash memory interface. Because rewriting is allowed on mounted memory, modifying program and data is performed efficiently. • Features of 512 Kbit flash memory • 128 K words x 8 bits/64 K words x 16 bits (16 K + 8 K + 8 K + 32 K) sector configuration • Automatic program algorithm (Embedded AlgorithmTM* : Similar to MBM29LV200.) • Built-in deletion pause/deletion resume function • Detection of completed writing/deleting by data polling and toggle bits. • Detection of completed writing/deleting by CPU interrupt. • Deletion is allowed on a sector-by-sector basis (sectors are combined freely). • Number of writing/deleting operations (minimum): 10,000 times • Sector protection • Expanded sector protection • Temporaly sector unprotection * : Embedded AlgorithmTM is a registered trademark of Advanced Micro Devices. Note : A function of reading manufacture code and device code is not provided. These codes are not accessible by command either. • Flash memory writing/deleting • Writing and reading data is not allowed simultaneously on the flash memory. • Data writing and deleting on the flash memory is performed by the processes as follows: Make a copy of program on flash memory onto RAM. Then, execute the program copied on the RAM. • List of registers and reset values in flash memory Flash memory control status register (FMCS) × : Undefined bit 7 6 5 4 3 2 1 0 0 0 0 X 0 0 0 0 56 MB90385 Series • Sector configuration For access from CPU, SA0 to SA3 are allocated in FF bank register. • Sector configuration of 512 Kbit flash memory Flash memory SA0 (32 Kbytes) CPU address FF0000H Writer address* 70000H FF7FFF H FF8000H 77FFFH 78000H SA1 (8 Kbytes) FF9FFF H FFA000H 79FFFH 7A000H SA2 (8 Kbytes) FFBFFF H FFC000 H 7BFFF H 7C000H SA3 (16 Kbytes) FFFFFF H 7FFFFH * : “Writer address” is an address equivalent to CPU address, which is used when data is written on flash memory, using parallel writer. When writing/ deleting data with general-purpose writer, the writer address is used for writing and deleting. 57 MB90385 Series s ELECTRIC CHARACTERISTICS 1. Absolute Maximum Rating Parameter Symbol VCC Power supply voltage Input voltage Output voltage Maximum clamp current Total maximum clamp current “L” level maximum output current “L” level average output current “L” level maximum total output current “L” level average total output current “H” level maximum output current “H” level average output current “H” level maximum total output current “H” level average total output current Power consumption Operating temperature Storage temperature *1 : AVcc and AVR should not exceed Vcc. *2 : VI and VO should not exceed Vcc + 0.3 V. *3 : A peak value of an applicable one pin is specified as a maximum output current. *4 : An average current value of an applicable one pin within 100 ms is specified as an average output current. (Average value is found by multiplying operating current by operating rate.) *5 : An average current value of all pins within 100 ms is specified as an average total output current. (Average value is found by multiplying operating current by operating rate.) (Continued) 58 AVCC AVR VI VO ICLAMP ∑ | ICLAMP | IOL1 IOL2 IOLAV1 IOLAV2 ∑IOL1 ∑IOL2 ∑IOLAV1 ∑IOLAV2 IOH1 IOH2 IOHAV1 IOHAV2 ∑IOH1 ∑IOH2 ∑IOHAV1 ∑IOHAV2 PD TA Tstg Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 − 2.0                   −40 −55 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 + 2.0 20 15 40 4 30 125 160 40 40 −15 −40 −4 −30 −125 −160 −40 −40 245 +105 +150 Unit V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mW °C °C VCC = AVCC*1 AVCC ≥ AVR*1 *2 *2 *6 *6 Normal output*3 High-current output*3 Normal output*4 High-current output*4 Normal output High-current output Normal output*5 High-current output*5 Normal output*3 High-current output*3 Normal output*4 High-current output*4 Normal output High-current output Normal output*5 High-current output*5 (VSS = AVSS = 0 V) Remarks MB90385 Series (Continued) *6 : • Applicable to pins: P10 to P17, P20 to P27, P30 to P33, P35*, P36*, P37, P40 to P44, P50 to P57 *: P35 and P36 are MB90387S and MB90F387S only. • Use within recommended operating conditions. • Use at DC voltage (current) . • The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the +B input pin open. • Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. • Sample recommended circuits: • Input/Output Equivalent circuits Protective diode VCC Limiting resistance +B input (0 V to 16 V) P-ch N-ch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 59 MB90385 Series 2. Recommended Operating Conditions Parameter Symbol Value Min 3.5 Power supply voltage VCC AVCC Smoothing capacitor Operating temperature CS TA 3.0 4.0 0.1 −40 Typ 5.0     Max 5.5 5.5 5.5 1.0 +105 Unit V V V µF °C (VSS = AVSS = 0.0V) Remarks Under normal operation Retain status of stop operation *2 *1 *1 : Use a ceramic capacitor, or a capacitor of similar frequency characteristics. On the Vcc pin, use a bypass capacitor that has a larger capacity than that of Cs. Refer to the following figure for connection of smoothing capacitor Cs. *2 : AVcc is a voltage at which accuracy is guaranteed. AVcc should not exceed Vcc. • C pin connection diagram C CS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 60 MB90385 Series 3. DC Characteristics Parame- Sym ter bol “H” level input voltage “L” level input voltage “H” level output voltage “L” level output voltage Input leak current Pin name (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Value Remarks Conditions Unit Min Typ Max — — — — VCC = 4.5 V, IOH = −4.0 mA VCC = 4.5 V, IOH = −14.0 mA VCC = 4.5 V, IOL = 4.0 mA VCC = 4.5 V, IOL = 20.0 mA VCC = 5.5 V, VSS < VI < VCC VCC = 5.0 V, Internally operating at 16 MHz, normal operation. VCC = 5.0 V, Internally operating at 16 MHz, writing on flash memory. VCC = 5.0 V, Internally operating at 16 MHz, deleting on flash memory. VCC = 5.0 V, Internally operating at 16 MHz, sleeping. VCC = 5.0 V, Internally operating at 2 MHz, transition from main clock mode, in timebase timer mode. 0.8 VCC VCC − 0.3 VSS − 0.3 VSS − 0.3 VCC – 0.5 VCC – 0.5 — — — — — — — — — — VCC + 0.3 VCC + 0.3 0.2 VCC VSS + 0.3 — — 0.4 0.4 +5 V V V V V V V V µA CMOS VIHS hysteresis input pin VIHM MD input pin VILS CMOS hysteresis input pin Pins other than P14 to P17 VILM MD input pin VOH1 VOH2 P14 to P17 VOL1 Pins other than P14 to P17 VOL2 P14 to P17 IIL All input pins –5 — — 25 30 mA ICC — 45 50 mA MB90F387/S Power supply current* ICCS VCC — 45 50 mA MB90F387/S — 8 0.75 12 1.0 mA MB90F387/S mA MB90387/S ICTS — 0.2 0.35 (Continued) 61 MB90385 Series (Continued) Parameter Symbol Pin name (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Rating Conditions Unit Remarks Min Typ Max VCC = 5.0 V, Internally operating at 8 kHz, subclock operation, TA = + 25°C VCC = 5.0 V, Internally operating at 8 kHz, subclock, sleep mode, TA = + 25°C VCC = 5.0 V, Internally operating at 8 kHz, clock mode, TA = + 25°C Stopping, TA = + 25°C Other than AVCC, AVSS, AVR, C, VCC, VSS RST  — — 0.3 40 1.2 100 mA MB90F387/S µA MB90387/S ICCL Power supply current* ICCLS VCC — 10 30 µA ICCT — 8 25 µA ICCH — 5 20 µA Input capacity Pull-up resistor Pull-down resistor CIN — 5 15 pF RUP   25 50 100 kΩ kΩ FLASH product is not provided with pull-down resistor. RDOWN MD2 25 50 100 * : Test conditions of power supply current are based on a device using external clock. 62 MB90385 Series 4. AC Characteristics (1) Clock timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Value Pin name Unit Remarks Min Typ Max X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0 — — — — 3 3 fCL Clock cycle time tHCYL tLCYL PWH, PWL PWLH,PWLL Input clock rise time and fall time Internal operation clock frequency Internal operation clock cycle time tCR, tCF fCP fLCP tCP tLCP — 125 — 10 — — 1.5 — 62.5 — — — 32.768 — 30.5 — 15.2 — — 8.192 — 122.1 8 16 — 333 — — — 5 16 — 666 — MHz When crystal or ceramic resonator is used*2 Parameter Symbol Clock frequency fC MHz External clock *1, *2 kHz ns µs ns µs ns When external clock is used When sub clock is used When main clock is used When sub clock is used Set duty factor at 30% to 70% as a guideline. Input clock pulse width MHz When main clock is used kHz ns µs *1 : Internal operation clock frequency should not exceed 16 MHz. *2 : When selecting the PLL clock, the range of clock frequency is limitted. Use this product within range as mentioned in “Relation among external clock frequency and internal clock frequency”. • Clock timing tHCYL X0 PWH tCF tLCYL X0A PWLH tCF PWLL tCR 0.8 VCC 0.2 VCC PWL tCR 0.8 VCC 0.2 VCC 63 MB90385 Series • PLL operation guarantee range Relation between internal operation clock frequency and power supply voltage Operation guarantee range of MB90F387/S and MB90387/S 5.5 Power voltage VCC (V) 4.0 3.5 3.0 A/D converter accuracy guarantee range PLL operation guarantee range 1.5 34 8 12 16 Internal clock fCP (MHz) Relation among external clock frequency and internal clock frequency Multiply by 4 16 Multiply Multiply by 3 by 2 Multiply by 1 Internal clock fCP (MHz) 12 9 8 4 x1/2 (no multiplication) 3 4 8 16 External clock fC (MHz)* * : fc is 8 MHz at maximum when crystal or ceramic resonator circuit is used. Rating values of alternating current is defined by the measurement reference voltage values shown below: • Input signal waveform • Output signal waveform Hysteresis input pin 0.8 VCC 0.2 VCC Output pin 2.4 V 0.8 V 64 MB90385 Series (2) Reset input timing Parameter Symbol Pin name Value Min 16 tCP*3 Reset input time tRSTL RST Oscillation time of oscillator*1 + 100 µs + 16 tCP*3 100 Max    Unit ns  µs Remarks Normal operation In sub clock*2, sub sleep*2, watch*2 and stop mode In timebase timer *1 : Oscillation time of oscillator is time that the amplitude reached the 90%. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR/ceramic oscillator, the oscillation time is between hundreds of µs to several ms. In the external clock, the oscillation time is 0 ms. *2 : Except for MB90F387S and MB90387S. *3 : Refer to "(1) Clock timing" ratings for tCP (internal operation clock cycle time). • In sub clock, sub sleep, watch and stop mode tRSTL RST 0.2 VCC 0.2 VCC 90% of amplitude X0 Internal operation clock Oscillation time of oscillator Internal reset 100 s + 16 tCP Wait time for stabilizing oscillation Execute instruction 65 MB90385 Series (3) Power-on reset Parameter Power supply rise time Power supply shutdown time (VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Value Symbol Pin name Conditions Unit Remarks Min Max tR tOFF VCC VCC  0.05 1 30  ms ms Repeated operation tR VCC 2.7 V 0.2 V 0.2 V tOFF 0.2 V Sudden change of power supply voltage may activate the power-on reset function. When changing power supply voltages during operation, raise the power smoothly by suppressing variation of voltages as shown below. When raising the power, do not use PLL clock. However, if voltage drop is 1V/s or less, use of PLL clock is allowed during operation. VCC 3.0 V VSS Limiting the slope of rising within 50 mV/ms is recommended. RAM data hold period 66 MB90385 Series (4) UART timing Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → valid SIN hold time (VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C) Value Symbol Pin name Conditions Unit Remarks Min Max tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX SCK1 SCK1, SOT1 SCK1, SIN1 SCK1, SIN1 SCK1 SCK1 SCK1, SOT1 SCK1, SIN1 SCK1, SIN1 External shift clock mode output pin is : CL = 80 pF+1TTL. Internal shift clock mode output pin is : CL = 80 pF+1TTL. 8 tCP * −80 100 60 4 tCP * 4 tCP *  60 60  +80     150   ns ns ns ns ns ns ns ns ns * : Refer to "(1) Clock timing" ratings for tCP (internal operation clock cycle time). Notes: • AC rating in CLK synchronous mode. • CL is a load capacitance value on pins for testing. 67 MB90385 Series • Internal shift clock mode SCK 0.8 V tSLOV 2.4 V tSCYC 2.4 V 0.8 V SOT 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC SIN 0.2 VCC • External shift clock mode SCK 0.2 VCC tSLOV 2.4 V tSLSH 0.2 VCC tSHSL 0.8 VCC 0.8 VCC SOT 0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC SIN 0.2 VCC 68 MB90385 Series (5) Timer input timing Parameter Input pulse width Symbol tTIWH tTIWL Pin name TIN0, TIN1 IN0 to IN3 (VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C) Value Conditions Unit Remarks Min Max  4 tCP *  ns * : Refer to "(1) Clock timing" ratings for tCP (internal operation clock cycle time). • Timer input timing TIN0, TIN1, IN0 to IN3 0.8 VCC 0.8 VCC 0.2 VCC tTIWH tTIWL 0.2 VCC (6) Trigger input timing Parameter Input pulse width Symbol tTRGH tTRGL Pin name INT4 to INT7, ADTG (VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C) Value Conditions Unit Remarks Min Max  5 tCP *  ns * : Refer to "(1) Clock timing" ratings for tCP (internal operation clock cycle time). • Trigger input timing INT4 to INT7, ADTG 0.8 VCC 0.8 VCC 0.2 VCC tTRGH tTRGL 0.2 VCC 69 MB90385 Series 5. A/D converter Parameter Resolution Total error Nonlinear error Differential linear error Zero transition voltage Full-scale transition voltage (VCC = AVCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, 3.0 V ≤ AVR − AVSS, TA = −40 °C to +105 °C) Value Pin Symbol Conditions Unit Remarks name Min Max     VOT VFST     AN0 to AN7 AN0 to AN7     AVSS − 1.5 LSB AVR − 3.5 LSB 66 tCP *1     10 ± 3.0 ± 2.5 ± 1.9 bit LSB LSB LSB V 1 LSB = AVR/1024 V With 16 MHz machine clock 5.5 V ≥ AVCC ≥ 4.5 V With 16 MHz machine clock 4.5 V > AVCC ≥ 4.0 V With 16 MHz machine clock 5.5 V ≥ AVCC ≥ 4.5 V With 16 MHz machine clock 4.5 V > AVCC ≥ 4.0 V AVSS + 0.5 AVSS + 2.5 LSB LSB AVR − 1.5 LSB  AVR + 0.5 LSB  ns Compare time   88 tCP *1   ns 32 tCP *1 Sampling time   128 tCP *1 Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supplying current Variation among channels AN0 to AN7 AN0 to AN7 AVR AVCC AVCC AVR AVR AN0 to AN7  AVSS AVSS + 2.7        ns     3.5  165    10 AVR AVCC 7.5 5 250 5 4 ns µA V V mA µA µA µA LSB IAIN VAIN  IA IAH IR IRH  *2 *2 *1 : Refer to "(1) Clock timing" ratings for tCP (internal operation clock cycle time). *2 : If A/D converter is not operating, a current when CPU is stopped is applicable (Vcc=AVcc=AVR=5.0 V). 70 MB90385 Series 6. Definition of A/D Converter Terms Resolution Linear error : Analog variation that is recognized by an A/D converter. : Deviation between a line across zero-transition line (“00 0000 00 0 0” ←→“00 0000 0001”) and full-scale transition line (“11 1111 11 1 0” ←→ “11 1111 1111”) and actual conversion characteristics. : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. : Difference between an actual value and an ideal value. A total error includes zero transition error, full-scale transition error, and linear error. Total error 3FF 3FE 3FD Differential linear error Total error Actual conversion characteristics 1.5 LSB Digital output {1 LSB × (N − 1) + 0.5 LSB} 004 003 002 001 0.5 LSB AVss VNT (Actually-measured value) Actual conversion characteristics Ideal characteristics Analog input AVR Total error of digital output “N” = VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVR − AVSS 1024 [LSB] 1 LSB = (Ideal value) [V] VOT (Ideal value) = AVSS + 0.5 LSB [V] VFST (Ideal value) = AVR − 1.5 LSB [V] VNT : A voltage at which digital output transits from (N-1) to N. (Continued) 71 MB90385 Series (Continued) Linear error 3FF 3FE 3FD Actual conversion characteristics {1 LSB × (N − 1) + VOT } N+1 VFST (actual measurement value) VNT (actual measurement value) Actual conversion characteristics Differential linear error Ideal characteristics Actual conversion characteristics Digital output Digital output N 004 003 002 N−1 V (N + 1) T (actual measurement value) VNT (actual measurement value) Actual conversion characteristics AVR Ideal characteristics 001 VOT (actual measurement value) AVss AVR N−2 Analog input AVss Analog input Linear error of digital output N = Differential linear error of digital output N = 1 LSB = VNT − {1 LSB × (N − 1) + VOT} 1 LSB V (N + 1) T − VNT 1 LSB VFST − VOT 1022 −1LSB [LSB] [LSB] [V] VOT : Voltage at which digital output transits from “000H” to “001H.” VFST : Voltage at which digital output transits from “3FEH” to “3FFH.” 72 MB90385 Series 7. Notes on A/D Converter Section Use the device with external circuits of the following output impedance for analog inputs: Recommended output impedance of external circuits are: Approx. 3.9 kΩ or lower (4.5 V ≤ AVcc ≤ 5.5 V) (sampling period=2.00 µs at 16-MHz machine clock), Approx. 11 kΩ or lower (4.0 V ≤ AVcc < 4.5 V) (sampling period=8.0 µs at 16-MHz machine clock). If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high as internal capacitor. If output impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient. • Analog input circuit model R Analog input Comparator C MB90F387/S, MB90387/S 4.5 V ≤ AVCC ≤ 5.5 V R = 2.35 kΩ, C = 36.4 pF : : 4.0 V ≤ AVCC < 4.5 V R = 16.4 kΩ, C = 36.4 pF : : Note : Use the values in the figure only as a guideline. • About errors As [AVR-AVss] become smaller, values of relative errors grow larger. 8. Flash Memory Program/Erase Characteristics Parameter Sector eraset time Chip erase time Word (16 bit width) programming time Program/Erase cycle Flash Data Retention Time  Average TA = + 85 °C TA = + 25 °C VCC = 5.0 V Conditions Value Min    10,000 20 Typ 1 4 16   Max 15  3,600   Unit s s µs cycle Year * Remarks Excludes 00H programming prior to erasure Excludes 00H programming prior to erasure Except for the over head time of the system * : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 °C) . 73 MB90385 Series s EXAMPLE CHARACTERISTICS • MB90F387 ICC − VCC TA = +25 °C, In external clock operation f = Internal operating frequency 30 25 20 ICC (mA) 15 10 5 0 2.5 f = 4 MHz f = 2 MHz 3.5 4.5 VCC (V) 5.5 6.5 f = 10 MHz f = 8 MHz f = 16 MHz ICCS − VCC TA = +25 °C, In external clock operation f = Internal operating frequency 10 8 ICCS (mA) 6 f = 10 MHz 4 2 0 2.5 f = 8 MHz f = 4 MHz f = 2 MHz 3.5 4.5 VCC (V) 5.5 6.5 f = 16 MHz ICCL − VCC TA = +25 °C, In external clock operation f = Internal operating frequency 350 300 250 ICCL ( A) 200 150 100 50 0 f = 8 kHz 3 4 5 VCC (V) 6 7 (Continued) 74 MB90385 Series ICCLS − VCC TA = +25 °C, In external clock operation f = Internal operating frequency 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICCLS ( A) f = 8 kHz 3 4 5 VCC (V) 6 7 ICCT − VCC TA = +25 °C, In external clock operation f = Internal operating frequency 10 9 8 7 ICCT ( A) 6 5 4 3 2 1 0 f = 8 kHz 3 4 5 VCC (V) 6 7 ICCH − VCC 30 25 ICCH ( A) 20 15 10 5 0 Stopping, TA = +25 °C 2 3 4 VCC (V) 5 6 7 (Continued) 75 MB90385 Series (Continued) (VCC - VOH) − IOH 1000 900 VCC VOH (mV) 800 700 600 500 400 300 200 100 0 TA = +25 °C, VCC = 4.5 V 0 1 2 3 4 5 IOH (mA) 6 7 8 9 10 VOL − IOL 1000 900 800 700 VOL (mV) 600 500 400 300 200 100 0 0 2 4 IOL (mA) 6 TA = +25 °C, VCC = 4.5 V 8 10 H level input voltage/ L level input voltage VIN − VCC TA = +25 °C 5 4 VIH VIN (V) 3 VIL 2 1 0 2.5 3 3.5 4 4.5 VCC (V) 5 5.5 6 76 MB90385 Series • MB90387 ICC − VCC TA = +25 °C, In external clock operation f = Internal operating frequency 25 20 ICC (mA) 15 f = 10 MHz 10 5 0 f = 8 MHz f = 4 MHz f = 2 MHz f = 16 MHz 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 VCC (V) ICCS − VCC TA = +25 °C, In external clock operation f = Internal operating frequency 9 8 7 ICCS (mA) 6 5 4 3 2 1 0 f = 4 MHz f = 2 MHz f = 10 MHz f = 8 MHz f = 16 MHz 2.5 3.5 4.5 VCC (V) 5.5 6.5 ICCL − VCC TA = +25 °C, In external clock operation f = Internal operating frequency 100 90 80 70 ICCL ( A) 60 50 40 30 20 10 0 f = 8 kHz 3 4 5 VCC (V) 6 7 (Continued) 77 MB90385 Series ICCLS − VCC TA = +25 °C, In external clock operation f = Internal operating frequency 10 9 8 ICCLS ( A) 7 6 5 4 3 2 1 0 f = 8 kHz 3 4 5 VCC (V) 6 7 ICCT − VCC TA = +25 °C, In external clock operation f = Internal operating frequency 10 9 8 7 ICCT ( A) 6 5 4 3 2 1 0 f = 8 kHz 3 4 5 VCC (V) 6 7 ICCH − VCC 30 25 20 ICCH ( A) 15 10 5 0 Stopping, TA = +25 °C 2 3 4 VCC (V) 5 6 7 (Continued) 78 MB90385 Series (Continued) (VCC - VOH) − IOH TA = +25 °C, VCC = 4.5 V 1000 900 800 VOH (mV) VCC 700 600 500 400 300 200 100 0 0 1 2 3 4 5 6 IOH (mA) 7 8 9 10 VOL − IOL 1000 900 800 700 VOL (mV) 600 500 400 300 200 100 0 0 TA = +25 °C, VCC = 4.5 V 1 2 3 4 5 6 IOL (mA) 7 8 9 10 H level input voltage/ L level input voltage VIN − VCC TA = +25 °C 5 4 VIH VIN (V) 3 2 1 0 2.5 VIL 3 3.5 4 4.5 VCC (V) 5 5.5 6 79 MB90385 Series s ORDERING INFORMATION Part number MB90F387PMT MB90387PMT MB90F387SPMT MB90387SPMT Package 48-pin plastic LQFP (FPT-48P-M26) Remarks 80 MB90385 Series s PACKAGE DIMENTION 48-pin plastic LQFP (FPT-48P-M26) 9.00±0.20(.354±.008)SQ Note 1) * : These dimensions include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. +.016 * 7.00 –0.10 .276 –.004 SQ 36 25 +0.40 0.145±0.055 (.006±.002) 37 24 0.08(.003) INDEX Details of "A" part 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) 48 13 "A" 0˚~8˚ LEAD No. 0.50(.020) 1 12 0.10±0.10 (.004±.004) (Stand off) 0.20±0.05 (.008±.002) 0.08(.003) M 0.25(.010) 0.60±0.15 (.024±.006) C 2003 FUJITSU LIMITED F48040S-c-2-2 Dimensions in mm (inches) Note : The values in parentheses are reference values. 81 MB90385 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 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