MB90F394H

FUJITSU SEMICONDUCTOR DATA SHEET DS07-13723-3E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90390 Series MB90F394H/V390H s DESCRIPTION The MB90390-series with up to five FULL-CAN* interfaces and FLASH ROM is especially designed for automotive and industrial applications. Its main feature are up to five on board CAN Interfaces, which conform to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN approach. With the new 0.35 µm CMOS technology, Fujitsu now offers on-chip FLASH-ROM program memory up to 512K bytes. An internal voltage booster removes the necessity for a second programming voltage. An on board voltage regulator provides 3 V to the internal MCU core. This creates a major advantage in terms of EMI and power consumption. The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external 4 MHz clock. The unit features 6 Stepper Motor Controllers with slew rate controlled high current outputs. Furthermore it features an 8 channel Output Compare Unit and a 6 channel Input Capture Unit with two separate 16-bit free running timers. Up to 4 UARTs constitute additional functionality for communication purposes. * : Controller Area Network (CAN) - License of Robert Bosch GmbH s PACKAGE 120-pin Plastic LQFP (FPT-120P-M21) MB90390 Series s FEATURES • • • • • • • • • • • • • • • • • • • • • • • • • 16-bit core CPU; 4 MHz external clock (24 MHz internal, 42 ns instruction execution time) New 0.35 µm CMOS Process Technology Internal voltage regulator supports 3 V MCU core, offering low EMI and low power consumption figures Up to five FULL-CAN interfaces; conforming to Version 2.0 Part A and Part B, flexible message buffering (mailbox and FIFO buffering can be mixed) Powerful interrupt functions (8 progr. priority levels; 8 external interrupts) EI2OS - Automatic transfer function indep.of CPU; 16 ch. of intelligent I/O Services 18-bit Time-base counter Watchdog Timer Up to 3 full duplex UARTs; support 10.4 KBand (USA standard ) 1 full duplex UART (SCI) Serial I/O : 1ch for synchronous data transfer Optional I2C with 400 Kbps A/D Converter : 8 ch to 15 ch. analog inputs (Resolution 10 bits or 8 bits) 16-bit reload timer × 2 ch ICU (Input capture) 16-bit × 6 ch (2 input pins are shared with OCU outputs) OCU (Output capture) 16-bit × 8 ch (2 output pins are shared with ICU input pins) 16-bit free running timer × 2 ch (FRT0 : ICU 0/1, OCU 0/1/2/3, FRT1 : ICU 2/3/4/5, OCU 4/5/6/7) 8/16-bit Programmable Pulse Generator 6ch × 16-bit / 12ch × 8-bit Stepping Motor Controller 6ch with slew rate controlled high current outputs Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) 4-byte instruction execution queue signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available Program Patch Function Fast Interrupt processing Low Power Consumption mode Sleep mode Timebase timer mode Stop mode CPU intermittent mode Sound Generator Real Time Watch Timer Programmable input levels (Automotive Hysteresis / CMOS Hysteresis, initial level is Automotive Hysteresis) Package : 120-pin plastic LQFP • • • • 2 MB90390 Series s PRODUCT LINEUP Part Number Parameter CPU System clock MB90F394H F2MC-16LX CPU On-chip PLL clock multiplier ( × 1, × 2, × 3, × 4, × 6, 1/2 when PLL stops) Minimum instruction execution time : 42 ns (4 MHz osc. PLL × 6) Boot-block Flash memory 384K bytes Hard-wired reset vector 10K bytes  0.35 µm CMOS with on-chip voltage regulator for internal power supply + Flash memory with On-chip charge pump for programming voltage 3.5 V to 5.5 V (4.5 V to 5.5 V if A/D Converter is used) −40 °C to +85 °C LQFP-120 2 channels UART External 16K bytes Yes MB90V390H ROM RAM Emulator-specific power supply*1 Technology 0.35 µm CMOS with on-chip voltage regulator for internal power supply Operating voltage range Temperature range Package 5 V ± 10%  PGA-299 3 channels Full duplex double buffer Supports asynchronous/synchronous (with start/stop bit) transfer Baud rate : 4808/9615/10417/19230/38460/62500/500000 bps (asynchronous) 500 K/1 M/2 Mbps (synchronous) at System clock = 24 MHz 1 channel  1 channel 1 channel UART (SCI) I2C (400 Kbps) Serial I/O Transfer can be started from MSB or LSB Supports internal clock synchronized transfer and external clock synchronized transfer Supports positive-edge and negative-edge clock synchronization Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock = 24 MHz 8 input channels 15 input channels 10-bit or 8-bit resolution Conversion time : Min 4.9 µs include sample time (per one channel) Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency) Supports External Event Count function Directly operates with the oscillation clock Facility to correct oscillation deviation Read/Write accessible Second/Minute/Hour registers Signals interrupts A/D Converter 16-bit Reload Timer (2 channels) Watch Timer (Continued) 3 MB90390 Series Part Number Parameter 16-bit I/O Timer (2 channels) MB90F394H MB90V390H Signals an interrupt when overflowing Supports Timer Clear when a match with Output Compare (Channel 0) Operation clock freq. : fsys/22, fsys/24, fsys/26, fsys/28 (fsys = System clock freq.) I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1, OCU 0/1/2/3 I/O Timer 1 (clock input FRCK1) corresponds to ICU 2/3/4/5, OCU 4/5/6/7 Signals an interrupt when a match with 16-bit I/O Timer Eight 16-bit compare registers. A pair of compare registers can be used to generate an output signal. OCU 6/7 outputs are shared with ICU 3/5 inputs Rising edge, falling edge or rising & falling edge sensitive Six 16-bit Capture registers Signals an interrupt upon external event ICU 3/5 inputs are shared with OCU 6/7 outputs 16-bit Output Compare (8 channels) 16-bit Input Capture (6 channels) Supports 8-bit and 16-bit operation modes Twelve 8-bit reload counters 8/16-bit Twelve 8-bit reload registers for L pulse width Programmable Pulse Twelve 8-bit reload registers for H pulse width Generator A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as (6 channels) 8-bit prescaler plus 8-bit reload counter Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 102.4 µs @fosc = 5 MHz (fsys = System clock frequency, fosc = Oscillation clock frequency) 2 channels Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 message buffers for data and ID’s Supports multiple messages Flexible configuration of acceptance filtering : Full bit compare/Full bit mask/Two partial bit masks Supports up to 1 Mbps Four high current outputs with controlled slew rate for each channel Synchronized two 8-bit PWM’s for each channel Can be programmed edge sensitive or level sensitive 8-bit PWM signal is mixed with tone frequency from 8-bit reload counter PWM frequency : 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8 kHz at System clock = 16 MHz Tone frequency : PWM frequency/2/ (reload value + 1) Virtually all external pins can be used as general purpose I/O All push-pull outputs Bit-wise programmable as input/output or peripheral signal Port-wise programmable as CMOS Hysteresis or automotive Hysteresis inputs (default) 5 channels CAN Interface (up to 5 channels) Stepping Motor Controller (6 channels) External Interrupt (8 channels) Sound Generator I/O Ports (Continued) 4 MB90390 Series (Continued) Part Number Parameter MB90F394H Supports automatic programming, Embedded AlgorithmTM*2 Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of erase cycles : 10,000 times Data retention time : 20 years Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory Boot block configuration Erase can be performed on each block Block protection with external programming voltage MB90V390H Flash Memory  *1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details. *2 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. 5 MB90390 Series s PIN ASSIGNMENTS • MB90V390H (TOP VIEW) P27/INT7 P26/INT6 P25/INT5 P24/INT4 P23/INT3 P22/INT2 P21/RX1 P20/TX1 P17/SGA P16/SGO P15/TOT0 P14/TIN0 X0 X1 VSS VCC P13/OUT5 P12/OUT4 P11/OUT3 P10/OUT2 P07/OUT1 P06/OUT0 P05/IN5/OUT7 P04/IN4 P03/IN3/OUT6 P02/IN2 P01/IN1 P00/IN0 P97/FRCK1/HCLKX PB7/FRCK0/HCLK P30/RX0 P31/TX0 P32/TIN1 P33/TOT1 P34/SOT0 P35/SCK0 P36/SIN0 P37/SIN1 P40/SCK1 P41/SOT1 P42/SDA P43/SCL P44 P45/ADTG VCC VSS C P46/INT0 P47/INT1 P50/PPG10 P51/PPG11 P52/PPG12 P53/PPG13 P54/PPG14 P55/PPG15 P56/PPG00/RX2 P57/PPG01/TX2 P90/SIN2 P91/SCK2 P92/SOT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RST MD0 MD1 MD2 DVSS DVCC PA7/PWM2M5 PA6/PWM2P5 PA5/PWM1M5 PA4/PWM1P5 PA3/PWM2M4 PA2/PWM2P4 PA1/PWM1M4 PA0/PWM1P4 DVSS DVCC P87/PWM2M3 P86/PWM2P3 P85/PWM1M3 P84/PWM1P3 P83/PWM2M2 P82/PWM2P2 P81/PWM1M2 P80/PWM1P2 DVSS DVCC P77/PWM2M1 P76/PWM2P1 P75/PWM1M1 P74/PWM1P1 6 P93/SIN3 P94/SCK3 P95/SOT3 P96/WOT AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 VSS PB0/PPG02/TX3/AN8 PB1/PPG03/RX3/AN9 PB2/PPG04/TX4/AN10 PB3/PPG05/RX4/AN11 PB4/SIN4/AN12 PB5/SCK4/AN13 PB6/SOT4/AN14 DVCC DVSS P70/PWM1P0 P71/PWM1M0 P72/PWM2P0 P73/PWM2M0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 (FPT-120P-M21) As seen with QFP120 probe cable MB90390 Series • MB90F394H (TOP VIEW) P27/INT7 P26/INT6 P25/INT5 P24/INT4 P23/INT3 P22/INT2 P21/RX1 P20/TX1 P17/SGA P16/SGO P15/TOT0 P14/TIN0 X0 X1 VSS VCC P13/OUT5 P12/OUT4 P11/OUT3 P10/OUT2 P07/OUT1 P06/OUT0 P05/IN5/OUT7 P04/IN4 P03/IN3/OUT6 P02/IN2 P01/IN1 P00/IN0 P97/FRCK1/HCLKX PB7/FRCK0/HCLK P30/RX0 P31/TX0 P32/TIN1 P33/TOT1 P34/SOT0 P35/SCK0 P36/SIN0 P37/SIN1 P40/SCK1 P41/SOT1 P42 P43 P44 P45/ADTG VCC VSS C P46/INT0 P47/INT1 P50/PPG10 P51/PPG11 P52/PPG12 P53/PPG13 P54/PPG14 P55/PPG15 P56/PPG00 P57/PPG01 P90 P91 P92 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RST MD0 MD1 MD2 DVSS DVCC PA7/PWM2M5 PA6/PWM2P5 PA5/PWM1M5 PA4/PWM1P5 PA3/PWM2M4 PA2/PWM2P4 PA1/PWM1M4 PA0/PWM1P4 DVSS DVCC P87/PWM2M3 P86/PWM2P3 P85/PWM1M3 P84/PWM1P3 P83/PWM2M2 P82/PWM2P2 P81/PWM1M2 P80/PWM1P2 DVSS DVCC P77/PWM2M1 P76/PWM2P1 P75/PWM1M1 P74/PWM1P1 P93/SIN3 P94/SCK3 P95/SOT3 P96/WOT AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 VSS PB0/PPG02 PB1/PPG03 PB2/PPG04 PB3/PPG05 PB4/SIN4 PB5/SCK4 PB6/SOT4 DVCC DVSS P70/PWM1P0 P71/PWM1M0 P72/PWM2P0 P73/PWM2M0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 (FPT-120P-M21) 7 MB90390 Series s PIN DESCRIPTION Pin no. 107 108 90 93 to 95 Pin name X1 X0 RST P00 to P02 IN0 to IN2 P03 96 IN3 OUT6 97 P04 IN4 P05 98 IN5 OUT7 99 to 104 P06, P07, P10 to P13 OUT0 to OUT5 109 110 111 112 113 114 115 to 120 1 2 P14 TIN0 P15 TOT0 P16 SGO P17 SGA P20 TX1 P21 RX1 P22 to P27 INT2 to INT7 P30 RX0 P31 TX0 D D D D D D D D D D D D D Circuit type A B D Oscillation output Oscillation input Reset input General purpose I/O Inputs for the Input Captures 0-2 General purpose I/O Input for the Input Capture 3 Output for the Output Compare 6 General purpose I/O Input for the Input Capture 4 General purpose I/O Input for the Input Capture 5 Output for the Output Compare 7 General purpose I/O Outputs for the Output Compares General purpose I/O TIN0 input for the 16-bit Reload Timer 0 General purpose I/O TOT0 output for the 16-bit Reload Timer 0 General purpose I/O SGO output for the Sound Generator General purpose I/O SGA output for the Sound Generator General purpose I/O TX output for CAN Interface 1 General purpose I/O RX input for CAN Interface 1 General purpose I/O External interrupt inputs for INT2 to INT7 General purpose I/O RX input for CAN Interface 0 General purpose I/O TX output for CAN Interface 0 Function (Continued) 8 MB90390 Series Pin no. 3 4 5 6 7 8 9 10 11 12 13 14 18, 19 20 to 25 Pin name P32 TIN1 P33 TOT1 P34 SOT0 P35 SCK0 P36 SIN0 P37 SIN1 P40 SCK1 P41 SOT1 P42 SDA P43 SCL P44 P45 ADTG P46, P47 INT0, INT1 P50 to P55 PPG10 to PPG15 P56 PPG00 RX2 P57 Circuit type D D D D D D D D D D D D D D General purpose I/O Function TIN1 input for the 16-bit Reload Timer 1 General purpose I/O TOT1 output for the 16-bit Reload Timer 1 General purpose I/O SOT output for UART 0 General purpose I/O SCK input/output for UART 0 General purpose I/O SIN input for UART 0 General purpose I/O SIN input for UART 1 General purpose I/O SCK input/output for UART 1 General purpose I/O SOT output for UART 1 General purpose I/O Serial data for I2C interface General purpose I/O Serial clock for I2C interface General purpose I/O General purpose I/O External trigger input of the A/D Converter General purpose I/O External interrupt inputs for INT0 to INT1 General purpose I/O Outputs for the Programmable Pulse Generators General purpose I/O Output for the Programmable Pulse Generator 0 RX input for CAN Interface 2 General purpose I/O 26 D 27 PPG01 TX2 P90 SIN2 D Output for the Programmable Pulse Generator 1 TX output for CAN Interface 2 General purpose I/O SIN input for UART 2 28 D (Continued) 9 MB90390 Series Pin no. 29 30 31 32 33 34 39 to 46 Pin name P91 SCK2 P92 SOT2 P93 SIN3 P94 SCK3 P95 SOT3 P96 WOT P60 to P67 AN0 to AN7 PB0 PPG02 TX3 AN8 PB1 PPG03 RX3 AN9 PB2 PPG04 TX4 AN10 PB3 PPG05 RX4 AN11 PB4 Circuit type D D D D D D E General purpose I/O Function SCK input/output for UART 2 General purpose I/O SOT output for UART 2 General purpose I/O SIN input for UART 3 (SCI) General purpose I/O SCK input/output for UART 3 (SCI) General purpose I/O SOT output for UART 3 (SCI) General purpose I/O WOT output for the Watch Timer General purpose I/O Inputs for the A/D Converter General purpose I/O Output for the Programmable Pulse Generator 2 TX output for CAN Interface 3 Input for the A/D Converter General purpose I/O Output for the Programmable Pulse Generator 3 RX input for CAN Interface 3 Input for the A/D Converter General purpose I/O Output for the Programmable Pulse Generator 4 TX output for CAN Interface 4 Input for the A/D Converter General purpose I/O Output for the Programmable Pulse Generator 5 RX input for CAN Interface 4 Input for the A/D Converter General purpose I/O 48 E 49 E 50 E 51 E 52 SIN4 AN12 E SIN input for the Serial I/O Input for the A/D Converter (Continued) 10 MB90390 Series Pin no. 53 Pin name PB5 SCK4 AN13 PB6 Circuit type General purpose I/O E Function SCK input/output for the Serial I/O Input for the A/D Converter General purpose I/O 54 SOT4 AN14 P70 to P73 PWM1P0 PWM1M0 PWM2P0 PWM2M0 P74 to P77 PWM1P1 PWM1M1 PWM2P1 PWM2M1 P80 to P83 PWM1P2 PWM1M2 PWM2P2 PWM2M2 P84 to P87 PWM1P3 PWM1M3 PWM2P3 PWM2M3 PA0 to PA3 PWM1P4 PWM1M4 PWM2P4 PWM2M4 PA4 to PA7 PWM1P5 PWM1M5 PWM2P5 PWM2M5 PB7 FRCK0 HCLK E SOT output for the Serial I/O Input for the A/D Converter General purpose I/O 57 to 60 F Output for Stepping Motor Controller channel 0 General purpose I/O F Output for Stepping Motor Controller channel 1 61 to 64 General purpose I/O F Output for Stepping Motor Controller channel 2 67 to 70 General purpose I/O F Output for Stepping Motor Controller channel 3 71 to 74 General purpose I/O F Output for Stepping Motor Controller channel 4 77 to 80 General purpose I/O F Output for Stepping Motor Controller channel 5 81 to 84 General purpose I/O D FRCK0 input for the 16-bit I/O Timer 0 Oscillation Clock output 91 (Continued) 11 MB90390 Series (Continued) Pin no. 92 55 65 75 85 56 66 76 86 35 36 37 38 88, 89 87 15 105 16 47 106 17 Pin name P97 FRCK1 HCLKX Circuit type General purpose I/O D Function FRCK1 input for the 16-bit I/O Timer 1 Inverted Oscillation Clock output DVcc  Dedicated power supply pins for the high current output buffers (Pin No. 57 to 84) DVss      C G    Dedicated ground pins for the high current output buffers (Pin No. 57 to 84) Dedicated power supply pin (5 V) for the A/D converter Dedicated pos. reference voltage pin for the A/D converter Dedicated neg. reference voltage pin for the A/D converter Dedicated power supply pin (0 V) for the A/D converter These are input pins used to designate the operating mode. They should be connected directly to VCC or VSS. This is an input pin used to designate the operating mode. It should be connected directly to VCC or VSS. These are power supply (5 V) input pins AVCC AVRH AVRL AVss MD1, MD0 MD2 Vcc Vss These are power supply (0 V) input pins This is the power supply stabilization capacitor pin. It should be connected to higher than or equal to 0.1 µF ceramic capacitor. C 12 MB90390 Series s I/O CIRCUIT TYPE Type X1 Clock input P-ch N-ch Circuit Remarks • Oscillation feedback resistor : 1 MΩ approx. X0 A Standby control signal VCC B R (pull-up) R CMOS HYS • CMOS Hysteresis input with pull-up Resistor : 50 kΩ approx. C R CMOS HYS • EVA device : CMOS Hysteresis input • Flash device : CMOS input. • CMOS output • CMOS Hysteresis input • Automotive Hysteresis input VCC P-ch D R R N-ch CMOS HYS Automotive HYS (Continued) 13 MB90390 Series (Continued) Type VCC P-ch Circuit • • • • Remarks CMOS output CMOS Hysteresis input Automotive Hysteresis input Analog input N-ch E P-ch Analog input N-ch R R CMOS HYS Automotive HYS Vcc P-ch High current • CMOS high current output • CMOS Hysteresis input • Automotive Hysteresis input F R R N-ch CMOS HYS Automotive HYS R CMOS HYS G R (pull-down) • EVA device : CMOS Hysteresis input with pulldown Resistor : 50 kΩ approx. • Flash device : CMOS input without pull-down. 14 MB90390 Series s HANDLING DEVICES Special care is required for the following when handling the device : • Preventing latch-up • Stabilization of supply voltage • Treatment of unused pins • Using external clock • Power supply pins (VCC/VSS) • Pull-up/down resistors • Crystal Oscillator Circuit • Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs • Connection of Unused Pins of A/D Converter if A/D Converter is unused. • Notes on Energization • Initialization • Caution on Operations during PLL Clock Mode 1. Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions : • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between VCC and VSS. • The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage. 2. Stabilization of supply voltage A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply voltage operating range. Therefore, the VCC supply voltage should be stabilized. For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values) at commercial frequencies (50 Hz to 60 Hz) fall below 10 of the standard VCC supply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching. 3. Treatment of unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 kΩ . Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. 4. Using external clock To use external clock, drive the X0 pin and leave X1 pin open. MB90390 Series X0 X1 15 MB90390 Series 5. Power supply pins (VCC/VSS) • If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latch up. To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally. • Connect VCC and VSS to the device from the current supply source at a low impedance. • As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between VCC and VSS in the vicinity of VCC and VSS pins of the device. VCC VSS VCC VSS VCC MB90390 Series VSS VCC VSS VSS VCC 6. Pull-up/down resistors The MB90390 Series does not support internal pull-up/down resistors. Use external components where needed. 7. Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic oscillator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground area for stabilizing the operation. 8. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN14) after turning-on the digital power supply (VCC) . Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable) . 9. Connection of Unused Pins of A/D Converter if A/D Converter is unused Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS. 10. Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 or more µs (0.2 V to 2.7 V) . 16 MB90390 Series 11. Initialization In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers, turn on the power again. 12. Notes on During Operation of PLL Clock Mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. 17 MB90390 Series s BLOCK DIAGRAMS MB90V390 X0, X1 RST Clock Controller 16LX CPU I/O Timer 0 RAM 16 K Input Capture 6 ch Output Compare 8 ch Prescaler x4 SOT3 to SOT0 SCK3 to SCK0 SIN3 to SIN0 Internal Data Bus UART 4 ch (1 ch SCI) 8/16-bit PPG 6 ch I/O Timer 1 FRCK0 IN5 to IN0 OUT7 to OUT0 FRCK1 PPG05 to PPG00 PPG15 to PPG10 Prescaler SOT4 SCK4 SIN4 AVcc AVss AN14 to AN0 AVRH AVRL ADTG 10-bit ADC 15 ch Serial I/O CAN 5 ch RX4 to RX0 TX4 to TX0 PWM1M5 to PWM1M0 PWM1P5 to PWM1P0 SMC 6 ch PWM2M5 to PWM2M0 PWM2P5 to PWM2P0 DVcc3 to DVcc0 DVss3 to DVss0 External Interrupt TIN1, TIN0 TOT1, TOT0 16-bit Reload Timer 2 ch Sound Generator WOT Watch Timer I2C Interface INT7 to INT0 SGO SGA SDA SCL 18 MB90390 Series MB90F394H X0, X1 RST Clock Controller 16LX CPU I/O Timer 0 FRCK0 RAM 10 K Input Capture 6 ch Output Compare 8 ch I/O Timer 1 IN5 to IN0 ROM/Flash 384 K OUT7 to OUT0 Prescaler x 3 SOT3, SOT1, SOT0 SCK3, SCK1, SCK0 SIN3, SIN1, SIN0 Internal Data Bus UART 3 ch (1 ch SCI) FRCK1 8/16-bit PPG 6 ch PPG05 to PPG00 PPG15 to PPG10 Prescaler SOT4 SCK4 SIN4 AVcc AVss AN7 to AN0 AVRH AVRL ADTG 10-bit ADC 8 ch Serial I/O CAN 2 ch RX1, RX0 TX1, TX0 PWM1M5 to PWM1M0 PWM1P5 to PWM1P0 SMC 6 ch PWM2M5 to PWM2M0 PWM2P5 to PWM2P0 DVcc3 to DVcc0 DVss3 to DVss0 External Interrupt TIN1, TIN0 TOT1, TOT0 16-bit Reload Timer 2 ch Sound Generator WOT Watch Timer INT7 to INT0 SGO SGA 19 MB90390 Series s MEMORY MAP MB90V390H FFFFFFH ROM (FF bank) FF0000H FEFFFFH ROM (FE bank) FE0000H FDFFFF H ROM (FD bank) FD0000H FCFFFF H FC0000H FBFFFFH FB0000H FA F F F F H ROM (FA bank) FA 0 0 0 0 H F9FFFFH ROM (F9 bank) F90000H 00FFFFH 008000H 0050FFH 004100H 003FFFH Peripheral 003500H 0030FFH RAM 12 K 000100H 0000BFH 000000H Peripheral 000100H 0000BFH 000000H 003500H 0028FFH ROM (Image of FF bank) RAM 4 K ROM (FC bank) ROM (FB bank) FF0000H FEFFFFH FFFFFFH MB90F394H ROM (FF bank) ROM (FE bank) FE0000H FDFFFF H ROM (FD bank) FD0000H FCFFFF H FC0000H FBFFFFH ROM (FB bank) FB0000H FA F F F F H ROM (FA bank) FA 0 0 0 0 H F9FFFFH ROM (F9 bank) F90000H 00FFFFH 004000H or 008000H 003FFFH Peripheral ROM (Image of FF bank) RAM 10 K Peripheral Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without using the far specification in the pointer declaration. For example, an attempt to access 00C000H accesses the value at FFC000H in ROM. The ROM area in bank FF exceeds 32/48K bytes, and its entire image cannot be shown in bank 00. The image between FF4000H/FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF3FFFH/FF7FFFH is visible only in bank FF. In MB90V390H, the image for only ROM data between FF8000H to FFFFFFH is visible in bank 00. As for MB90F394H, it is possible to set the FF bank area which looks the 00 bank image in the ROM mirror function select register (ROMM) . 20 MB90390 Series s I/O MAP Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH to 1FH 20H 21H 22H 23H Serial Mode Control 0 Status 0 Input/Output Data 0 Rate and Data 0 Register Port 0 Data Register Port 1 Data Register Port 2 Data Register Port 3 Data Register Port 4 Data Register Port 5 Data Register Port 6 Data Register Port 7 Data Register Port 8 Data Register Port 9 Data Register Port A Data Register Port B Data Register Analog Input Enable 0 Analog Input Enable 1/ ADC Select Input Level Select Register Input Level Select Register Port 0 Direction Register Port 1 Direction Register Port 2 Direction Register Port 3 Direction Register Port 4 Direction Register Port 5 Direction Register Port 6 Direction Register Port 7 Direction Register Port 8 Direction Register Port 9 Direction Register Port A Direction Register Port B Direction Register AbbreviaAccess tion PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PDRB ADER0 ADER1 ILSR ILSR DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA DDRB Reserved UMC0 USR0 UIDR0/ UODR0 URD0 R/W R/W R/W R/W UART0 00000100 00010000 XXXXXXXX 0000000X R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Port 6, A/D Port B, A/D Ports Ports Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 11111111 01111111 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 (Continued) 21 MB90390 Series Address 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H Register Serial Mode Control 1 Status 1 Input/Output Data 1 Rate and Data 1 Serial Mode Control 2 Status 2 Input/Output Data 2 Rate and Data 2 Serial Mode Control 4 Serial Mode Control 4 Serial Data 4 Serial I/O Prescaler/Edge Selector 4 External Interrupt Enable External Interrupt Request External Interrupt Level External Interrupt Level A/D Control Status 0 A/D Control Status 1 A/D Data 0 A/D Data 1 PPG0 Operation Mode Control Register PPG1 Operation Mode Control Register PPG0 and PPG1 Clock Select Register Address Detection Control Register 1 PPG2 Operation Mode Control Register PPG3 Operation Mode Control Register PPG2 and PPG3 Clock Select Register Clock Output Enable Register PPG4 Operation Mode Control Register PPG5 Operation Mode Control Register PPG4 and PPG5 Clock Select Register AbbreviaAccess tion UMC1 USR1 UIDR1/ UODR1 URD1 UMC2 USR2 UIDR2/ UODR2 URD2 SMCS4 SMCS4 SDR4 CDCR4 ENIR EIRR ELVR ELVR ADCS0 ADCS1 ADCR0 ADCR1 PPGC0 PPGC1 PPG01 PACSR1 PPGC2 PPGC3 PPG23 CKOE PPGC4 PPGC5 PPG45 Reserved R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Initial value 00000100 00010000 UART1 XXXXXXXX 0000000X 00000100 00010000 UART2 XXXXXXXX 0000000X XXXX0000 00000010 XXXXXXXX 0 X 0 X 0000 00000000 XXXXXXXX 00000000 00000000 00000000 00000000 XXXXXXXX 000010XX 0X000XX1 0X000001 000000XX 00000000 0X000XX1 0X000001 000000XX XXXXXX00 0X000XX1 0X000001 000000XX Serial I/O External Interrupt A/D Converter 16-bit Programable Pulse Generator 0/1 Address Maching Detection Function 1 16-bit Programable Pulse Generator 2/3 Clock Output 16-bit Programable Pulse Generator 4/5 (Continued) 22 MB90390 Series Address 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H PWM Control 1 Register PPG6 Operation Mode Control Register PPG7 Operation Mode Control Register PPG6 and PPG7 Clock Select Register PPG8 Operation Mode Control Register PPG9 Operation Mode Control Register PPG8 and PPG9 Clock Select Register PPGA Operation Mode Control Register PPGB Operation Mode Control Register PPGA and PPGB Clock Select Register Timer Control Status 0 Timer Control Status 0 Timer Control Status 1 Timer Control Status 1 Input Capture Control Status 0/1 Input Capture Control Status 2/3 Input Capture Control Status 4/5 Output Compare Control Status 0 Output Compare Control Status 1 Output Compare Control Status 2 Output Compare Control Status 3 Output Compare Control Status 4 Output Compare Control Status 5 Sound Control Sound Control Watch Timer Control Watch Timer Control PWM Control 0 AbbreviaAccess tion PPGC6 PPGC7 PPG67 Reserved PPGC8 PPGC9 PPG89 Reserved PPGCA PPGCB PPGAB Reserved TMCSR0 TMCSR0 TMCSR1 TMCSR1 ICS01 ICS23 ICS45 Reserved OCS0 OCS1 OCS2 OCS3 OCS4 OCS5 SGCR SGCR WTCR WTCR PWC0 Reserved PWC1 Reserved R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name 16-bit Programable Pulse Generator 6/7 Initial value 0X000XX1 0X000001 000000XX 0X000XX1 0X000001 000000XX 0X000XX1 0X000001 000000XX 00000000 XXXX0000 00000000 XXXX0000 00000000 00000000 00000000 0000XX00 0XX00000 0000XX00 0XX00000 0000XX00 0XX00000 00000000 0XXXXXX0 000XX000 00000000 00000XX0 16-bit Programable Pulse Generator 8/9 16-bit Programable Pulse Generator A/B 16-bit Reload Timer 0 16-bit Reload Timer 1 Input Capture 0/1 Input Capture 2/3 Input Capture 4/5 Output Compare 0/1 Output Compare 2/3 Output Compare 4/5 Sound Generator Watch Timer Stepping Motor Controller 0 Stepping Motor Controller 1 00000XX0 (Continued) 23 MB90390 Series Address 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 90H to 9DH 9EH 9FH A0H A1H A2H to A7H A8H A9H AAH to ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H ROM Mirror PWM Control 5 PWM Control 4 PWM Control 3 PWM Control 2 Register AbbreviaAccess tion PWC2 Reserved PWC3 Reserved PWC4 Reserved PWC5 Reserved Reserved ROMM Reserved W R/W R/W R/W R/W Resource name Stepping Motor Controller 2 Stepping Motor Controller 3 Stepping Motor Controller 4 Stepping Motor Controller 5 Initial value 00000XX0 00000XX0 00000XX0 00000XX0 ROM Mirror XXXXXXX1 70H to 8FH Reserved for CAN Interface 0/1. Refer to “s CAN CONTROLLERS” Address Maching Detection Function 0 Delayed Interrupt Low Power Controller Low Power Controller Watchdog Timer Time Base Timer Address Detection Control Register 0 Delayed Interrupt/Release Low-power Mode Clock Selector PACSR0 DIRR LPMCR CKSCR Reserved R/W R/W R/W R/W 00000000 XXXXXXX0 00011000 11111100 Watchdog Control Time Base Timer Control Flash Control Status (MB90F394H only. Otherwise reserved) Interrupt Control Register 00 Interrupt Control Register 01 Interrupt Control Register 02 Interrupt Control Register 03 Interrupt Control Register 04 Interrupt Control Register 05 Interrupt Control Register 06 WDTC TBTC Reserved FMCS Reserved ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 R/W R/W XXXXX111 1XX00100 R/W Flash Memory 000X0XX0 R/W R/W R/W R/W R/W R/W R/W Interrupt Controller 00000111 00000111 00000111 00000111 00000111 00000111 00000111 (Continued) 24 MB90390 Series Address B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H to FFH 3500H 3501H 3502H 3503H 3504H 3505H 3506H 3507H 3508H 3509H 350AH 350BH 350CH 350DH 350EH 350FH 3510H 3511H 3512H 3513H 3514H 3515H 3516H 3517H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Register Interrupt Control Register 07 Interrupt Control Register 08 Interrupt Control Register 09 Interrupt Control Register 10 Interrupt Control Register 11 Interrupt Control Register 12 Interrupt Control Register 13 Interrupt Control Register 14 Interrupt Control Register 15 AbbreviaAccess tion ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Reserved PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 PRLL4 PRLH4 PRLL5 PRLH5 PRLL6 PRLH6 PRLL7 PRLH7 PRLL8 PRLH8 PRLL9 PRLH9 PRLLA PRLHA PRLLB PRLHB R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Initial value 00000111 00000111 00000111 00000111 Interrupt Controller 00000111 00000111 00000111 00000111 00000111 XXXXXXXX 16-bit Programable Pulse Generator 0/1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 16-bit Programable Pulse Generator 2/3 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 16-bit Programable Pulse Generator 4/5 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 16-bit Programable Pulse Generator 6/7 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 16-bit Programable Pulse Generator 8/9 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 16-bit Programable Pulse Generator A/B XXXXXXXX XXXXXXXX XXXXXXXX (Continued) 25 MB90390 Series Address 3518H 3519H 351AH 351BH 351CH 351DH 351EH 351FH 3520H 3521H 3522H 3523H 3524H 3525H 3526H 3527H 3528H 3529H 352AH 352BH 352CH 352DH 352EH 352FH 3530H 3531H 3532H 3533H 3534H 3535H 3536H 3537H Register Serial Mode Register Serial Control Register Reception/Transmission Data Register Serial Status Register Extended Communication Control Reg. Extended Status/Control Register Baud Rate Register 0 Baud Rate Register 1 Input Capture 0 Input Capture 0 Input Capture 1 Input Capture 1 Input Capture 2 Input Capture 2 Input Capture 3 Input Capture 3 Input Capture 4 Input Capture 4 Input Capture 5 Input Capture 5 Timer Data 0 Timer Data 0 Timer Control 0 Timer Control 0 Output Compare 0 Output Compare 0 Output Compare 1 Output Compare 1 Output Compare 2 Output Compare 2 Output Compare 3 Output Compare 3 AbbreviaAccess tion SMR3 SCR3 RDR3/ TDR3 SSR3 ECCR3 ESCR3 BGR03 BGR13 IPCP0 IPCP0 IPCP1 IPCP1 IPCP2 IPCP2 IPCP3 IPCP3 IPCP4 IPCP4 IPCP5 IPCP5 TCDT0 TCDT0 TCCS0 TCCS0 OCCP0 OCCP0 OCCP1 OCCP1 OCCP2 OCCP2 OCCP3 OCCP3 R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Initial value 00000000 00000000 00000000 UART3 00001000 000000XX 00000X00 00000000 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000000 00000000 00000000 0XXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Input Capture 0/1 Input Capture 2/3 Input Capture 4/5 I/O Timer 0 Output Compare 0/1 Output Compare 2/3 (Continued) 26 MB90390 Series Address 3538H 3539H 353AH 353BH 353CH 353DH 353EH 353FH 3540H 3541H 3542H 3543H 3544H to 3545H 3546H 3547H 3548H 3549H 354AH 354BH 354CH 354DH 354EH 354FH 3550H 3551H 3552H 3553H 3554H 3555H 3556H 3557H Register Output Compare 4 Output Compare 4 Output Compare 5 Output Compare 5 Timer Data 1 Timer Data 1 Timer Control 1 Timer Control 1 Timer 0/Reload 0 Timer 0/Reload 0 Timer 1/Reload 1 Timer 1/Reload 1 AbbreviaAccess tion OCCP4 OCCP4 OCCP5 OCCP5 TCDT1 TCDT1 TCCS1 TCCS1 TMR0/ TMRLR0 TMR0/ TMRLR0 TMR1/ TMRLR1 TMR1/ TMRLR1 Reserved R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Initial value XXXXXXXX Output Compare 4/5 XXXXXXXX XXXXXXXX XXXXXXXX 00000000 00000000 00000000 0XXXXXXX I/O Timer 1 16-bit Reload Timer 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 16-bit Reload Timer 1 Frequency Dtata Amplitude Data Decrement Grade Tone Count Sub-second Data Sub-second Data Sub-second Data Second Data Minute Data Hour Data PWM1 Compare 0 PWM2 Compare 0 PWM1 Select 0 PWM2 Select 0 PWM1 Compare 1 PWM2 Compare 1 PWM1 Select 1 PWM2 Select 1 SGFR SGAR SGDR SGTR WTBR WTBR WTBR WTSR WTMR WTHR PWC10 PWC20 PWS10 PWS20 PWC11 PWC21 PWS11 PWS21 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Stepping Motor Controller 1 Stepping Motor Controller 0 Watch Timer Sound Generator XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XX000000 XX000000 XXX00000 XXXXXXXX XXXXXXXX 00000000 X0000000 XXXXXXXX XXXXXXXX 00000000 X0000000 (Continued) 27 MB90390 Series Address 3558H 3559H 355AH 355BH 355CH 355DH 355EH 355FH 3560H 3561H 3562H 3563H 3564H 3565H 3566H 3567H 3568H 3569H 356AH 356BH 356CH 356DH 356EH 356FH Register PWM1 Compare 2 PWM2 Compare 2 PWM1 Select 2 PWM2 Select 2 PWM1 Compare 3 PWM2 Compare 3 PWM1 Select 3 PWM2 Select 3 PWM1 Compare 4 PWM2 Compare 4 PWM1 Select 4 PWM2 Select 4 PWM1 Compare 5 PWM2 Compare 5 PWM1 Select 5 PWM2 Select 5 Output Compare Control Status 6 Output Compare Control Status 7 Output Compare 6 Output Compare 6 Output Compare 7 Output Compare 7 CAN Direct Mode Register CAN RX/TX redirect register AbbreviaAccess tion PWC12 PWC22 PWS12 PWS22 PWC13 PWC23 PWS13 PWS23 PWC14 PWC24 PWS14 PWS24 PWC15 PWC25 PWS15 PWS25 OCS6 OCS7 OCCP6 OCCP6 OCCP7 OCCP7 CDMR CANSWR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Initial value XXXXXXXX Stepping Motor Controller 2 XXXXXXXX 00000000 X0000000 XXXXXXXX XXXXXXXX 00000000 X0000000 XXXXXXXX XXXXXXXX 00000000 X0000000 XXXXXXXX XXXXXXXX 00000000 X0000000 0000XX00 XXX00000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Stepping Motor Controller 3 Stepping Motor Controller 4 Stepping Motor Controller 5 Output Compare 6/7 CAN Clock Sync CAN 0/1/2/3 XXXXXXX0 XXXX0000 3570H to Reserved for CAN Interface 2/3/4. Refer to “s CAN CONTROLLERS” 359FH 35A0H 35A1H 35A2H 35A3H 35A4H 35A5H 35A6H 35A7H 35A8H 35A9H to 35AAH 28 I2C Bus Status Register I C Bus Control Register I2C Ten Bit Slave Address Register I2C Ten Bit Address Mask Register I2C Seven Bit Slave Address Register I C Seven Bit Address Mask Register I C Data Register 2 2 2 IBSR IBCR ITBAL ITBAH ITMKL ITMKH ISBA ISMK IDAR Reserved R R/W R/W R/W R/W R/W R/W R/W R/W I2C Interface 00000000 00000000 00000000 XXXXXX00 11111111 00XXXX11 X0000000 01111111 00000000 (Continued) MB90390 Series Address 35ABH 35ACH to 35BFH 35C0H 35C1H 35C2H 35C3H to 35C8H 35C9H 35CAH 35CBH 35CCH to 35DFH 35E0H 35E1H 35E2H 35E3H 35E4H 35E5H 35E6H to 35EFH 35F0H 35F1H 35F2H 35F3H 35F4H 35F5H Register I2C Clock Control Register AbbreviaAccess tion ICCR Reserved R/W Resource name I2C Interface Initial value X0011111 Parameter Register Low Byte Parameter Register High Byte Clock Modulator Control Register CMPRL CMPRH CMCR Reserved R/W R/W R/W Clock Modulator 11111101 XX000010 00010000 Input Capture Edge 0/1 Input Capture Edge 2/3 Input Capture Edge 4/5 ICE01 ICE23 ICE45 Reserved R/W R R/W Input Capture 0/1 Input Capture 2/3 Input Capture 4/5 XXXXX0XX XXXXXXXX XXXXX0XX Detection Address Setting Register 0 (Low-order) Detection Address Setting Register 0 (Middle-order) Detection Address Setting Register 0 (High-order) Detection Address Setting Register 1 (Low-order) Detection Address Setting Register 1 (Middle-order) Detection Address Setting Register 1 (High-order) PADR0 PADR0 PADR0 PADR1 PADR1 PADR1 Reserved R/W R/W R/W R/W R/W R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Address Maching Detection Function 0 Detection Address Setting Register 3 (Low-order) Detection Address Setting Register 3 (Middle-order) Detection Address Setting Register 3 (High-order) Detection Address Setting Register 4 (Low-order) Detection Address Setting Register 4 (Middle-order) Detection Address Setting Register 4 (High-order) PADR3 PADR3 PADR3 PADR4 PADR4 PADR4 R/W R/W R/W R/W R/W R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Address Maching Detection Function 1 (Continued) 29 MB90390 Series (Continued) Address 35F6H 35F7H 35F8H 35F9H to 35FFH 3600H to 36FFH 3700H to 37FFH 3800H to 38FFH 3900H to 39FFH 3A00H to 3AFFH 3B00H to 3BFFH 3C00H to 3CFFH 3D00H to 3DFFH 3E00H to 3EFFH 3F00H to 3FFFH Register Detection Address Setting Register 5 (Low-order) Detection Address Setting Register 5 (Middle-order) Detection Address Setting Register 5 (High-order) AbbreviaAccess tion PADR5 PADR5 PADR5 Reserved Reserved for CAN Interface 0. Refer to “s CAN CONTROLLERS” Reserved for CAN Interface 0. Refer to “s CAN CONTROLLERS” Reserved for CAN Interface 1. Refer to “s CAN CONTROLLERS” Reserved for CAN Interface 1. Refer to “s CAN CONTROLLERS” Reserved for CAN Interface 2. Refer to “s CAN CONTROLLERS” Reserved for CAN Interface 2. Refer to “s CAN CONTROLLERS” Reserved for CAN Interface 3. Refer to “s CAN CONTROLLERS” Reserved for CAN Interface 3. Refer to “s CAN CONTROLLERS” Reserved for CAN Interface 4. Refer to “s CAN CONTROLLERS” Reserved for CAN Interface 4. Refer to “s CAN CONTROLLERS” R/W R/W R/W Resource name Initial value XXXXXXXX Address Maching XXXXXXXX Detection Function 1 XXXXXXXX • Explanation on read/write R/W : Readable and Writeble R : Read only W : Write only • Explanation on initial values 0 : Initial value is “0”. 1 : Initial value is “1”. X : Initial value is undefined. Note : Any write access to reserved addresses in I/O map should not be performed. A read access to reserved address results in reading “X”. 30 MB90390 Series s CAN CONTROLLERS The CAN controller has the following features : • Conforms to CAN Specification Version 2.0 Part A and B - Supports transmission/reception in standard frame and extended frame formats • Supports transmitting of data frames by receiving remote frames • 16 transmitting/receiving message buffers - 29-bit ID and 8-byte data - Multi-level message buffer configuration • Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as ID acceptance mask - Two acceptance mask registers in either standard frame format or extended frame formats • Bit rate programmable from 10 Kbps to 2 Mbps (when input clock is at 16 MHz) List of Control Registers (1) Address CAN0 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H CAN1 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H CAN2 003570H 003571H 003572H 003573H 003574H 003575H 003576H 003577H 003578H 003579H CAN3 003580H 003581H 003582H 003583H 003584H 003585H 003586H 003587H 003588H 003589H CAN4 003590H 003591H 003592H 003593H 003594H 003595H 003596H Register Message buffer valid register Transmit request register Transmit cancel register AbbreviaAccess tion BVALR TREQR TCANR TCR RCR RRTRR ROVRR RIER R/W R/W W R/W R/W R/W R/W R/W Initial Value 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Transmit 003597H complete register 003598H Receive complete register 003599H 00007AH 00008AH 00357AH 00358AH 00359AH Remote request 00007BH 00008BH 00357BH 00358BH 00359BH receiving register Receive overrun register 00007CH 00008CH 00357CH 00358CH 00359CH 00007DH 00008DH 00357DH 00358DH 00359DH 00007EH 00008EH 00357EH 00358EH 00359EH Receive interrupt 00007FH 00008FH 00357FH 00358FH 00359FH enable register 31 MB90390 Series List of Control Registers (2) Address CAN0 003700H 003701H 003702H 003703H 003704H 003705H 003706H 003707H 003708H 003709H CAN1 CAN2 CAN3 CAN4 003900H 003B00H 003D00H 003F00H 003901H 003B01H 003D01H 003F01H 003902H 003B02H 003D02H 003F02H 003903H 003B03H 003D03H 003F03H 003904H 003B04H 003D04H 003F04H 003905H 003B05H 003D05H 003F05H 003906H 003B06H 003D06H 003F06H 003907H 003B07H 003D07H 003F07H 003908H 003B08H 003D08H 003F08H 003909H 003B09H 003D09H 003F09H Register Control status register Last event indicator register Receive/transmit error counter Bit timing register IDE register Transmit RTR register Remote frame receive waiting register Transmit interrupt enable register AbbreviaAccess tion CSR LEIR RTEC BTR IDER TRTRR R/W, R R/W R R/W R/W R/W Initial Value 00XXX000 0XXXX0X1 XXXXXXXX 000X0000 00000000 00000000 X1111111 11111111 XXXXXXXX XXXXXXXX 00000000 00000000 XXXXXXXX XXXXXXXX 00000000 00000000 XXXXXXXX XXXXXXXX AMSR R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX AMR0 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX AMR1 R/W XXXXXXXX XXXXXXXX 00370AH 00390AH 003B0AH 003D0AH 003F0AH 00370BH 00390BH 003B0BH 003D0BH 003F0BH 00370CH 00390CH 003B0CH 003D0CH 003F0CH 00370DH 00390DH 003B0DH 003D0DH 003F0DH 00370EH 00390EH 003B0EH 003D0EH 003F0EH 00370FH 00390FH 003B0FH 003D0FH 003F0FH 003710H 003711H 003712H 003713H 003714H 003715H 003716H 003717H 003718H 003719H 00371AH 003910H 003B10H 003D10H 003F10H RFWTR R/W TIER R/W 003911H 003B11H 003D11H 003F11H Acceptance mask select 003912H 003B12H 003D12H 003F12H register 003913H 003B13H 003D13H 003F13H 003914H 003B14H 003D14H 003F14H 003915H 003B15H 003D15H 003F15H Acceptance mask register 0 003916H 003B16H 003D16H 003F16H 003917H 003B17H 003D17H 003F17H 003918H 003B18H 003D18H 003F18H 003919H 003B19H 003D19H 003F19H Acceptance mask register 1 00391AH 003B1AH 003D1AH 003F1AH 00371BH 00391BH 003B1BH 003D1BH 003F1BH 32 MB90390 Series List of Message Buffers (ID Registers) (1) Address CAN0 CAN1 CAN2 CAN3 CAN4 003600H 003800H 003A00H 003C00H 003E00H to to to to to 00361FH 00381FH 003A1FH 003C1FH 003E1FH 003620H 003621H 003622H 003623H 003624H 003625H 003626H 003627H 003628H 003629H 003820H 003A20H 003C20H 003E20H 003821H 003A21H 003C21H 003E21H 003822H 003A22H 003C22H 003E22H 003823H 003A23H 003C23H 003E23H 003824H 003A24H 003C24H 003E24H 003825H 003A25H 003C25H 003E25H 003826H 003A26H 003C26H 003E26H 003827H 003A27H 003C27H 003E27H 003828H 003A28H 003C28H 003E28H 003829H 003A29H 003C29H 003E29H ID register 2 IDR2 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 3 IDR3 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 4 IDR4 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 5 IDR5 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 6 IDR6 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 7 IDR7 R/W XXXXXXXX XXXXXXXX 33 ID register 1 IDR1 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 0 IDR0 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Register Generalpurpose RAM Abbreviation  Access Initial Value XXXXXXXX to XXXXXXXX XXXXXXXX XXXXXXXX R/W 00362AH 00382AH 003A2AH 003C2AH 003E2AH 00362BH 00382BH 003A2BH 003C2BH 003E2BH 00362CH 00382CH 003A2CH 003C2CH 003E2CH 00362DH 00382DH 003A2DH 003C2DH 003E2DH 00362EH 00382EH 003A2EH 003C2EH 003E2EH 00362FH 00382FH 003A2FH 003C2FH 003E2FH 003630H 003631H 003632H 003633H 003634H 003635H 003636H 003637H 003638H 003639H 003830H 003A30H 003C30H 003E30H 003831H 003A31H 003C31H 003E31H 003832H 003A32H 003C32H 003E32H 003833H 003A33H 003C33H 003E33H 003834H 003A34H 003C34H 003E34H 003835H 003A35H 003C35H 003E35H 003836H 003A36H 003C36H 003E36H 003837H 003A37H 003C37H 003E37H 003838H 003A38H 003C38H 003E38H 003839H 003A39H 003C39H 003E39H 00363AH 00383AH 003A3AH 003C3AH 003E3AH 00363BH 00383BH 003A3BH 003C3BH 003E3BH 00363CH 00383CH 003A3CH 003C3CH 003E3CH 00363DH 00383DH 003A3DH 003C3DH 003E3DH 00363EH 00383EH 003A3EH 003C3EH 003E3EH 00363FH 00383FH 003A3FH 003C3FH 003E3FH MB90390 Series List of Message Buffers (ID Registers) (2) Address CAN0 003640H 003641H 003642H 003643H 003644H 003645H 003646H 003647H 003648H 003649H CAN1 CAN2 Address CAN3 CAN4 Register Abbreviation Access Initial Value XXXXXXXX XXXXXXXX ID register 8 IDR8 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 9 IDR9 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 10 IDR10 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 11 IDR11 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 12 IDR12 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 13 IDR13 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 14 IDR14 R/W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ID register 15 IDR7 R/W XXXXXXXX XXXXXXXX 003840H 003A40H 003C40H 003E40H 003841H 003A41H 003C41H 003E41H 003842H 003A42H 003C42H 003E42H 003843H 003A43H 003C43H 003E43H 003844H 003A44H 003C44H 003E44H 003845H 003A45H 003C45H 003E45H 003846H 003A46H 003C46H 003E46H 003847H 003A47H 003C47H 003E47H 003848H 003A48H 003C48H 003E48H 003849H 003A49H 003C49H 003E49H 00364AH 00384AH 003A4AH 003C4AH 003E4AH 00364BH 00384BH 003A4BH 003C4BH 003E4BH 00364CH 00384CH 003A4CH 003C4CH 003E4CH 00364DH 00384DH 003A4DH 003C4DH 003E4DH 00364EH 00384EH 003A4EH 003C4EH 003E4EH 00364FH 00384FH 003A4FH 003C4FH 003E4FH 003650H 003651H 003652H 003653H 003654H 003655H 003656H 003657H 003658H 003659H 003850H 003A50H 003C50H 003E50H 003851H 003A51H 003C51H 003E51H 003852H 003A52H 003C52H 003E52H 003853H 003A53H 003C53H 003E53H 003854H 003A54H 003C54H 003E54H 003855H 003A55H 003C55H 003E55H 003856H 003A56H 003C56H 003E56H 003857H 003A57H 003C57H 003E57H 003858H 003A58H 003C58H 003E58H 003859H 003A59H 003C59H 003E59H 00365AH 00385AH 003A5AH 003C5AH 003E5AH 00365BH 00385BH 003A5BH 003C5BH 003E5BH 00365CH 00385CH 003A5CH 003C5CH 003E5CH 00365DH 00385DH 003A5DH 003C5DH 003E5DH 00365EH 00385EH 003A5EH 003C5EH 003E5EH 00365FH 00385FH 003A5FH 003C5FH 003E5FH 34 MB90390 Series List of Message Buffers (DLC Registers and Data Registers) (1) Address CAN0 003660H 003661H 003662H 003663H 003664H 003665H 003666H 003667H 003668H 003669H CAN1 CAN2 Address CAN3 CAN4 Register DLC register 0 DLC register 1 DLC register 2 DLC register 3 DLC register 4 DLC register 5 DLC register 6 DLC register 7 DLC register 8 DLC register 9 DLC register 10 DLC register 11 DLC register 12 DLC register 13 DLC register 14 DLC register 15 Abbreviation DLCR0 DLCR1 DLCR2 DLCR3 DLCR4 DLCR5 DLCR6 DLCR7 DLCR8 DLCR9 DLCR10 DLCR11 DLCR12 DLCR13 DLCR14 DLCR15 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 003860H 003A60H 003C60H 003E60H 003861H 003A61H 003C61H 003E61H 003862H 003A62H 003C62H 003E62H 003863H 003A63H 003C63H 003E63H 003864H 003A64H 003C64H 003E64H 003865H 003A65H 003C65H 003E65H 003866H 003A66H 003C66H 003E66H 003867H 003A67H 003C67H 003E67H 003868H 003A68H 003C68H 003E68H 003869H 003A69H 003C69H 003E69H 00366AH 00386AH 003A6AH 003C6AH 003E6AH 00366BH 00386BH 003A6BH 003C6BH 003E6BH 00366CH 00386CH 003A6CH 003C6CH 003E6CH 00366DH 00386DH 003A6DH 003C6DH 003E6DH 00366EH 00386EH 003A6EH 003C6EH 003E6EH 00366FH 00386FH 003A6FH 003C6FH 003E6FH 003670H 003671H 003672H 003673H 003674H 003675H 003676H 003677H 003678H 003679H 003870H 003A70H 003C70H 003E70H 003871H 003A71H 003C71H 003E71H 003872H 003A72H 003C72H 003E72H 003873H 003A73H 003C73H 003E73H 003874H 003A74H 003C74H 003E74H 003875H 003A75H 003C75H 003E75H 003876H 003A76H 003C76H 003E76H 003877H 003A77H 003C77H 003E77H 003878H 003A78H 003C78H 003E78H 003879H 003A79H 003C79H 003E79H 00367AH 00387AH 003A7AH 003C7AH 003E7AH 00367BH 00387BH 003A7BH 003C7BH 003E7BH 00367CH 00387CH 003A7CH 003C7CH 003E7CH 00367DH 00387DH 003A7DH 003C7DH 003E7DH 00367EH 00387EH 003A7EH 003C7EH 003E7EH 00367FH 00387FH 003A7FH 003C7FH 003E7FH 35 MB90390 Series List of Message Buffers (DLC Registers and Data Registers) (2) Address CAN0 003680H to 003687H CAN1 CAN2 Address CAN3 CAN4 Register Data register 0 (8 bytes) Data register 1 (8 bytes) Data register 2 (8 bytes) Data register 3 (8 bytes) Data register 4 (8 bytes) Data register 5 (8 bytes) Data register 6 (8 bytes) Data register 7 (8 bytes) Data register 8 (8 bytes) Data register 9 (8 bytes) Abbreviation DTR0 Access Initial Value XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX 003880H 003A80H 003C80H 003E80H to to to to 003887H 003A87H 003C87H 003E87H R/W 003688H 003888H 003A88H 003C88H 003E88H to to to to to 00368FH 00388FH 003A8FH 003C8FH 003E8FH 003690H to 003697H 003890H 003A90H 003C90H 003E90H to to to to 003897H 003A97H 003C97H 003E97H DTR1 R/W DTR2 R/W 003698H 003898H 003A98H 003C98H 003E98H to to to to to 00369FH 00389FH 003A9FH 003C9FH 003E9FH 0036A0H 0038A0H 003AA0H 003CA0H 003EA0H to to to to to 0036A7H 0038A7H 003AA7H 003CA7H 003EA7H 0036A8H 0038A8H 003AA8H 003CA8H 003EA8H to to to to to 0036AFH 0038AFH 003AAFH 003CAFH 003EAFH 0036B0H 0038B0H 003AB0H 003CB0H 003EB0H to to to to to 0036B7H 0038B7H 003AB7H 003CB7H 003EB7H 0036B8H 0038B8H 003AB8H 003CB8H 003EB8H to to to to to 0036BFH 0038BFH 003ABFH 003CBFH 003EBFH 0036C0H 0038C0H 003AC0H 003CC0H 003EC0H to to to to to 0036C7H 0038C7H 003AC7H 003CC7H 003EC7H 0036C8H 0038C8H 003AC8H 003CC8H 003EC8H to to to to to 0036CFH 0038CFH 003ACFH 003CCFH 003ECFH DTR3 R/W DTR4 R/W DTR5 R/W DTR6 R/W DTR7 R/W DTR8 R/W DTR9 R/W 0036D0H 0038D0H 003AD0H 003CD0H 003ED0H Data register 10 to to to to to (8 bytes) 0036D7H 0038D7H 003AD7H 003CD7H 003ED7H 0036D8H 0038D8H 003AD8H 003CD8H 003ED8H Data register 11 to to to to to (8 bytes) 0036DFH 0038DFH 003ADFH 003CDFH 003EDFH 0036E0H 0038E0H 003AE0H 003CE0H 003EE0H Data register 12 to to to to to (8 bytes) 0036E7H 0038E7H 003AE7H 003CE7H 003EE7H 0036E8H 0038E8H 003AE8H 003CE8H 003EE8H Data register 13 to to to to to (8 bytes) 0036EFH 0038EFH 003AEFH 003CEFH 003EEFH DTR10 R/W DTR11 R/W DTR12 R/W DTR13 R/W 36 MB90390 Series List of Message Buffers (DLC Registers and Data Registers) (3) Address CAN0 CAN1 CAN2 Address CAN3 CAN4 Register Abbreviation DTR14 Access Initial Value XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX 0036F0H 0038F0H 003AF0H 003CF0H 003EF0H Data register 14 to to to to to (8 bytes) 0036F7H 0038F7H 003AF7H 003CF7H 003EF7H 0036F8H 0038F8H 003AF8H 003CF8H 003EF8H Data register 15 to to to to to (8 bytes) 0036FFH 0038FFH 003AFFH 003CFFH 003EFFH R/W DTR15 R/W 37 MB90390 Series s INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER Interrupt cause Reset INT9 instruction Exception Time Base Timer External Interrupt INT0 to INT7 CAN 0 RX CAN 0 TX/NS CAN 1 RX CAN 1 TX/NS PPG 0/1 / (CAN 2 RX) PPG 2/3 / (CAN 2 TX/NS) PPG 4/5 / (CAN 3 RX) PPG 6/7 / (CAN 3 TX/NS) PPG 8/9 / (CAN 4 RX) PPG A/B / (CAN 4 TX/NS) 16-bit Reload Timer 0 16-bit Reload Timer 1 Input Capture 0/1 Output compare 0/1 Input Capture 2/3 / Output Compare 6 Output Compare 2/3 Input Capture 4/5 / Output Compare 7 Output Compare 4/5 / (I C) A/D Converter I/O Timer 0 / I/O Timer 1 / Watch Timer Serial I/O Sound Generator UART 0 RX UART 0 TX UART 1 RX UART 1 TX N/A N/A 2 EI2OS clear N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H Interrupt control register Number    ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 Address    0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH (Continued) 38 MB90390 Series (Continued) Interrupt cause (UART 2 RX) / UART 3 RX (UART 2 TX) / UART 3 TX Flash Memory Delayed interrupt N/A N/A EI2OS clear Interrupt vector Number #39 #40 #41 #42 Address FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register Number ICR14 ICR15 Address 0000BEH 0000BFH : The interrupt request flag is cleared by the EI2OS interrupt clear signal. : The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available. N/A : The interrupt request flag is not cleared by the EI2OS interrupt clear signal. Notes : For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags are cleared by the EI2OS interrupt clear signal. At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused by the first event. So it is recommended not to use the EI2OS for this interrupt number. If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control register (ICR) is asserted. This means that different interrupt sources share the same EI2OS Descriptor which should be unique for each interrupt source. For this reason, when one interrupt source uses the EI2OS, the other interrupt should be disabled. 39 MB90390 Series s ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol VCC AVCC Power supply voltage AVRH, AVRL DVCC Input voltage Output voltage Maximum Clamp Current Total Maximum Clamp Current “L” level maximum output current “L” level average output current “L” level maximum output current “L” level average output current “L” level maximum overall output current “L” level maximum overall output current “L” level average overall output current “L” level average overall output current “H” level maximum output current “H” level average output current “H” level maximum output current “H” level average output current “H” level maximum overall output current “H” level maximum overall output current “H” level average overall output current “H” level average overall output current Power consumption Operating temperature Storage temperature VI VO ICLAMP Σ|ICLAMP| IOL1 IOLAV1 IOL2 IOLAV2 ΣIOL1 ΣIOL2 ΣIOLAV1 ΣIOLAV2 IOH1 IOHAV1 IOH2 IOHAV2 ΣIOH1 ΣIOH2 ΣIOHAV ΣIOHAV PD TA TSTG Rating Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 −2.0                   −40 −55 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 +2.0 20 15 4 40 30 100 330 50 250 −15 −4 −40 −30 −100 −330 −50 −250 800 +85 +150 Unit V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA VCC = AVCC*1 AVCC ≥ AVRH, AVCC ≥ AVRL, AVRH ≥ AVRL VCC ≥ DVCC *2 *2 *5 *5 Normal outputs*3 Normal outputs, average value High current outputs*4 High current outputs, average value Sum of all normal outputs Sum of all high current outputs Sum of all normal outputs, average value Sum of all high current outputs, average value Normal outputs*3 Normal outputs, average value High current outputs*4 High current outputs, average value Sum of all normal outputs Sum of all high current outputs Sum of all normal outputs, average value Sum of all high current outputs, average value (VSS = AVSS = 0 V) Remarks mW MB90F394H °C °C (Continued) 40 MB90390 Series (Continued) *1: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on. *2: VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximun current to/from a input is limited by some means with external components, the ICLAMP rating supercedes the VI rating. *3: Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P90 to P97, PB0 to PB7 *4: Applicable to pins: P70 to P77, P80 to P87, PA0 to PA7 *5: • Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67 P70 to P77, P80 to P87, P90 to P97, PA0 to PA7, PB0 to PB6, PB7 • Use within recommended operating conditions. • Use at DC voltage (current) • The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the +B input pin open. • Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. • Sample recommended circuits: • Input/output equivalent circuits Protective diode VCC Limiting resistance +B input (0 V to 16 V) P-ch N-ch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 41 MB90390 Series 2. Recommended Conditions Value Min 3.5 3.0 4.5 0.1 −40 Typ 5.0     Max 5.5 5.5 5.5 1.0 +85 (VSS = AVSS = 0 V) Unit V V V µF °C Remarks Under normal operation Retain RAM data in stop mode *1 *2 Parameter Symbol VCC AVCC Power supply voltage Smoothing capacitor Operating temperature CS TA *1 : AVCC is a voltage at which accuracy is guaranteed. AVCC should not exceed VCC. *2 : Use a ceramic capacitor, or a capacitor of similar frequency characteristics. On the VCC pin, use a bypass capacitor that has a larger capacity than that of CS. Refer to the following figure for connection of smoothing capacitor CS. • C Pin Connection Diagram C CS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 42 MB90390 Series 3. DC Characteristics Parameter Symbol VIHS Input H voltage (At VCC = 5 V ± 10%) Pin  Condition  (TA = −40 °C to +85 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V) Value Min 0.8 VCC Typ  Max VCC + 0.3 Unit Remarks Port inputs if CMOS Hysteresis input levels are selected Port inputs if AUTOMOTIVE Hysteresis input levels are selected RST input pin (CMOS Hysteresis) MD input pin Port inputs if CMOS Hysteresis input levels are selected Port inputs if AUTOMOTIVE Hysteresis input levels are selected RST input pin (CMOS Hysteresis) MD input pin V VIHA   0.8 VCC  VCC + 0.3 V VIHR VIHM VILS       0.8 VCC VCC − 0.3 VSS − 0.3    VCC + 0.3 VCC + 0.3 0.2 VCC V V V Input L voltage (At VCC = 5 V ± 10%) VILA   VSS − 0.3  0.5 VCC V VILR VILM Output H voltage VOH1   Normal outputs   VCC = 4.5 V, IOH1 = −4.0 mA VCC = 4.5 V, IOH2 = −40.0 mA VSS − 0.3 VSS − 0.3 VCC − 0.5    0.2 VCC VSS + 0.3  V V V TA = − 40 °C   V TA = + 25 °C TA = + 85 °C   0.4 V TA = − 40 °C   0.5 V TA = + 25 °C TA = + 85 °C −5  5 µA Output H voltage VOH2 High current outputs VCC = 4.5 V, VCC − 0.5 IOH2 = −30.0 mA VCC = 4.5 V, IOH2 = −30.0 mA VCC = 4.5 V, IOL1 = 4.0 mA VCC = 4.5 V, IOL2 = 40.0 mA VCC = 4.5 V, IOL2 = 30.0 mA VCC = 4.5 V, IOL2 = 30.0 mA VCC = 5.5 V, VSS < VI < VCC Output L voltage VOL1 Normal outputs Output L voltage VOL2 High current outputs Input leak current IIL  (Continued) 43 MB90390 Series (TA = −40 °C to +85 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V) Parameter Symbol Pin Condition VCC = 5.0 V, Internal frequency : 20 MHz, At normal operation. VCC = 5.0 V, Internal frequency : 24 MHz, At normal operation. VCC = 5.0 V, Internal frequency : 20 MHz, At writing FLASH memory. VCC = 5.0 V, Internal frequency : 24 MHz, At writing FLASH memory. VCC = 5.0 V, Internal frequency : 20 MHz, At erasing FLASH memory. VCC = 5.0 V, Internal frequency : 24 MHz, At erasing FLASH memory. VCC VCC = 5.0 V, Internal frequency : 20 MHz, At Sleep mode. VCC = 5.0 V, Internal frequency : 24 MHz, At Sleep mode. VCC = 5.0 V, Internal frequency : 2.5 MHz, At Main Timer mode VCC = 5.0 V, Internal frequency : 20 MHz, At PLL Timer mode, external frequency = 5 MHz VCC = 5.0 V, Internal frequency : 24 MHz, At PLL Timer mode, external frequency = 4 MHz VCC = 5.0 V, At Stop mode, TA = +25°C Value Min  Typ 50 Max 70 Unit Remarks mA MB90F394H  60 85 mA MB90F394H  65 85 mA MB90F394H ICC  75 100 mA MB90F394H  70 90 mA MB90F394H  80 105 mA MB90F394H Power supply current* ICCS  22 30 mA MB90F394H  27 36 mA MB90F394H ICTS  0.3 0.6 mA MB90F394H ICTSPLL4  4 6 mA MB90F394H ICTSPLL6  5 7 mA MB90F394H ICCH  5 100 µA MB90F394H (Continued) 44 MB90390 Series (Continued) Symbol (TA = −40 °C to +85 °C, VCC = 5.0 V ± 10%, VSS = AVSS = 0 V) Pin Other than C, AVCC, AVSS, AVRH, AVRL, VCC, VSS, DVCC, DVSS, P70 to P77, P80 to P87, PA0 to PA7 P70 to P77, P80 to P87, PA0 to PA7 Condition Value Min Typ Max Unit Remarks Parameter   5 15 pF Input capacity CIN   15 30 pF * : The power supply current is measured with an external clock. 45 MB90390 Series 4. AC Characteristics (1) Clock Timing (TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = AVSS = 0 V) Symbol Pin X0, X1 X0 Oscillation cycle time tCYL X0, X1 X0 Input clock pulse width Input clock rise and fall time PWH, PWL tCR, tCF X0 X0 Value Min 3 3 125 83.33 20  Typ       Max 8 12 333 333  5 Unit MHz MHz ns ns ns ns Remarks When using a crystal oscillator or a ceramic oscilltor* When using an external clock* When using a crystal oscillator or a ceramic oscillator When using an external clock Duty ratio is about 30% to 70%. When using external clock When using clock modulation, be sure that the maximum momentary frequency Fmax does not exceed 24 MHz. Refer to the Clock Modulator chapter of the Hardware Manual. Parameter Oscillation frequency fC Machine clock frequency fCP  1.5  24 MHz Machine clock cycle time tCP  41.67  666 ns * : When selecting the PLL clock, the range of clock frequency is limitted. Use this product within range as mentioned in “• Guaranteed PLL operation range”. • Clock Timing tCYL X0 PWH tCF PWL tCR 0.8 VCC 0.2 VCC 46 MB90390 Series • Guaranteed PLL operation range Guaranteed operation range Guaranteed PLL operation range (PLL2=1) 5.5 Power supply voltage VCC (V) 4.5 3.5 Guaranteed PLL operation range (PLL2=0) Guaranteed A/D converter operation range 1.5 4 8 Machine clock fCP (MHz) 20 24 Guaranteed operation range of MB90F394H • PLL2 (bit 0 in PLLC register) = 0 Guaranteed oscilation frequency range Machine clock fCP (MHz) 20 16 12 8 6 4 1.5 3 4 6 8 10 ×1*1 (CS=00) ×4 (CS=11) ×3 (CS=10) ×2 (CS=01) ×1/2 (PLL off) 12 External clock fC (MHz)*2 • PLL2 (bit 0 in PLLC register) = 1 ×6 (CS=10) Guaranteed oscilation frequency range ×4 (CS=01) ×2 (CS=00) 24 Machine clock fCP (MHz) 16 8 6 1.5 3 4 6 8 10 ×1/2 (PLL off) 12 External clock fC (MHz)*2 *1 : PLL × 1 guaranteed operation range is from 4.0 MHz to 12 MHz. *2 : When using a crystal oscillator or a ceramic oscillator, the maximum oscillation clock frequency is 8 MHz External clock frequency and Machine clock frequency 47 MB90390 Series (2) Reset Standby Input (TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V) Pin Value Min 16 tCP*1 Oscillation time of oscillator*2 + 100µs + 16 tCP*1 100 Max    Unit ns ns µs Remarks Under normal operation In Stop mode In Time Base Timer mode Parameter Symbol Reset input time tRSTL RST *1 : “tCP” represents one cycle time of the machine clock. No reset can fully initialize the Flash Memory if it is performing the automatic algorithm. *2 : Oscillation time of oscillator is the time that the amplitude reaches 90%. In the crystal oscillator, the oscillation time is between several ms and to tens of ms. In FAR / ceramic oscillators, the oscillation time is between hundreds of µs to several ms. With an external clock, the oscillation time is 0 ms. • Under Normal Operation tRSTL RST 0.2 VCC 0.2 VCC • In Stop Mode tRSTL RST 0.2 VCC 90% of amplitude 0.2 VCC X0 Internal operation clock Oscillation time of oscillator +100 µs 16 tCP Oscillation setting time Instruction execution Internal reset 48 MB90390 Series (3) Power On Reset (TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V) Pin VCC VCC Condition  Value Min 0.05 1 Max 30  Unit ms ms Due to repetitive operation Remarks Parameter Power on rise time Power off time Symbol tR tOFF tR 2.7 V 0.2 V 0.2 V tOFF If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you startup smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within 1 V/s, you can operate while using the PLL clock. 0.2 V VCC VCC 3V VSS Holds RAM data We recommend a rise of 50 mV/ms maximum. 49 MB90390 Series (4) UART0/1/2/3, Serial I/O Timing Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX (TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V) Pin SCK0 to SCK4 SCK0 to SCK4, SOT0 to SOT4 Internal clock operation output SCK0 to SCK4, pins are SIN0 to SIN4 CL = 80 pF + 1 TTL. SCK0 to SCK4, SIN0 to SIN4 SCK0 to SCK4 SCK0 to SCK4 SCK0 to SCK4, External clock SOT0 to SOT4 operation output pins are SCK0 to SCK4, CL = 80 pF + 1 TTL. SIN0 to SIN4 SCK0 to SCK4, SIN0 to SIN4 Condition Value Min 8 tCP −80 100 60 4 tCP 4 tCP  60 60 Max  +80     150   Unit ns ns ns ns ns ns ns ns ns Remarks Parameter Serial clock cycle time SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCK ↓ → SOT delay time Valid SIN → SCK ↑ SCK ↑ → Valid SIN hold time Notes : • AC characteristic in CLK synchronized mode. • CL is load capacity value of pins when testing. • tCP is the machine cycle. 50 MB90390 Series • Internal Shift Clock Mode SCK 0.8 V tSLOV 2.4 V tSCYC 2.4 V 0.8 V SOT 0.8 V tIVSH VIH tSHIX VIH VIL SIN VIL • External Shift Clock Mode tSLSH VIH VIL tSLOV 2.4 V VIL tSHSL VIH SCK SOT 0.8 V tIVSH VIH tSHIX VIH VIL SIN VIL 51 MB90390 Series (5) Timer Related Resource Input Timing (TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V) Condition  Value Min 4 tCP Max  Unit ns Remarks Parameter Input pulse width Symbol tTIWH tTIWL Pin TIN0, TIN1 IN0 to IN5 • Timer Input Timing VIH VIH VIL tTIWH tTIWL VIL (6) Trigger Input Timing (TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V) Pin INT0 to INT7, ADTG Condition Value Min 5 tCP 1 Max   Unit ns µs Remarks Under normal operation In stop mode Parameter Symbol tTRGH tTRGL Input pulse width  • Trigger Input Timing VIH VIH VIL tTRGH tTRGL VIL (7) Slew Rate High Current Outputs Symbol tR2 tF2 (TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V) Condition  Value Min 15 Typ  Max  Unit Remarks Parameter Pin P70 to P77, P80 to P87, PA0 to PA7 Output Rise/Fall time ns • Slew Rate Output Timing VH VL tR2 tF2 VH VL VH = VOL2 + 0.9 ´ (VOH2 - VOL2) VL = VOL2 + 0.1 ´ (VOH2 - VOL2) 52 MB90390 Series (8) I2C Timing (TA = −40 °C to +85 °C, VCC = 3.5 V to 5.5 V, VSS = 0 V) Parameter SCL clock frequency Hold time (repeated) START condition SDA ↓ → SCL ↓ “L” width of the SCL clock “H” width of the SCL clock Set-up time for a repeated START condition SCL ↑ → SDA ↓ Data hold time SCL ↓ → SDA ↓ ↑ Data set-up time SDA ↓ ↑ → SCL ↑ Set-up time for STOP condition SCL ↑ → SDA ↑ Bus free time between a STOP and START condition Symbol fSCL tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tSUSTO tBUS R = 1.3 kΩ, C = 50 pF*1 Condition Standard-mode Min 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 Max 100     3.45*2    Fast-mode*4 Min 0 0.6 1.3 0.6 0.6 0 100 0.6 1.3 Max 400     0.9*3    Unit kHz µs µs µs µs µs ns µs µs *1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal. *3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSUDAT ≥ 250 ns must then be met. *4 : For use at over 100 kHz, set the machine clock to at least 6 MHz. SDA tBUS tLOW SCL tSUDAT tHDSTA tHDSTA tHDDAT tHIGH tSUSTA tSUSTO 53 MB90390 Series 5. A/D Converter (TA = −40 °C to +85 °C, 3.0 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V ± 10%, VSS = AVSS = 0 V) Symbol     VOT VFST   IAIN VAIN   IA IAH IR IRH  Pin     AN0 to AN7 AN0 to AN7   AN0 to AN7 AN0 to AN7 AVRH AVRL AVCC AVCC AVRH AVRH AN0 to AN7 Value Min     AVRL − 1.5 AVRH − 3.5 3.3 1.6 −5 AVRL AVRL + 2.7 0      Typ     AVRL + 0.5 AVRH − 1.5 66 tCP 32 tCP     3.5  165   Max 10 ±3.0 ±2.5 ±1.9 AVRL + 2.5 AVRH + 0.5 16500 Unit bit LSB LSB LSB LSB LSB µs µs µA V V V mA µA µA µA LSB * * Remarks Parameter Resolution Conversion error Nonlinearity error Differential nonlinearity error Zero reading voltage Full scale reading voltage Compare time Sampling time Analog port input current Analog input voltage range Reference voltage range Power supply current Reference voltage current Offset between input channels ∞ +5 AVRH AVCC AVRH − 2.7 7.5 5 250 5 4 * : When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) . Terminology Conversion error : Absolute maximum conversion deviation with respect to the theoretical conversion line. Nonlinearity : Relative maximum conversion deviation with respect to the theoretical conversion line connecting to the device unique zero reading voltage and full scale reading voltage. Differential nonlinearity : Max conversion deviation in any two adjacent reading voltages with respect to the the oretical LSB conversion step. Zero reading voltage : Input voltage which results in the minimum conversion value. Full scale reading voltage : Input voltage which results in the maximum coversion value. Notes : The accuracy gets worse as AVRH − AVRL becomes smaller. 54 MB90390 Series 6. Definition of A/D Converter Terms : Analog variation that is recognized by an A/D converter. : Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” ) and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion characteristics. Differential linear : Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal error value. Total error : Difference between an actual value and an ideal value. A total error includes zero transition error, full-scale transition error, and linear error. Resolution Linear error Total error 3FF 3FE 3FD Digital output {1 LSB × (N − 1) + 0.5 LSB} Actual conversion characteristics 1.5 LSB 004 003 002 001 0.5 LSB AVSS Analog input VNT (Actually-measured value) Actual conversion characteristics Ideal characteristics AVRH Total error of digital output “N” = VNT − {1 LSB × (N − 1) + 0.5 LSB} 1 LSB AVRH − AVSS 1 LSB = (Ideal value) [V] 1024 VOT (Ideal value) = AVSS + 0.5 LSB [V] VFST (Ideal value) = AVRH − 1.5 LSB [V] [LSB] VNT : A voltage at which digital output transitions from (N − 1) to N. (Continued) 55 MB90390 Series (Continued) Linear error 3FF 3FE 3FD Digital output Actual conversion characteristics {1 LSB × (N − 1) + VOT } N+1 VFST (actual measurement value) VNT (actual measurement value) Actual conversion characteristics Actual conversion characteristics Differential linear error Ideal characteristics Digital output N 004 003 002 N−1 V (N + 1) T (actual measurement value) VNT (actual measurement value) Actual conversion characteristics AVRH Analog input Ideal characteristics 001 VOT (actual measurement value) AVSS Analog input AVRH N−2 AVSS Linear error of digital output N = Differential linear error of digital output N = 1 LSB = VNT − {1 LSB × (N − 1) + VOT} 1 LSB V (N+1) T − VNT 1 LSB VFST − VOT 1022 −1 LSB [LSB] [V] [LSB] VOT : Voltage at which digital output transits from “000H” to “001H.” VFST : Voltage at which digital output transits from “3FEH” to “3FFH.” 56 MB90390 Series 7. Notes on A/D Converter Section Use the device with external circuits of the following output impedance for analog inputs : Recommended output impedance of external circuits are : Approx. 3.1 kΩ or lower (4.5 V ≤ AVCC ≤ 5.5 V) (sampling period = 1.60 µs at 20 MHz machine clock) . If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high as internal capacitor. If toutput impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient. • Analog input circuit model Analog input R Comparator C R = 2.35 kΩ, C = 36.4 pF : : Note : Use the values in the figure only as a guideline. 8. Flash Memory Program/Erase Characteristics Parameter Sector erase time Chip erase time Word (16 bit width) programming time Programs/Erase cycle Flash Data Retention Time  Average TA = +85 °C TA = +25 °C VCC = 5.0 V Conditions Value MIn    10,000 20 Typ 1 9 16   Max 15  3,600   Unit s s µs cycle Year * Remarks Excludes programming prior to erasure Excludes programming prior to erasure Except for the over head time of the system * : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 °C) . 57 MB90390 Series s EXAMPLE CHARACTERISTICS ICC − VCC (Ta = +25 °C) 60 fcp = 20 MHz 50 fcp = 15 MHz 10 40 ICCS [mA] ICC [mA] fcp = 10 MHz 30 fcp = 5 MHz 20 fcp = 2.5 MHz 10 4 8 12 14 ICCS − VCC (fcp = 2.5 MHz, Ta = +25 °C) 6 2 0 2.0 3.0 4.0 5.0 VCC [V] 6.0 7.0 0 2.0 3.0 4.0 5.0 VCC [V] 6.0 7.0 ICTS − VCC (fcp = 2.5 MHz, Ta = +25 °C) 20 600 18 500 16 14 400 ICCS [ A] ICTS [ A] 12 10 8 6 4 100 2 0 2.0 3.0 4.0 5.0 VCC [V] 6.0 7.0 0 2.0 3.0 ICCH − VCC (Ta = +25 °C) 300 200 4.0 5.0 VCC [V] 6.0 7.0 58 MB90390 Series s ORDERING INFORMATION Part number MB90F394HPMT MB90V390HCR Package 120-pin Plastic LQFP (FPT-120P-M21) 299-pin Ceramic PGA (PGA-299C-A01) For evaluation Remarks 59 MB90390 Series s PACKAGE DIMENSION 120-pin Plastic LQFP (FPT-120P-M21) Note 1) * : These dimensions do not include resin protrusion. Resin protrusion is +0.25 (.010) MAX (each side) . Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 18.00±0.20(.709±.008)SQ * 16.00 –0.10 .630 +.016 SQ –.004 90 61 +0.40 91 60 0.08(.003) Details of "A" part 1.50 –0.10 .059 –.004 +0.20 +.008 (Mounting height) INDEX 0~8˚ 120 31 "A" 0.10±0.05 (.004±.002) (Stand off) 0.25(.010) LEAD No. 1 30 0.50(.020) 0.22±0.05 (.009±.002) 0.08(.003) M 0.145 .006 +0.05 –0.03 +.002 –.001 0.60±0.15 (.024±.006) C 2002 FUJITSU LIMITED F120033S-c-4-4 Dimensions in mm (inches) . Note : The values in parentheses are reference values. 60 MB90390 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0405 © FUJITSU LIMITED Printed in Japan