MB90F439SPMC

FUJITSU MICROELECTRONICS DATA SHEET DS07-13727-2E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90435 Series MB90437L (S) /438L (S) /F438L (S) MB90439 (S) /F439 (S) /V540G ■ DESCRIPTION The MB90435 series with FLASH ROM is specially designed for industrial applications. The instruction set by F2MC-16LX CPU core inherits an AT architecture of the F2MC* family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions.The micro controller has a 32-bit accumulator for processing long word data. The MB90435 series has peripheral resources of 8/10-bit A/D converters, UART (SCI) , extended I/O serial interfaces, 8/16-bit timer, I/O timer (input capture (ICU) , output compare (OCU) ) . * : F2MC is the abbreviation of FUJITSU Flexible Microcontroller. ■ FEATURES • Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from : divided-by-2 of oscillation or one to four times the oscillation Minimum instruction execution time : 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock, VCC of 5.0 V) Subsystem Clock : 32 kHz (Continued) The information for microcontroller supports is shown in the following homepage. Be sure to refer to the "Check Sheet" for the latest cautions on development. "Check Sheet" is seen at the following support page "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development. http://edevice.fujitsu.com/micom/en-support/ Copyright©2002-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2008.8 MB90435 Series • Instruction set to optimize controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions Enhanced precision calculation realized by the 32-bit accumulator • Instruction set designed for high level language (C language) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions • Program patch function (for two address pointers) • Enhanced execution speed : 4-byte Instruction queue • Enhanced interrupt function : 8 levels, 34 factors • Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI2OS) • Embedded ROM size and types Mask ROM : 64 Kbytes / 128 Kbytes / 256 Kbytes Flash ROM : 128 Kbytes/256 Kbytes Embedded RAM size : 2 Kbytes/4 Kbytes/6 Kbytes/8 Kbytes (evaluation chip) • Flash ROM Supports automatic programming, Embedded Algorithm Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory Erase can be performed on each block Block protection with external programming voltage • Low-power consumption (stand-by) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) CPU intermittent operation mode Clock mode Hardware stand-by mode • Process 0.5 µm CMOS technology • I/O port General-purpose I/O ports : 81 ports • Timer Watchdog timer : 1 channel 8/16-bit PPG timer : 8/16-bit × 4 channels 16-bit re-load timer : 2 channels • 16-bit I/O timer 16-bit free-run timer : 1 channel Input capture : 8 channels Output compare : 4 channels • Extended I/O serial interface : 1 channel • UART 0 With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used. (Continued) 2 DS07-13727-2E MB90435 Series (Continued) • UART 1 With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized serial (extended I/O serial) can be used. • External interrupt circuit (8 channels) A module for starting an extended intelligent I/O service (EI2OS) and generating an external interrupt which is triggered by an external input. • Delayed interrupt generation module Generates an interrupt request for switching tasks. • 8/10-bit A/D converter (8 channels) 8/10-bit resolution can be selectively used. Starting by an external trigger input. Conversion time : 26.3 µs • External bus interface : Maximum address space 16 Mbytes • Package: QFP-100, LQFP-100 DS07-13727-2E 3 MB90435 Series ■ PRODUCT LINEUP Features CPU System clock MB90F438L (S) /F439 (S) MB90437L (S) /438L (S) /439 (S) F2MC-16LX CPU On-chip PLL clock multiplier (×1, ×2, ×3, ×4, 1/2 when PLL stop) Minimum instruction exection time : 62.5 ns (4 MHz osc. PLL × 4) Flash memory MB90F438L(S) : 128 Kbytes MB90F439(S) : 256 Kbytes MB90F438L(S) : 4 Kbytes MB90F439(S) : 6 Kbytes MB90F438L/F439 : Two clocks system MB90F438LS/F439S : One clock system Mask ROM : MB90437L(S): 64 Kbytes MB90438L(S): 128 Kbytes MB90439(S): 256 Kbytes MB90437L(S): 2 Kbytes MB90438L(S): 4 Kbytes MB90439(S): 6 Kbytes MB90437L/438L/439 : Two clocks system MB90437LS/438LS/439S : One clock system *3 −40 °C to 105 °C QFP100, LQFP100 ⎯ PGA-256 None External MB90V540G ROM RAM 8 Kbytes Clocks Operating voltage range Temperature range Package Emulator-specify power supply*2 UART0 Two clocks system*1 Full duplex double buffer Support asynchronous/synchronous (with start/stop bit) transfer Baud rate : 4808/5208/9615/10417/19230/38460/62500/500000 bps (asynchronous) 500 K/1 M/2 Mbps (synchronous) at System clock = 16 MHz Full duplex double buffer Asynchronous (start-stop synchronized) and CLK-synchronous communication Baud rate : 1202/2404/4808/9615/19230/31250/38460/62500 bps (asynchronous) 62.5 K/125 K/250 K/500 K/1 M/2 Mbps (synchronous) at 6, 8, 10, 12, 16 MHz Transfer can be started from MSB or LSB Supports internal clock synchronized transfer and external clock synchronized transfer Supports positive-edge and nagative-edge clock synchronization Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock = 16 MHz 10-bit or 8-bit resolution 8 input channels Conversion time : 26.3 µs (per one channel) (Continued) UART1 (SCI) Serial I/O A/D Converter 4 DS07-13727-2E MB90435 Series (Continued) Features 16-bit Reload Timer (2 channels) 16-bit Free-run Timer MB90F438L (S) /F439 (S) MB90437L (S) /438L (S) /439 (S) MB90V540G Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency) Supports External Event Count function Signals an interrupt when overflow Supports Timer Clear when a match with Output Compare (Channel 0) Operation clock freq. : fsys/22, fsys/24, fsys/26, fsys/28 (fsys = System clock freq.) Signals an interrupt when a match with 16-bit Free-run Timer 16-bit Output Compare Four 16-bit compare registers (4 channels) A pair of compare registers can be used to generate an output signal 16-bit Input Capture (8 channels) Rising edge, falling edge or rising & falling edge sensitive Four 16-bit Capture registers Signals an interrupt upon external event Supports 8-bit and 16-bit operation modes Eight 8-bit reload counters Eight 8-bit reload registers for L pulse width Eight 8-bit reload registers for H pulse width A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter 4 output pins Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz (fsys = System clock frequency, fosc = Oscillation clock frequency) Sub-clock for low power operation Can be programmed edge sensitive or level sensitive External access using the selectable 8-bit or 16-bit bus is enabled (external bus mode.) Virtually all external pins can be used as general purpose I/O All push-pull outputs and schmitt trigger inputs Bit-wise programmable as input/output or peripheral signal 8/16-bit Programmable Pulse Generator (4 channels) 32 kHz Sub-clock External Interrupt (8 channels) External bus interface I/O Ports Supports automatic programming, Embeded Algorithm Write/Erase/Erase-Suspend/Erase-Resume commands A flag indicating completion of the algorithm Number of erase cycles : 10,000 times Flash Memory Data retention time : 10 years Boot block configuration Erase can be performed on each block Block protection by externally programmed voltage *1 : If the one clock system is used, equip X0A and X1A with clocks from the tool side. *2 : It is setting of DIP switch S2 when Emulator pod (MB2145-507) is used.Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details. *3 : OPERATING VOLTAGE RANGE Products Operation guarantee range MB90F439 (S) /439 (S) /V540G MB90F438L (S) /437L (S) /438L (S) 4.5 V to 5.5 V 3.5 V to 5.5 V DS07-13727-2E 5 MB90435 Series ■ PIN ASSIGNMENT (TOP VIEW) P17/AD15 P16/AD14 P15/AD13 P14/AD12 P13/AD11 P12/AD10 P11/AD09 P10/AD08 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 X0 VSS P20/A16 P21/A17 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL/WR P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SOT0 P41/SCK0 P42/SIN0 P43/SIN1 P44/SCK1 VCC P45/SOT1 P46/SOT2 P47/SCK2 C P50/SIN2 P51/INT4 P52/INT5 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 X0A X1A PA0 RST P97 P96 P95 P94 P93/INT3 P92/INT2 P91/INT1 P90/INT0 P87/TOT1 P86/TIN1 P85/OUT1 P84/OUT0 P83/PPG3 P82/PPG2 P81/PPG1 P80/PPG0 P77/OUT3/IN7 P76/OUT2/IN6 P75/IN5 P74/IN4 P73/IN3 P72/IN2 P71/IN1 P70/IN0 HST MD2 P53/INT6 P54/INT7 P55/ADTG AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P56/TIN0 P57/TOT0 MD0 MD1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (FPT-100P-M06) (Continued) 6 DS07-13727-2E MB90435 Series (Continued) (TOP VIEW) 100 P21/A17 99 P20/A16 98 P17/AD15 97 P16/AD14 96 P15/AD13 95 P14/AD12 94 P13/AD11 93 P12/AD10 92 P11/AD09 91 P10/AD08 90 P07/AD07 89 P06/AD06 88 P05/AD05 87 P04/AD04 86 P03/AD03 85 P02/AD02 84 P01/AD01 83 P00/AD00 82 VCC 81 X1 80 X0 79 VSS 78 X0A 77 X1A 76 PA0 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL/WR P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SOT0 P41/SCK0 P42/SIN0 P43/SIN1 P44/SCK1 VCC P45/SOT1 P46/SOT2 P47/SCK2 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 RST P97 P96 P95 P94 P93/INT3 P92/INT2 P91/INT1 P90/INT0 P87/TOT1 P86/TIN1 P85/OUT1 P84/OUT0 P83/PPG3 P82/PPG2 P81/PPG1 P80/PPG0 P77/OUT3/IN7 P76/OUT2/IN6 P75/IN5 P74/IN4 P73/IN3 P72/IN2 P71/IN1 P70/IN0 DS07-13727-2E P50/SIN2 P51/INT4 P52/INT5 P53/INT6 P54/INT7 P55/ADTG AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P56/TIN0 P57/TOT0 MD0 MD1 MD2 HST 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (FPT-100P-M20) 7 MB90435 Series ■ PIN DESCRIPTION Pin No. LQFP*2 80 81 78 77 75 50 QFP*1 82 83 80 79 77 52 Pin name X0 X1 X0A X1A RST HST P00 to P07 83 to 90 85 to 92 AD00 to AD07 P10 to P17 91 to 98 93 to 100 AD08 to AD15 I I Circuit type Function A High speed crystal oscillator input pins (Oscillation) Low speed crystal oscillator input pins. For the one clock system parts, perfom external pull-down processing. A (Oscillation) Low speed crystal oscillator input pins. For the one clock system parts, leave it open. B C External reset request input pin Hardware standby input pin General I/O port with programmable pull-up. This function is enabled in the single-chip mode. I/O pins for 8 lower bits of the external address/data bus. This function is enabled when the external bus is enabled. General I/O port with programmable pull-up. This function is enabled in the single-chip mode. I/O pins for 8 higher bits of the external address/data bus. This function is enabled when the external bus is enabled. General I/O port with programmable pull-up. In external bus mode, this function is valid when the corresponding bits in the external address output control register (HACR) are set to “1”. I 8-bit output pins for A16 to A23 at the external address bus. In external bus mode, this function is valid when the corresponding bits in the external address output control register (HACR) are set to “0”. General I/O port with programmable pull-up. This function is enabled in the single-chip mode. Address latch enable output pin. This function is enabled when the external bus is enabled. General I/O port with programmable pull-up. This function is enabled in the single-chip mode. Read strobe output pin for the data bus. This function is enabled when the external bus is enabled. General I/O port with programmable pull-up. This function is enabled in the single-chip mode or when the WR/WRL pin output is disabled. I Write strobe output pin for the data bus. This function is enabled when both the external bus and the WR/WRL pin output are enabled. WRL is write-strobe output pin for the lower 8 bits of the data bus in 16-bit access. WR is write-strobe output pin for the 8 bits of the data bus in 8-bit access. (Continued) P20 to P27 99 to 6 1 to 8 A16 to A23 P30 7 9 ALE P31 8 10 RD I I P32 10 12 WRL WR 8 DS07-13727-2E MB90435 Series Pin No. LQFP*2 QFP*1 Pin name Circuit type Function General I/O port with programmable pull-up. This function is enabled in the single-chip mode, external bus 8-bit mode or when WRH pin output is disabled. P33 11 13 WRH I Write strobe output pin for the 8 higher bits of the data bus. This function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the WRH output pin is enabled. General I/O port with programmable pull-up. This function is enabled in the single-chip mode or when the hold function is disabled. Hold request input pin. This function is enabled when both the external bus and the hold functions are enabled. General I/O port with programmable pull-up. This function is enabled in the single-chip mode or when the hold function is disabled. Hold acknowledge output pin. This function is enabled when both the external bus and the hold functions are enabled. General I/O port with programmable pull-up. This function is enabled in the single-chip mode or when the external ready function is disabled. Ready input pin. This function is enabled when both the external bus and the external ready functions are enabled. General I/O port with programmable pull-up. This function is enabled in the single-chip mode or when the CLK output is disabled. CLK output pin. This function is enabled when both the external bus and CLK outputs are enabled. General I/O port. This function is enabled when UART0 disables the serial data output. Serial data output pin for UART0. This function is enabled when UART0 enables the serial data output. General I/O port. This function is enabled when UART0 disables serial clock output. Serial clock I/O pin for UART0. This function is enabled when UART0 enables the serial clock output. General I/O port. This function is always enabled. Serial data input pin for UART0. Set the corresponding Port Direction Register to input if this function is used. General I/O port. This function is always enabled. Serial data input pin for UART1. Set the corresponding Port Direction Register to input if this function is used. (Continued) P34 12 14 HRQ I P35 13 15 HAK I P36 14 16 RDY I P37 15 17 CLK P40 16 18 SOT0 P41 17 19 SCK0 P42 18 20 SIN0 P43 19 21 SIN1 G G G G H DS07-13727-2E 9 MB90435 Series Pin No. LQFP*2 QFP*1 Pin name P44 Circuit type Function General I/O port. This function is enabled when UART1 disables the clock output. Serial clock pulse I/O pin for UART1. This function is enabled when UART1 enables the serial clock output. General I/O port. This function is enabled when UART1 disables the serial data output. Serial data output pin for UART1. This function is enabled when UART1 enables the serial data output. General I/O port. This function is enabled when the Extended I/O serial interface disables the serial data output. 20 22 SCK1 P45 G 22 24 SOT1 P46 G 23 25 SOT2 G Serial data output pin for the Extended I/O serial interface. This function is enabled when the Extended I/O serial interface enables the serial data output. General I/O port. This function is enabled when the Extended I/O serial interface disables the clock output. P47 24 26 SCK2 P50 26 28 SIN2 P51 to P54 27 to 30 29 to 32 INT4 to INT7 P55 31 33 ADTG P60 to P63 36 to 39 38 to 41 AN0 to AN3 P64 to P67 41 to 44 43 to 46 AN4 to AN7 P56 45 47 TIN0 D E E D D D G Serial clock pulse I/O pin for the Extended I/O serial interface . This function is enabled when the Extended I/O serial interface enables the Serial clock output. General I/O port. This function is always enabled. Serial data input pin for the Extended I/O serial interface . Set the corresponding Port Direction Register to input if this function is used. General I/O port. This function is always enabled. External interrupt request input pins for INT4 to INT7. Set the corresponding Port Direction Register to input if this function is used. General I/O port. This function is always enabled. Trigger input pin for the A/D converter. Set the corresponding Port Direction Register to input if this function is used. General I/O port. This function is enabled when the analog input enable register specifies a port. Analog input pins for the 8/10-bit A/D converter. This function is enabled when the analog input enable register specifies A/D. General I/O port. The function is enabled when the analog input enable register specifies a port. Analog input pins for the 8/10-bit A/D converter. This function is enabled when the analog input enable register specifies A/D. General I/O port. This function is always enabled. Event input pin for the 16-bit reload timers 0. Set the corresponding Port Direction Register to input if this function is used. (Continued) 10 DS07-13727-2E MB90435 Series Pin No. LQFP*2 QFP*1 Pin name P57 Circuit type Function General I/O port. This function is enabled when the 16-bit reload timers 0 disables the output. Output pin for the 16-bit reload timers 0. This function is enabled when the 16-bit reload timers 0 enables the output. General I/O ports. This function is always enabled. Trigger input pins for input captures ICU0 to ICU5. Set the corresponding Port Direction Register to input if this function is used. General I/O ports. This function is enabled when the OCU disables the waveform output. Event output pins for output compares OCU2 and OCU3. This function is enabled when the OCU enables the waveform output. Trigger input pins for input captures ICU6 and ICU7. Set the corresponding Port Direction Register to input and disable the OCU waveform output if this function is used. General I/O ports. This function is enabled when 8/16-bit PPG disables the waveform output. Output pins for 8/16-bit PPGs. This function is enabled when 8/16-bit PPG enables the waveform output. General I/O ports. This function is enabled when the OCU disables the waveform output. 46 48 TOT0 P70 to P75 D 51 to 56 53 to 58 IN0 to IN5 D P76 , P77 57 , 58 59 , 60 OUT2 , OUT3 D IN6 , IN7 P80 to P83 59 , 62 61 to 64 PPG0 to PPG3 P84 , P85 63 , 64 65 , 66 OUT0 , OUT1 P86 65 67 TIN1 D D D Waveform output pins for output compares OCU0 and OCU1. This function is enabled when the OCU enables the waveform output. General I/O port. This function is always enabled. Input pin for the 16-bit reload timers 1. Set the corresponding Port Direction Register to input if this function is used. General I/O port. This function is enabled when the 16-bit reload timers 0 disables the output. Output pin for the 16-bit reload timers 1.This function is enabled when the 16-bit reload timers 1 enables the output. General I/O port. This function is always enabled. External interrupt request input pins for INT0 to INT3. Set the corresponding Port Direction Register to input if this function is used. General I/O port. (Continued) P87 66 68 TOT1 P90 to P93 67 to 70 69 to 72 INT0 to INT3 P94 D D 71 73 D DS07-13727-2E 11 MB90435 Series (Continued) Pin No. LQFP*2 72 73 74 76 32 QFP*1 74 75 76 78 34 Pin name P95 P96 P97 PA0 AVCC Circuit type D D D D Power supply Power supply Power supply Power supply C F ⎯ Power supply Power supply General I/O port. General I/O port. General I/O port. General I/O port. Function Power supply pin for the A/D Converter. This power supply must be turned on or off while a voltage higher than or equal to AVCC is applied to VCC. Power supply pin for the A/D Converter. External reference voltage input pin for the A/D Converter. This power supply must be turned on or off while a voltage higher than or equal to AVRH is applied to AVCC. External reference voltage input pin for the A/D Converter. Input pins for specifying the operating mode. The pins must be directly connected to VCC or VSS. Input pin for specifying the operating mode. The pin must be directly connected to VCC or VSS. Power supply stabilization capacitor pin. It should be connected externally to an 0.1 µF ceramic capacitor. Input pin for power supply (5.0 V) . Input pin for power supply (0.0 V) . 35 37 AVSS 33 35 AVRH 34 47 48 49 25 21, 82 9, 40, 79 36 49 50 51 27 23, 84 11, 42, 81 AVRL MD0 MD1 MD2 C VCC VSS *1 : FPT-100P-M06 *2 : FPT-100P-M20 12 DS07-13727-2E MB90435 Series ■ I/O CIRCUIT TYPE Circuit type A X1,X1A Clock input Diagram Remarks • High-speed oscillation feedback resistor : 1 MΩ approx. • Low-speed oscillation feedback resistor : 10 MΩ approx. X0,X0A Hard, soft standby control B • Hysteresis input • Pull-up resistor : 50 kΩ approx. R (Pull-up) R HYS input C R HYS input • Hysteresis input D VCC P-ch • CMOS level output • CMOS Hysteresis input N-ch R HYS input (Continued) DS07-13727-2E 13 MB90435 Series Circuit type E Diagram Remarks • CMOS level output • CMOS Hysteresis input • Analog input VCC P-ch N-ch P-ch Analog input N-ch R HYS input F R HYS input • Hysteresis input • Pull-down Resistor : 50 kΩ approx. (except FLASH devices) R (Pull-down) G VCC P-ch • CMOS level output • CMOS Hysteresis input • TTL level input (FLASH devices in FLASH writer mode only) N-ch R R T HYS input TTL level input (Continued) 14 DS07-13727-2E MB90435 Series (Continued) Circuit type H Pull-up ON/OFF select signal VCC P-ch P-ch Diagram Remarks • CMOS level output • CMOS Hysteresis input • Programmable pull-up resistor : 50 kΩ approx. VCC N-ch R HYS input I Pull-up ON/OFF select signal VCC P-ch P-ch VCC • CMOS level output • CMOS Hysteresis input • TTL level input (FLASH devices in FLASH writer mode only) • Programmable pull-up resistor : 50 kΩ approx. N-ch R HYS input R T TTL level input DS07-13727-2E 15 MB90435 Series ■ HANDLING DEVICES (1) Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions : • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between VCC and VSS. • The AVcc power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. For the same reason, care must also be taken in not allowing the analog power-supply voltage (AVCC, AVRH) to exceed the digital power-supply voltage. (2) Handling unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefor they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 kΩ. Unused bi-directional pins should be set to the output state and can be left open, or the input state with the above described connection. (3) Using external clock To use external clock, drive X0 pin only and leave X1 pin unconnected. Below is a diagram of how to use external clock. MB90435 Series X0 Open X1 (4) Use of the sub-clock Use one clock system parts when the sub-clock is not used. In that case, pull-down the pin X0A and leave the pin X1A open. When using two clock system parts, a 32 kHz oscillator has to be connected to the X0A and X1A pins. (5) Power supply pins (VCC/VSS) In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However you must connect the pins to an external power and a ground line to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via the lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pins near the device. VCC VSS VCC VSS VCC MB90435 Series VSS VCC VSS VSS VCC 16 DS07-13727-2E MB90435 Series (6) Pull-up/down resistors The MB90435 Series does not support internal pull-up/down resistors (except Port0 − Port3 : pull-up resistors) . Use external components where needed. (7) Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via the shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuits do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground area for stabilizing the operation. (8) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC) . Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable) . (9) Connection of Unused Pins of A/D Converter Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS. (10) N.C. Pin The N.C. (internally connected) pin must be opened for use. (11) Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 µs or more (0.2 V to 2.7 V) . (12) Initialization In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers, please turn on the power again. (13) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions In the Signed multiplication and division instructions (“DIV A, Ri” and “DIVW A, RWi”) , the value of the corresponding bank register (DTB, ADB, USB, SSB) is set in “00H”. If the values of the corresponding bank registers (DTB, ADB, USB, SSB) are set to other than “00H”, the remainder by the execution result of the instruction is not stored in the register of the instruction operand. (14) Using REALOS The use of EI2OS is not possible with the REALOS real time operating system. (15) Caution on Operations during PLL Clock Mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. DS07-13727-2E 17 MB90435 Series ■ BLOCK DIAGRAM X0, X1 X0A, X1A RST HST 16-bit Free-run Timer 16-bit Input Capture 8 ch. 16-bit Output Compare 4 ch. IN0 to IN5 IN6/OUT2, IN7/OUT3 OUT0, OUT1 Clock Controller F2MC 16LX CPU RAM 2 K/4 K/6 K/8 K ROM/Flash 64K/128 K/256 K (ROM only) Prescaler SOT0 SCK0 SIN0 Prescaler SOT1 SCK1 SIN1 Prescaler SOT2 SCK2 SIN2 AVCC AVSS AN0 to AN7 AVRH AVRL ADTG 10-bit A/D Converter 8 ch. External Interrupt 8 ch. Serial I/O External Bus Interface UART1 (SCI) FMC-16 Bus 16-bit Reload Timer 2 ch. TIN0, TIN1 TOT0, TOT1 UART0 8/16-bit PPG 4 ch. PPG0 to PPG3 AD00 to AD15 A16 to A23 ALE RD WRL WRH HRQ HAK RDY CLK INT0 to INT7 18 DS07-13727-2E MB90435 Series ■ MEMORY MAP The memory space of the MB90435 Series is shown below. MB90V540G FFFFFFH ROM (FF bank) FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H External 00FFFFH 00FFFFH 004000H 003FFFH Peripheral 003900H External 002000H 0020FFH 001FF5H 001FF0H ROM correction 0010FFH RAM 8 K 000100H External 0000BFH 000000H Peripheral 000000H 0008FFH RAM 2 K 000100H 0000BFH Peripheral External 0000BFH 000000H RAM 4 K 000100H External Peripheral 0000BFH 000000H 000100H External Peripheral 0018FFH RAM 6 K 003900H External ROM (Image of FF bank) ROM (Image of FF bank) Peripheral 003900H 002000H External 00FFFFH 004000H 003FFFH Peripheral 003900H 002100H External ROM (Image of FF bank) 00FFFFH 004000H 003FFFH Peripheral ROM (Image of FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) FFFFFFH ROM (FF bank) FF0000H FF0000H FEFFFFH FE0000H ROM (FE bank) MB90F437L (S) MB90F438L (S)/438L (S) FFFFFFH ROM (FF bank) FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H External ROM (FE bank) ROM (FD bank) ROM (FC bank) MB90F439 (S) /439 (S) ROM (FF bank) FFFFFFH External External 004000H 003FFFH Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits address are the same, the table in ROM can be referenced without using the “far” specification in the pointer declaration. For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.The ROM area in bank FF exceeds 48 Kbytes, and its entire image cannot be shown in bank 00.The image between FF4000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF3FFFH is visible only in bank FF. DS07-13727-2E 19 MB90435 Series ■ I/O MAP Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH to 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register Analog Input Enable register Port 0 pull-up control register Port 1 pull-up control register Port 2 pull-up control register Port 3 pull-up control register Serial Mode Control Register 0 Serial Status Register 0 Serial input data register 0/ Serial output data register 0 Rate and data register 0 Register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Abbreviation Access Resource name PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA Reserved DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA ADER PUCR0 PUCR1 PUCR2 PUCR3 UMC0 USR0 UIDR0/ UODR0 URD0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W UART0 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 6, A/D Port 0 Port 1 Port 2 Port 3 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B _ _ _ _ _ _ _0B 1 1 1 1 1 1 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B 0 0 0 1 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0XB (Continued) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB _ _ _ _ _ _ _XB 20 DS07-13727-2E MB90435 Series Address 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H Register Serial mode register 1 Serial control register 1 Serial input data register 1/ Serial output data register 1 Serial status register 1 UART1 prescaler control register Serial Edge select register Serial I/O prescaler Serial mode control register Serial mode control register Serial data register Serial Edge select register External interrupt enable register External interrupt request register External interrupt level register External interrupt level register A/D control status register 0 A/D control status register 1 A/D data register 0 A/D data register 1 PPG0 operation mode control register PPG1 operation mode control register PPG0/1 clock selection register PPG2 operation mode control register PPG3 operation mode control register PPG2/3 Clock Selection Register PPG4 operation mode control register PPG5 operation mode control register PPG4/5 clock selection register PPG6 operation mode control register PPG7 operation mode control register PPG6/7 clock selection register Abbreviation Access Resource name Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B SMR1 SCR1 SIDR1/ SODR1 SSR1 U1CDCR SES1 Prohibited SCDCR SMCS SMCS SDR SES2 ENIR EIRR ELVR ELVR ADCS0 ADCS1 ADCR0 ADCR1 PPGC0 PPGC1 PPG01 Prohibited PPGC2 PPGC3 PPG23 Prohibited PPGC4 PPGC5 PPG45 Prohibited PPGC6 PPGC7 PPG67 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W A/D Converter External Interrupt Extended I/O Serial Interface UART1 XXXXXXXXB 0 0 0 0 1_0 0B 0_ _ _1 1 1 1B _ _ _ _ _ _ _0B 0_ _ _1 1 1 1B _ _ _ _0 0 0 0B 0 0 0 0 0 0 1 0B XXXXXXXXB _ _ _ _ _ _ _0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 1 _ XXB 0 _ 0 0 0 _ _ 1B 16-bit Programmable Pulse 0 _ 0 0 0 0 0 1B Generator 0/1 0 0 0 0 0 0 _ _B 0 _ 0 0 0 _ _1B 16-bit Programmable Pulse 0 _ 0 0 0 0 0 1B Generator 2/3 0 0 0 0 0 0 _ _B 0 _ 0 0 0 _ _ 1B 16-bit Programmable Pulse 0 _ 0 0 0 0 0 1B Generator 4/5 0 0 0 0 0 0 _ _B 0 _ 0 0 0 _ _ 1B 16-bit Programmable Pulse 0 _ 0 0 0 0 0 1B Generator 6/7 0 0 0 0 0 0 _ _B (Continued) DS07-13727-2E 21 MB90435 Series Address 47H to 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH to 6BH 6CH 6DH 6EH 6FH 70H to 7FH 80H to 8FH 90H to 9DH 9EH 9FH A0H A1H Register Abbreviation Access Resource name Prohibited ICS01 ICS23 ICS45 ICS67 TMCSR0 TMCSR0 TMR0/ TMRLR0 TMR0/ TMRLR0 TMCSR1 TMCSR1 TMR1/ TMRLR1 TMR1/ TMRLR1 OCS0 OCS1 OCS2 OCS3 Prohibited TCDT TCDT TCCS ROMM Reserved Reserved Prohibited Address Match Detection Function Low Power Controller Low Power Controller R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ROM Mirror I/O Timer 16-bit Reload Timer 1 16-bit Reload Timer 0 Initial value Input capture control status register 0/1 Input capture control status register 2/3 Input capture control status register 4/5 Input capture control status register 6/7 Input Capture 0/1 0 0 0 0 0 0 0 0B Input Capture 2/3 0 0 0 0 0 0 0 0B Input Capture 4/5 0 0 0 0 0 0 0 0B Input Capture 6/7 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B _ _ _ _ 0 0 0 0B XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B _ _ _ _ 0 0 0 0B XXXXXXXXB XXXXXXXXB Output Compare 0 0 0 0 _ _ 0 0B 0/1 _ _ _0 0 0 0 0B Output Compare 0 0 0 0 _ _ 0 0B 2/3 _ _ _ 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B _ _ _ _ _ _ _ 1B Timer control status register 0 Timer control status register 0 Timer register 0/reload register 0 Timer register 0/reload register 0 Timer control status register 1 Timer control status register 1 Timer register 1/reload register 1 Timer register 1/reload register 1 Output compare control status register 0 Output compare control status register 1 Output compare control status register 2 Output compare control status register 3 Timer Counter Data register Timer Counter Data register Timer Counter Control status register ROM mirror function selection register Program address detection control status register Delayed interrupt/release register Low-power mode control register Clock selection register PACSR DIRR LPMCR CKSCR R/W R/W R/W R/W 0 0 0 0 0 0 0 0B Delayed Interrupt _ _ _ _ _ _ _ 0B 0 0 0 1 1 0 0 0B 1 1 1 1 1 1 0 0B (Continued) 22 DS07-13727-2E MB90435 Series Address A2H to A4H A5H A6H A7H A8H A9H AAH ABH to ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H to FFH Register Automatic ready function select register External address output control register Abbreviation Access Prohibited ARSR HACR ECSR WDTC TBTC WTC Prohibited W W W R/W R/W R/W Resource name Initial value 0 0 1 1 _ _ 0 0B External Memory Access Watchdog Timer Time Base Timer Watch Timer 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 _B XXXXX 1 1 1B 1 - - 0 0 1 0 0B 1 X 0 0 0 0 0 0B Bus control signal selection register Watchdog Timer control register Time Base Timer Control register Watch timer control register Flash memory control status register (Flash only, otherwise reserved) Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 FMCS Prohibited ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 External R/W Flash Memory 0 0 0 X 0 0 0 0B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B (Continued) DS07-13727-2E 23 MB90435 Series Address 1FF0H 1FF1H 1FF2H 1FF3H 1FF4H 1FF5H 3900H 3901H 3902H 3903H 3904H 3905H 3906H 3907H 3908H 3909H 390AH 390BH 390CH 390DH 390EH 390FH 3910H to 3917H 3918H 3919H 391AH 391BH 391CH 391DH 391EH 391FH Register Program address detection register 0 Program address detection register 0 Program address detection register 0 Program address detection register 1 Program address detection register 1 Program address detection register 1 Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Abbreviation Access Resource name Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB PADR0 PADR0 PADR0 PADR1 PADR1 PADR1 PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 PRLL4 PRLH4 PRLL5 PRLH5 PRLL6 PRLH6 PRLL7 PRLH7 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reserved 16-bit Programmable Pulse Generator 6/7 16-bit Programmable Pulse Generator 4/5 16-bit Programmable Pulse Generator 2/3 16-bit Programmable Pulse Generator 0/1 Address Match Detection Function XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Input Capture Register 0 Input Capture Register 0 Input Capture Register 1 Input Capture Register 1 Input Capture Register 2 Input Capture Register 2 Input Capture Register 3 Input Capture Register 3 IPCP0 IPCP0 IPCP1 IPCP1 IPCP2 IPCP2 IPCP3 IPCP3 R R R R R R R R Input Capture 2/3 Input Capture 0/1 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued) 24 DS07-13727-2E MB90435 Series (Continued) Address 3920H 3921H 3922H 3923H 3924H 3925H 3926H 3927H 3928H 3929H 392AH 392BH 392CH 392DH 392EH 392FH 3930H to 39FFH 3A00H to 3AFFH 3B00H to 3BFFH 3C00H to 3CFFH 3D00H to 3DFFH 3E00H to 3FFFH • Read/write notation R/W : Reading and writing permitted R : Read-only W : Write-only • Initial value notation 0 : Initial value is “0”. 1 : Initial value is “1”. X : Initial value is undefined. Register Input Capture Register 4 Input Capture Register 4 Input Capture Register 5 Input Capture Register 5 Input Capture Register 6 Input Capture Register 6 Input Capture Register 7 Input Capture Register 7 Output Compare Register 0 Output Compare Register 0 Output Compare Register 1 Output Compare Register 1 Output Compare Register 2 Output Compare Register 2 Output Compare Register 3 Output Compare Register 3 Abbreviation Access IPCP4 IPCP4 IPCP5 IPCP5 IPCP6 IPCP6 IPCP7 IPCP7 OCCP0 OCCP0 OCCP1 OCCP1 OCCP2 OCCP2 OCCP3 OCCP3 R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Reserved Reserved Reserved Reserved Reserved Reserved Resource name Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Input Capture 4/5 Input Capture 6/7 Output Compare 0/1 Output Compare 2/3 Note : Any write access to reserved addresses in I/O map should not be performed. A read access to reserved addresses results in reading “X”. DS07-13727-2E 25 MB90435 Series ■ INTERRUPT MAP Interrupt cause Reset INT9 instruction Exception Reserved Reserved Reserved Reserved External Interrupt INT0/INT1 Time Base Timer 16-bit Reload Timer 0 8/10-bit A/D Converter I/O Timer External Interrupt INT2/INT3 Serial I/O 8/16-bit PPG 0/1 Input Capture 0 External Interrupt INT4/INT5 Input Capture 1 8/16-bit PPG 2/3 External Interrupt INT6/INT7 Watch Timer 8/16-bit PPG 4/5 Input Capture 2/3 8/16-bit PPG 6/7 Output Compare 0 Output Compare 1 Input Capture 4/5 Output Compare 2/3 - Input Capture 6/7 16-bit Reload Timer 1 UART 0 RX UART 0 TX UART 1 RX UART 1 TX Flash Memory Delayed interrupt 26 EI2OS clear N/A N/A N/A N/A N/A N/A N/A *1 N/A *1 *1 N/A *1 *1 N/A *1 *1 *1 N/A *1 N/A N/A *1 N/A *1 *1 *1 *1 *1 *2 *1 *2 *1 N/A N/A Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register Number ⎯ ⎯ ⎯ ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Address ⎯ ⎯ ⎯ 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH DS07-13727-2E MB90435 Series *1 : The interrupt request flag is cleared by the EI2OS interrupt clear signal. *2 : The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available. Notes : • N/A : The interrupt request flag is not cleared by the EI2OS interrupt clear signal. • For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags are cleared by the EI2OS interrupt clear signal. • At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by a hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused by the first event. So it is recommended not to use the EI2OS for this interrupt number. • If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control register (ICR) is asserted. This means that different interrupt sources share the same EI2OS Descriptor which should be unique for each interrupt source. For this reason, when one interrupt source uses the EI2OS, the other interrupt should be disabled. DS07-13727-2E 27 MB90435 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol VCC AVCC AVRH, AVRL VI VO ICLAMP Σ| ICLAMP | IOL IOLAV ΣIOL ΣIOLAV IOH IOHAV ΣIOH ΣIOHAV PD TA TSTG Value Min VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 VSS − 0.3 − 2.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ −40 −55 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 + 2.0 20 15 4 100 50 −15 −4 −100 −50 500 400 +105 +150 Units V V V V V mA mA mA mA mA mA mA mA mA mA mW mW °C °C (VSS = AVSS = 0.0 V) Remarks VCC = AVCC*1 AVCC ≥ AVRH/AVRL, AVRH ≥ AVRL*1 *2 *2 *6 *6 *3 *4 *5 *3 *4 *5 Flash device Mask ROM Power supply voltage Input voltage Output voltage Maximum clamp current Total maximum clamp current “L” level max output current “L” level avg. output current “L” level max overall output current “L” level avg. overall output current “H” level max output current “H” level avg. output current “H” level max overall output current “H” level avg. overall output current Power consumption Operating temperature Storage temperature *1 : AVCC, AVRH, AVRL should not exceed VCC. Also, AVRH, AVRL should not exceed AVCC, and AVRL does not exceed AVRH. *2 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supercedes the VI rating. *3 : The maximum output current is a peak value for a corresponding pin. *4 : Average output current is an average current value observed for a 100 ms period for a corresponding pin. *5 : Total average current is an average current value observed for a 100 ms period for all corresponding pins. *6 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 • Use within recommended operating conditions. • Use at DC voltage (current) . • The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on result. (Continued) 28 DS07-13727-2E MB90435 Series (Continued) • Care must be taken not to leave the +B input pin open. • Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. • Sample recommended circuits : • Input/Output Equivalent circuits Protective diode VCC +B input (0 V to 16 V) Limiting resistance P-ch N-ch R Note : Average output current = operating current × operating efficiency WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. DS07-13727-2E 29 MB90435 Series 2. Recommended Conditions Parameter Symbol Min 4.5 Power supply voltage VCC, AVCC CS TA 3.5 3.0 0.022 −40 Value Typ 5.0 5.0 ⎯ 0.1 ⎯ Max 5.5 5.5 5.5 1.0 +105 Units V V V µF °C (VSS = AVSS = 0.0 V) Remarks Under normal operation : MB90F439 (S) /439 (S) /V540G Under normal operation : MB90F438L (S) /437L (S) /438L (S) Maintain RAM data in stop mode * Smooth capacitor Operating temperature *: Use a ceramic capacitor or a capacitor of better 4. AC characteristics. The VCC Capacitor should be greater than this capacitor. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. • C Pin Connection Diagram C CS 30 DS07-13727-2E MB90435 Series 3. DC Characteristics (MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) (MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Value SymParameter Pin name Condition Units Remarks bol Min Typ Max CMOS ⎯ 0.8 VCC ⎯ VCC + 0.3 V VIHS hysteresis input pin Input H TTL input VIH ⎯ 2.0 ⎯ ⎯ V voltage pin MD input VIHM ⎯ VCC − 0.3 ⎯ VCC + 0.3 V pin CMOS ⎯ VCC − 0.3 ⎯ 0.2 VCC V VILS hysteresis input pin Input L TTL input VIL ⎯ ⎯ ⎯ 0.8 V voltage pin MD input VILM ⎯ VSS − 0.3 ⎯ VCC + 0.3 V pin Output H All output VCC = 4.5 V, VOH ⎯ ⎯ V VCC − 0.5 voltage pins IOH = −4.0 mA Output L All output VCC = 4.5 V, VOL ⎯ ⎯ 0.4 V voltage pins IOL = 4.0 mA Input leak VCC = 5.5 V, IIL ⎯ −5 ⎯ 5 µA current VSS < VI < VCC P00 to P07, P10 to P17, Pull-up RUP P20 to P27, ⎯ 25 50 100 kΩ resistance P30 to P37, RST Pull-down RDO MD2 ⎯ 25 50 100 kΩ resistance WN (Continued) DS07-13727-2E 31 MB90435 Series (Continued) (MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) (MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Value SymParameter Pin name Condition Units Remarks bol Min Typ Max Internal frequency : 16 MHz, ⎯ 40 55 mA At normal operating ICC Internal frequency : 16 MHz, ⎯ 50 70 mA Flash device At Flash programming/erasing Internal frequency : 16 MHz, ICCS ⎯ 12 20 mA At sleep mode ⎯ 300 600 µA VCC = 5.0 V ± 1%, ⎯ 600 1100 µA MB90F348L (S) Internal frequency : 2 MHz, ICTS MB90437L (S) / At pseudo timer mode ⎯ 200 400 µA Power 438L (S) VCC supply ⎯ 400 750 µA MB90F438L (S) current* Internal frequency : 8 kHz, ICCL ⎯ 50 100 µA Mask ROM At sub operation, TA = 25 °C ⎯ 150 300 µA Flash device Internal frequency : 8 kHz, ICCLS ⎯ 15 40 µA At sub sleep, TA = 25 °C Internal frequency : 8 kHz, ICCT ⎯ 7 25 µA At timer mode, TA = 25 °C ICCH1 At stop, TA = 25 °C ⎯ 5 20 µA At hardware standby mode, ICCH2 ⎯ 50 100 µA TA = 25 °C Input capacity CIN Other than AVCC, AVSS, AVRH, AVRL, C, VCC, VSS ⎯ ⎯ 5 15 pF * : The power supply current testing conditions are when using the external clock. 32 DS07-13727-2E MB90435 Series 4. AC Characteristics (1) Clock Timing (MB90F438L (S) /437L (S) /438L (S) : VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) (MB90F439 (S) /439 (S) /V540G : VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C) Parameter Symbol Pin name Value Min 3 Oscillation frequency fC fCL tCYL tLCYL Input clock pulse width Input clock rise and fall time Machine clock frequency Machine clock cycle time PWH, PWL PWLH, PWLL tCR, tCF fCP fLCP tCP tLCP X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0 ⎯ ⎯ ⎯ ⎯ 3 ⎯ 62.5 Oscillation cycle time 200 ⎯ 10 ⎯ ⎯ 1.5 ⎯ 62.5 ⎯ Typ ⎯ ⎯ 32.768 ⎯ ⎯ 30.5 ⎯ 15.2 ⎯ ⎯ 8.192 ⎯ 122.1 Max 16 5 ⎯ 333 333 ⎯ ⎯ ⎯ 5 16 ⎯ 666 ⎯ Units Remarks MHz VCC = 5.0 V±10% MHz kHz ns ns µs ns µs ns Duty ratio is about 30% to 70%. When using external clock VCC = 5.0 V±10% VCC